Silicon carbide semiconductor device and power conversion device

Abstract

The purpose of the present disclosure is, in a silicon carbide semiconductor device having an SJ structure and an insulation gate structure, to realize low-resistance contact to a pillar region, to suppress variations in withstand voltage, and to reduce channel resistance and JFET resistance. An SJ-SiC-MOSFET (101) comprises an SJ region (90), and a MOSFET region (91) on the upper surface of the SJ region (90). The SJ region (90) comprises a plurality of n-type first pillar regions (21) and a plurality of p-type second pillar regions (30) that extend in a first direction parallel to a first main surface and that are alternately arranged in a second direction parallel to the first main surface and perpendicular to the first direction. The MOSFET region (91) comprises a plurality of BPW regions (31) that are formed from p-type silicon carbide, that are electrically connected to the second pillar regions (30), that extend in the second direction, and that are arranged in the first direction at a second repeat cycle (d2) shorter than a first repeat cycle (d1) which is a repeat cycle of the second pillar regions (30).

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] As semiconductor devices used in power electronics, vertical elements having electrodes on both sides of a semiconductor substrate are mainstream, and typical examples include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). When a normal vertical MOSFET is turned off, a depletion layer extends in the drift layer and functions as a voltage-resistant layer. If the drift layer is thin or has a high impurity concentration, only a thin depletion layer is formed, and the voltage-resistant property of the element decreases.

[0003] On the other hand, when the MOSFET is in the on-state, a current flows through the semiconductor substrate and the drift layer, and the resistance that this current experiences is called the on-resistance. The drift resistance, which is the resistance of the drift layer, is higher than the resistance of the semiconductor substrate, and is therefore one of the main resistance components of the MOSFET. Therefore, the on-resistance can be substantially reduced by lowering the drift resistance. A typical method for lowering the on-resistance is to reduce the thickness of the drift layer or to increase the impurity concentration of the drift layer. For these reasons, there is a trade-off between high breakdown voltage and low on-resistance.

[0004] A superjunction structure (hereinafter also referred to as an SJ structure) has been proposed as a structure that resolves the trade-off between breakdown voltage and on-resistance. In the SJ structure, p-type pillars and n-type pillars are alternately arranged in the drift layer along a direction perpendicular to the direction of current flow. According to the SJ structure, in addition to the depletion layer that spreads from the pn junction surface or metal junction surface present near the surface of the semiconductor element, a depletion layer also spreads from the pn junction surface between the p-type pillar and the n-type pillar. That is, a depletion layer is formed in the drift layer to the same depth as the depth of the p-type pillar or the n-type pillar. For example, when the conductivity type of the drift layer is n-type, even if the impurity concentration of the n-type pillar is increased to reduce the drift resistance, a high breakdown voltage can be maintained by maintaining the balance of the impurity concentration between the n-type pillar and the p-type pillar so that the inside of the n-type pillar and the p-type pillar are completely depleted. Therefore, it is expected that the SJ structure will dramatically improve the trade-off between the breakdown voltage and on-resistance of a semiconductor device.

[0005] Methods for forming the above-mentioned pillars include a multi-epitaxial method (hereinafter also referred to as a multi-epi method) and a buried epitaxial method (hereinafter also referred to as a buried epi method). The multi-epitaxial method is a method in which an epitaxial growth process and an ion implantation process are alternately repeated. The buried epi method is a method in which an epitaxial layer is further formed to fill a trench formed in an epitaxial layer after a trench is formed in the epitaxial layer. In either method, there is a limit to how narrow the interval between the pillar structures can be. In particular, in the case of a semiconductor device using silicon carbide (SiC), which is currently becoming increasingly widespread as a wide band gap material, it is difficult to narrow the interval between the pillar structures as described below.

[0006] The problems with the multi-epi method are explained below. Generally, the thermal diffusion coefficient of impurities is very small in SiC. The thermal diffusion coefficient of p-type impurities such as Al and B in SiC is also very small. Therefore, in order to form a p-type region using the multi-epi method, it is necessary to form a uniform profile by performing high-energy ion implantation multiple times. Therefore, in the multi-epi method, it is necessary to form a thick resist for ion implantation and to separate regions where ions are implanted and regions where they are not.

[0007] In order to form p-type pillar regions at low cost using the multi-epitaxial method, it is necessary to minimize the number of epitaxial growth steps. However, reducing the number of epitaxial growth steps increases the ion implantation energy, which requires a thick resist.

[0008] As described above, in the multi-epi method, there is a trade-off between the width of the p-type pillar region and the process cost, and there is a limit to the width of the p-type pillar that is practical for industrial applications.

[0009] The buried epitaxial method has similar issues. Compared to silicon (Si), which is the mainstream material for power devices, SiC has stronger atomic bonds, making it difficult to etch using reactive ion etching (RIE) and other methods. As a result, SiC has a smaller selectivity with respect to the etching mask than Si, which places more restrictions on the aspect ratio of trenches that can be formed by etching. Therefore, even if the buried epitaxial method is used with SiC, there is a limit to the practical width of p-type pillars. As described above, with SiC, the pillar spacing in the SJ structure tends to be wider than with Si.

[0010] In addition to the pillar spacing issue, SiC MOSFETs have a very high channel resistance. The channel mobility is several hundred cm for n-type Si-MOSFETs. 2 / Vs, whereas n-type SiC-MOSFETs have a resistance of only a few tens of cm 2 / Vs.

[0011] Furthermore, SiC has the problem of extremely low hole mobility. For example, the hole mobility in Si is 500 cm 2 / Vs, 1500cm 2 / Vs, which is about one-third of the electron mobility. On the other hand, in the case of SiC, the hole mobility is 100 cm 2 / Vs, 1100cm 2 This is about one-tenth of the electron mobility of about 1 / Vs.

[0012] This low hole mobility has a negative effect on the dynamic characteristics of MOSFETs. Compared to Si, SiC has a dielectric breakdown field about 10 times higher, so the charge stored in the depletion layer of the drift layer is also about 10 times higher. For dynamic characteristics, it is important to achieve a fast response of the depletion layer. However, in SiC-MOSFETs, the depletion layer charge amount, which is 10 times that of Si-MOSFETs, must be charged and discharged through holes, which have much lower mobility than Si, especially in the p-type region. Therefore, various problems will occur unless the contact region is formed more densely in the p-type region. Specifically, the generation of a potential in the p-type region increases the stress on the gate insulating film, which causes a decrease in product life or a decrease in dV / dt resistance.

[0013] In order to achieve charge balance in an SJ-MOSFET, more depletion layer charge is generated per unit area than in a normal planar MOSFET. Since the SJ-MOSFET must extract this charge through the p-type pillar region, which has a relatively low concentration, the above issues are more pronounced in the SJ-MOSFET than in a normal planar MOSFET.

[0014] Furthermore, while the high dielectric breakdown field characteristic of SiC brings about the benefit of lowering the resistance of the drift layer, it also causes the problem of an increased electric field in the gate insulating film provided in contact with the SiC. In SiC-MOSFETs, the problem of a decrease in the gate insulating film life due to an increase in the electric field in the JFET region arises, which was not considered in SiC-MOSFETs with their small dielectric breakdown field. For this reason, the JFET region must be made narrower in SiC-MOSFETs than in Si-MOSFETs. As the JFET region becomes narrower, the resistance of the JFET region (JFET resistance) increases, which, like the increase in channel resistance, becomes an obstacle to reducing the on-resistance, especially in low-voltage elements. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] Patent No. 6377302 [Non-patent literature]

[0016] [Non-Patent Document 1] T. Fujihira, “Theory of Semiconductor Superjunction Devices,” Jpn. J. Appl. Phys., vol. 36, pp. 6254-6262, 1997. [Non-Patent Document 2] SK Lee., et al., “Low resistivity ohmic titanium carbide contacts to n- and p-type 4H-silicon carbide” Solid-State Electronics 44 (2000) 1179-1186. [Non-Patent Document 3] C. Darmodya and N. Goldsmanb, “Incomplete ionization in aluminum-doped 4H-silicon carbide” J. Appl. Phys. 126, 145701 (2019). Summary of the Invention [Problem to be solved by the invention]

[0017] Considering the above restrictions and issues, a possible method for realizing a high-performance, easy-to-use SJ-MOSFET in SiC is to make the repetition period of the MOSFET shorter than the repetition period of the p-type pillars, as shown in Patent Document 1. This increases the channel width density of the SiC, realizing low resistance.

[0018] However, even with the above measures, problems still remain. First, even if the repetition period of the MOSFET is made smaller than that of the p-pillars, if the repetition direction of the MOSFET and the p-pillars is the same, the repetition period of the MOSFET is limited to an integer fraction of the repetition period of the p-pillars. In addition, misalignment of the MOSFET and the SJ region causes variations in the breakdown voltage. This is because the electric field applied to the pn junction changes significantly depending on where the JFET region of the MOSFET is located between the p-pillars.

[0019] In addition, no channel region is formed above the p-pillar, which is limited to a relatively large width, resulting in higher channel resistance and JFET resistance compared to conventional planar MOSFETs.

[0020] The present disclosure has been made to solve the above-mentioned problems, and aims to achieve low-resistance contact in a pillar region, suppress variations in breakdown voltage, and reduce channel resistance and JFET resistance in a silicon carbide semiconductor device having an SJ structure and an insulated gate structure. [Means for solving the problem]

[0021] The silicon carbide semiconductor device of the present disclosure comprises an n-type silicon carbide substrate having a first main surface and a second main surface opposing each other, an SJ region made of silicon carbide provided on the first main surface of the silicon carbide substrate, and a MOSFET region provided on an upper surface of the SJ region. The SJ region comprises a plurality of n-type first pillar regions and a plurality of p-type second pillar regions extending in a first direction parallel to the first main surface and arranged alternately in a second direction parallel to the first main surface and perpendicular to the first direction. The MOSFET region extends in the second direction and is arranged in the first direction with a second repetition period that is shorter than the first repetition period which is the repetition period of the second pillar regions. 、p a plurality of BPW regions made of silicon carbide of a type; and a plurality of gate electrodes provided via a gate insulating film in each trench provided on each BPW region in a second direction. ,of Prepare. Effect of the Invention

[0022] According to the silicon carbide semiconductor device of the present disclosure, a low-resistance contact to the second pillar region is realized, the variation in breakdown voltage is suppressed, and the channel resistance and JFET resistance are reduced. Objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic plan view of an SJ-SiC-MOSFET according to the first or second embodiment. [Diagram 2] FIG. 1 is a perspective view of a unit cell of the SJ-SiC-MOSFET of the first embodiment. [Diagram 3] FIG. 1 is a perspective view of a unit cell of the SJ-SiC-MOSFET of the first embodiment. [Figure 4] FIG. 2 is an xy plan view of the boundary between the SJ region and the MOSFET region of the SJ-SiC-MOSFET 101 of the first embodiment. [Diagram 5]FIG. 5 is a cross-sectional view of the SJ-SiC-MOSFET 101 according to the first embodiment taken along the line A1-A1' in FIG. [Figure 6] 5 is a cross-sectional view of the SJ-SiC-MOSFET 101 according to the first embodiment taken along the line A2-A2' in FIG. [Figure 7] FIG. 1 is a diagram showing a pn diode structure used in a trial calculation example of the optimum design of the SJ region. [Figure 8] FIG. 13 is a diagram showing the relationship between the pillar pitch and the on-resistance and the impurity concentration in an optimized SJ region. [Figure 9] FIG. 7 shows the results of a TCAD simulation of the electric field distribution above the pn diode structure of FIG. 6. [Figure 10] 11 is a diagram showing the relationship between the average current density and sheet resistance in a current path for holes from an intersection region to a source electrode, and the impurity concentration in a first pillar region. FIG. [Figure 11] FIG. 13 is a graph showing the acceptor impurity concentration dependence of hole mobility and ionization rate in a p-type region. [Figure 12] FIG. 13 is a diagram showing the dependency of resistivity of a p-type region on the acceptor impurity concentration. [Figure 13] 11 is a diagram showing the relationship between the impurity concentration of the connection region and the area occupancy in the xy plane. [Figure 14] FIG. 1 shows the diode structure used in the TCAD calculations. [Figure 15] FIG. 4 is a diagram showing the time waveform of a current flowing through a cathode. [Figure 16] 13 is a diagram showing a time waveform of a voltage difference between immediately above and immediately below a mobility reducing region. FIG. [Figure 17] FIG. 13 is a diagram showing the results of trial calculations of the relationship between the impurity concentration of the connection region and the area occupancy in the xy plane when the resistivity of the connection region is 1 mΩcm 2 and 0.3 mΩcm 2 . [Figure 18] FIG. 1 is a perspective view of a unit cell of an SJ-SiC-MOSFET according to a first modified example of the first embodiment. [Figure 19] FIG. 2 is a plan view in an xy plane passing through an intersection region of an SJ-SiC-MOSFET according to a first modified example of the first embodiment. [Figure 20] FIG. 20 is a cross-sectional view of the SJ-SiC-MOSFET according to the first modified example of the first embodiment, taken along the line A1-A1' in FIG. [Figure 21] 20 is a cross-sectional view of the SJ-SiC-MOSFET according to the first modified example of the first embodiment, taken along the line A2-A2' in FIG. [Figure 22] FIG. 11 is a perspective view of a unit cell of an SJ-SiC-MOSFET according to a second modified example of the first embodiment. [Figure 23] FIG. 11 is a plan view in an xy plane passing through an intersection region of an SJ-SiC-MOSFET according to a second modified example of the first embodiment. [Figure 24] FIG. 24 is a cross-sectional view of the SJ-SiC-MOSFET according to the second modified example of the first embodiment, taken along the line A1-A1' in FIG. [Diagram 25] FIG. 24 is a cross-sectional view of the SJ-SiC-MOSFET according to the second modified example of the first embodiment, taken along the line A2-A2' in FIG. [Figure 26] FIG. 13 is a perspective view of a unit cell of an SJ-SiC-MOSFET according to a third modified example of the first embodiment. [Figure 27] FIG. 13 is a plan view in an xy plane passing through an intersection region of an SJ-SiC-MOSFET according to a third modified example of the first embodiment. [Figure 28] FIG. 27 is a cross-sectional view of the SJ-SiC-MOSFET according to a third modified example of the first embodiment, taken along the line A1-A1' in FIG. [Figure 29] FIG. 28 is a cross-sectional view of the SJ-SiC-MOSFET according to the third modified example of the first embodiment, taken along the line A2-A2' in FIG. [Diagram 30] FIG. 11 is a cross-sectional view in the xz plane passing through the first pillar region of the SJ-SiC-MOSFET of the fourth modified example of the first embodiment. [Diagram 31] FIG. 11 is a cross-sectional view in the xz plane passing through the second pillar region of the SJ-SiC-MOSFET of the fourth modified example of the first embodiment. [Diagram 32] FIG. 11 is a perspective view of a unit cell of an SJ-SiC-MOSFET according to a second embodiment. [Diagram 33]Perspective view of the unit cell of the SJ-SiC-MOSFET according to the first modification of Embodiment 2. [Diagram 34] Perspective view of the unit cell of the SJ-SiC-MOSFET according to the second modification of Embodiment 2. [Diagram 35] Perspective view of the unit cell of the SJ-SiC-MOSFET according to the third modification of Embodiment 2. [Diagram 36] Configuration diagram of the power conversion system according to Embodiment 3.

Mode for Carrying Out the Invention

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. The drawings are schematically shown, and the mutual relationships of the sizes and positions of the images shown in different drawings are not necessarily accurately described and can be changed as appropriate. Also, in the following description, the same reference numerals are given to the same components in the drawings, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0025] In the embodiments described in this specification, as an example of a semiconductor device, a silicon carbide (SiC) semiconductor device is used, and an n-channel silicon carbide MOSFET with the first conductivity type being n-type and the second conductivity type being p-type will be described as an example. The description of the high and low potentials is for the case where the first conductivity type is n-type and the second conductivity type is p-type. When the first conductor is p-type and the second conductivity type is n-type, the description of the high and low potentials is reversed. Further, in the entire semiconductor device, a region other than the active region where unit cells are periodically arranged is referred to as an outer peripheral region in this application.

[0026] <A. Embodiment 1> <A-1. Configuration> First, the configuration of the silicon carbide semiconductor device according to Embodiment 1 will be described.

[0027] Fig. 1 is a schematic plan view of a silicon carbide MOSFET having an SJ structure (hereinafter referred to as SJ-SiC-MOSFET) 101, which is a silicon carbide semiconductor device according to embodiment 1, or an SJ-SiC-MOSFET 102, which is a silicon carbide semiconductor device according to embodiment 2, viewed from the top. In Fig. 1, a gate pad 81 is formed on part of the top surface of SJ-SiC-MOSFETs 101, 102, and a source electrode 80 is formed adjacent to this. In addition, a gate wiring 82 is formed to extend from gate pad 81.

[0028] FIG. 2 is a perspective view of a unit cell of the SJ-SiC-MOSFET 101. In FIG. 2, the configuration above the MOSFET region 91 is omitted in order to visualize the configuration of the unit cell. The unit cell of the SJ-SiC-MOSFET 101 shown in FIG. 2 is periodically repeated below the source electrode 80 in FIG. 1. The z-axis direction in FIG. 2 is the surface direction of the chip constituting the SJ-SiC-MOSFET 101. The x-axis and y-axis directions in FIG. 2 are the directions of each side of the chip constituting the SJ-SiC-MOSFET 101, respectively. However, the way in which these axes are taken is not necessarily uniquely defined, and has a certain degree of arbitrariness. The x-axis and y-axis are horizontal to the surface direction of the chip and perpendicular to the z-axis, and may be at an angle of at least a certain degree, for example, 10° or more, relative to each other.

[0029] We now move on to a specific description of Fig. 2. For simplicity, only the internal region of the semiconductor layer made of SiC and the trench gate portion are shown in Fig. 2. To simply show the three-dimensional structure, Fig. 2 shows the SJ-SiC-MOSFET 101 cut out at various cross sections.

[0030] 2, SJ-SiC-MOSFET 101 includes an n-type silicon carbide substrate 10, an n-type drift layer 20, an SJ region 90, and a MOSFET region 91. The upper and lower surfaces of silicon carbide substrate 10 in Fig. 2 are also referred to as a first main surface and a second main surface, respectively.

[0031] The drift layer 20 is formed on the silicon carbide substrate 10. The SJ region 90 is formed on the drift layer 20. The MOSFET region 91 is formed on the SJ region 90. The SJ region 90 is not in contact with the silicon carbide substrate 10 in FIG. 2, but may be in contact with the silicon carbide substrate 10 as shown in FIG. 3. That is, the SJ region 90 may be formed on the silicon carbide substrate 10 via the drift layer 20, or may be formed directly on the silicon carbide substrate 10.

[0032] The SJ region 90 includes a plurality of n-type first pillar regions 21 and a plurality of p-type second pillar regions 30. Each of the first pillar regions 21 and each of the second pillar regions 30 extends in the x-axis direction and is alternately arranged in a striped pattern in the y-axis direction with a repetition period d1. That is, each of the first pillar regions 21 and each of the second pillar regions 30 extends in the x-axis direction, which is a first direction parallel to the first main surface of the silicon carbide substrate 10, and is alternately arranged in the y-axis direction, which is a second direction parallel to the first main surface and perpendicular to the x-axis. The repetition period d1 is also referred to as a first repetition period. A small portion of the second pillar region 30 may extend into the MOSFET region 91.

[0033] Although the impurity concentrations of the first pillar region 21 and the second pillar region 30 may vary due to process variations and the like, it is desirable to design them so as to achieve a general charge balance. Charge balance refers to the sum of the space charge densities when the first pillar region 21 and the second pillar region 30 at the same depth are fully depleted, with the positive and negative charges canceling out and becoming approximately zero. Specifically, the SJ region 90 may be designed so that the product of the width of the first pillar region 21 and the impurity concentration of the first pillar region 21 is approximately equal to the product of the width of the second pillar region 30 and the impurity concentration of the second pillar region 30.

[0034] The MOSFET region 91 includes an n-type JFET region 22, a p-type body region 32, a source region 23 which is an n-type impurity region, a p-type body contact region 33, a gate insulating film 50, a gate electrode 60, a p-type BPW region 31, and a p-type connection region 34.

[0035] The JFET region 22 is formed on the SJ region 90. The body region 32 is formed on the JFET region 22. The source region 23 is formed on the body region 32. The body contact region 33 is formed so as to reach the body region 32 from the upper surface of the source region 23 through the source region 23. A trench 55 is formed so as to penetrate the source region 23 and the body region 32 from the upper surface of the source region 23. A gate insulating film 50 made of a thin silicon oxide film having a thickness of about 50 nm to 100 nm is formed on the inner wall of the trench 55. A gate electrode 60 made of polycrystalline silicon or the like is formed inside the trench 55 via the gate insulating film 50. Here, the side surface of the trench 55 may have any plane orientation. For example, when the polytype of the silicon carbide semiconductor is 4H-SiC, if the side surface of the trench 55 is formed parallel to the <11-20> direction, the channel region can utilize the m plane of (1-100) or (-1100). Therefore, a channel region which is less susceptible to the effect of the off-angle of silicon carbide substrate 10 and has little variation can be formed.

[0036] At the bottom of the trench 55, a plurality of p-type BPW regions 31 extending in the y-axis direction are formed in stripes in the x-axis direction with a repeating period d2. That is, the BPW regions 31 extend in the y-axis direction perpendicular to the x-axis direction, which is the extension direction of the second pillar region 30 of the SJ region 90. The repeating period d2 of the BPW region 31 is also referred to as the second repeating period. The repeating period d2 of the BPW region 31 is shorter than the repeating period d1 of the second pillar region 30. The intersection of the BPW region 31 and the second pillar region 30 is defined as an intersection region 92. In the intersection region 92, the BPW region 31 is connected to the second pillar region 30.

[0037] The connection region 34 is provided in contact with or near the intersection region 92. Here, the connection region 34 being near the intersection region 92 means that the connection region 34 is located at a position where it is electrically connected to the intersection region 92 with low resistance. Specifically, if the distance between the connection region 34 and the intersection region 92 is shorter than ¼ of the separation distance between adjacent intersection regions 92 in the repeating direction of the intersection regions 92, the connection region 34 may be considered to be near the intersection region 92. The connection region 34 extends in the vertical direction, i.e., the z-axis direction, and is connected to the body region 32. The impurity concentration of the BPW region 31 is desirably higher than the impurity concentration of the second pillar region 30, but may be equal to or lower than the impurity concentration of the second pillar region 30.

[0038] The JFET regions 22 are formed between the trenches 55 and between the BPW regions 31 with a higher impurity concentration than the first pillar regions 21. The JFET regions 22 are also formed on top of the p-type second pillar regions 30.

[0039] The body region 32 is formed on the JFET region 22 and is formed to fill the gaps between the trenches 55. The source region 23 is formed on the upper portion of the body region 32 so as to be in contact with the gate insulating film 50. The body contact regions 33 penetrate the source region 23 and are periodically formed so as to be in contact with the body region 32.

[0040] Fig. 4 is an xy plan view of the boundary between the SJ region 90 and the MOSFET region 91 of the SJ-SiC-MOSFET 101. In Fig. 4, the direction perpendicular to the paper and toward the front side is the z-axis positive direction. As shown in Fig. 4, an intersection region 92 is defined at the intersection of the BPW region 31 and the second pillar region 30. The BPW region 31 is formed mainly by ion implantation and therefore protrudes into the SJ region 90, but it is not necessary for the BPW region 31 to be formed by a method other than ion implantation and not to protrude into the SJ region 90. The BPW region 31 is connected to the second pillar region 30 at the intersection region 92. The connection region 34 is formed adjacent to the intersection region 92 and extends in the z-axis direction.

[0041] In Fig. 4, a cross section that is parallel to the z-axis and passes through the center of second pillar region 30 is defined as A1-A1' cross section. Similarly, a cross section that is parallel to the z-axis and passes through the center of first pillar region 21 is defined as A2-A2' cross section. Fig. 5 is an A1-A1' cross section of SJ-SiC-MOSFET 101, and Fig. 6 is an A2-A2' cross section of SJ-SiC-MOSFET 101. Unlike Figs. 2 and 3, Figs. 5 and 6 show the structure above MOSFET region 91 without omission.

[0042] As shown in FIGS. 5 and 6, the SJ-SiC-MOSFET 101 includes an interlayer insulating film 51, a source electrode 80 which is an upper electrode, a first ohmic contact region 70, and a drain electrode 83 which is a lower electrode. The interlayer insulating film 51 covers an upper portion of the gate electrode 60 and insulates the gate electrode 60 from the source electrode 80. A contact hole exposing the body contact region 33 is formed in the interlayer insulating film 51. The source electrode 80 is formed on the interlayer insulating film 51 and in the contact hole, and the source electrode 80 contacts the body contact region 33 through the contact hole. Specifically, a first ohmic contact region 70 is formed at the boundary between the source electrode 80 and the body contact region 33, and the source electrode 80 contacts the body contact region 33 through the first ohmic contact region 70.

[0043] As shown in FIG. 5, the BPW region 31 is connected to the second pillar region 30 in the intersection region 92. Further, the BPW region 31 is connected to the body region 32 via the connection region 34. The body region 32 is connected to the source electrode 80 via the body contact region 33 and the first ohmic contact region 70. With this configuration, the hole conduction path from the source electrode 80 to the second pillar region 30 has a lower resistance. An n-type JFET region 22 is also formed on the upper part of the second pillar region 30. Since this JFET region 22 extends in the y-axis direction and reaches the upper part of the first pillar region 21, it contributes to conduction. In FIGS. 5 and 6, the source region 23 does not contact the first ohmic contact region 70. However, actually, in the cross-section between the A1 - A1' cross-section and the A2 - A2' cross-section, the source region 23 contacts the first ohmic contact region 70 and is in ohmic connection with the source electrode 80.

[0044] As shown in FIG. 6, in the A2 - A2' cross-section, the first pillar region 21 occupies the entire SJ region 90. Also, in the A2 - A2' cross-section, the connection region 34 does not exist in the MOSFET region 91. The structure of the other A2 - A2' cross-section is substantially equal to the structure of the A1 - A1' cross-section shown in FIG. 5.

[0045] <A-2. Manufacturing method> The manufacturing method of the SJ - SiC - MOSFET 101 will be described. First, the method of forming the SJ region 90 will be described. As described above, the SJ formation methods include the multi - epi method and the embedded - epi method, and either method may be used.

[0046] First, the embedded - epi method will be described. On the n - type silicon carbide substrate 10, a drift layer 20 with a thickness of 5 μm or more and 200 μm or less is epitaxially grown by chemical vapor deposition (CVD method). The silicon carbide substrate 10 has a (0001) plane with an off - angle for the plane orientation of the first main surface, which is the positive z - axis direction surface, has a 4H polytype, and an n - type impurity concentration of 1×10 18 cm -3 or more and 5×1019 cm -3 The drift layer 20 has an n-type impurity concentration of 1×10 14 cm -3 From the above, 5 x 10 17 cm -3 The following silicon carbide:

[0047] Next, a SiO2 layer is formed on the drift layer 20. Then, this SiO2 layer is processed into a stripe shape by photolithography, reactive ion etching, or the like. Then, using an etching gas that has a selectivity with SiO2, a trench 55 with a width of about 1 μm to 10 μm is formed in the drift layer 20. It is desirable that the trench 55 has a large ratio of depth to width and is deeply etched in the depth direction to the entire drift layer 20. However, with an emphasis on reducing the width of the trench 55, the depth of the trench 55 may be about half the depth of the drift layer 20. Such an SJ structure using the trench 55 is also called a half SJ structure or a small SJ structure. The drift layer 20 between the trenches 55 that is left unetched during the formation of the trenches 55 becomes the first pillar region 21.

[0048] Next, a p-type SiC layer is epitaxially grown on the trench 55 by CVD, and the trench 55 is completely filled with the p-type epitaxial layer. Here, aluminum (Al) or boron (B) is typically used as the p-type impurity for the epitaxial layer filling the trench 55. In this way, the second pillar region 30 is formed. It is desirable that the p-type impurity concentration of the second pillar region 30 is set so as to realize charge balance in relation to the n-type impurity concentration of the first pillar region 21 as described above.

[0049] When the trenches 55 are filled with the p-type epitaxial layer, the p-type epitaxial layer is also formed on the mesa region between the trenches 55. Therefore, only the p-type epitaxial layer on the mesa region is removed by a method such as chemical mechanical polishing, and the SJ region 90 is completed with both the first pillar region 21 and the second pillar region 30 exposed on the surface of the semiconductor layer.

[0050] Next, a case where the multi-epi method is used will be described. On an n-type silicon carbide substrate 10, an n-type epitaxial layer having a thickness of several hundreds of nm to several tens of μm is formed by a CVD method. Then, a SiO2 film is formed on the n-type epitaxial layer, and a mask for ion implantation is created by patterning the film by photolithography. Next, ion implantation is performed while changing the implantation energy and dose amount within a range that does not penetrate the ion implantation mask, to form a p-type region having a uniform impurity concentration distribution in the depth direction. Here, the implantation energy that does not penetrate the ion implantation mask depends on the thickness of the ion implantation mask, and is, for example, several hundreds keV to several MeV. B or Al is used as the implantation element. Then, the mask for ion implantation is removed.

[0051] After that, an n-type epitaxial layer is formed again, and the p-type region is extended in the depth direction by the above-mentioned method. By repeating this process multiple times, the obtained p-type region becomes the second pillar region 30, and the n-type epitaxial layer between the second pillar regions 30 becomes the first pillar region 21, and the SJ region 90 is obtained.

[0052] In the above, for the sake of simplicity, a method of forming a p-type region by performing ion implantation into an n-type epitaxial layer has been described, but the n-type and p-type may be reversed. Also, after forming an n-type epitaxial layer with a low impurity concentration, ion implantation may be performed on the entire surface to form an n-type region that will become the drift layer 20 or the first pillar region 21. In general, ion implantation has a smaller impurity variation than epitaxial growth, so that the deviation from the charge balance state in the SJ region 90 can be reduced. Therefore, it is possible to suppress the variation in on-resistance or withstand voltage and realize an SJ region 90 with a high yield. Furthermore, although it is costly, the n-type region and the p-type region may be formed by forming masks separately to further increase the degree of freedom in design. The impurity implanted when forming the n-type region is generally nitrogen (N) or phosphorus (P).

[0053] The cost of the multi-epi method mainly depends on the number of multi-epi. On the other hand, in order to reduce the number of multi-epi, a special process such as setting the ion implantation energy to MeV is required, which leads to a deterioration in performance, for example, an increase in implantation defects due to an increase in implantation energy, or an increase in processing dimensions due to a thicker implantation mask. In addition, although details will be described later, in general, in an SJ-MOSFET, the more miniaturized it is, that is, the higher the aspect ratio of the second pillar region 30 is, the higher the p-type impurity concentration is, and the shorter the repetition period is, the higher the performance is, that is, the lower the on-resistance at the same breakdown voltage is. Therefore, in the multi-epi method, there is a trade-off between cost and performance, and the balance is mainly determined by the number of multi-epi.

[0054] In both the buried epitaxial method and the multi-epi method, the relationship between the impurity concentrations in the silicon carbide substrate 10, drift layer 20, and SJ region 90 is as follows. First, the silicon carbide substrate 10 has the highest impurity concentration in the n-type region. The impurity concentration in the drift layer 20 is designed to be equal to or lower than the impurity concentration in the first pillar region 21. Next, the p-type impurity concentration in the second pillar region 30 varies depending on the design of the charge balance in the SJ region 90. In this specification, it is basically considered that charge balance is achieved if the total amount of donors / total amount of acceptors is in the range of 0.5 to 2 in the xy plane at a constant depth in the SJ region 90 in the active region.

[0055] Next, a method for forming the MOSFET region 91 will be described. First, an n-type epitaxial layer is formed on the SJ region 90. Here, the epitaxial layer formed may be used as the JFET region 22 as it is by controlling the epi conditions so as to obtain the impurity concentration of the JFET region 22. This makes it possible to reduce the number of steps for forming the JFET region 22. Alternatively, for example, 1×10 14 cm -3 After forming an n-type epitaxial layer with a low impurity concentration such as GaN, GaN, etc., ion implantation may be performed into the epitaxial layer to increase the n-type impurity concentration to form the JFET region 22. This method can reduce the variation in the impurity concentration of the JFET region 22, thereby reducing product variation and increasing the yield.

[0056] One of the features of the SiC-MOSFET 101 is that the impurity concentration of the JFET region 22 is higher than the impurity concentrations of the drift layer 20 and the first pillar region 21. This allows the MOSFET formed on the second pillar region 30 to also contribute to current flow through the JFET region 22. The impurity concentration of the JFET region 22 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The impurity concentration of the JFET region 22 may be the same as the impurity concentration of the first pillar region 21.

[0057] Next, acceptor ions such as Al are implanted into the surface layer of the JFET region 22 to form a p-type body region 32. The impurity concentration of the body region 32 is, for example, 5×10 17 cm -3 More than 1×10 19 cm -3 The impurity concentration of the body region 32 may be about 0.5 μm or more and 2 μm or less. If the body region 32 is deep, the channel length can be increased and the short circuit resistance can be increased. Note that a p-type epitaxial layer may be formed on the JFET region 22 as the body region 32.

[0058] Next, an n-type source region 23 and a p-type body contact region 33 are formed in the surface layer of the body region 32 by ion implantation and photolithography. The source region 23 is formed by implanting N ions or P ions. The n-type impurity concentration of the source region 23 is 1×10 18 More than 1×10 21 cm -3 This exceeds the p-type impurity concentration of the body region 32. The body contact region 33 is formed by implanting Al ions or B ions. The impurity concentration of the body contact region 33 is 5×10 18 cm -3 More than 1×10 22 cm -3 ≦p-type impurity concentration, which exceeds the p-type impurity concentration of the body region 32.

[0059] Next, a mask for trench etching is formed by depositing an SiO2 film and photolithography. Then, using this mask, a trench 55 penetrating the body region 32 is formed by RIE or the like. Furthermore, a p-type BPW region 31 is formed by ion implantation in the lower part of the trench 55. At this time, the mask for etching the trench 55 may also be used as a mask for ion implantation to form the BPW region, thereby reducing the number of steps for creating the mask. It is desirable that the p-type impurity concentration of the BPW region 31 is equal to or higher than the p-type impurity concentration of the body region 32.

[0060] Next, p-type connection region 34 is formed using, for example, photolithography and oblique ion implantation into trench 55. Connection region 34 may be formed in contact with intersection region 92 or in the vicinity of intersection region 92. The p-type impurity concentration of connection region 34 may be equal to or higher than the p-type impurity concentration of body region 32.

[0061] Next, annealing is performed for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300° C. to 1900° C. This annealing electrically activates the n-type impurity ions and p-type impurity ions implanted into the silicon carbide semiconductor layer.

[0062] Next, the surface of the silicon carbide semiconductor layer is thermally oxidized to form a silicon oxide film of a desired thickness on the inner wall of the trench 55 as the gate insulating film 50. Furthermore, a conductive polycrystalline silicon film is formed on the gate insulating film 50 by low-pressure CVD and patterned to form a gate electrode 60 inside the trench 55. Thereafter, an interlayer insulating film 51 made of silicon oxide is formed by low-pressure CVD.

[0063] Next, contact holes are formed that penetrate the interlayer insulating film 51 and the gate insulating film 50 and reach the body contact region 33 and the source region 23 in the active region. Note that in Figures 5 and 6, the contact holes in the interlayer insulating film 51 and the gate insulating film 50 do not reach the source region 23. However, in an xz cross section that does not pass through the body contact region 33, the contact holes in the interlayer insulating film 51 and the gate insulating film 50 reach the source region 23.

[0064] Next, a metal film mainly composed of Ni is formed by a sputtering method or the like. Further, heat treatment is performed at a temperature of 600°C to 1100°C to react the metal film mainly composed of Ni with the silicon carbide layer in the body contact region 33, and a silicide is formed between the two. Subsequently, the remaining metal film other than the silicide formed by the reaction is removed by wet etching. As a result, the remaining silicide becomes the first ohmic contact region 70.

[0065] Thereafter, a metal film mainly composed of Ni is formed on the second main surface which is the back surface of the silicon carbide substrate 10, and heat treatment is performed to form a second ohmic region (not shown).

[0066] Note that the outer peripheral region is also formed simultaneously in the steps so far. A general structure is assumed for the outer peripheral region. For example, a step of forming a field insulating film under the outer peripheral polycrystalline silicon film may be provided separately.

[0067] Next, a wiring metal such as Al is formed on the surface side of the silicon carbide substrate 10 by a sputtering method or a vapor deposition method, and is processed into a predetermined shape by photolithography technology to form a source electrode 80, a gate pad 81, and a gate wiring 82. The source electrode 80 and the gate pad 81 are in contact with the first ohmic contact region 70 and the gate electrode 60, respectively.

[0068] Finally, if a drain electrode 83 which is a metal film is formed on the surface of the second ohmic region (not shown) formed on the back surface of the silicon carbide substrate 10, the SiC-MOSFET 101 shown in FIGS. 1 to 6 is completed.

[0069] <A-3. Operation> Next, the operation of the SJ-SiC-MOSFET 101 will be described. Hereinafter, the SJ-SiC-MOSFET 101 with a 4H-type silicon carbide semiconductor material will be described as an example. Power devices perform various operations in power conversion devices such as inverters. As operations and states in which the SJ-SiC-MOSFET 101 exhibits effects, the off state, on state, and switching operations (turn-on, turn-off) will be described.

[0070] <A-3-1. Off State> First, a general off state common to n-channel SJ-MOSFETs will be described. In the off state, the gate voltage is below the threshold value, generally 0 V or a few negative volts, and no n-channel is formed, resulting in a high-resistance state. In an inverter, a high voltage is applied to the drain of the device in this off state. When a positive voltage is applied to the drain, a reverse bias is applied to the pn junction between the first pillar region 21 and the second pillar region 30 in the SJ region 90. Therefore, a depletion layer extends in the lateral direction of the SJ region 90. When the drain voltage exceeds a certain value, the first pillar region 21 and the second pillar region 30 are completely depleted. As a result, the drain-source resistance increases significantly, and the off state can be maintained. At this time, if the charge balance is not perfect, even if one side is completely depleted, the other side will not be completely depleted, resulting in an additional electric field.

[0071] In the off state, when the drain voltage further increases, the longitudinal electric field increases. Depending on the design, the location where the electric field reaches its maximum is mainly at the bottom of the SJ region 90 or the pn junction between the body region 32 and the JFET region 22. When the maximum electric field at this time exceeds the breakdown electric field of SiC (about 3 MV / cm), breakdown due to avalanche current occurs.

[0072] Thus, it is understood that in designing an SJ-MOSFET, it is very important to adjust the charge balance between the first pillar region 21 and the second pillar region 30. For example, Fujihira's theory (Non-Patent Document 1) is well-known as a theory for optimizing the design of the first pillar region 21 and the second pillar region 30. The technology disclosed herein is also premised on the use of an SJ structure optimized based on Fujihira's theory.

[0073] As an example, we will show the results of the optimum design of the SJ region. For simplicity, we consider a pn diode structure in which the p-type pillar and n-type pillar have the same width, as shown in Figure 7. When the optimum design based on Fujihira's theory is implemented for this pn diode structure, the on-resistance of the SJ layer and the element breakdown voltage can be calculated using the following equations.

[0074]

number

[0075] In formula (1), R on.sp is the on-resistance, d is the pillar width / 2, V B is the breakdown voltage, μ is the mobility, ε S is the dielectric constant of the semiconductor, E C represents the dielectric breakdown field.

[0076] Under the optimum design conditions where equation (1) holds, V B The maximum electric field when applied is just E C The breakdown is shown in the following equations (2) and (3).

[0077]

number

[0078]

number

[0079] Here, Ezmax is the maximum electric field in the vertical direction at the center of the SJ layer, and Exmax is the maximum electric field in the horizontal direction at the center of the SJ layer.

[0080] In the structure shown in Figure 6, the width and impurity concentration of the p-pillar are equal to those of the n-pillar. When the cathode voltage rises to a certain voltage, the depletion layer spreads by d from the pn junction surface of the p-pillar and n-pillar. At this time, the n-pillar and p-pillar are fully depleted, and an electric field Exmax is applied horizontally at the center of the SJ layer, and vertically at the top and bottom ends of the center of the pillar of the SJ layer. At the time of breakdown, an electric field Ezmax is applied vertically at the center of the SJ, and an electric field Exmax+Ezmax is applied vertically at the top and bottom ends of the center of the pillar of the SJ layer. When this value reaches the breakdown electric field, breakdown occurs. In this structure, the breakdown voltage and on-resistance can be maximized by designing the electric fields in the vertical and horizontal directions to be equal, as shown in equation (3).

[0081] The impurity concentration N of the n- and p-type pillars at this time can be calculated from equations (2), (3) and Gauss's law as follows:

[0082]

number

[0083] Figure 8 shows the relationship between the pillar pitch 4d (μm), which is the repetition period of the pillars, and the on-resistance R on.sp (mΩcm 2 ) and impurity concentration N(cm -3 ) is calculated. As the pillar pitch 4d decreases, the on-resistance R on.sp It can be seen that the impurity concentration N increases while the pillar pitch 4d decreases. on.sp It can be said that when the capacitance is reduced, the total amount of charge required for charging and discharging the pillars tends to increase.

[0084] It has already been described that the SJ pillar is completely depleted during the holding of the breakdown voltage. The electric field distribution in the SJ pillar at that time is as shown in Fig. 9. Fig. 9 is the calculation result of the electric field by TCAD simulation for the SiC pn diode structure corresponding to extracting half of the repetition period (half pitch) of the pn diode structure shown in Fig. 7. The electric field strength on the vertical axis of Fig. 9 extracts the value near the top of the SJ layer where breakdown is likely to occur. The horizontal axis of Fig. 9 represents the distance from the center of the n-type pillar using d which is half of the pillar width. From Fig. 9, it can be seen that the electric field strength increases as it approaches the center of the n-type pillar. Therefore, for example, when a plurality of JFET regions are formed in the SJ pillar and a repetitive structure parallel to the SJ pillar is assumed as shown in Patent Document 1, due to a slight misalignment of the patterns between the SJ pillar and the MOSFET region, the maximum electric field applied to the JFET region of the MOSFET changes, and the breakdown voltage varies. On the other hand, in the SJ-SiC-MOSFET 101 of this embodiment, since the JFET region 22 of the MOSFET region 91 intersects the first pillar region 21 and the second pillar region 30, the maximum electric field is independent of the magnitude of the misalignment. Therefore, the variation in the breakdown voltage can be reduced.

[0085] <A-3-2. On-state> In the on-state, a positive voltage equal to or higher than the threshold value, for example, a voltage of about 15 V, is applied to the gate electrode 60. At this time, an n-type inversion layer channel is induced at the interface between the gate insulating film 50 and the channel region directly below the gate insulating film 50, that is, the body region 32 sandwiched between the n-type JFET region 22 and the source region 23. As a result, the source region 23 and the JFET region 22 are connected with low resistance, and as a result, the drain electrode 83 and the source electrode 80 are connected with low resistance.

[0086] According to the SJ-SiC-MOSFET 101, not only does the stripe direction of the SJ region 90 intersect with the stripe direction of the MOSFET region 91, but the JFET region 22 is also formed in the upper part of the second pillar region 30, thereby reducing the JFET resistance and channel resistance. As shown in Fig. 2, the MOSFET in the upper part of the second pillar region 30 can also pass a current to the first pillar region 21 through the JFET region 22.

[0087] Quantifying the effect of the SJ-SiC-MOSFET 101. The on-resistance of the SJ-SiC-MOSFET 101 can be roughly expressed by the following formula.

[0088]

number

[0089] Here, R on.sp is the on-resistance, R sub is the substrate resistance, R driftSJ is the resistance of the drift layer 20 and the first pillar region 21, R JFET is the resistance of JFET region 22, R ch represents the channel resistance. JFET can be decomposed as follows:

[0090]

number

[0091] Here, R JFETmos is the resistance value that contributes to the on-resistance in the current distribution when the SJ region 90 is a normal n-type drift layer that does not have the p-type second pillar region 30. JFETspred is an additional resistance component that occurs when the current flows around the top of the second pillar region 30. a is the occupancy rate of the first pillar region 21 in the SJ region 90, specifically, the width of the first pillar region 21 divided by the repeat period d1 of the second pillar region 30. Basically, R JFETmos , R JFETspredBoth of these can be reduced by increasing the impurity concentration of the JFET region 22. If the impurity concentration of the JFET region 22 is higher than that of the first pillar region 21, the JFET resistance becomes sufficiently small. In addition, if the occupancy rate a of the first pillar region 21 in the SJ region 90 is increased, the R JFETspred Since the contribution of the MOSFET is reduced, the on-resistance can be further reduced.

[0092] As a comparative example, consider a conventional SJ-MOSFET. In a conventional SJ-MOSFET, a MOSFET is not formed on the upper part of the second pillar region 30. Therefore, assuming a repetition period of the MOSFET similar to that of the SJ-SiC-MOSFET 101, the on-resistance is expressed by the following formula.

[0093]

number

[0094] In equation (7), the third term on the right side represents the channel resistance, and the fourth term on the right side represents the JFET resistance. The occupancy rate a of the first pillar region 21 in the SJ region 90 is equal to or less than 1. Therefore, the channel resistance and JFET resistance of the conventional SJ-MOSFET are higher than the channel resistance and JFET resistance of the SJ-SiC-MOSFET 101, respectively.

[0095] <A-3-3.ターンオフ> Next, we will discuss the turn-off of the switching operation. Turn-off is an operation in which the n-channel disappears and the device enters the off state when the gate voltage switches from a state in which the on-current flows with low resistance to a voltage below the threshold, such as 0 or -10 V. At this time, the drain voltage increases rapidly, and then the current drops to near zero.

[0096] The transition of the element state during the turn-off state will be described. First, the element receives a current I Lcurrent flows while the drain voltage is in a low on-state. The gate driver extracts charge from the gate terminal, causing the gate voltage to drop. This increases the resistance of the channel region, the drain voltage starts to increase, the MOSFET transitions from the linear region to the saturation region, and the depletion layer starts to spread in the JFET region 22 and drift layer 20. In the early stages of the turn-off operation, the extraction of charge from the gate, i.e., the current flowing from the gate to the driver, is mainly consumed to compensate for the charge caused by the spread of the depletion layer. Expressed in terms of a circuit, the gate current is consumed to accumulate negative charge on the gate side of the gate-drain capacitance Cgd. As a result, the gate voltage does not change, and only the drain voltage increases rapidly. This is called the Miller period. The drain voltage is equal to the load voltage V L It rises to.

[0097] After the drain voltage increases, the gate voltage starts to decrease and the current starts to decrease at the same time. This is because the load voltage V L This is because the depletion layer expands enough to hold the charge, and Cgd is sufficiently charged, so that the gate current can be used to change the gate voltage, that is, to charge and discharge the gate-source capacitance Cgs. When the current drops to near zero (the device's breakdown voltage leakage level) and the voltage at the gate reaches the set off voltage, the turn-off is complete.

[0098] The time integral of the product of the drain current and drain voltage generated during this series of turn-off periods is the turn-off loss, which is part of the switching loss. To reduce the turn-off loss, it is necessary to shorten the Miller period by increasing the rate at which the drain voltage increases while a constant current IL is flowing. Reducing Cgd is generally an effective way to shorten the Miller period.

[0099] The SJ-SiC-MOSFET 101 has a feature that the extension direction of the first pillar region 21 and the second pillar region 30 constituting the SJ region 90 crosses the extension direction of the BPW region 31 of the MOSFET region 91. In the first half of the mirror period of the turn-off operation, a depletion layer begins to spread from the pn junction of the first pillar region 21 and the second pillar region 30 of the SJ region 90. At this time, the charge and discharge charge passes through the intersection region 92, flows through the BPW region 31 and the connection region 34, and reaches the source electrode 80 through the body region 32 and the body contact region 33. The current due to the charge and discharge charge is spatially concentrated in the intersection region 92 and the connection region 34. Here, the problem with SiC is that the mobility of holes is significantly smaller than the mobility of electrons. If the connection region 34 is not formed with a sufficiently low resistance, the charge and discharge charge cannot be discharged smoothly.

[0100] If holes are not smoothly released to the source electrode 80 during the turn-off operation, the following problems occur. First, the potentials of the connection region 34 and the BPW region 31 rise due to the influence of the drain voltage. Specifically, a delay in the release of holes causes an excess of positive charges, raising the potential. This causes a large electric field to be applied to the gate insulating film 50 between the gate electrode 60 and the BPW region 31 and the connection region 34, leading to destruction in the worst case. Even if destruction does not occur, the application of additional stress to the gate insulating film 50 reduces the life of the gate insulating film 50.

[0101] Therefore, in order to prevent the gate insulating film 50 from being destroyed or its lifespan from being shortened, it is necessary to form a current path from the intersection region 92 to the source electrode 80. First, the charge amount Q per unit area required for the complete depletion of the first pillar region 21 is tot (C / cm 2 ) is required. Q tot 2, is equal to the total amount of impurities in the second pillar region 30 near the intersection region 92. Therefore, assuming that the depth of the SJ region 90 is L, the occupancy rate of the width of the second pillar region 30 in the SJ pillar pitch d1 is β (β=(width of the second pillar region 30) / d1), and the impurity concentration is Na, Q tot is expressed by the following formula:

[0102]

number

[0103] Here, q is the elementary charge. The charge Qtot is the time t rise It is necessary to design the connection region 34, the BPW region 31 and other p-type regions so that the voltage generated in the p-type region near the intersection region 92 when the p-type region is discharged at 1 V, is at least 5 V or less.

[0104] t rise is the rate of voltage rise at turn-off (dV / dt) and the load voltage V L It depends on the SiC device used in power electronics equipment. Since the technology enabling high-speed operation has advanced, it is desirable to consider dV / dt up to about 100 kV / μs. In that case, t rise can be expressed by the following formula:

[0105]

number

[0106] According to equations (8) and (9), the average current density i ave (A / cm 2 )teeth,

[0107]

number

[0108] Furthermore, under the optimal design where equation (3) holds, the voltage V B When a voltage is applied, if the depth L of the SJ region 90 is approximately equal to the depth of the drift layer 20, the relationship between the electric field and the breakdown voltage is expressed by the following formula.

[0109]

number

[0110] This formula assumes that the drift layer 20 has a space charge of 0 and a dielectric breakdown field of half the Ec of SiC (∵Ec / 2=E xmax ) is regarded as an insulating film. This is because the effect of the potential distribution due to space charge can be ignored at a macroscopic level due to charge balance. From equations (2), (3), (4), and (11), Na can be expressed in terms of the withstand voltage, and the following equation is obtained.

[0111]

number

[0112] Here, N = Na, d = d1 × β / 2. By transforming equation (12), the following equation is obtained.

[0113]

number

[0114] Here, the load voltage V L is generally designed to be sufficiently lower than the avalanche voltage, so for example, V L =V B Assuming that the quotient is 1 / 2, we get the following equation:

[0115]

number

[0116] By eliminating NaL from equations (9) and (14), the average current density i ave is expressed by the following formula:

[0117]

number

[0118] Thus, the structural parameters (d1, β) and the physical constant ε S , and operating conditions (V L =V BThe average current density flowing at turn-off can be expressed by the following equation: Iave / 2, dV / dt=100 kV / μs. In the SJ-SiC-MOSFET 101, assuming current flow of this Iave, the voltage generated in the BPW region 31 and the connection region 34 can be designed to be sufficiently low, for example, to a value below 5 V. The sheet resistance, which is the resistance per area of ​​the current flow path of holes from the intersection region 92 to the source electrode 80, is R ptot (Ωcm 2 ), R ptot is dV / dt=100kV / μs, V L =V B The following equation must be satisfied under the condition of / 2.

[0119]

number

[0120] R ptot By modifying equation (16) with a focus on the above, we obtain the following equation.

[0121]

number

[0122] 10 is a graph of equations (15) and (17). In FIG. 10, the horizontal axis represents the pillar pitch d1 of the SJ region 90, and the vertical axis represents the average current density i ave and the sheet resistance R of the current path of the holes from the intersection region 92 to the source electrode 80 ptot This represents the assumption (dV / dt=100kV / μs, V L =V B / 2), the SJ-MOSFET optimally designed based on Fujihira’s theory has an average current density i ave From Figure 10, a current of i ave It can be seen that the smaller the pillar pitch d1 of the SJ region 90, the larger the transient current that flows. Assuming that d1 is about 3 μm, i ave is 1000A / cm 2In the SJ-SiC-MOSFET 101, the width 2d of the second pillar region 30 is set to 1 μm or more and 10 μm or less. In other words, the repetition period d1 of the second pillar region 30 is set to 2 μm or more and 20 μm or less. Under these conditions, R ptot is 3mΩcm 2 If designed as follows, the desired effect can be obtained.

[0123] R ptot First, the contact resistance between the body contact region 33 and the source electrode 80 via the first ohmic contact region 70 is 1×10 -5 Ωcm 2 More than 1×10 -4 Ωcm 2 Therefore, for example, if the area occupancy rate of the connection area between the first ohmic contact region 70 and the body contact region 33 in the active region is set to about 20%, the contact resistivity can be reduced to 1×10 -4 Ωcm 2 Even if we make a high assumption, the contact resistance is still 0.5mΩcm. 2 Then, R ptot The contribution to is small enough to be ignored.

[0124] Next, the internal resistance of the p-type region of the MOSFET region 91 will be described. Here, the p-type region refers to the body contact region 33, the body region 32, the connection region 34, the BPW region 31, and the second pillar region 30. A problem specific to SiC is that the p-type region in general has low hole mobility and high resistance. This point will be quantitatively discussed. First, the hole mobility is concentration dependent. Even if the acceptor is properly activated by active region annealing, the acceptor level is relatively deep from the valence band, so the ionization rate of the acceptor is low at room temperature. The ionization rate of the acceptor is the ratio of the acceptor impurity concentration to the actual formation of holes. The ionization rate is concentration dependent. Regarding the concentration dependence of the hole mobility and the ionization rate p / Na, Non-Patent Document 3 was referred to. Figure 11 shows the impurity concentration dependence of the hole mobility and the ionization rate p / Na used in the following calculations. The horizontal axis of Figure 11 is the acceptor impurity concentration Na (cm -3 ) and the vertical axis represents the hole mobility (cm) at 300K. 2 / Vs) and ionization rate p / Na. Based on the concentration dependence of the hole mobility and ionization rate p / Na shown in Figure 11, the resistivity ρ of the p-type region was calculated using ρ=1 / qμNaγ, and the result is shown in Figure 12. Here, γ is the activation rate. The horizontal axis of Figure 12 shows the acceptor impurity concentration Na (cm -3 ) and the vertical axis represents the resistivity ρ (Ωcm) of the p-type region.

[0125] Based on FIG. 11, the body contact region 33 and the body region 32 are R ptot First, the impurity concentration of the body contact region 33 is set to a low level of 5×10 18 cm -3 Assume that the thickness is set to 1 μm, and the area occupancy rate in the active region is set to a low 20%. Even with such strict assumptions, the sheet resistance value in the vertical direction of the body contact region 33 is calculated to be 0.38 mΩ cm based on the resistivity in FIG. 2 Next, the impurity concentration of the body region 32 is set to a low value of 5×10 17 cm -3Assume that the thickness is 2 μm and the area occupancy rate in the active region is 80%. The sheet resistance value in the vertical direction of the body contact region 33 is 0.63 mΩ cm, calculated based on the resistivity in FIG. 2 This is also small and negligible. In addition, the BPW region 31 is adjacent to the connection region 34 and has an impurity concentration higher than that of the body region 32, so it does not contribute to vertical conduction and R ptot The contribution to is negligible.

[0126] Therefore, R ptot The main factor affecting is the resistance of the connection region 34. The length of the connection region 34 in the depth direction is assumed to be a relatively long value of 3 μm. Based on this assumption, in the connection region 34, the generated voltage is 5 V and the resistivity is 3 mΩ cm 2 Impurity concentration Na(cm -3 The relationship between the area occupancy rate in the xy plane and the resistivity was calculated based on the resistivity calculation results in Figure 12. The results are shown in Figure 13.

[0127] To reduce the JFET resistance, a certain amount of current must pass through the JFET region 22 above the second pillar region 30. When the ratio between the width of the second pillar region 30 and the width of the first pillar region 21 is 1:1, the area ratio of the second pillar region 30 to the SJ region 90 in the xy plane is 50%. In that case, if the JFET region 22 can be formed in more than half of the area in the xy plane of the upper region of the second pillar region 30, the effect of this technology can be obtained to a minimum. In that case, the area occupancy rate of the connection region 34 in the xy plane is 25% or less. Therefore, from FIG. 13, the impurity concentration of the connection region 34 is 4×10 17 cm -3or more. To more reliably enjoy the effects of the present technology, it is desirable to further reduce the area occupancy rate of the connection region 34 in the xy plane. By reducing the area occupancy rate of the connection region 34, the area occupancy rate of the JFET region 22 increases. As a result, the JFET resistance in the upper part of the second pillar region 30 is reduced, and the channel width density that contributes to the flow of the on-current increases. For example, if the area occupancy rate of the connection region 34 is set to 10% or less, the effects of the present technology can be more significantly obtained. In that case, the impurity concentration of the connection region 34 is 2×10 18 cm -3 Anything above that is fine.

[0128] The discussion so far has mainly been about the conditions for the connection region 34 that allow a current of an average value obtained by dividing the discharge charge of the second pillar region 30 by the voltage rise time to flow smoothly. On the other hand, the current caused by the spread of the depletion layer in the actual SJ region 90 is not as simple as described above, but is nonlinear and complex. This is because the depletion layer capacitance of a semiconductor is a variable capacitance that depends on the applied voltage. Of course, the above discussion of the average value can also describe the rough behavior of the switching characteristics of the MOSFET, and the connection region 34 can be designed based on that. However, more detailed calculations are necessary to further improve performance.

[0129] Therefore, the current flowing during switching in a pn diode structure with d1 = 3 μm was calculated using TCAD. Figure 14 shows the pn diode structure used in the TCAD calculation. This diode structure has a p-type pillar region 71 and an n-type pillar region 72. Furthermore, a region in which the hole mobility is locally reduced (hereinafter referred to as the mobility reduction region) 73 is provided above the p-type pillar region 71 in order to simulate the connection region 34. The hole mobility of the mobility reduction region 73 was calculated using μ hjoint and the hole mobility of the other p-type pillar regions 71 is expressed as μ h This is expressed as:

[0130] Figure 15 shows the time waveform of the current flowing through the cathode when the cathode voltage is increased from 0V to 1200V at dV / dt = 100kV / μs. The time it takes for the voltage to increase is 1.2×10 -8 s, the cathode current is concentrated in the first half of the voltage rise. This is because the depletion layer width is small at the beginning of the depletion layer expansion in the SJ region 90, so the depletion layer capacitance is the largest, but as the depletion layer expands, the depletion layer capacitance decreases. The peak value of the cathode current is 3250 A / cm 2 As a result, the current flowing is two to three times that when d1=3 μm in FIG.

[0131] 16 shows the time waveform of the voltage difference between immediately above and immediately below the mobility reducing region 73. In FIG. -8 The region after s shows the voltage rise due to the entire mobility reduction region 73 being depleted, so it need not be taken into consideration. ptot =3mΩcm 2 If the resistance R of the mobility reduction region 73 is less than this, a sufficient effect can be expected. pJoint is 3mΩcm 2 It can be seen that even if the voltage is less than 5 V, a voltage exceeding 5 V can be generated momentarily. This is because the cathode current is concentrated during the period when the depletion layer begins to expand, when the depletion layer capacitance is high. pJoint to one-third, i.e., 1 mΩ cm 2 If the R pJoint is reduced to less than one tenth, i.e. 0.3 mΩ cm 2 By doing so, the generated voltage can be kept below 5V for the entire period, allowing the full benefits of this technology to be obtained.

[0132] 12, the impurity concentration Na (cm -3 ) and the area occupancy rate in the xy plane, 2 , 0.3mΩcm 2 The results of the calculation for the case of R are shown in Figure 17.ptot =1mΩcm 2 In order to achieve this, when the area occupancy of the connection region 34 is 25%, the acceptor concentration of the connection region 34 must be 4×10 18 cm -3 In addition, when the area occupancy rate of the connection region 34 is 10%, the acceptor concentration of the connection region 34 is set to 3×10 19 cm -3 Also, R ptot =0.3mΩcm 2 In order to achieve this, when the area occupancy of the connection region 34 is 25%, the acceptor concentration of the connection region 34 must be 4×10 19 cm -3 In addition, when the area occupancy rate of the connection region 34 is 10%, the acceptor concentration of the connection region 34 is set to 1×10 20 cm -3 It would be better to change it to:

[0133] <A-3-4.ターンオン> Next, we will discuss the turn-on of the switching operation. Turn-on occurs when the load voltage V L When the gate voltage is switched from a state where n is applied to a voltage above the threshold, such as 15 V, an n-channel is induced and the MOSFET turns on. At this time, the drain current increases rapidly, and then the voltage drops to near the on-voltage.

[0134] The transition of the element state during turn-on will be described. First, the current I L The load voltage V generated by L is applied to the drain electrode 83. The gate voltage starts to rise as the gate terminal is charged by the gate driver. When the gate voltage exceeds the threshold voltage Vth, the resistance of the channel region starts to decrease and the drain current starts to increase. At this time, the drain voltage is V L Since the MOSFET operates in the saturation region, the drain current varies depending on the gate voltage. The drain voltage is V LSince it remains unchanged, the increase in the gate voltage at this time, in terms of circuit representation, is determined by the rate at which positive charge accumulates on the gate side of the gate-source capacitance Cgs. The drain current is the current I flowing through the load L and continues to rise until

[0135] After the increase in the drain current, if the gate current continues to flow, the drain voltage begins to decrease. This is because the charging of positive charge by the gate current is consumed to compensate for the narrowing of the depletion layer of the MOSFET. In terms of circuit representation, it is because the gate current is consumed for the discharge of Cgd of the gate-drain capacitance. During this period, the gate voltage does not change, and similar to the turn-off moment, this is called the mirror period. By charging positive charge to the gate terminal of Cgd during the mirror period, the space charge accumulated in the depletion layer of the drift region can be compensated. As a result, the drain voltage begins to decrease. When the drain voltage has decreased sufficiently, the operating region of the MOSFET changes from the saturation region to the linear region. Thereby, the gate voltage further rises, and finally, by increasing to the specified value, the drain voltage decreases to the on-voltage, and the turn-on is completed.

[0136] The time integral of the product of the drain current and the drain voltage generated during these series of turn-on periods is the turn-on loss among the switching losses. In order to reduce this turn-on loss, it is necessary to shorten the mirror period, that is, to increase the rate of decrease of the drain voltage in the state where a constant current I L is flowing. Generally, reducing Cgd is effective for shortening the mirror period. This point is the same as at turn-off. Therefore, although the sign of dV / dt, which is the rate of change of voltage at turn-on, is opposite to that at turn-off, the same discussion can be applied. Therefore, since the conditions required for the connection region 34 are the same as at turn-off, the details are omitted. This concludes the explanation of the operation of the SJ-MOSFET.

[0137] <A-4. Modification Example> 18 is a perspective view of a unit cell of an SJ-SiC-MOSFET 101A according to a first modified example of the first embodiment. The SJ-SiC-MOSFET 101A differs from the SJ-SiC-MOSFET 101 in that a p-type connection region 34 is provided not only for the BPW region 31 above the second pillar region 30 but also for the BPW region 31 above the first pillar region 21. That is, the BPW region 31 above the first pillar region 21 is connected to the body region 32 via the connection region 34. This allows a current flowing to the BPW region 31 due to a fluctuation in the electric field in the n-type first pillar region 21 to flow separately from the charging and discharging of the SJ pillar, thereby reducing the electric field applied to the gate insulating film 50.

[0138] Fig. 19 is a plan view of the SJ-SiC-MOSFET 101A in an xy plane passing through the intersection region 92 between the BPW region 31 and the second pillar region 30. As shown in Fig. 19, the connection region 34 is formed in contact not only with the intersection region 92 of the BPW region 31 but also with portions other than the intersection region 92.

[0139] Fig. 20 is a cross-sectional view of the SJ-SiC-MOSFET 101A taken along A1-A1' in Fig. 19. Fig. 20 is similar to Fig. 5. Fig. 21 is a cross-sectional view of the SJ-SiC-MOSFET 101A taken along A2-A2' in Fig. 19.

[0140] Fig. 22 is a perspective view of a unit cell of an SJ-SiC-MOSFET 101B according to a second modified example of the first embodiment. Fig. 23 is a plan view of the SJ-SiC-MOSFET 101B in an xy plane passing through an intersection region 92 between the BPW region 31 and the second pillar region 30. Fig. 24 is a cross-sectional view of the SJ-SiC-MOSFET 101B taken along A1-A1' in Fig. 23. Fig. 25 is a cross-sectional view of the SJ-SiC-MOSFET 101B taken along A2-A2' in Fig. 23.

[0141] The SJ-SiC-MOSFET 101B differs from the SJ-SiC-MOSFET 101 in that the connection region 34 connecting the body region 32 and the BPW region 31 is provided over the entirety of one side surface of each trench 55. In Fig. 22 to Fig. 25, a configuration is illustrated in which the connection region 34 is provided on the side surface of each trench 55 on the negative side in the x-axis direction.

[0142] According to this configuration, the channel width density is reduced, so the channel resistance increases, but the saturation current density is reduced instead, so the short circuit resistance increases. Also, the connection resistance to the second pillar region 30 is reduced, so the electric field applied to the gate insulating film 50 is reduced. Furthermore, the increase in JFET resistance is minimized, and the current path above the second pillar region 30 can be utilized, so the effect of this technology can be fully enjoyed.

[0143] Fig. 26 is a perspective view of a unit cell of an SJ-SiC-MOSFET 101C according to a third modified example of the first embodiment. Fig. 27 is a plan view of the SJ-SiC-MOSFET 101C in an xy plane passing through an intersection region 92 between the BPW region 31 and the second pillar region 30. Fig. 28 is a cross-sectional view of the SJ-SiC-MOSFET 101C taken along A1-A1' in Fig. 27. Fig. 29 is a cross-sectional view of the SJ-SiC-MOSFET 101C taken along A2-A2' in Fig. 27.

[0144] SJ-SiC-MOSFET 101C differs from SJ-SiC-MOSFET 101 in that trenches 55 having connection regions 34 provided over the entire side surfaces on both sides and trenches 55 having no connection regions 34 except in the vicinity of intersection region 92 are arranged alternately. In other words, for some trenches 55, connection regions 34 are formed in contact with the entire side surfaces on both sides of trench 55, and for other trenches 55, connection regions 34 are formed only at the intersection between BPW region 31 below trench 55 and second pillar region 30.

[0145] According to this configuration, since the channel width density decreases in the same way as in the SJ-SiC-MOSFET 101B, the channel resistance increases. However, instead, the saturation current density decreases, so the short-circuit withstand increases. Also, since the connection resistance to the second pillar region 30 decreases, the electric field applied to the gate insulating film 50 is reduced. Furthermore, the increase in the JFET resistance is minimized, and the current path above the second pillar region 30 can also be utilized, so the effects of this technology can be fully enjoyed.

[0146] In the SJ-SiC-MOSFET 101C, the trenches 55 covered by the connection regions 34 on both sides do not contribute to the static characteristics of the transistor. Therefore, the gate electrode 60 formed in the trench 55 may be left floating without being connected to the gate wiring 82. Also, the gate electrode 60 formed in the trench 55 may be connected to the source electrode 80 to form a dummy trench gate. In that case, since the input capacitance of the gate as seen in the entire MOSFET can be approximately halved, the switching speed that can be operated with the same gate driver, that is, dV / dt, dI / dt, etc., can be increased, and a MOSFET that is easy to operate at high speed can be realized.

[0147] In the SJ-SiC-MOSFET 101C, the repetition period of the trenches 55 does not have to be constant at 1:1, and may be, for example, 2:3 or 1:5. By changing the repetition period, the trade-off between the input capacitance of the gate and the on-resistance can be adjusted, and an optimal form may be provided.

[0148] Figures 30 and 31 are cross-sectional views of the SJ-SiC-MOSFET 101D of the fourth modification of Embodiment 1. Figure 30 is a cross-sectional view in the xz plane passing through the first pillar region 21. Figure 31 is a cross-sectional view in the xz plane passing through the second pillar region 30. The SJ-SiC-MOSFET 101D is different from the SJ-SiC-MOSFET 101B of the second modification in that the first pillar region 21 and the second pillar region 30 are not directly connected to the BPW region 31 but are connected via the connection region 34.

[0149] <A-5. Effects> An SJ-SiC-MOSFET 101 which is a silicon carbide semiconductor device according to the first embodiment includes an n-type silicon carbide substrate 10, an SJ region 90 made of silicon carbide, and a MOSFET region 91 provided on an upper surface of the SJ region 90. The silicon carbide substrate 10 has a first main surface and a second main surface which face each other. The SJ region 90 is provided on the first main surface of the silicon carbide substrate 10. The SJ region 90 extends in the x-axis direction which is a first direction parallel to the first main surface, and includes a plurality of n-type first pillar regions 21 and a plurality of p-type second pillar regions 30 which are alternately arranged in the y-axis direction which is a second direction parallel to the first main surface and perpendicular to the first direction. The MOSFET region 91 includes a plurality of BPW regions 31 made of p-type silicon carbide, a plurality of gate electrodes 60, a plurality of JFET regions 22 made of n-type silicon carbide, a plurality of body regions 32 made of p-type silicon carbide, a plurality of body contact regions 33 made of p-type silicon carbide, a source region 23 which is a plurality of impurity regions made of n-type silicon carbide, and at least one connection region 34 made of p-type silicon carbide. Each BPW region 31 extends in the y-axis direction, is arranged in the x-axis direction with a second repeat period d2 shorter than the first repeat period d1 which is the repeat period of the second pillar region 30, and is connected to the second pillar region 30. Each gate electrode 60 is provided in each trench 55 provided in the y-axis direction on each BPW region 31 via a gate insulating film 50. Each JFET region 22 extends in the y-axis direction between two adjacent BPW regions 31 and between two adjacent trenches 55. Each body region 32 is provided on and in contact with each JFET region 22. Each body contact region 33 is provided on and has a lower resistivity than each body region 32. A source region 23 is provided on and in contact with each trench 55 and each body contact region 33 on each body region 32. At least one connection region 34 is in contact with at least one JFET region 22 and connects at least one BPW region 31 and at least one body region 32. The SJ-SiC-MOSFET 101 includes a source electrode 80 that is an upper surface electrode provided on each body contact region 33, and a drain electrode 83 that is a lower surface electrode provided on the second main surface of the silicon carbide substrate 10.With the above configuration, a low-resistance contact to the second pillar region 30 is realized, variations in breakdown voltage are suppressed, and channel resistance and JFET resistance are reduced.

[0150] <B. Embodiment 2> <B-1. Configuration> FIG. 32 is a perspective view of a unit cell of the SJ-SiC-MOSFET 102 according to Embodiment 2. The SJ-SiC-MOSFET 101 of Embodiment 1 was a trench-type MOSFET, while the SJ-SiC-MOSFET 102 is a planar-type MOSFET. That is, the SJ-SiC-MOSFET 102 applies the characteristic configuration of the SJ-SiC-MOSFET 101 described in Embodiment 1 to a planar-type MOSFET.

[0151] In the SJ-SiC-MOSFET 102, only the configuration of the MOSFET region 91 is different from that of the SJ-SiC-MOSFET 101. Hereinafter, the MOSFET region 91 of the SJ-SiC-MOSFET 102 will be described.

[0152] The p-type body region 32 and the n-type JFET region 22 are alternately arranged on the SJ region 90. The body region 32 extends along the y-axis direction and a plurality of them are arranged at a repetition period d21 along the x-axis direction. In Embodiment 1, the repetition period d2 of the BPW region 31 was referred to as the second repetition period, while in Embodiment 2, the repetition period d21 of the body region 32 is referred to as the second repetition period. The repetition period d21 of the body region 32 is shorter than the repetition period d1 of the second pillar region 30. The JFET region 22 is arranged between the body regions 32. The n-type source region 23 is formed on the surface layer of the body region 32. The p-type body contact region 33 reaches the body region 32 through the source region 23 from the upper surface of the source region 23. The surface layer of the body region 32 sandwiched between the JFET region 22 and the source region 23 is defined as the channel region. The gate electrode 60 is formed on the channel region and the JFET region 22 via the gate insulating film 50. The above is the configuration of the MOSFET region 91.

[0153] The gate electrode 60 is covered by the interlayer insulating film 51 and insulated from the source electrode 80. Contact holes are formed in the gate insulating film 50 and the interlayer insulating film 51. The source electrode 80 is formed inside the contact hole and on the interlayer insulating film 51. The source electrode 80 makes ohmic contact with the body contact region 33 and the source region 23 via the first ohmic contact region 70 inside the contact hole.

[0154] Unlike the SJ-SiC-MOSFET101, the MOSFET region 91 of the SJ-SiC-MOSFET102 does not include the trench 55, the BPW region 31, and the connection region 34. The relatively high-concentration body region 32 is directly connected to the second pillar region 30. The intersection of the body region 32 and the second pillar region 30 becomes the intersection region 92. Therefore, the surface resistance R in the hole conduction path from the intersection region 92 to the source electrode 80 ptot is reduced and suppressed to a small value. Thus, the effects of the present technology can be enjoyed to a certain extent without adding a special structure.

[0155] <B-2. Manufacturing Method> The manufacturing method of the SJ-SiC-MOSFET102 is generally the same as the manufacturing method of the SJ-SiC-MOSFET101 described in Embodiment 1. After forming the SJ region 90 on the silicon carbide substrate 10, it is the same as Embodiment 1 until further growing an n-type epi region. After that, although the structure is different, forming the body region 32, the JFET region 22, the source region 23, and the body contact region 33 by a photolithography process, an ion implantation process, and an activation annealing process is also the same as Embodiment 1. There are no processes for forming the trench etching, the BPW region 31, and the connection region 34. After that, a high-quality gate insulating film 50 is formed by thermal oxidation. The subsequent processes are the same as Embodiment 1.

[0156] <B-3. Modification Example> 33 is a perspective view of a unit cell of an SJ-SiC-MOSFET 102A according to a first modified example of the second embodiment. The SJ-SiC-MOSFET 102A differs from the SJ-SiC-MOSFET 102 in that the body contact region 33 penetrates the body region 32 to reach the SJ region 90. This allows the body contact region 33 to also function as the connection region 34 of the first embodiment, which connects the second pillar region 30 and the body region 32. The second pillar region 30 and the body region 32 are connected using the body contact region 33 having a high concentration of p-type impurities, thereby reducing the sheet resistance R in the current path for holes from the second pillar region 30 to the source electrode 80. ptot As a result, the electric field applied to the gate insulating film 50 can be reduced.

[0157] The impurity concentration of the body contact region 33 may be the same or different between the lower portion and the upper portion in contact with the SJ region 90.

[0158] 34 is a perspective view of a unit cell of an SJ-SiC-MOSFET 102B according to a second modification of the second embodiment. In the SJ-SiC-MOSFET 102B, the body region 32 and the second pillar region 30 are not connected. On the other hand, the body contact region 33 penetrates the body region 32, protrudes from the lower surface of the body region 32, and is connected to the second pillar region 30 to form an intersection region 92. That is, the lower part of the body contact region 33 protruding from the lower surface of the body region 32 has the function of the connection region 34 in the first embodiment.

[0159] The lower part of the body contact region 33 is striped and adjacent to the JFET region 22. With this configuration, the body region 32 and the second pillar region 30 are connected by the body contact region 33 having a high impurity concentration, so that switching loss can be reduced. In addition, the lower part of the body contact region 33 having the function of the connection region 34 is adjacent to the JFET region 22, so that the JFET resistance can be reduced and the on-resistance can be further reduced. The impurity concentration of the body contact region 33 may be the same or different between the lower part and the upper part in contact with the JFET region 22.

[0160] 35 is a perspective view of a unit cell of an SJ-SiC-MOSFET 102C according to a third modification of the second embodiment. In the SJ-SiC-MOSFET 102C, the body contact region 33 protrudes from the lower surface of the body region 32 only in the upper part of the second pillar region 30, and is connected to the second pillar region 30 to form an intersection region 92. In the upper part of the first pillar region 21, the body contact region 33 does not protrude from the lower surface of the body region 32. In other respects, the SJ-SiC-MOSFET 102C has a similar configuration to the SJ-SiC-MOSFET 102B.

[0161] According to this configuration, the area occupancy rate of the JFET region 22 in the xy plane is larger than that of the SJ-SiC-MOSFET 102B, so that the on-resistance can be reduced. Also, as in the SJ-SiC-MOSFET 102B, the body region 32 and the second pillar region 30 are connected by the body contact region 33 with a high impurity concentration, so that R ptot The impurity concentration of the body contact region 33 may be the same or different between the lower portion and the upper portion in contact with the JFET region 22.

[0162] In the description of the first and second embodiments, the MOSFET regions 91 and the SJ regions 90 are connected in all the intersection regions 92. However, when viewed uniformly and macroscopically throughout the active region, ptot As long as the on-resistance is kept low, the MOSFET regions 91 and the SJ regions 90 do not need to be connected in all of the intersection regions 92, and it is sufficient that they are connected directly or via the connection regions 34 or the body contact regions 33 in, for example, 80% or more of the intersection regions 92. In this case, the on-resistance may be further reduced by, for example, forming a JFET region 22 in the intersection region 92 where the MOSFET region 91 and the SJ region 90 are not connected.

[0163] In Embodiment 1 and Embodiment 2, the SJ-SiC-MOSFET has been described as an example of a silicon carbide semiconductor device having an SJ structure and a MOSFET structure. However, the technology of the present disclosure can also be applied to an IGBT in addition to a MOSFET. In this case, an emitter electrode, a collector electrode, and an emitter region are used instead of a source electrode, a drain electrode, and a source region. Also, a p-type collector layer is provided between the silicon carbide substrate 10 and the drain electrode.

[0164] <B-4. Effect> The SJ-SiC-MOSFET 102, which is a silicon carbide semiconductor device of Embodiment 2, includes an n-type silicon carbide substrate 10, an SJ region 90 made of silicon carbide, and a MOSFET region 91 provided on the upper surface of the SJ region 90. The silicon carbide substrate 10 has a first main surface and a second main surface facing each other. The SJ region 90 is provided on the first main surface of the silicon carbide substrate 10. The SJ region 90 extends in the x-axis direction, which is a first direction parallel to the first main surface, and includes a plurality of n-type first pillar regions 21 and a plurality of p-type second pillar regions 30 alternately arranged in the y-axis direction, which is a second direction parallel to the first main surface and perpendicular to the first direction. The MOSFET region 91 includes a plurality of body regions 32 made of p-type silicon carbide, a plurality of JFET regions 22 made of n-type silicon carbide, a plurality of source regions 23, which are impurity regions made of n-type silicon carbide, a plurality of body contact regions 33 made of p-type silicon carbide, and a plurality of gate electrodes 60 provided via a gate insulating film 50 on each body region 32 between each source region 23 and each JFET region 22. Each body region 32 extends in the y-axis direction and is arranged with a second repetition period d21 shorter than the first repetition period d1 of the second pillar region 30 in the x-axis direction, and is connected to each second pillar region. Each JFET region 22 is provided between each body region 32. Each source region 23 is provided on the surface layer of each body region 32. Each body contact region 33 reaches each body region 32 from the upper surface of each source region 23 through each source region 23 and has a lower resistivity than each body region 32. The plurality of gate electrodes 60 are provided via a gate insulating film 50 on each body region 32 between each source region 23 and each JFET region 22. The SJ-SiC-MOSFET 102 includes a source electrode 80, which is an upper surface electrode provided on the plurality of body contact regions 33, and a drain electrode 83, which is a lower surface electrode formed on the second main surface of the silicon carbide substrate 10. With the above configuration, a low-resistance contact to the second pillar region 30 is realized, variations in breakdown voltage are suppressed, and channel resistance and JFET resistance are reduced.

[0165] <C. Embodiment 3> In the present embodiment, the silicon carbide semiconductor devices according to the above-mentioned first and second embodiments are applied to a power converter. Although application of the silicon carbide semiconductor devices according to the first and second embodiments is not limited to a specific power converter, hereinafter, as a third embodiment, a case in which the silicon carbide semiconductor devices according to the first and second embodiments are applied to a three-phase inverter will be described.

[0166] FIG. 36 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0167] The power conversion system shown in Fig. 36 includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be configured from various sources. For example, the power supply 100 can be configured from a DC system, a solar cell, or a storage battery, or it can be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 can also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0168] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 36, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.

[0169] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as a motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.

[0170] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and free wheel diodes (not shown), and converts DC power supplied from the power source 100 into AC power by switching the switching elements, and supplies the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit, and can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element. The silicon carbide semiconductor device according to either of the above-mentioned first and second embodiments is applied to each switching element of the main conversion circuit 201. Two switching elements of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0171] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 described later, the drive circuit 202 outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0172] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) for each switching element of the main conversion circuit 201 to be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0173] In the power conversion device according to the present embodiment, the silicon carbide semiconductor devices according to the first and second embodiments are applied as switching elements of main conversion circuit 201, and therefore reliability and conversion efficiency are improved.

[0174] In the present embodiment, an example in which the silicon carbide semiconductor device according to the first and second embodiments is applied to a two-level three-phase inverter has been described, but the application of the silicon carbide semiconductor device according to the first and second embodiments is not limited to this, and the silicon carbide semiconductor device according to the first and second embodiments can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is described, but the silicon carbide semiconductor device according to the first and second embodiments can be applied to a three-level or multi-level power conversion device, and when power is supplied to a single-phase load, the silicon carbide semiconductor device according to the first and second embodiments can be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the silicon carbide semiconductor device according to the first and second embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0175] Furthermore, the power conversion device to which the silicon carbide semiconductor device according to the first and second embodiments is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.

[0176] In addition, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted. The above description is an example in all respects. It is understood that countless modified examples not illustrated can be assumed. [Explanation of symbols]

[0177] 10 silicon carbide substrate, 20 drift layer, 21 first pillar region, 22 JFET region, 23 source region, 30 second pillar region, 31 BPW region, 32 body region, 33 body contact region, 34 connection region, 50 gate insulating film, 51 interlayer insulating film, 55 trench, 60 gate electrode, 70 first ohmic contact region, 71 p-type pillar region, 72 n-type pillar region, 73 mobility reduction region, 80 source electrode, 81 source pad, 82 gate wiring, 83 drain electrode, 90 SJ region, 91 MOSFET region, 92 intersection region, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

1. an n-type silicon carbide substrate having a first main surface and a second main surface opposed to each other; an SJ region made of silicon carbide provided on the first main surface of the silicon carbide substrate; a MOSFET region provided on an upper surface of the SJ region, the SJ region includes a plurality of n-type first pillar regions and a plurality of p-type second pillar regions extending in a first direction parallel to the first main surface and alternately arranged in a second direction parallel to the first main surface and perpendicular to the first direction, The MOSFET region is a plurality of BPW regions made of p-type silicon carbide, the BPW regions extending in the second direction and arranged in the first direction with a second repeating period shorter than a first repeating period which is a repeating period of the second pillar regions; a plurality of gate electrodes provided in each trench provided in the second direction on each of the BPW regions via a gate insulating film; Silicon carbide semiconductor device.

2. the plurality of BPW regions are connected to the second pillar region; The silicon carbide semiconductor device according to claim 1 .

3. The MOSFET region is a plurality of JFET regions made of n-type silicon carbide extending in the second direction between two adjacent ones of the BPW regions and between two adjacent ones of the trenches; a plurality of body regions made of p-type silicon carbide provided on and in contact with each of the JFET regions; at least one connection region made of p-type silicon carbide contacting at least one of the JFET regions and connecting at least one of the BPW regions and at least one of the body regions; The silicon carbide semiconductor device according to claim 1 .

4. The MOSFET region is a plurality of body contact regions each made of p-type silicon carbide having a lower resistivity than each of the body regions and provided on each of the body regions; a plurality of impurity regions made of n-type silicon carbide provided on each of the body regions in contact with each of the trenches and each of the body contact regions, a top electrode provided on each of the body contact regions; a lower surface electrode provided on the second main surface of the silicon carbide substrate. The silicon carbide semiconductor device according to claim 3 .

5. Each of the second pillar regions and each of the BPW regions are directly connected to each other. The silicon carbide semiconductor device according to claim 1 .

6. the at least one connection region is a plurality of connection regions contacting each of the JFET regions and connecting each of the BPW regions and each of the body regions; Each of the second pillar regions and each of the BPW regions are connected via each of the connection regions. The silicon carbide semiconductor device according to claim 3 .

7. the at least one connection region is a plurality of connection regions contacting each of the JFET regions and connecting each of the BPW regions and each of the body regions; the plurality of connection regions include a connection region provided on each of the first pillar regions; The silicon carbide semiconductor device according to claim 3 .

8. the at least one connection region is a plurality of connection regions contacting each of the JFET regions and connecting each of the BPW regions and each of the body regions; Each of the connection regions is provided in contact with the entire side surface on one side of each of the trenches. The silicon carbide semiconductor device according to claim 3 .

9. the at least one connection region is a plurality of connection regions contacting each of the JFET regions and connecting each of the BPW regions and each of the body regions; The plurality of connection regions are provided in contact with the entire side surfaces on both sides of the trench for some of the trenches, and are provided only at an intersection between the BPW region and the second pillar region in a lower portion of the trench for other of the trenches. The silicon carbide semiconductor device according to claim 3 .

10. each of the second pillar regions and each of the BPW regions is directly connected to each other at 80% or more of the intersections between the second pillar regions and the BPW regions; The silicon carbide semiconductor device according to claim 1 .

11. the at least one connection region is a plurality of connection regions contacting each of the JFET regions and connecting each of the BPW regions and each of the body regions; the second pillar regions and the BPW regions are connected to each other via the connection regions at 80% or more of the intersections between the second pillar regions and the BPW regions; The silicon carbide semiconductor device according to claim 3 .

12. The n-type impurity concentration of each of the JFET regions is higher than the n-type impurity concentration of each of the first pillar regions; The silicon carbide semiconductor device according to claim 3 .

13. an area occupancy rate of the at least one connection region in a plane parallel to the first main surface is 25% or less; The silicon carbide semiconductor device according to claim 3 .

14. The p-type impurity concentration of the at least one connection region is 4×10 １７ cm －３ That's all.

14. The silicon carbide semiconductor device according to claim 3, 6, 7, 8, 9, 11, 12, or 13.

15. an n-type silicon carbide substrate having a first main surface and a second main surface opposed to each other; an SJ region made of silicon carbide provided on the first main surface of the silicon carbide substrate; a MOSFET region provided on an upper surface of the SJ region, the SJ region includes a plurality of n-type first pillar regions and a plurality of p-type second pillar regions extending in a first direction parallel to the first main surface and alternately arranged in a second direction parallel to the first main surface and perpendicular to the first direction, The MOSFET region is a plurality of body regions extending in the second direction and arranged in the first direction at a second repeating period that is shorter than a first repeating period that is a repeating period of the second pillar regions, the body regions being made of p-type silicon carbide; Silicon carbide semiconductor device.

16. the plurality of body regions are connected to each of the second pillar regions; The silicon carbide semiconductor device according to claim 15 .

17. the MOSFET region includes a plurality of JFET regions made of n-type silicon carbide provided between the body regions; The silicon carbide semiconductor device according to claim 15 or 16.

18. The MOSFET region is a plurality of impurity regions made of n-type silicon carbide provided in a surface layer of each of the body regions; a plurality of body contact regions made of p-type silicon carbide having a lower resistivity than each of the body regions, the body contact regions extending from the upper surface of each of the impurity regions through each of the impurity regions to reach each of the body regions; a plurality of gate electrodes provided on each of the body regions between each of the impurity regions and each of the JFET regions via a gate insulating film; a top electrode provided on the body contact regions; a lower surface electrode provided on the second main surface of the silicon carbide substrate. The silicon carbide semiconductor device according to claim 17 .

19. each of the second pillar regions and each of the body regions are directly connected to each other; The silicon carbide semiconductor device according to any one of claims 15 to 18.

20. each of the body contact regions extends through each of the body regions and contacts each of the second pillar regions; Each of the second pillar regions and each of the body regions are connected via each of the body contact regions. The silicon carbide semiconductor device according to claim 18 .

21. the second pillar regions and the body regions are directly connected to each other at 80% or more of the intersections between the second pillar regions and the body regions; 21. The silicon carbide semiconductor device according to claim 3, 4, 6 to 9, 11 to 13, or 15 to 20.

22. the second pillar regions and the body regions are connected to each other via the body contact regions at 80% or more of the intersections between the second pillar regions and the body regions; The silicon carbide semiconductor device according to claim 4 , 18 , or 20 .

23. A main conversion circuit having the silicon carbide semiconductor device according to any one of claims 1 to 22, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; A control circuit that outputs a control signal to the drive circuit to control the drive circuit. Power conversion equipment.

Images