Solid-state imaging device, driving method for solid-state imaging device, and electronic device

Abstract

To provide a solid-state image sensor, a driving method thereof, and an electronic device, which can surely prevent the generation of inverted video noise even when there are variations in elements for each row, and can achieve high image quality.SOLUTION: In each column, a pixel signal monitoring unit 43 fixes a conversion code of an AD conversion unit of an ADC 41 to a predetermined code when the signal level LVRST of a read reset signal VRST 11 of a pixel signal VSL read to a vertical signal line LSGN11 exceeds a preset reference voltage Vref (as an example, when the signal level LVRST of the read reset signal VRST11 is lowered by a second reference voltage Vref2).SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device, a driving method for a solid-state imaging device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Complementary Metal Oxide Semiconductor (CMOS) image sensors are in practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate electric charges. CMOS image sensors are widely used as part of various electronic devices, such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones.

[0003] CMOS image sensors have a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel, and the mainstream readout method is the column-parallel output type, which selects a row in the pixel array and reads out the pixels simultaneously in the column direction.

[0004] Incidentally, an example of the pixel configuration of a CMOS image sensor is a four-transistor (4Tr) pixel having, for example, one photodiode (photoelectric conversion element), a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element, and a selection transistor as a selection element.

[0005] The transfer transistor is selected by a control signal TG during a predetermined transfer period to become conductive, and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode to the floating diffusion FD. The reset transistor is selected by a control signal RST during a predetermined reset period to become conductive, and resets the floating diffusion FD to the potential of the power supply line. The selection transistor is selected and turned on during read scanning, which causes the source follower transistor to output the column output read signal Pixout, which is a voltage signal obtained by converting the charge of the floating diffusion FD, to the vertical signal line LSGN.

[0006] For example, in a read scan period, after the floating diffusion FD is reset to, for example, the potential of the power supply line during the reset period, the charge of the floating diffusion FD is converted into a voltage signal by the source follower transistor and output to the vertical signal line LSGN as a read reset signal (voltage) VRST. Then, during a predetermined transfer period, the charge (electrons) photoelectrically converted and accumulated in the photodiode is transferred to the floating diffusion FD. Then, the charge in the floating diffusion FD is converted into a voltage signal by the source follower transistor and output to the vertical signal line LSN1 as a readout signal (voltage) VSIG. The output signal of the pixel is processed as a differential signal (VSIG-VRST).

[0007] However, in a CMOS image sensor having such pixels, when very strong light (high brightness light) is incident on one or more pixels, the pixel output becomes saturated, causing a high brightness signal to be erroneously output as a low brightness signal, resulting in the disadvantage of so-called inverted video noise (so-called sunspots) being output.

[0008] This problem will be described in further detail with reference to FIGS. FIG. 1 is a diagram for explaining a readout reset signal and a readout signal as pixel signals read out from a pixel, and for explaining the problem of the formation of a blocked-up image when high-luminance light is incident. FIG. 2 is a diagram showing an example of a blocked-up black image formed when high-luminance light is incident on a pixel. FIG. 3 is a diagram showing an example of the configuration of a pixel signal readout circuit system in which a clamp circuit is disposed to suppress black level fluctuations that are a cause of the occurrence of blocked-up pixels. FIG. 4 is a diagram for explaining the principle of suppressing fluctuations in the black level by the clamp circuit.

[0009] In a CMOS image sensor, as shown in FIG. 1, luminance information is represented by a difference ΔV1 between the black level LB1 of the readout reset signal VRST of the pixel signal Pixout and the signal level LS of the readout signal VSIG. When high-luminance light is incident on a pixel, a phenomenon occurs in which a signal component leaks into the read reset signal VRST, which is originally near the black level LB1. As a result, as shown in FIG. 1, the black level LB1 changes significantly to the black level LB2, and the difference between the signal level SL and the black level LB attenuates from ΔV1 to ΔV2 (ΔV1 > ΔV2), resulting in an image that is darker than the original brightness (a blocked-up image) as shown in FIG. 2.

[0010] In order to prevent the effects of fluctuations in the black level LB, a CMOS image sensor has been proposed in which a clamp circuit that clamps the black level to a predetermined level is arranged in the pixel signal column readout system, as shown in FIG. 3 (see, for example, Patent Document 1).

[0011] The clamp circuit 1 in FIG. 3 is formed by connecting a clamp transistor CTr between a vertical signal line SLGN1 from which a pixel signal Pixout is read out in each column of the pixel array and a power supply potential VDD. The gate voltage of the clamp transistor CTr is controlled by a clamp signal CTP from a clamp level generating circuit 2 .

[0012] As shown in FIG. 4, for example, when very strong light (high brightness light) is incident on one or more pixels, clamp circuit 1 clamps black level LB1 to black level LB3 and maintains the difference between signal level SL and black level LB at ΔV3 (ΔV1 ≒ ΔV3 > ΔV2), preventing the difference from attenuating and fluctuating from ΔV1 to ΔV2 (ΔV1 > ΔV2). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] JP 2011-160046 A Summary of the Invention [Problem to be solved by the invention]

[0014] However, in the above-mentioned CMOS image sensor, the clamp signal CLP, which is a reference signal for controlling the clamp voltage, is generated by the clamp level generation circuit 2 and is common to all columns. As a result, the clamp level varies due to element variations from column to column, resulting in columns where clamping is not performed properly. In this case, data from columns where the clamp is not at the desired level will also be converted by ADC3, and the variations will propagate to the final output. As a result, the center of the high-brightness light source becomes blackened (see image example Figure 2).

[0015] The present invention aims to provide a solid-state imaging device, a driving method for a solid-state imaging device, and electronic equipment that can reliably prevent the occurrence of inversion video noise even if there is variation in elements from column to column, and thereby achieve high image quality. [Means for solving the problem]

[0016] A solid-state imaging device according to a first aspect of the present invention comprises a pixel section in which pixels that perform photoelectric conversion are arranged in a matrix, and a readout circuit having an analog-to-digital (AD) conversion function that converts pixel signals read out from the pixels as voltage signals to signal lines from analog signals to digital signals, wherein the pixel signals read out from the pixels include a readout reset signal and a readout signal that are read out in sequence from the pixels, and the readout circuit includes an AD conversion section that converts the pixel signals read out to the signal line from analog signals to digital signals, and a pixel signal monitoring section that changes the conversion code of the AD conversion section to a code different from a normal conversion code when the signal level of the readout reset signal for the pixel signal read out to the signal line exceeds a predetermined reference voltage.

[0017] A second aspect of the present invention is a method for driving a solid-state imaging device having a pixel section in which pixels that perform photoelectric conversion are arranged in a matrix, and a readout circuit having an analog-to-digital (AD) conversion function that converts pixel signals read out from the pixels as voltage signals to signal lines from analog signals to digital signals, wherein the readout circuit includes an AD conversion section that converts the pixel signals read out to the signal lines from analog signals to digital signals, wherein the pixel signals read out from the pixels include a readout reset signal and a readout signal that are read out sequentially from the pixels, and when a signal level of the readout reset signal of the pixel signal read out to the signal line exceeds a predetermined reference voltage, the readout circuit changes the conversion code of the AD conversion section to a code different from a normal conversion code.

[0018] An electronic device according to a third aspect of the present invention comprises a solid-state imaging device and an optical system for forming an image of a subject on the solid-state imaging device, the solid-state imaging device comprising a pixel section in which pixels that perform photoelectric conversion are arranged in a matrix, and a readout circuit having an analog-to-digital (AD) conversion function for converting pixel signals read out from the pixels as voltage signals to signal lines from analog signals to digital signals, the pixel signals read out from the pixels including a readout reset signal and a readout signal which are read out sequentially from the pixels, the readout circuit comprising an AD conversion section for converting the pixel signals read out to the signal line from analog signals to digital signals, and a pixel signal monitoring section for changing the conversion code of the AD conversion section to a code different from a normal conversion code when the signal level of the readout reset signal of the pixel signal read out to the signal line exceeds a predetermined reference voltage. Effect of the Invention

[0019] According to the present invention, even if there is a variation in elements between columns, it is possible to reliably prevent the occurrence of inversion video noise, and thus it is possible to realize high image quality. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams for explaining a readout reset signal and a readout signal as pixel signals read out from a pixel, and for explaining the problem of a blocked-up image being formed when high-luminance light is incident. [Diagram 2] 1A and 1B are diagrams illustrating an example of a blocked-up black image formed when high-luminance light is incident on a pixel; [Diagram 3] 1 is a diagram showing an example of the configuration of a pixel signal readout circuit system in which a clamp circuit that suppresses black level fluctuations that are a cause of blocked-up pixels is disposed; [Figure 4] 1A and 1B are diagrams for explaining the principle of suppressing fluctuations in the black level by a clamp circuit. [Diagram 5] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention. [Figure 6]1 is a circuit diagram showing an example of a pixel according to the first embodiment. [Figure 7] 11 is a diagram showing the operation timing of shutter scan and read scan during normal pixel read operation in the first embodiment. FIG. [Figure 8] 1 is a diagram for explaining an example of the configuration of a readout system for column outputs of a pixel unit of a solid-state imaging device according to a first embodiment of the present invention. FIG. [Figure 9] FIG. 2 is a diagram illustrating a configuration of a column readout circuit according to the first embodiment of the present invention. [Figure 10] 1 is a circuit diagram showing a configuration example of an amplifier serving as an amplifying section according to a first embodiment of the present invention. [Figure 11] 2 is a circuit diagram showing an example of the configuration of a pixel signal monitoring unit according to the first embodiment of the present invention. FIG. [Figure 12] 4 is a timing chart for explaining a pixel signal readout process of the solid-state imaging device according to the first embodiment of the present invention. [Figure 13] FIG. 11 is a diagram showing a column readout system of a solid-state imaging device according to a second embodiment of the present invention. [Figure 14] 1 is a diagram showing an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0022] (First embodiment) FIG. 5 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention. In this embodiment, the solid-state imaging device 10 is formed of, for example, a CMOS image sensor.

[0023] As shown in FIG. 5, the solid-state imaging device 10 has as its main components a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the column read circuit 40, and the timing control circuit 60 constitute a pixel signal read unit 70.

[0024] In this first embodiment, the column readout circuit 40 of the solid-state imaging device 10 has an analog-to-digital (AD) conversion function that converts pixel signals read out as voltage signals from pixels that perform photoelectric conversion in the pixel section 20 to signal lines from analog signals to digital signals, as will be described in detail later. In the first embodiment, the pixel signals read out from the pixels include a read reset signal VRST11 and a read signal VSIG11 which are sequentially read out from the pixels. The column readout circuit 40 includes an AD conversion unit that converts the pixel signal PIXOUT read out to the vertical signal line from an analog signal to a digital signal, and a pixel signal monitoring unit that changes the conversion code of the AD conversion unit to a code different from the conversion code corresponding to normal luminance information when the signal level of the readout reset signal VRST11 of the pixel signal read out to the vertical signal line exceeds a preset reference voltage Vref.

[0025] In the first embodiment, when the signal level of the readout reset signal VRST11 of the pixel signal read out to the vertical signal line exceeds a preset reference voltage, the pixel signal monitoring unit fixes the conversion code of the AD conversion unit to a predetermined code, for example, fixing the data for that period to all "1".

[0026] The pixel signal monitoring unit has a comparison unit that compares a reference voltage with the read pixel signal. The comparison unit is capable of setting a first reference voltage Vref1 having a level equivalent to the signal level of the readout reset signal VRST11 at the time of reset, and a second reference voltage Vref2 having a level greater than the first reference voltage Vref1, and compares the readout reset signal VRST11 of the pixel signal read out to the vertical signal line input to the signal input unit with the reference voltages Vref1, Vref2 set in the voltage setting unit.

[0027] The comparison unit initializes the potential of the signal input unit with a first reference voltage Vref1 level and an offset voltage during the pixel reset period and during a predetermined period at the start of readout of the readout reset signal after reset release, and after the initialization, compares the readout reset signal VRST11 of the pixel signal read out to the vertical signal line with a second reference voltage Vref2 set in the voltage setting unit, and fixes the conversion code of the AD conversion unit to a predetermined code if the signal level of the readout reset signal VRST11 exceeds the second reference voltage Vref2.

[0028] In the first embodiment, the second reference voltage Vref2 is set to a voltage value between the first reference voltage Vref1 and a voltage corresponding to a black level when high-luminance light is incident. The voltage equivalent to the black level when high-brightness light is incident is the level at which the blackout phenomenon occurs or may occur due to a decrease in (signal-black level) when high-brightness light is incident.

[0029] In this first embodiment, the readout section 70 is configured to be capable of performing a first readout in one readout scan period, in which a readout reset signal VRST11 (reset voltage Vrst) is read out in a first readout period following a reset period, and a second readout in which a readout signal VSIG11 (signal voltage Vsig) corresponding to the accumulated charge of the photoelectric conversion element is read out in a second readout period following a transfer period which is performed after the first readout period following the reset period.

[0030] In a normal pixel readout operation, a shutter scan is performed by driving the readout unit 70, and then a readout scan is performed, but the first readout and second readout are performed during the readout scan period.

[0031] Below, an overview of the configuration and function of each part of the solid-state imaging device 10 will be given, and then the configuration of the clipping circuit and the associated readout process will be described in detail.

[0032] (Configuration of pixel section 20 and pixel PXL) The pixel section 20 has a plurality of pixels, each including a photodiode (photoelectric conversion element) and an in-pixel amplifier, arranged in a two-dimensional matrix of N rows and M columns.

[0033] FIG. 2 is a circuit diagram showing an example of a pixel according to the first embodiment.

[0034] This pixel PXL has, for example, a photodiode (PD) which is a photoelectric conversion element. For this photodiode PD, there is provided one transfer transistor TG-Tr as a transfer element, one reset transistor RST-Tr as a reset element, one source follower transistor SF-Tr as a source follower element, and one selection transistor SEL-Tr as a selection element.

[0035] The photodiode PD generates and accumulates a signal charge (here, electrons) in an amount corresponding to the amount of incident light. In the following, a case will be described in which the signal charges are electrons and each transistor is an n-type transistor, but the signal charges may be holes and each transistor may be a p-type transistor. Furthermore, the first embodiment is also effective in cases where each transistor is shared between a plurality of photodiodes, and in cases where a three-transistor (3Tr) pixel that does not have a selection transistor is employed.

[0036] The transfer transistor TG-Tr is connected between the photodiode PD and a floating diffusion FD (Floating Diffusion), and is controlled by a control signal TG applied to the gate through a control line. The transfer transistor TG-Tr is selected and turned on when the control signal is at high level (H), and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode PD to the floating diffusion FD.

[0037] The reset transistor RST-Tr is connected between a power supply line VRst and a floating diffusion FD, and is controlled by a control signal RST applied to the gate through a control line. The reset transistor RST-Tr may be configured to be connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD, and controlled by a control signal RST applied to the gate via a control line. The reset transistor RST-Tr is selected and turned on while the control signal RST is at H level, and resets the floating diffusion FD to the potential of the power supply line VRst (or the power supply line Vdd of the power supply voltage VDD).

[0038] The source follower transistor SF-Tr and the selection transistor SEL-Tr are connected in series between a power supply line Vdd of a power supply voltage VDD and a vertical signal line LSGN11. A floating diffusion FD is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled by a control signal SEL applied to the gate through a control line. The selection transistor SEL-Tr is selected and turned on when the control signal SEL is at H level, which causes the source follower transistor SF-Tr to output the column output readout voltage (signal) VSL (PIXOUT), which is a voltage signal obtained by converting the charge of the floating diffusion FD, to the vertical signal line LSGN11. These operations are performed simultaneously in parallel for each pixel in one row, since the gates of the transfer transistors TG-Tr, reset transistors RST-Tr, and selection transistors SEL-Tr are connected on a row-by-row basis.

[0039] In the pixel section 20, the pixels PXL are arranged in N rows and M columns, so that there are N control lines for each of the control signals SEL, RST, and TG, and M vertical signal lines LSGN11. In FIG. 5, the control lines for the control signals SEL, RST, and TG are shown as one row scanning control line.

[0040] The vertical scanning circuit 30 drives pixels in the shutter row and the readout row through row scanning control lines under the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs a row selection signal of the row address of a read row for reading out a signal and a shutter row for resetting the charge accumulated in the photodiode PD in accordance with the address signal.

[0041] As described above, in a normal pixel read operation, the readout section 70 is driven by the vertical scanning circuit 30 to perform shutter scanning, and then read scanning is performed.

[0042] FIG. 7 is a diagram showing the operation timing of shutter scan and read scan during normal pixel read operation in the first embodiment.

[0043] The control signal SEL, which controls whether the selection transistor SEL-Tr is on (conductive) or off (non-conductive), is set to a low level (L) during the shutter scan period PSHT to hold the selection transistor SEL-Tr in a non-conductive state, and is set to an H level during the read scan period PRDO to hold the selection transistor SEL-Tr in a conductive state. During the shutter scan period PSHT, the control signal TG is set to high level (H) for a predetermined period while the control signal RST is at high level (H), and the photodiode PD and the floating diffusion FD are reset through the reset transistor RST-Tr and the transfer transistor TG-Tr.

[0044] During the read scan period PRDO, the control line RST is set to a high level (H) and the floating diffusion FD is reset through the reset transistor RST-Tr, and a pixel read signal VRST11 (reset voltage Vrst) in the reset state is read out during the first read period PRD1 after this reset period PR. After the readout period PRD1, the control signal TG is set to a high level (H) for a predetermined period, and the accumulated charge in the photodiode PD is transferred to the floating diffusion FD through the transfer transistor TG-Tr, and a pixel readout signal VSIG11 (signal voltage Vsig) corresponding to the accumulated electrons (charges) during the second readout period PRD2 after this transfer period PT is read out.

[0045] In the normal pixel readout operation of the first embodiment, the accumulation period (exposure period) EXP is the period from when the photodiode PD and the floating diffusion FD are reset and the control signal TG is switched to the L level during the shutter scan period PSHT to when the control signal TG is switched to the L level to end the transfer period PT of the readout scan period PRDO, as shown in FIG. 7.

[0046] The column readout circuit 40 may include a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and may be configured to enable column parallel processing by the plurality of column signal processing circuits.

[0047] The column readout circuit 40 can be configured to include a correlated double sampling (CDS) circuit, an ADC (analog-to-digital converter; AD converter), an amplifier (AMP), and the like.

[0048] In this way, the column readout circuit 40 may be configured to include an ADC 41 that converts the readout signal VSL of each column output of the pixel section 20 into a digital signal, as shown in FIG. 8(A), for example. Alternatively, the column readout circuit 40 may be provided with an amplifier (AMP) 42 as an amplifier section that amplifies the readout signal VSL of each column output of the pixel section 20, as shown in FIG. 8B, for example.

[0049] The column readout circuit 40 of the first embodiment further includes a pixel signal monitoring unit (PMC) 43. In each column, when the signal level LVRST of the read reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 exceeds a preset reference voltage Vref, the pixel signal monitoring unit 43 fixes the conversion code of the AD conversion unit of the ADC 41 to a predetermined code. In addition, in the first embodiment, the case where the reference voltage Vref is exceeded refers to the case where the signal level LVRST of the read reset signal VRST11 becomes lower than the second reference voltage Vref2, for example.

[0050] Here, an example of a specific configuration and function of the pixel signal monitoring unit 43 will be described in relation to the column readout circuit 40 including the amplifier 42 in FIG. 8(B).

[0051] FIG. 9 is a diagram for explaining the configuration of the column readout circuit according to the first embodiment of the present invention.

[0052] The column readout circuit 40A in FIG. 9 is composed of an amplifier 42A as an amplifier section, an ADC 41A, and a pixel signal monitoring section 43A.

[0053] The amplifier 42A amplifies the pixel signal VSL (PIXOUT) propagated through the vertical signal line LSGN11, and outputs the amplified pixel signal as an amplifier output AMPout to the ADC 41A and the pixel signal monitoring unit 43A.

[0054] FIG. 10 is a circuit diagram showing a configuration example of an amplifier serving as an amplifying section according to the first embodiment of the present invention.

[0055] The amplifier 42A includes an operational amplifier (hereinafter referred to as op-amp) 421, a sampling capacitor (input capacitor: Cc) C421, a feedback capacitor (feedback capacitor: Cf) C422, an auto-zero switch section SW421, an output node ND421, and a reference potential Vref1.

[0056] The operational amplifier 421 has two input terminals: a first input terminal, which in this first embodiment is an inverting input terminal (-), and a second input terminal, which in this first embodiment is a non-inverting input terminal (+), and obtains an amplifier output AMPout by multiplying (amplifying) the difference between the input voltage VSL to the first input terminal (-) and the reference potential Vref1 to the second input terminal (+) by a gain A0. The output terminal of the operational amplifier 421 is connected to an output node ND421.

[0057] In the amplifier 42A, the control signal AZ42 is set to H level for a predetermined period after the readout reset signal VRST11 of the pixel signal VSL is input (a predetermined period after the start of the first readout period for reading out pixel signals in a reset state). This causes the auto-zero switch SW421 of the amplifier 42A to be turned on. This causes the operational amplifier 421 of the amplifier 42A to enter a reset state. As a result, the output signal (amplifier output) AMPout of the operational amplifier 421 of the amplifier 42A during the auto-zero operation becomes the reference potential Vref1.

[0058] The ADC 41 converts the analog readout reset signal VRST11 and the readout signal VSIG11, which are the outputs of each column of the pixel section 20 amplified by an amplifier 42A serving as an amplifier section, into digital signals (AD conversion). The ADC 41 of the first embodiment is configured to include a calculation unit 411 that processes the AD conversion code to be constant when it receives a flag signal Col_det, for example at an active high level (H), from the pixel signal monitoring unit 43A, indicating that a black level exceeding a reference level has been input.

[0059] In the first embodiment, when the pixel signal monitoring unit 43A receives a flag signal Col_det indicating that a reference level (a black level that is higher (lower) than the second reference voltage Vref2 in this example) has been input, as an active high level (H), the calculation unit 411 fixes the AD conversion code to all "1" so that the code is constant.

[0060] When the signal level LVRST of the read reset signal VRST11 of the pixel signal VSL, which is read out to the vertical signal line LSGN11 and amplified by the amplifier 42A, becomes lower due to the second reference voltage Vref2, the pixel signal monitoring unit 43A outputs a flag signal Col_det, for example, at an active high level (H), to the calculation unit 411 of the ADC41A so as to fix the conversion code of the AD conversion unit of the ADC41 to a predetermined code.

[0061] The pixel signal monitoring unit 43A in FIG. 9 is configured with a 1-bit comparator having a comparison unit 431 that compares a readout reset signal VRST11 input to a signal input unit IS43 with a reference voltage Vref(1,2) set in a voltage setting unit VS43, and a latch unit 432 that latches a comparison result signal S431 of the comparison unit 431 and outputs a flag signal Col_det, for example, at an active high level (H) to the calculation unit 411 of the ADC41A so as to fix the conversion code of the AD conversion unit of the ADC41 to a predetermined code during this latch period.

[0062] More specifically, the comparison unit 431 is capable of setting a first reference voltage Vref1 having a level equivalent to the signal level of the read reset signal VRST11 when set as the reference voltage Vref, and a second reference voltage Vref2 having a level higher than the first reference voltage Vref1. The comparator 431 compares a read reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 input to the signal input unit IS43 with the reference voltages Vref1, Vref2 set in the voltage setting unit VS43.

[0063] In the first embodiment, the first reference voltage Vref1 is set to a voltage value equal to the output voltage of the amplifier 42A during auto-zero.

[0064] The pixel signal monitoring unit 43 includes a comparison unit 431, and initializes the potential of the signal input unit IS43 to the level of a first reference voltage Vref1 during a pixel reset period PR and a predetermined period at the start of readout of the readout reset signal VRST11 after reset release. After the initialization, the comparison unit 431 compares the readout reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 with a second reference voltage Vrrf2 set in a voltage setting unit VS43, and fixes the conversion code of the AD conversion unit of the ADC41A to a predetermined code, for example all "1's", if the signal level of the readout reset signal VRST11 exceeds the second reference voltage Vref2.

[0065] As described above, in the first embodiment, the case where the reference voltage Vref is exceeded refers to, for example, the case where the signal level LVRST of the read reset signal VRST11 becomes lower than the second reference voltage Vref2. The second reference voltage Vref2 is set to a voltage value between the first reference voltage Vref1 and a voltage corresponding to the black level LB when high-luminance light is incident. As mentioned above, the voltage equivalent to the black level when high-brightness light is incident is the level at which the black crush phenomenon occurs or may occur due to a decrease in (signal-black level) when high-brightness light is incident.

[0066] FIG. 11 is a circuit diagram showing an example of the configuration of the pixel signal monitoring unit according to the first embodiment of the present invention.

[0067] The comparison unit 431 in the pixel signal monitoring unit 43A in FIG. 11 is configured to include a first comparator 4311, an AC coupling capacitor C431, an auto-zero switch SW431 that can be switched between a connected state and a non-connected state by a first reset signal RST, a first reference switch SW432 that can be switched between a connected state and a non-connected state by the first reset signal RST, a second reference switch SW433 that can be switched between a connected state and a non-connected state by a second reset signal RST_B that is in phase with the first reset signal RST, and a second comparator 4312 that processes an output signal S4311 of the first comparator 4311.

[0068] The first reset signal RST is a signal in phase with the control signal RST of the reset transistor RST-Tr of the pixel.

[0069] The first comparator 4311 has a first input terminal, which in this embodiment is an inverting input terminal (-), connected to an AC coupling capacitor C431 and connected via the AC coupling capacitor C431 to a supply line of the amplifier output AMPout, which is the amplified pixel signal of the amplifier 42A, and an auto-zero switch SW431 is connected between the first input terminal (-) and the output terminal. In the first comparator 4311, the first reference switch SW432 is connected between the second input terminal, in this embodiment the non-inverting input terminal (+), and the supply line of the first reference voltage Vref1, and the second reference switch SW433 is connected between the second input terminal (+) and the supply line of the second reference voltage Vref2.

[0070] In the comparison section 431, a first comparator 4311 forming a first comparison stage (stage 1) performs a comparison operation in response to a first enable signal EN1 that is active, for example, at a high level (H). The second comparator 4312 forming the second comparison stage (stage 2) performs a comparison operation in response to the second enable signal EN2 which becomes active high level (H) after the first enable signal EN1.

[0071] The latch unit 432 is formed, for example, by a D-type flip-flop DFF432, and latches the output signal S4312 of the second comparator 4312, which becomes the output signal of the comparison unit 431, in synchronization with the latch signal latch.When the latch signal latch becomes high level (H), the comparison operation of the comparison unit 431 is confirmed, and the flag signal Col_det is output, for example, at an active high level (H), to the calculation unit 411 of the ADC41A.

[0072] In this first embodiment, after the first enable signal EN1 becomes active high level (H) and the first comparator 4311 enters comparison operation, the first reset signal PST becomes active high level (H) for a predetermined reset period PR. As a result, the auto-zero switch SW431 is in a conductive state, the first input terminal (-) and the output terminal are connected, and the first comparator 4311 is configured as a voltage follower. At that time, the first reference voltage Vref1 is supplied to the second input terminal (+), the first comparator 4311 performs an auto-zero operation, and the first reference voltage Vref1 and the first comparator 4311 offset voltage Vofs are held in the signal input unit IP43. The first reset signal RST becomes an inactive low level (L), the second reset signal RST_B becomes a high level (H), the auto-zero switch SW431 and the first reference switch SW432 become disconnected, the second reference switch SW433 becomes conductive, and the reference voltage switches from the first reference voltage Vref1 to the second reference voltage Vref2. After this switching, the second enable signal EN2 becomes active high level (H), and the second comparator 4312 starts a comparison operation. An output signal S 4312 of the second comparator 4312 indicating the comparison result of the comparing section 431 is output to the latch section 432 .

[0073] The latch unit 432 latches a detection signal that detects that the signal level of at least the read reset signal VRST11 among the output signals of the comparison unit 431 has exceeded the second reference voltage Vref2, and during this latching period, outputs a flag signal Col_det, which instructs the conversion code of the AD conversion unit of the ADC41A to be fixed to a predetermined code, for example at an active high level (H) to the calculation unit 411 of the ADC41A.

[0074] The horizontal scanning circuit 50 scans and horizontally transfers signals processed by a plurality of column signal processing circuits such as ADCs of the column readout circuit 40, and outputs them to a signal processing circuit (not shown).

[0075] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the column readout circuit 40, the horizontal scanning circuit 50, and the like.

[0076] The configuration and function of each part of the solid-state imaging device 10 have been outlined above. Next, a pixel signal readout process of the solid-state imaging device 10 according to the first embodiment of the present invention will be described with reference to FIGS. 12(A) to (J) and FIG. In the following, a case where light of normal luminance is incident and a case where light of high luminance is incident will be described.

[0077] 12A to 12J are timing charts illustrating the readout process of pixel signals of the solid-state imaging device 10 according to the first embodiment of the present invention. 12(A) to (J) are shown including the operation of pixel signal monitoring unit 43A when high luminance light is incident. Figure 12(A) shows the read level of the pixel signal PIXOUT, Figure 12(B) shows the first reset signal RST, Figure 12(C) shows the first enable signal, Figure 12(D) shows the output signal stage1out of the first comparator 4311, Figure 12(E) shows the second enable signal, Figure 12(F) shows RST_B during the second reset sample period, Figure 12(G) shows the output signal stage2out of the second comparator 4312, Figure 12(H) shows the latch signal latch, Figure 12(I) shows the flag signal Col_det, and Figure 12(J) shows the output signal (output data) ADCout of ADC41.

[0078] During the read scan period PRDO, as shown in FIG. 7, in order to select a row in the pixel array, the control signal SEL to the control line connected to each pixel PXL in the selected row is set to H level, and the selection transistor SEL-Tr of the pixel PXL becomes conductive. In this selected state, as shown in FIG. 7, during a reset period PR1, the reset transistor RST-Tr is selected and turned on while the control signal RST is at H level, and the floating diffusion FD is reset to the power supply potential VDD. The period from when the reset period PR1 has elapsed (when the reset transistor RST-Tr is in a non-conductive state) until the transfer period PT1 begins is the first read period PRD1 during which the reset voltage Vrst in the reset state is read out.

[0079] As described above, during the first readout period PRD1 after the reset period PR1, the readout reset signal VRST11, which is a pixel readout voltage in a reset state, is read out through the vertical signal line LSGN11, supplied to the column readout circuit 40 via a load circuit not shown, and is, for example, held after the AD conversion process.

[0080] The read reset signal VRST11 input to the column read circuit 40 of each column is first amplified in the amplifier 42A, and the amplifier output AMPout is output to the ADC 41A and the pixel signal monitoring unit 43A. In the amplifier 42A, the control signal AZ42 is set to H level for a predetermined period after the readout reset signal VRST11 of the pixel signal VSL is input (a predetermined period after the start of the first readout period for reading out pixel signals in a reset state). This causes the operational amplifier 421 of the amplifier 42A to enter a reset state. As a result, the output signal (amplifier output) AMPout of the operational amplifier 421 of the amplifier 42A during the auto-zero operation becomes the reference potential Vref1.

[0081] (When light of normal brightness is incident) In the pixel signal monitoring unit 43A, after the first enable signal EN1 becomes active high level (H) and the first comparator 4311 of the comparison unit 431 enters comparison operation, the first reset signal PST is held at active high level (H) for a predetermined reset period PR. As a result, the auto-zero switch SW431 is brought into a conductive state, the first input terminal (-) and the output terminal of the first comparator 4311 are connected, and the first comparator 4311 is configured as a voltage follower. At that time, the first reference voltage Vref1 is supplied to the second input terminal (+), the first comparator 4311 performs an auto-zero operation, and the first reference voltage Vref1 and the first comparator 4311 offset voltage Vofs are held in the signal input section IP43. This cancels out the variations between columns. Next, the first reset signal RST becomes an inactive low level (L), the second reset signal RST_B becomes a high level (H), the auto-zero switch SW431 and the first reference switch SW432 become disconnected, the second reference switch SW433 becomes conductive, and the reference voltage switches from the first reference voltage Vref1 to the second reference voltage Vref2. After this switching, the second enable signal EN2 becomes active high level (H), and the second comparator 4312 starts a comparison operation. Then, the output signal S 43112 of the second comparator 4312 indicating the comparison result of the comparing section 431 is output to the latch section 432 .

[0082] For example, in the latch section 432 formed by a D-type flip-flop DFF432, the output signal S4312 of the second comparator 4312, which becomes the output signal of the comparison section 431, is latched in synchronization with the latch signal latch, and when the latch signal latch becomes high level (H), the comparison operation of the comparison section 431 is confirmed and the flag signal Col_det is output to the calculation section 411 of the ADC41A, for example, at an active high level (H) or low level (L). Here, since it is assumed that light of normal brightness is incident, a black level LB of the read reset signal VRST11 that does not exceed the level of the second reference voltage Vref2 (higher than the level of the second reference voltage Vref2) is input. Therefore, the output signals of the first comparator 4311 and the second comparator 4312 in the comparison unit 431 become low level (L), and a low level (L) flag signal Col_det is output from the latch unit 432 in the pixel signal monitoring unit 43A to the calculation unit 411 in the ADC 41A.

[0083] In the ADC 41, the analog readout reset signal VRST11 of each column output of the pixel section 20 amplified by an amplifier 42A serving as an amplifier section is converted into a digital signal (AD conversion). Then, in the calculation unit 411 of the ADC 41, the pixel signal monitoring unit 43A receives a flag signal Col_det, for example at a low level (L), indicating that a black level that does not exceed the level of the second reference voltage Vref2, which is the reference level (higher than the reference level), has been input. Therefore, when light of normal luminance is incident, the AD conversion code is stored in a memory (not shown) as the converted code.

[0084] (When high-intensity light is incident) In this case, since high-luminance light is incident, the black level LB of the read reset signal VRST11 is a black level that exceeds the level of the second reference voltage Vref2 (lower than the level of the second reference voltage Vref2). Therefore, the output signals of the first comparator 4311 and the second comparator 4312 of the comparison unit 431 become high level (H), a high level (H) flag signal Col_det is output from the latch unit 432 of the pixel signal monitoring unit 43A to the calculation unit 411 of the ADC 41A, and the enable signal EN1 is held at an active high level (H) during the period.

[0085] In the ADC 41, the analog readout reset signal VRST11 of each column output of the pixel section 20 amplified by an amplifier 42A serving as an amplifier section is converted into a digital signal (AD conversion). Then, in the calculation unit 411 of the ADC 41, the pixel signal monitoring unit 43A receives a flag signal Col_det at a high level (H) indicating that a black level that exceeds the level of the second reference voltage Vref2, which is the reference level (lower than the level of the second reference voltage Vref2), has been input. Therefore, when light of normal luminance is incident, the AD conversion code is held in a memory (not shown) as a fixed code (fixed to all "1"s).

[0086] Here, the first read period PRD1 ends and the transfer period PT1 begins. As shown in Figure 7, during a transfer period PT1, the transfer transistor TG-Tr is selected and turned on while the control signal TG is at a high level (H), and the charge (electrons) photoelectrically converted and accumulated in the photodiode PD is transferred to the floating diffusion FD. After the transfer period PT1 has elapsed (the transfer transistor TG-Tr is in a non-conductive state), a second readout period PRD2 begins in which the signal voltage Vsig corresponding to the charge accumulated by the photodiode PD after photoelectric conversion is read out.

[0087] As described above, after the first readout period PRD1, the control signal TG is set to an H level for a predetermined period, and the accumulated charge in the photodiode PD is transferred to the floating diffusion FD through the transfer transistor TG-Tr, and a readout signal VSIG11, which is a pixel readout voltage corresponding to the electrons (charges) accumulated in the second readout period PRD2 after this transfer period PT1, is read out to the vertical signal line LSGN11.

[0088] The read signal VSIG11 input to the column read circuit 40 of each column is first amplified in the amplifier 42A, and the amplifier output AMPout is output to the ADC 41A and the pixel signal monitor 43A.

[0089] In the ADC 41, an analog read signal VSIG11 of the output of each column of the pixel section 20 amplified by an amplifier 42A serving as an amplifier section is converted into a digital signal (AD conversion). The AD conversion code of the read signal VSIG11 is a fixed code and is stored in a memory (not shown).

[0090] Then, for example, in the read circuit 40 constituting part of the read section 70, the difference (Vsig-Vrst) between the read signal VSIG11 (signal voltage Vsig) read out in the second read period PRD2 and the read reset signal VRST11 (reset voltage Vrst) read out in the first read period PRD1 is taken, and CDS processing is performed. In both normal brightness and high brightness, the reduction in the pixel output difference (Vsig-Vrst) between the signal voltage Vsig and the reset voltage (black level) Vrst is extremely small, so it is possible to prevent the occurrence of the black crush phenomenon that occurs when this difference is reduced.

[0091] As described above, according to the first embodiment, the pixel signal monitoring unit 43 includes a comparison unit 431, and initializes the potential of the signal input unit IS43 to the level of the first reference voltage Vref1 during the pixel reset period PR and a predetermined period at the start of readout of the readout reset signal VRST11 after reset release. After the initialization, the comparison unit 431 compares the readout reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 with the second reference voltage Vrrf2 set in the voltage setting unit VS43, and if the signal level of the readout reset signal VRST11 exceeds the second reference voltage Vref2, fixes the conversion code of the AD conversion unit of the ADC41A to a predetermined code, for example all “1”. In each column, when the signal level LVRST of the read reset signal VRST11 of the pixel signal VSL, which is read out to the vertical signal line LSGN11 and amplified by the amplifier 42, exceeds a preset reference voltage Vref (as an example, when the signal level LVRST of the read reset signal VRST11 becomes lower due to a second reference voltage Vref2), the pixel signal monitoring unit 43 fixes the conversion code of the AD conversion unit of the ADC41 to a predetermined code.

[0092] Therefore, according to the first embodiment, since the reduction in the pixel output difference (Vsig-Vrst) between the signal voltage Vsig and the reset voltage (black level) Vrst, both at normal brightness and at high brightness, is extremely small, it is possible to prevent the occurrence of the crushed black phenomenon that occurs when this difference is reduced. Thus, according to the first embodiment, even if there is variation in elements from column to column, it is possible to reliably prevent the occurrence of inverted video noise (prevent sunspots), and ultimately achieve high image quality.

[0093] Second Embodiment FIG. 13 is a diagram showing a column readout system of a solid-state imaging device according to the second embodiment of the present invention.

[0094] The solid-state imaging device 10B according to the second embodiment differs from the solid-state imaging device 10 according to the first embodiment in the following respects. In a solid-state imaging device 10B according to the second embodiment, a clamp circuit 44 is provided that clamps the black level LBRST of the read reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 of each column to a predetermined level LBN. Here, the predetermined level of the black level corresponds to the black level LBNM at normal luminance.

[0095] The clamp circuit 44 in FIG. 13 is formed by connecting a clamp transistor CLP-Tr and a selection transistor SL-Tr in series between a vertical signal line SLGN11 from which a pixel signal PIXOUT is read out in each column of the pixel array and a predetermined power supply, for example, a power supply potential VDD. The gate voltages of the clamp transistors CLP-Tr arranged corresponding to each column are commonly connected to a supply line of a clamp signal CLP from the clamp level generation circuit 200, and the gate voltages of the selection transistors SL-Tr are commonly connected to a supply line of a clamp selection signal CSL.

[0096] In this embodiment, the clamp selection signal CSL is set to an active H level by the readout section 70 during the reset period PR and the first readout period PRD1 of the readout scan PRDO.

[0097] As shown in FIG. 4, for example, when very strong light (high brightness light) is incident on one or more pixels, the clamp circuit 44 clamps the black level LB1 to the black level LB3 and maintains the difference between the signal level SL and the black level LB at ΔV3 (ΔV1 ≒ ΔV3 > ΔV2), thereby preventing the difference from attenuating and fluctuating from ΔV1 to ΔV2 (ΔV1 > ΔV2).

[0098] However, in the above-mentioned CMOS image sensor, the clamp signal CLP, which is a reference signal for controlling the clamp voltage, is common to all columns. As a result, the clamp level can vary due to element variations from column to column, and columns can be affected by poor clamping. In the second embodiment, even if such a state occurs, the column readout circuit 40 includes a comparison unit 431 and a latch unit 432, and initializes the potential of the signal input unit IS43 to the level of the first reference voltage Vref1 during the pixel reset period PR and a predetermined period at the start of readout of the readout reset signal VRST11 after reset release, and after the initialization, compares the readout reset signal VRST11 of the pixel signal VSL read out to the vertical signal line LSGN11 with the second reference voltage Vrrf2 set in the voltage setting unit VS43, and if the signal level of the readout reset signal VRST11 exceeds the second reference voltage Vref2, the column readout circuit 40 has a pixel signal monitoring unit 43 that fixes the conversion code of the AD conversion unit of the ADC41A to a predetermined code, for example all "1", thereby obtaining the following effects. According to the second embodiment, the reduction in the pixel output difference (Vsig-Vrst) between the signal voltage Vsig and the reset voltage (black level) Vrst is extremely small both during normal brightness and during high brightness, and it is therefore possible to prevent the occurrence of the crushed black phenomenon that occurs when this difference is reduced.

[0099] In this way, according to the second embodiment, even if there is variation in elements from column to column, it is possible to reliably prevent the occurrence of inversion video noise, and ultimately to achieve high image quality.

[0100] The solid-state imaging device 10 described above can be applied as an imaging device to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

[0101] FIG. 14 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied.

[0102] As shown in FIG. 14, the electronic device 300 includes a CMOS image sensor 310 to which the solid-state imaging device 10 according to the present embodiment can be applied. Furthermore, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (forms an image of a subject). The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal from the CMOS image sensor 310 .

[0103] The signal processing circuit 330 performs a predetermined signal processing on the output signal of the CMOS image sensor 310 . The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor such as an LCD display, or output to a printer. It can also be recorded directly on a recording medium such as a memory card, and various other forms are possible.

[0104] As described above, by incorporating the above-mentioned solid-state imaging device 10 as the CMOS image sensor 310, it is possible to provide a high-performance, small-sized, low-cost camera system. This makes it possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where the camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height. [Explanation of symbols]

[0105] REFERENCE SIGNS LIST 10, 10B... solid-state imaging device, 20... pixel section, 30... vertical scanning circuit, 40, 40B... column readout circuit, 41, 41A... ADC, 411... calculation section, 42, 42A... amplifier, 43, 43A... pixel signal monitoring section, 431... comparison section, 432... latch section, 4311... first comparator, 4312... second comparator, SW431... auto-zero switch, SW432... third comparator 1 reference switch, SW433···second reference switch, C431···sampling capacitor, Vref1···first reference voltage, Vref2···second reference voltage, 44···clamp circuit, 50···horizontal scanning circuit, 60···timing control circuit, 70···readout section, 300···electronic device, 310···CMOS image sensor, 320···optical system, and 330···signal processing circuit (PRC).

Claims

1. a pixel section in which pixels performing photoelectric conversion are arranged in a matrix; A readout circuit having an analog-to-digital (AD) conversion function for converting a pixel signal, which is read out as a voltage signal from the pixel to a signal line, from an analog signal to a digital signal, The pixel signal read out from the pixel is A readout reset signal and a readout signal are sequentially read out from the pixels, The read circuit includes: an AD conversion unit that converts the pixel signal read out to the signal line from an analog signal to a digital signal; a pixel signal monitoring unit that changes a conversion code of the AD conversion unit to a code different from a normal conversion code when a signal level of a readout reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, The pixel signal monitoring unit a first reference voltage having a level corresponding to the signal level of the read reset signal at the time of reset; a second reference voltage having a level higher than the first reference voltage; a comparison unit that compares a readout reset signal of the pixel signal read out to the signal line and input to a signal input unit with the reference voltage set in a voltage setting unit, The comparison unit is a potential of the signal input unit is initialized to the first reference voltage during a reset period of the pixel and during a predetermined period at the start of readout of the readout reset signal after reset release, and after the initialization, a readout reset signal of the pixel signal read out to the signal line is compared with the second reference voltage set in a voltage setting unit, and when a signal level of the readout reset signal exceeds the second reference voltage, a conversion code of the AD conversion unit is fixed to a predetermined code; The comparison unit is A first comparator; A sampling capacitor; a first auto-zero switch that can be switched between a connected state and a non-connected state by a first reset signal; a first reference switch that can be switched between a connected state and a non-connected state by a first reset signal; a second reference switch that can be switched between a connected state and a non-connected state by a second reset signal having a phase opposite to that of the first reset signal; The first comparator is a first input terminal connected to the sampling capacitor and connected to a supply line of the pixel signal via the sampling capacitor; the auto-zero switch is connected between the first input terminal and an output terminal; the first reference switch is connected between the second input terminal and a supply line of the first reference voltage; the second reference switch is connected between the second input terminal and a supply line of the second reference voltage; The comparison unit is a second comparator for processing the output signal of the first comparator; The first comparator performs a comparison operation in response to an active first enable signal; The second comparator performs a comparison operation in response to a second enable signal that becomes active after the first enable signal. Solid-state imaging device.

2. The pixel signal monitoring unit When a signal level of a readout reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, the conversion code of the AD conversion unit is fixed to a predetermined code.

2. The solid-state imaging device according to claim 1.

3. The second reference voltage is set to a voltage value between the first reference voltage and a voltage corresponding to a black level when high-luminance light is incident.

3. The solid-state imaging device according to claim 1.

4. The comparison unit is After the first enable signal becomes active and the first comparator enters a comparison operation, the first reset signal is active for a predetermined period, the first input terminal and the output terminal of the first comparator are connected, the first reference voltage is supplied to the second input terminal, the first comparator performs an auto-zero operation, and the first reference voltage and the offset voltage of the first comparator are held in the signal input section; the first reset signal becomes inactive, the auto-zero switch and the first reference switch become in a non-connected state, and the reference voltage is switched from the first reference voltage to the second reference voltage, and after the switching, the second enable signal becomes active and the second comparator enters a comparison operation; When the signal level of the read reset signal exceeds the second reference voltage, the conversion code of the AD conversion unit is fixed to a predetermined code.

4. The solid-state imaging device according to claim 1.

5. The pixel signal monitoring unit a latch unit that latches a detection signal that detects that the signal level of at least the read reset signal among the output signals of the comparator has exceeded the second reference voltage, and outputs a flag signal to the AD converter that instructs the AD converter to fix a conversion code of the AD converter to a predetermined code.

5. The solid-state imaging device according to claim 1.

6. The read circuit includes: an amplifier that amplifies the pixel signal propagated through the signal line and outputs the amplified pixel signal to the pixel signal monitoring unit and the AD conversion unit; The first reference voltage is set to a voltage value equal to the output voltage of the amplifier during auto-zero.

6. The solid-state imaging device according to claim 1.

7. The pixel is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the electric charge stored in the photoelectric conversion element during a transfer period; a floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a source follower element that converts the charge of the floating diffusion into a voltage signal with a gain according to the amount of charge; A reset element that resets the floating diffusion to a predetermined potential during a reset period.

7. The solid-state imaging device according to claim 1.

8. A clamp circuit that clamps the black level to a predetermined level is disposed in the column readout system of the pixel signal.

8. A solid-state imaging device according to claim 1.

9. a pixel section in which pixels performing photoelectric conversion are arranged in a matrix; A readout circuit having an analog-to-digital (AD) conversion function for converting a pixel signal, which is read out as a voltage signal from the pixel to a signal line, from an analog signal to a digital signal, The read circuit includes: an AD conversion unit that converts the pixel signal read out to the signal line from an analog signal to a digital signal; a pixel signal monitoring unit that changes a conversion code of the AD conversion unit to a code different from a normal conversion code when a signal level of a readout reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage. A method for driving a solid-state imaging device, comprising: The pixel signal read out from the pixel is A readout reset signal and a readout signal are sequentially read out from the pixels, In the read circuit, When a signal level of a readout reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, changing the conversion code of the AD conversion unit to a code different from a normal conversion code; In the pixel signal monitoring unit, a first reference voltage having a level corresponding to the signal level of the read reset signal at the time of reset; a second reference voltage having a level higher than the first reference voltage; In the comparison section, a readout reset signal of the pixel signal read out to the signal line input to a signal input unit can be compared with the reference voltage set in a voltage setting unit, In the comparison unit, a potential of the signal input unit is initialized to the first reference voltage during a reset period of the pixel and during a predetermined period at the start of readout of the readout reset signal after reset release, and after the initialization, a readout reset signal of the pixel signal read out to the signal line is compared with the second reference voltage set in a voltage setting unit, and when a signal level of the readout reset signal exceeds the second reference voltage, a conversion code of the AD conversion unit is fixed to a predetermined code; The comparison unit is A first comparator; A sampling capacitor; a first auto-zero switch that can be switched between a connected state and a non-connected state by a first reset signal; a first reference switch that can be switched between a connected state and a non-connected state by a first reset signal; a second reference switch that can be switched between a connected state and a non-connected state by a second reset signal having a phase opposite to that of the first reset signal; The first comparator is a first input terminal connected to the sampling capacitor and connected to a supply line of the pixel signal via the sampling capacitor; the auto-zero switch is connected between the first input terminal and an output terminal; the first reference switch is connected between the second input terminal and a supply line of the first reference voltage; the second reference switch is connected between the second input terminal and a supply line of the second reference voltage; The comparison unit is a second comparator for processing an output signal of the first comparator; The first comparator performs a comparison operation in response to an active first enable signal; The second comparator performs a comparison operation in response to a second enable signal that becomes active after the first enable signal. A method for driving a solid-state imaging device.

10. A solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device; The solid-state imaging device includes: a pixel section in which pixels performing photoelectric conversion are arranged in a matrix; A readout circuit having an analog-to-digital (AD) conversion function for converting a pixel signal, which is read out as a voltage signal from the pixel to a signal line, from an analog signal to a digital signal, The pixel signal read out from the pixel is A readout reset signal and a readout signal are sequentially read out from the pixels, The read circuit includes: an AD conversion unit that converts the pixel signal read out to the signal line from an analog signal to a digital signal; a pixel signal monitoring unit that changes a conversion code of the AD conversion unit to a code different from a normal conversion code when a signal level of a readout reset signal of the pixel signal read out to the signal line exceeds a preset reference voltage, The pixel signal monitoring unit a first reference voltage having a level corresponding to the signal level of the read reset signal at the time of reset; a second reference voltage having a level higher than the first reference voltage; a comparison unit that compares a readout reset signal of the pixel signal read out to the signal line and input to a signal input unit with the reference voltage set in a voltage setting unit, The comparison unit is a potential of the signal input unit is initialized to the first reference voltage during a reset period of the pixel and during a predetermined period at the start of readout of the readout reset signal after reset release, and after the initialization, a readout reset signal of the pixel signal read out to the signal line is compared with the second reference voltage set in a voltage setting unit, and when a signal level of the readout reset signal exceeds the second reference voltage, a conversion code of the AD conversion unit is fixed to a predetermined code; The comparison unit is A first comparator; A sampling capacitor; a first auto-zero switch that can be switched between a connected state and a non-connected state by a first reset signal; a first reference switch that can be switched between a connected state and a non-connected state by a first reset signal; a second reference switch that can be switched between a connected state and a non-connected state by a second reset signal having a phase opposite to that of the first reset signal; The first comparator is a first input terminal connected to the sampling capacitor and connected to a supply line of the pixel signal via the sampling capacitor; the auto-zero switch is connected between the first input terminal and an output terminal; the first reference switch is connected between the second input terminal and a supply line of the first reference voltage; the second reference switch is connected between the second input terminal and a supply line of the second reference voltage; The comparison unit is a second comparator for processing the output signal of the first comparator; The first comparator performs a comparison operation in response to an active first enable signal; The second comparator performs a comparison operation in response to a second enable signal that becomes active after the first enable signal. electronic equipment.

Images