Conversion Lookaside Buffer Invalidation
JP7629005B2Active Publication Date: 2025-02-12ARM LTD
Patent Information
- Application Number
- JP2022515726
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2019-09-10
- Filing Date
- 2020-08-26
- Publication Date
- 2025-02-12
- Estimated Expiration
- 2040-08-26
Smart Images
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Abstract
One type of invalidation instruction is described that targets a translation lookaside buffer (TLB), specifically a first type of TLB. The first type of TLB stores combined stage 1 and 2 entries that depend on both stage 1 translation data and stage 2 translation data, and is configured to ignore TLB invalidation commands that invalidate based on a first set of one or more invalidation conditions, including address-based invalidation conditions that depend on matching intermediate addresses. A second type of TLB other than the first type ignores invalidation commands triggered by the first type of TLB invalidation instruction. This approach helps limit the performance impact of stage 2 invalidations in systems that support combined stage 1 and 2 TLBs that cannot be invalidated by intermediate addresses.
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Citation Information
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