Semiconductor Device

Abstract

To increase pressure resistance of the periphery and vicinity of a semiconductor device.SOLUTION: Each of a plurality of trench 101 in a group, includes: an insulation layer 133 formed in the trench in an active region; a gate electrode 137 arranged on an upper part in the insulation layer 133; and a first field plate 135 formed in a lower part in the insulation layer 133. A first trench 102 is formed in an outer peripheral region on the outer side of the active region. A second trench 153 is formed on the outer side of the first trench 102. A mesa portion 103 is formed between the first and second trenches (102, 153). Second and third field plates (136, 147) are respectively formed in insulation layers of the first trench 102 and the second trench 153. The mesa portion 103 has a second conductive semiconductor region electrically connected to the outermost side of a first main electrode. A gate electrode is not included on the upper portion in the first trench 102.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of increasing the breakdown voltage of the outer periphery and its vicinity. [Background technology]

[0002] Trench-gate power MOSFETs are widely used as power semiconductor devices that perform switching operations of large currents. Patent Document 1 discloses a semiconductor device in which a field plate electrode is provided under the gate electrode in the gate trench of the MOSFET. This device can increase the impurity concentration in the drift region, thereby reducing the on-resistance. In addition, since a field electrode is provided under the gate electrode, the gate input charge Qg can be increased. Furthermore, a structure is disclosed in which a trench peripheral structure is provided in the peripheral region around the MOSFET, in which a field electrode is provided in the trench. The device disclosed in Patent Document 1 has a plurality of trenches 110 in a peripheral region 300, as shown in Fig. 1 of Patent Document 1. A field plate electrode 130 is provided inside the plurality of trenches 110. An auxiliary electrode 50 and a gate electrode 60 are provided inside the trench 100 provided in the active region 200. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6624370 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the device disclosed in Patent Document 1, the depletion layer under the outermost region connected to the source electrode 80 (i.e., the region between the trench 110 in the peripheral region 300 and the outermost trench 100 in the active region 200) may penetrate between the trenches 100. In this case, the distance between the gate electrode 60 inside the outermost trench 100 in the active region 200 and the depletion layer becomes short, so that it may not be possible to ensure a sufficient breakdown voltage.

[0005] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing the breakdown voltage of the outer periphery and its vicinity. [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor device according to one or more embodiments includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on an upper portion of the first semiconductor region; a third semiconductor region of the first conductivity type provided on an upper portion of the second semiconductor region; The above 3 a first main electrode electrically connected to the semiconductor region and the second semiconductor region; a plurality of trenches provided in an active region within the first semiconductor region; a first trench provided in a peripheral region outside the active region; a second trench provided outside the first trench in a peripheral region outside the active region; a mesa portion provided between the first and second trenches; a first insulating layer disposed within the first trench; a second insulating layer disposed within the second trench; a second field plate disposed within the first insulating layer of the first trench; a third field plate disposed within the second insulating layer of the second trench; Each of the plurality of trench groups includes: an insulating layer provided within the trench; a gate electrode provided in an upper portion of the insulating layer; a first field plate provided in a lower portion of the insulating layer; the mesa portion has a second conductivity type semiconductor region electrically connected to the first main electrode at its outermost portion, The first trench has a gate electrode in an upper portion thereof. First, the thickness of the first insulating layer in the first trench at the same height as the gate electrode is greater than the thickness of the insulating layer on the side surface of the gate electrode provided in the upper portion of the insulating layer in the plurality of trench groups. It is characterized by: Effect of the Invention

[0007] According to the above configuration, it is possible to provide a semiconductor device that can increase the breakdown voltage of the outer periphery and its vicinity. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a top view illustrating a portion of a semiconductor device according to one or more embodiments. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB of FIG. [Figure 4] FIG. 4 is a view showing a cross section taken along line BB of FIG. 1 according to another embodiment. [Diagram 5] FIG. 5 is a view showing a cross section taken along line CC in FIG. [Figure 6] FIG. 6 is a view showing a cross section taken along line DD of FIG. [Figure 7] FIG. 7 is a view showing an E-E cross section of FIG. [Figure 8] 8(a) and (b) are cross-sectional views showing schematic electric potential distribution. [Figure 9] 9(a) and (b) are cross-sectional views showing schematic electric field distribution. [Figure 10] 10(a) and (b) are cross-sectional views that diagrammatically show impact ionization and are diagrams for explaining the breakdown point. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] With reference to the drawings, one or more embodiments will be described in detail. In the following description of the drawings, the same or similar parts may be denoted by the same or similar reference numerals. The description of the drawings is schematic, and the relationship between thickness and dimensions, the ratio of thickness of each layer, etc. are merely examples, and do not limit the technical idea of ​​the invention. In addition, the relationship and ratio of dimensions may differ between drawings. In the following embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but the conductivity types may be selected in reverse, and the first conductivity type may be p-type and the second conductivity type may be n-type. In the following description, when describing the positional relationship of the members, the terms "upper", "lower", "right side", "left side", etc. are used as necessary based on the orientation of the referenced drawings, but do not limit the technical idea of ​​the invention. In addition, the terms "upper", "lower", "right side", "left side", etc. may be used when the members are not in contact with each other. In addition, when describing the direction, the X-axis and the Y-axis may be illustrated. Here, mainly in the cross-sectional view, the "lateral direction" and the "length direction" may mean the X-direction shown in the drawing or the direction opposite to the X-direction. Moreover, the "height direction" may refer to the Y direction in the drawings, and the "depth direction" may refer to the direction opposite to the Y direction in the drawings.

[0010] FIG. 1 is a top view showing a part of a semiconductor device according to one or more embodiments. In this semiconductor device, a peripheral trench 154 is provided near the outer periphery of the semiconductor device so as to surround an active region. Here, in a direction (X direction) perpendicular to the longitudinal direction of the trench 101 in the active region, a plurality of first connection trenches 105 are provided at intervals to connect with the outer trench 153 forming the mesa portion with the further outer trench. A trench 153 is provided on the outer periphery side of the target mesa portion 103. The trench 153 forms the target mesa portion 103 and is connected to the first connection trench 105. The peripheral trench 154 is connected to the plurality of first connection trenches 105. The plurality of first connection trenches 105 are connected to the trench 153. The peripheral trench 154, the first connection trench 105, and the trench 153 may be made of the same material, or may be formed integrally. The semiconductor device of the embodiment includes an active region including some or all of the trenches 101, and an outer periphery region including an outer periphery trench 154 surrounding the periphery of the active region. The active region has a trench group including a plurality of trenches 101 including some or all of the trenches 101. The second connection trench 151 is provided so as to connect the ends of the trenches continuing from the longitudinal direction (Y direction) of the trench 101 in the active region to each other. In a plan view, the multiple third connection trenches 152 are provided at intervals from each other in a location that is not on an extension line of the trench 101, and are provided so as to connect the connection trench 151 and the outer periphery trench 154. In addition, the end of the second connection trench 151 is connected to the end of the trench 153, and as a whole surrounds the active region.

[0011] FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1. In this semiconductor device, a drift region 113 is provided on the drain region 116. In the drift region 113, a trench 102, one or more trenches 100 provided inside the trench 102 in the peripheral region, and a base region 114 are provided. An insulating layer 133 is filled inside the trench 100. A field plate 135 and a gate electrode 137 spaced apart from the field plate 135 are provided inside the insulating layer 133 provided in the trench 100. A field plate 136 is provided inside the insulating layer 133 provided in the trench 102, but a gate electrode 137 is not provided. The trench 139 includes the peripheral trench 154 shown in FIG. 1, the first connection trench 105, and an outer trench 153 forming the target mesa portion 103, and they are connected to each other. A field plate 141 is provided inside the insulating layer 133 filled in the trench 139. Here, the field plate 142 connects the field plates (141, 142, 140) provided inside the insulating layer 133 of the peripheral trench 154, the first connection trench 105, and the outer trench 153 to each other. Here, the drift region 113 may be a first conductive type semiconductor, the base region 114 may be a second conductive type semiconductor, the source region 115 may be a first conductive type semiconductor, and the drain region 116 may be a first conductive type semiconductor. Note that the source region 115 is not provided between the trench 102 and the trench 139, between the trench 102 and the trench 100, or between the trenches 100 and 100.

[0012] An interlayer insulating film 117 is provided on a portion of the drift region 113 where the base region 114 is not provided, the field plate 142 in the trench 139, the field plate 136 in the trench 102, the gate electrode 137, and the upper portion of the base region 114. A source electrode 111 is provided on the upper portion of the interlayer insulating film 117. Here, the source electrode 111 is electrically connected to the source region 115, the base region 114, and the field plate 142 via a contact hole 143 provided in the interlayer insulating film 117. A first protective film 119 is provided on the upper portion of the source electrode 111, and a second protective film 121 is provided on the upper portion of the first protective film 119.

[0013] Here, only the field plate 136 is provided inside the inner trench (mesa trench) 102 forming the outermost mesa portion 103 where the source electrode 111 is connected to the base region 114. In other words, an insulating layer 133 is provided inside the trench 100 in the other peripheral region, and a field plate 135 and a gate electrode 137 are provided inside the insulating layer 133. On the other hand, the gate electrode 137 is not provided inside the inner trench 102 forming the outermost mesa portion 103 where the source electrode 111 is connected to the base region 114. As shown in FIG. 2, in the outermost mesa portion 103 where the source electrode 111 is connected to the second conductive type semiconductor region such as the base region 114, the depletion layer 161 is in a state of intruding upward into the mesa portion compared to the mesa portion 103 further inside, but since the gate electrode 137 is not provided, the distance between the depletion layer 161 and the gate electrode can be secured. This makes it possible to suppress electric field concentration near the trench 102 and to suppress deterioration of the breakdown voltage.

[0014] FIG. 3 is a cross-sectional view taken along the line BB in FIG. 1. The cross-sectional view in FIG. 3 omits the source electrode 111 and the first protective film 119 on the upper surface of the interlayer insulating film 117 and the like. In this semiconductor device, the drift region 113 has a trench 100 in the peripheral region, a trench 101 in the active region, a source region 115, and a target mesa portion 103 sandwiched between the peripheral trench 154, the trench 102, and the outer trench 153. The source region 115 in the active region is provided between the trenches 101, and is electrically connected to the source electrode 111 and the base region 114 through a hole or groove in the interlayer insulating film 117 provided between the trenches 101. The second conductive type semiconductor region 145 provided outside the outer trench 153 is separated from the base region 114 and is at a floating potential.

[0015] Here, only the field plate 136 is provided inside the trench 102, and no gate electrode is provided. The height of the upper surface of the field plate 136 in the trench 102 where no gate electrode is provided is approximately the same as the height of the upper surface of the field plate 135 in the trench 101 in the active region. Also, the height of the upper surface of the field plate 147 in the trench 153 outside the target mesa portion 103 is approximately the same as the height of the upper surface of the field plate 135 in the trench 101 in the active region. In other words, the height of the upper surfaces of the field plates 136 and 147 in the trench 102 where no gate electrode is provided and in the outer trench 153 are not provided up to the height of the upper surface of the gate electrode, and the upper parts of these trenches are filled with an insulating layer. This alleviates the dense distribution of the electric field near the sidewall of the trench 102, and also alleviates the electric field at the breakdown point at the bottom of the trench 102. This increases the breakdown voltage of the semiconductor device.

[0016] Moreover, gate electrode 137 is not provided in first connection trench 105. Furthermore, field plate 141 in outer peripheral trench 154 extending in the longitudinal direction (Y direction) of trench 153 is connected to source electrode 111 via a contact hole provided in interlayer insulating film 117. Although a displacement current is likely to occur in field plate 147 in outer trench 153, the displacement current flows from field plate 147 through field plate 142 in the first connection trench and through field plate 141 in trench 154 to source electrode 111. As a result, the path along which the displacement current flows to source electrode 111 is shorter than when field plate 135 is pulled up only from the end of trench 153 in the longitudinal direction (Y direction), and the displacement current of the semiconductor device can be reduced.

[0017] FIG. 4 is another embodiment of the BB cross section of FIG. 1. In the cross section of FIG. 4, the source electrode 111 on the upper surface of the interlayer insulating film 117 and the like is omitted. In this semiconductor device, the drift region 113 has a trench 100 in the peripheral region, a trench 101 in the active region, a source region 115, and a target mesa portion 103 sandwiched between a peripheral trench 154, a trench 102, and an outer trench 153. Only a field plate 136 is provided inside the trench 102, and no gate electrode is provided. Here, the height of the top surface of the field plate 147 in the trench 153 outside the target mesa portion 103 is higher than the height of the top surface of the field plate 136 in the trench 102, and may be approximately the same as the height of the top surface of the gate electrode 137 in the trench 101 in the active region. This configuration also reduces the electric field at the top of trench 102, the electric field at the breakdown point at the bottom of the trench, and the electric field near the sidewall of peripheral trench 154 on the outer trench 153 side. This makes it possible to increase the breakdown voltage.

[0018] FIG. 5 is a cross-sectional view of CC in FIG. 1. In this semiconductor device, the drift region 113 includes a trench 100 including a peripheral trench 154, field plates 135 and 141, and a gate electrode 137, and a second conductive type semiconductor region 145 extending from the end of the trench 100 to the outer periphery. Here, the second conductive type semiconductor region 145 is separated from the base region 114 and is at a floating potential. The dotted line region inside the trench 100 corresponds to the second connection trench 151. Here, the gate electrode 137 does not extend to the outer periphery side, that is, to the peripheral trench 154 side, beyond the field plate 135. This makes it possible to ensure the distance between the depletion layer 161 and the gate electrode 137. In addition, the semiconductor device of the embodiment does not need to be provided with the second conductive type semiconductor region 145. Here, the cross section of the trench 101 in the active region may also be the same as the cross section of the peripheral trench 154.

[0019] 6 is a DD cross-sectional view of FIG. 1. In this semiconductor device, drift region 113 includes trench 152 including field plate 141, and base region 114. The dotted lines in trench 152 are peripheral trench 154 and second connection trench 151, and each trench is connected to trench 152. Field electrode 141 is provided in peripheral trench 154 and second connection trench 151 via an insulating layer. The field plate in second connection trench 151 is connected to field plate 147 in trench 153. Here, base region 114 extends to the side of trench 152. The field plate 142 in trench 152 is cut away at a portion facing base region 114, forming an L-shaped cross section. The field plate in the second connection trench 151 surrounded by the dotted line may be higher than the height of the top surface of the field plate 136 in the trench 102, similar to the height of the top surface of the field plate 147 in the outer trench 153 shown in Figure 4, or may be approximately the same height as the top surface of the gate electrode 137 in the trench 101 in the active region.

[0020] Fig. 7 is an E-E cross-sectional view of Fig. 1. In this semiconductor device, the drift region 113 includes a peripheral trench 154, a second connection trench 151, a second conductive type semiconductor region 145, and a base region 114.

[0021] 8(a) and 8(b) are diagrams showing potential distribution, and FIG. 8(a) is a diagram obtained by simulating the potential distribution near trenches 153, 155, and 100 shown in FIG. 4. The trench in the center of FIG. 8(a) corresponds to trench 102 in FIG. 2. That is, the height of the top surface of the field plate inside the trench in the center of FIG. 8(a) is almost the same as the height of the top surface of the field plate inside the trench on the right side of the drawing. Furthermore, the trench in the center of the drawing does not have a gate electrode similar to that in the trench on the right side of the drawing, and is filled with an insulating film. On the other hand, the height of the top surface of the field plate inside the trench in the center of FIG. 8(b) of the comparative example is higher than the height of the top surface of the field plate in the trench on the right side of the drawing, and is almost the same as the height of the top surface of the gate electrode. It can be seen that the concentration of potential lines near insulating layer 133 on the sidewall of the trench in the center of FIG. 8(a) is sparser than the concentration of potential lines near insulating layer 133 on the sidewall of the trench in the center of FIG. 8(b). As described above, according to the semiconductor device according to one or more embodiments, it is possible to increase the breakdown voltage in and around the outer periphery.

[0022] Figures 9(a) and 9(b) are diagrams showing electric field distributions in the same structure as Figures 8(a) and 8(b). It can be seen that the electric field strength in the region of the central trench in Figure 9(a) where no gate electrode or field plate is provided and which is filled with an insulating layer (near the region indicated by P in Figure 9(a)) is lower than the electric field strength in the insulating layer on the sidewall of the central trench in Figure 9(b) (near the insulating layer indicated by Q in Figure 9(b)).

[0023] Figures 10(a) and 10(b) are diagrams showing the breakdown points in the same structure as Figures 8(a) and 8(b). In Figure 10(b), the breakdown occurs at the bottom of the trench on the left side, and the impact is large, while in Figure 10(a), the breakdown occurs at the bottom of the trench on the right side, and the impact is smaller than in Figure 10(b).

[0024] As described above, in one or more of the above embodiments, by not providing an electrode in the upper part of the trench 102, the breakdown voltage can be improved.

[0025] One or more of the above-described embodiments can be applied to semiconductor devices including MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulate Gate Bipolar Transistors).

[0026] Although the embodiments have been described above, the descriptions and drawings forming part of this disclosure do not limit the present invention, and various alternative embodiments, embodiments, and operation techniques will become apparent to those skilled in the art. Thus, the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined by the invention-specific matters related to the appropriate claims from the above description. [Industrial Applicability]

[0027] The invention is particularly applicable to power semiconductor devices. [Explanation of symbols]

[0028] 100,101,102,139 Trench 103 Target Mesa 105 First Connection Trench 111,115 Source Region 113 Drift Region 114 Base Area 116 Drain Region 117 Interlayer insulating film 121 Second protective film 133 Insulating Layer 135, 136, 140, 141, 142, 147 Field Plates 137 Gate electrode 143 Contact hole 145 Second Conductive Type Semiconductor Region 151 Second Connection Trench 153,154 Periphery trench 161 Depletion Layer

Claims

1. A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on an upper portion of the first semiconductor region; a third semiconductor region of the first conductivity type provided on an upper portion of the second semiconductor region; a first main electrode electrically connected to the third semiconductor region and the second semiconductor region; a plurality of trenches provided in an active region in the first semiconductor region; a first trench provided in a peripheral region outside the active region; a second trench provided outside the first trench in a peripheral region outside the active region; a mesa portion provided between the first and second trenches; a first insulating layer disposed within the first trench; a second insulating layer disposed within the second trench; a second field plate disposed within the first insulating layer of the first trench; a third field plate disposed within the second insulating layer of the second trench; Each of the plurality of trench groups includes: an insulating layer provided within the trench; a gate electrode provided in an upper portion of the insulating layer; a first field plate provided in a lower portion of the insulating layer; the mesa portion has a second conductivity type semiconductor region electrically connected to the first main electrode at its outermost portion, A semiconductor device characterized in that the first trench does not have a gate electrode in an upper portion of the first trench, and the thickness of the first insulating layer in the first trench at the same height as the gate electrode is thicker than the thickness of the insulating layer on a side of the gate electrode provided in the upper portion of the insulating layer of the plurality of trench groups.

2. A semiconductor device as described in claim 1, characterized in that the height of an upper surface of at least a portion of the third field plate is higher than the height of an upper surface of the gate electrode.

3. 3. The semiconductor device according to claim 1, wherein the height of an upper surface of the third field plate is higher than the height of an upper surface of the second field plate.

4. 4. The semiconductor device according to claim 1, wherein the third field plate is connected to the first main electrode at a plurality of points in a longitudinal direction.

5. A semiconductor device, a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on an upper portion of the first semiconductor region; a third semiconductor region of the first conductivity type provided on an upper portion of the second semiconductor region; a first main electrode electrically connected to the third semiconductor region and the second semiconductor region; a plurality of trenches provided in an active region in the first semiconductor region; a first trench provided in a peripheral region outside the active region; a second trench provided outside the first trench in a peripheral region outside the active region; a mesa portion provided between the first and second trenches; a first insulating layer disposed within the first trench; a second insulating layer disposed within the second trench; a second field plate disposed within the first insulating layer of the first trench; a third field plate disposed within the second insulating layer of the second trench; Each of the plurality of trench groups includes: an insulating layer provided within the trench; a gate electrode provided in an upper portion of the insulating layer; a first field plate provided in a lower portion of the insulating layer; the mesa portion has a second conductivity type semiconductor region electrically connected to the first main electrode at its outermost portion, the first trench does not have a gate electrode in an upper portion within the first trench; The semiconductor device includes: a peripheral trench provided outside the second trench; a third insulating layer disposed within the outer periphery trench; a fourth field plate provided within the insulating layer; a first connection trench connecting the outer circumferential trench and the second trench at a plurality of locations in a longitudinal direction; a fifth field plate provided in the first connection trench via an insulating layer and connecting the third field plate and the fourth field plate, a fourth field plate connected to the first main electrode;

6. A semiconductor device as described in claim 1 or 5, characterized in that inside the first trench, positions corresponding to the gate electrodes arranged in the multiple groups of trenches are filled with only an insulating layer.

7. A semiconductor device as described in claim 1 or 5, characterized in that the thickness of the first insulating layer in the first trench at the same height as the gate electrodes provided in the multiple trench groups is thicker than the thickness of the first insulating layer on the side of the second field plate in the first trench.

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