Semiconductor Device

Abstract

To provide a technology capable of improving avalanche resistance by efficiently discharging carriers at turn-off in a horizontal semiconductor device having a trench gate.SOLUTION: A semiconductor device 1 includes a semiconductor layer 10, a plurality of trench gates 30 extending deep from one main surface of the semiconductor layer 10, and a trench drain 40 extending deep from one main surface of the semiconductor layer 10. The semiconductor layer 10 has a P-type hole drain region 16 provided in the region between the trench gate 30 and the trench drain 40. The hole drain region 16 is electrically connected to a source electrode 24 and configured such that the lower end thereof is positioned deeper than a body region 13.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Development of lateral semiconductor devices with trench gates is underway, and examples are disclosed in Patent Documents 1 and 2. In this type of semiconductor device, electrons are injected vertically from a source electrode disposed on one main surface of a semiconductor layer through a channel formed on a side surface of the trench gate. The injected electrons can flow to a drain electrode disposed on one main surface of the semiconductor layer through a trench drain extending from one main surface of the semiconductor layer toward the depth. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-184553 A [Patent Document 2] JP 2016-062967 A Summary of the Invention [Problem to be solved by the invention]

[0004] According to the study by the present inventors, it has been found that in this type of semiconductor device, when an avalanche phenomenon occurs at the time of turn-off, holes tend to remain in the region between the trench gate and the trench drain. There is a concern that the heat generated by the remaining holes will reduce the avalanche resistance. This specification provides a technology that can improve the avalanche resistance in a lateral semiconductor device having a trench gate by efficiently discharging carriers at the time of turn-off. [Means for solving the problem]

[0005] One embodiment of the semiconductor device disclosed in this specification may include a semiconductor layer, a drain electrode, a source electrode, a plurality of trench gates, and a trench drain. The drain electrode is disposed on at least a portion of one of the main surfaces of the semiconductor layer. The source electrode is disposed on at least a portion of the one of the main surfaces of the semiconductor layer. Each of the plurality of trench gates extends from the one of the main surfaces of the semiconductor layer toward a deep portion. Each of the plurality of trench gates has a gate electrode and a gate insulating film covering a bottom surface and a side surface of the gate electrode. The trench drain extends from the one of the main surfaces of the semiconductor layer toward a deep portion. The trench drain has a drain connection region electrically connected to the drain electrode, and a drain insulating film covering a side surface of the drain connection region. The semiconductor layer may have a drain region of a first conductivity type, a drift region of a first conductivity type provided on the drain region and having a lower impurity concentration than the drain region, a body region of a second conductivity type provided on the drift region and electrically connected to the source electrode, a source region of a first conductivity type provided on the body region and electrically connected to the source electrode, and a carrier discharge region of a second conductivity type provided in a region between the trench gate and the trench drain. Each of the trench gates is provided so as to extend from one main surface of the semiconductor layer beyond the body region to reach the drift region. The trench drain is provided so as to extend from one main surface of the semiconductor layer beyond the drift region to reach the drain region. The carrier discharge region is electrically connected to the source electrode and configured such that a lower end is located at a depth equal to or greater than the depth of the body region. In this semiconductor device, a carrier discharge region is provided in a region between the trench gate and the trench drain. Therefore, when the semiconductor device is turned off, carriers are efficiently discharged through the carrier discharge region, so that carriers are prevented from remaining in the region between the trench gate and the trench drain. This semiconductor device can have a high avalanche resistance.

[0006] In the semiconductor device of the above embodiment, the carrier ejection region may be in contact with a side surface of the trench drain.

[0007] In the semiconductor device of the above embodiment, the gate insulating film may have a lower gate insulating film covering the bottom surface and lower portions of the side surfaces of the gate electrode, and an upper gate insulating film covering upper portions of the side surfaces of the gate electrode and having a thickness thinner than that of the lower gate insulating film. The upper gate insulating film is in contact with the body region. This semiconductor device can achieve both low channel resistance and high dielectric breakdown of the gate insulating film.

[0008] In the semiconductor device of the above embodiment, the semiconductor layer may further include a body contact region of a second conductivity type provided on the body region and having a higher impurity concentration than the body region. The body contact region is disposed between the trench gate and the trench drain and is in contact with the source electrode. In this semiconductor device, carriers are more efficiently discharged when the semiconductor device is turned off, so that carriers are further prevented from remaining in the region between the trench gate and the trench drain. This semiconductor device can have a high avalanche resistance. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a main portion of a semiconductor device; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] As shown in FIG. 1, the semiconductor device 1 is a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10, a drain electrode 22 disposed on at least a portion of the surface of the semiconductor layer 10, a source electrode 24 disposed on at least a portion of the surface of the semiconductor layer 10, a plurality of trench gates 30, and a plurality of trench drains 40. For the purpose of clarity in the drawing, only one of the plurality of trench gates 30 is labeled with a reference symbol. The material of the semiconductor layer 10 is not particularly limited, and may be, for example, silicon. Alternatively, the material of the semiconductor layer 10 may be, for example, silicon carbide or a nitride semiconductor. The semiconductor layer 10 is made of N + A drain region 11 of N type, a drift region 12 of N type, a body region 13 of P type, + a body contact region 14 of N + 1. The n-type source region 15 and the p-type hole ejection region 16 .

[0011] The drain region 11 is an N-type region containing a high concentration of n-type impurities, and is provided in the back layer portion of the semiconductor layer 10, and is disposed at a position exposed on the back surface of the semiconductor layer 10.

[0012] The drift region 12 is an N-type region containing n-type impurities at a lower concentration than the drain region 11, and is provided on the drain region 11 and disposed between the drain region 11 and the body region 13. The drift region 12 contacts the bottom surface and lower portions of the side surfaces of each of the multiple trench gates 30.

[0013] The body region 13 is a P-type region containing p-type impurities, and is provided in a surface layer portion of the semiconductor layer 10 and is disposed between the drift region 12 and the source region 15. The body region 13 is disposed in a region between adjacent trench gates 30 and contacts an upper portion of each of the side surfaces of the multiple trench gates 30. The body region 13 is further disposed in a region between the trench gate 30 and the trench drain 40.

[0014] The body contact region 14 is a P-type region containing a higher concentration of p-type impurities than the body region 13, and is provided on the body region 13. The body contact region 14 is provided in a surface layer portion of the semiconductor layer 10, and is disposed at a position exposed on the surface of the semiconductor layer 10, and is in ohmic contact with the source electrode 24. Therefore, the body region 13 is electrically connected to the source electrode 24 via the body contact region 14. The body contact region 14 is disposed in a region between adjacent trench gates 30. The body contact region 14 is further disposed in a region between the trench gate 30 and the trench drain 40.

[0015] The source region 15 is an N-type region containing a high concentration of n-type impurities, and is provided in the surface layer portion of the semiconductor layer 10, disposed at a position exposed on the surface of the semiconductor layer 10, and in ohmic contact with the source electrode 24. The source region 15 is disposed in a region between adjacent trench gates 30, and contacts an upper portion of each of the side surfaces of the multiple trench gates 30. The source region 15 is not disposed in a region between the trench gate 30 and the trench drain 40.

[0016] The hole ejection region 16 is a p-type region containing p-type impurities, and is provided in a region between the trench gate 30 and the trench drain 40. In this example, the hole ejection region 16 is arranged so as to be in contact with the side surface of the trench drain 40. The hole ejection region 16 is further configured so that its upper end is in contact with the body region 13 and protrudes from the body region 13 toward a deep portion. In this example, the lower end of the hole ejection region 16 is located deeper than the body region 13 and further deeper than the trench gate 30. Alternatively, the lower end of the hole ejection region 16 may be located shallower than the trench gate 30. In this manner, the hole ejection region 16 is electrically connected to the source electrode 24 via the body region 13 and the body contact region 14. The hole ejection region 16 is also arranged away from the drain region 11. Alternatively, the hole ejection region 16 may be in contact with the drain region 11.

[0017] The trench gates 30 are arranged between a pair of trench drains 40, and are arranged, for example, in a stripe shape when viewed in a plan view, although this is not particularly limited. Therefore, the trench gates 30 are arranged side by side along at least one direction when viewed in a plan view. In this example, three trench gates 30 are arranged between the pair of trench drains 40, but at least two or more trench gates 30 may be arranged. Each of the trench gates 30 extends from the surface of the semiconductor layer 10 toward the deep part, and is provided so as to reach the drift region 12 beyond the body region 13.

[0018] Each of the trench gates 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the drain electrode 22 and the source electrode 24 via an interlayer insulating film. The gate insulating film 34 covers the bottom and side surfaces of the gate electrode 32 and separates the gate electrode 32 from the semiconductor layer 10. In this example, the gate insulating film 34 has a lower gate insulating film 34a and an upper gate insulating film 34b. The lower gate insulating film 34a covers the lower part of the bottom and side surfaces of the gate electrode 32. The upper gate insulating film 34b covers the upper part of the side surfaces of the gate electrode 32 and has a thickness smaller than that of the lower gate insulating film 34a. The entire body region 13 at a portion separating the drift region 12 and the source region 15 is in contact with the upper gate insulating film 34b. Since the thin upper gate insulating film 34b is in contact with the portion of the body region 13 where a channel (inversion layer) is formed, the channel resistance is suppressed to be low. On the other hand, since the thick lower gate insulating film 34a contacts the bottom and lower portions of the side surfaces of the trench gate 30, dielectric breakdown in these portions is suppressed.

[0019] Each of the trench drains 40 extends from the surface of the semiconductor layer 10 toward the deep part, and is provided so as to reach the drain region 11 beyond the body region 13 and the drift region 12. Each of the trench drains 40 has a drain connection region 42 and a drain insulating film 44. The drain connection region 42 is an N-type region containing a high concentration of n-type impurities, and is provided at a position where the upper end is exposed on the surface of the semiconductor layer 10, and the lower end is in contact with the drain region 11. The drain connection region 42 is in ohmic contact with the drain electrode 22. Therefore, the drain region 11 is electrically connected to the drain electrode 22 via the drain connection region 42. The drain connection region 42 may be any conductor, for example, a metal. The drain insulating film 44 covers the side surface of the drain connection region 42 and separates the drain connection region 42 from the drift region 12, the hole ejection region 16, the body region 13, and the body contact region 14.

[0020] Next, the operation of the semiconductor device 1 will be described. When a voltage that makes the drain electrode 22 more positive than the source electrode 24 is applied between the drain electrode 22 and the source electrode 24, and a voltage higher than the threshold voltage is applied to the gate electrode 32, the semiconductor device 1 turns on. At this time, a channel (inversion layer) is formed in the body region 13 that contacts the side surface of the trench gate 30. Electrons injected from the source region 15 connected to the source electrode 24 are injected into the drift region 12 through the channel formed in the body region 13. The electrons injected into the drift region 12 further flow vertically in the drift region 12, and then flow to the drain electrode 22 disposed on the surface of the semiconductor layer 10 through the drain region 11 and the drain connection region 42. In this way, conduction occurs between the drain electrode 22 and the source electrode 24, and the semiconductor device 1 turns on.

[0021] When the voltage applied to the gate electrode 32 falls below the threshold voltage, the channel in the body region 13 disappears, and the semiconductor device 1 turns off. If a high voltage such as a surge is applied when the semiconductor device 1 is turned off, avalanche breakdown may occur near the bottom surface of the trench gate 30. In particular, avalanche breakdown may occur near the bottom surface of the outermost trench gate 30, i.e., the trench gate 30 facing the region between the trench gate 30 and the trench drain 40.

[0022] The holes generated by this avalanche breakdown tend to remain in the region between the trench gate 30 and the trench drain 40. However, in the semiconductor device 1, the hole discharge region 16 is provided in the region between the trench gate 30 and the trench drain 40. Therefore, the holes generated near the bottom surface of the trench gate 30 by the avalanche breakdown are efficiently discharged to the source electrode 24 via the hole discharge region 16. Furthermore, in the semiconductor device 1, the body contact region 14 is also provided in the region between the trench gate 30 and the trench drain 40, so that the holes passing through the hole discharge region 16 are efficiently discharged to the source electrode 24. Therefore, the semiconductor device 1 can have a high avalanche resistance since heat generation caused by the remaining holes is suppressed when the semiconductor device 1 is turned off.

[0023] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]

[0024] 1: Semiconductor device 10: Semiconductor layer 11: Drain region 12: Drift region 13: Body area 14: Body contact area 15: Source area 16: Hole drainage area 22: Drain electrode 24: Source electrode 30: Trench Gate 32: Gate electrode 34: Gate insulating film 40: Trench drain 42: Drain connection area 44: Drain insulating film

Claims

1. A semiconductor layer; a drain electrode disposed on at least a portion of one major surface of the semiconductor layer; a source electrode disposed on at least a portion of the one principal surface of the semiconductor layer; a plurality of trench gates extending from the one main surface of the semiconductor layer toward a deep portion, each of the plurality of trench gates having a gate electrode and a gate insulating film covering a bottom surface and a side surface of the gate electrode; a trench drain extending from the one main surface of the semiconductor layer toward a deep portion, the trench drain having a drain connection region electrically connected to the drain electrode and a drain insulating film covering a side surface of the drain connection region; The semiconductor layer is a drain region of a first conductivity type; a first conductivity type drift region provided on the drain region and having a lower impurity concentration than the drain region; a body region of a second conductivity type provided on the drift region and electrically connected to the source electrode; a source region of a first conductivity type provided on the body region and electrically connected to the source electrode; a second conductivity type carrier ejection region provided in a region between the trench gate and the trench drain; each of the plurality of trench gates is provided from one main surface of the semiconductor layer, across the body region, and reaching the drift region; the trench drain is provided so as to extend from one main surface of the semiconductor layer, across the drift region, and reach the drain region; the carrier discharge region is electrically connected to the source electrode and has a lower end located at a depth equal to or greater than the depth of the body region; the source region is disposed in a region between adjacent ones of the trench gates, and is not disposed in a region between the trench gate and the trench drain; A semiconductor device, wherein a lower end of the carrier discharge region is located shallower than the trench gate.

2. The semiconductor device according to claim 1 , wherein the carrier ejection region is in contact with a side surface of the trench drain.

3. The gate insulating film is a lower gate insulating film covering the bottom surface and lower portions of the side surfaces of the gate electrode; an upper gate insulating film covering an upper portion of the side surface of the gate electrode and having a thickness smaller than that of the lower gate insulating film; 3. The semiconductor device according to claim 1, wherein the upper gate insulating film is in contact with the body region.

4. The semiconductor layer further comprises: a body contact region of a second conductivity type provided on the body region and having a higher impurity concentration than the body region; 4. The semiconductor device according to claim 1, wherein the body contact region is disposed in a region between the trench gate and the trench drain, and is in contact with the source electrode.

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