Acoustic wave device, filter, multiplexer, wafer and method for manufacturing same

Abstract

To provide an elastic wave device capable of improving the bonding strength between an interlayer and a piezoelectric substrate.SOLUTION: An elastic wave device comprises: a support substrate 10; a first interlayer 12 provided on the support substrate 10 and having average grain diameter of crystal grains of 100 nm or more; a second interlayer 13 provided on the first interlayer 12, where roughness of an interface 32 with the first interlayer 12 is smaller than that of an interface between the support substrate 10 and the first interlayer 12, the second interlayer being thinner than the first interlayer 12, and having average grain diameter of crystal grains of less than 100 nm; a piezoelectric substrate 14 directly bonded onto the second interlayer 13; and a pair of comb-shaped electrodes 20 provided on the piezoelectric substrate 14.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an acoustic wave device, a filter, a multiplexer, and a wafer, and a method for manufacturing the same. [Background technology]

[0002] As an acoustic wave device used in communication devices such as smartphones, an acoustic wave device having an IDT (Interdigital Transducer) having a pair of comb-shaped electrodes on a piezoelectric substrate is known. It is known to use a composite substrate in which a piezoelectric substrate is bonded onto a support substrate in an acoustic wave device (e.g., Patent Document 1). It is known to provide an intermediate layer between the support substrate and the piezoelectric substrate (e.g., Patent Documents 2 and 3). It is known to make the bonding surface of the support substrate an uneven surface (e.g., Patent Document 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-034363 A [Patent Document 2] International Publication No. 2018 / 203430 [Patent Document 3] International Publication No. 2019 / 082806 [Patent Document 4] JP 2020-161899 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the structure in which an intermediate layer is provided between the support substrate and the piezoelectric substrate as in Patent Documents 2 and 3, spurious signals cannot be sufficiently suppressed. Spurious signals can be suppressed by making the interface between the support substrate and the intermediate layer a rough or uneven surface. However, when the intermediate layer is formed on a rough or uneven surface, sufficient bonding strength between the intermediate layer and the piezoelectric substrate cannot be maintained.

[0005] The present invention has been made in consideration of the above-mentioned problems, and an object of the present invention is to improve the bonding strength between an intermediate layer and a piezoelectric substrate. [Means for solving the problem]

[0006] The present invention is an acoustic wave device comprising a support substrate, a first intermediate layer provided on the support substrate and having an average crystal grain size of 100 nm or more, a second intermediate layer provided on the first intermediate layer, the interface roughness with the first intermediate layer being smaller than the interface roughness between the support substrate and the first intermediate layer, being thinner than the first intermediate layer, and having an average crystal grain size of less than 100 nm, a piezoelectric substrate directly bonded onto the second intermediate layer, and a pair of comb electrodes provided on the piezoelectric substrate.

[0007] In the above configuration, the piezoelectric substrate may have an amorphous layer at the interface with the second intermediate layer.

[0008] In the above configuration, the arithmetic mean roughness between the support substrate and the first intermediate layer may be 10 nm or more, and the arithmetic mean roughness between the first intermediate layer and the second intermediate layer may be 1 nm or less.

[0009] In the above configuration, the second intermediate layer may have a thickness that is 0.1 times or less the thickness of the first intermediate layer.

[0010] In the above configuration, the thickness of the piezoelectric substrate may be equal to or less than twice the average pitch of the electrode fingers of the pair of comb-shaped electrodes.

[0011] In the above configuration, the second intermediate layer may be mainly composed of aluminum oxide or aluminum oxynitride.

[0012] In the above configuration, the first intermediate layer may be composed mainly of aluminum oxide or aluminum oxynitride.

[0013] In the above configuration, the piezoelectric substrate may be a lithium tantalate substrate or a lithium niobate substrate.

[0014] The present invention is a filter including the above acoustic wave device.

[0015] The present invention is a multiplexer including the above filter.

[0016] The present invention is a wafer comprising: a support substrate; a first intermediate layer provided on the support substrate, the first intermediate layer having an average crystal grain size of 100 nm or more; a second intermediate layer provided on the first intermediate layer, the second intermediate layer having an interface roughness with the first intermediate layer smaller than the interface roughness between the support substrate and the first intermediate layer, being thinner than the first intermediate layer, and the second intermediate layer having an average crystal grain size of less than 100 nm; and a piezoelectric substrate directly bonded onto the second intermediate layer.

[0017] The present invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a first intermediate layer having an average crystal grain size of 100 nm or more on a support substrate; planarizing a surface of the first intermediate layer; and forming a surface of the first intermediate layer by: the roughness of the interface with the first intermediate layer is smaller than the roughness of the interface between the support substrate and the first intermediate layer; The method for manufacturing a wafer includes the steps of: forming a second intermediate layer that is thinner than the first intermediate layer and has an average crystal grain size of less than 100 nm; and directly bonding a piezoelectric substrate onto the second intermediate layer.

[0018] In the above configuration, the step of directly bonding the piezoelectric substrate onto the second intermediate layer can include the step of directly bonding the piezoelectric substrate onto the second intermediate layer by using a surface activation method. Effect of the Invention

[0019] According to the present invention, the bonding strength between the intermediate layer and the piezoelectric substrate can be improved. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1(a) is a plan view of an acoustic wave resonator in accordance with a first embodiment, and FIG. 1(b) is a cross-sectional view taken along line AA of FIG. 1(a). [Diagram 2] 2(a) to 2(e) are cross-sectional views (part 1) illustrating a method for manufacturing the acoustic wave resonator in accordance with the first embodiment. [Diagram 3] 3(a) to 3(c) are cross-sectional views (part 2) illustrating the method for manufacturing the acoustic wave resonator in accordance with the first embodiment. [Figure 4] 4(a) to 4(c) are schematic diagrams showing a method for bonding substrates in the first embodiment. [Diagram 5] 5(a) and 5(b) are diagrams showing AFM images of the upper surface of the intermediate layer in the wafer manufacturing method in Example 1. FIG. [Figure 6] 6(a) to 6(c) are diagrams showing AFM images of the upper surface of the intermediate layer in the wafer manufacturing method in Example 1. FIG. [Figure 7] 7(a) and 7(b) are diagrams showing AFM images of the upper surface of the intermediate layer in the wafer manufacturing method in Comparative Example 1. FIG. [Figure 8] 8(a) and 8(b) are schematic plan views of a wafer in a wafer manufacturing method in Comparative Example 1. FIG. [Figure 9] 9(a) to 9(c) are AFM images of the top surface of the intermediate layer in experiment 3. [Figure 10] 10(a) to 10(c) are AFM images of the top surface of the intermediate layer in experiment 3. [Figure 11] FIG. 11(a) is a circuit diagram of a filter in accordance with the second embodiment, and FIG. 11(b) is a circuit diagram of a duplexer in accordance with a first modified example of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, embodiments of the present invention will be described with reference to the drawings. EXAMPLES

[0022] Fig. 1(a) is a plan view of an acoustic wave resonator according to a first embodiment, and Fig. 1(b) is a cross-sectional view taken along line AA of Fig. 1(a). The arrangement direction of the electrode fingers is the X direction, the extension direction of the electrode fingers is the Y direction, and the lamination direction of the support substrate and the piezoelectric substrate is the Z direction. The X direction, Y direction, and Z direction do not necessarily correspond to the X-axis direction and Y-axis direction of the crystal orientation of the piezoelectric substrate. When the piezoelectric substrate is a rotated Y-cut X-propagation substrate, the X direction is the X-axis direction of the crystal orientation.

[0023] As shown in FIG. 1(a) and FIG. 1(b), an intermediate layer 12 is provided on a support substrate 10, and an intermediate layer 13 is provided on the intermediate layer 12. A piezoelectric substrate 14 is bonded onto the intermediate layer 13. An interface 30 between the support substrate 10 and the intermediate layer 12 is a rough or uneven surface. An interface 32 between the intermediate layers 12 and 13 and an interface 34 between the intermediate layer 12 and the piezoelectric substrate 14 are mirror surfaces. The arithmetic mean roughness Ra of the interface 30 is, for example, 10 nm or more, for example, 100 nm or more. The arithmetic mean roughness Ra of the interfaces 32 and 34 is, for example, 1 nm or less, for example, 0.1 nm or less. The thicknesses of the intermediate layers 12, 13 and the piezoelectric substrate 14 are T2, T3 and T4, respectively. Note that since the interface 32 is a rough or uneven surface, the thickness T2 is an average thickness.

[0024] An acoustic wave resonator 26 is provided on the piezoelectric substrate 14. The acoustic wave resonator 26 has an IDT 22 and a reflector 24. The reflectors 24 are provided on both sides of the IDT 22 in the X direction. The IDT 22 and the reflector 24 are formed by the metal film 16 on the piezoelectric substrate 14.

[0025] The IDT 22 includes a pair of comb electrodes 20 facing each other. The comb electrodes 20 include a plurality of electrode fingers 18 and a bus bar 19 to which the plurality of electrode fingers 18 are connected. The region where the electrode fingers 18 of the pair of comb electrodes 20 intersect is an intersection region 25. The length of the intersection region 25 is the aperture length. The pair of comb electrodes 20 are provided facing each other such that the electrode fingers 18 are substantially alternated in at least a part of the intersection region 25. The acoustic wave excited by the plurality of electrode fingers 18 in the intersection region 25 propagates mainly in the X direction. The pitch of the electrode fingers 18 of one of the pair of comb electrodes 20 is substantially the wavelength λ of the acoustic wave. If the pitch of the plurality of electrode fingers 18 (the pitch between the centers of the electrode fingers 18) is D, the pitch of the electrode fingers 18 of one comb electrode 20 is the pitch D of two electrode fingers 18. The reflector 24 reflects the acoustic wave (surface acoustic wave) excited by the electrode fingers 18 of the IDT 22. As a result, the acoustic wave is confined within the intersection region 25 of the IDT 22.

[0026] The main mode elastic wave 46 (surface acoustic wave, for example, SH (Shear Horizontal) wave) excited by the IDT 22 is mainly reflected at the interfaces 32 and 34 between the piezoelectric substrate 14 and the intermediate layers 12 and 13, and is confined in the piezoelectric substrate 14. This makes it possible to suppress loss. The elastic wave 48, such as a bulk wave, which is faster than the main mode elastic wave, passes through the interfaces 32 and 34, is reflected at the interface 30 between the support substrate 10 and the intermediate layer 12, and returns to the IDT 22. This causes spurious signals. By making the interface 30 a rough or uneven surface, the elastic wave 48 is scattered at the interface 30. In addition, by making the intermediate layer 12 thick, the elastic wave 48 is attenuated when it propagates through the intermediate layer 12. This makes it possible to suppress spurious signals.

[0027] The piezoelectric substrate 14 is a single crystal lithium tantalate (LiTaO3) substrate or a single crystal lithium niobate (LiNbO3) substrate, for example, a rotated Y-cut X-propagation lithium tantalate substrate or a rotated Y-cut X-propagation lithium niobate substrate. When the main mode elastic wave 46 is an SH wave, the piezoelectric substrate 14 is, for example, a 36° to 48° rotated Y-cut X-propagation lithium tantalate substrate.

[0028] The support substrate 10 is, for example, a silicon substrate, a sapphire substrate, an alumina substrate, a spinel substrate, a quartz substrate, a silicon carbide substrate, or a silicon nitride substrate. The silicon substrate is a single crystal or polycrystalline Si substrate, the sapphire substrate is a single crystal Al2O3 substrate, the alumina substrate is a polycrystalline or amorphous Al2O3 substrate, the spinel substrate is a polycrystalline MgAl2O4 substrate, the quartz substrate is a single crystal SiO2 substrate, the silicon carbide substrate is a single crystal, polycrystalline or amorphous SiC substrate, and the silicon nitride substrate is a polycrystalline or amorphous SiN substrate. The linear expansion coefficient of the support substrate 10 in the X direction is smaller than the linear expansion coefficient of the piezoelectric substrate 14 in the X direction. This can reduce the frequency temperature dependency of the acoustic wave resonator.

[0029] The intermediate layer 12 is, for example, an aluminum oxide layer, an aluminum nitride oxide layer, a silicon nitride layer, or a silicon layer. The sound velocity of the bulk wave propagating through the intermediate layer 12 is faster than the sound velocity of the bulk wave propagating through the piezoelectric substrate 14. This allows the elastic wave 46 to be confined within the piezoelectric substrate 14. The intermediate layer 12 is polycrystalline, and the average grain size of the crystal grains is 100 nm or more.

[0030] The intermediate layer 13 is, for example, an aluminum oxide layer or an aluminum oxynitride (AlON) layer, and is a bonding layer that bonds the intermediate layer 12 to the piezoelectric substrate 14. The intermediate layer 13 is polycrystalline, and the average grain size of the crystal grains is less than 100 nm.

[0031] In order to have some degree of elastic wave energy present within the piezoelectric substrate 14, the thickness T4 of the piezoelectric substrate 14 is, for example, 1λ or less. In order to confine the elastic waves within the piezoelectric substrate 14, the thickness T2 of the intermediate layer 12 is, for example, 1λ or more. Since the support substrate 10 supports the other layers, the thickness of the support substrate 10 is, for example, 50 μm or more. The thickness T3 of the intermediate layer 13 is, for example, 5 nm or more since it functions as a bonding layer, and is 100 nm or less since it does not reflect the elastic waves.

[0032] The metal film 16 is a film whose main component is, for example, aluminum (Al), copper (Cu) or molybdenum (Mo). An adhesive film such as a titanium (Ti) film or a chromium (Cr) film may be provided between the electrode fingers 18 and the piezoelectric substrate 14. The adhesive film is thinner than the electrode fingers 18. An insulating film may be provided so as to cover the electrode fingers 18. The insulating film functions as a protective film or a temperature compensation film.

[0033] The wavelength λ of the elastic wave is, for example, 1 μm to 6 μm. When two electrode fingers 18 are considered as one pair, the number of pairs is, for example, 20 to 300 pairs. The duty ratio of the IDT 22 is a value obtained by dividing the thickness of the electrode fingers 18 by the pitch of the electrode fingers 18, and is, for example, 30% to 70%. The aperture length of the IDT 22 is, for example, 10λ to 50λ.

[0034] [Production method of Example 1] 2(a) to 3(c) are cross-sectional views showing a method for manufacturing an acoustic wave resonator according to the first embodiment. As shown in FIG. 2(a), the upper surface of the support substrate 10 is made rough or uneven. When the upper surface of the support substrate 10 is made irregularly rough, the upper surface of the support substrate 10 is polished with a coarse abrasive to make the upper surface of the support substrate 10 rough. When the upper surface of the support substrate 10 is made regular (i.e., periodic) uneven, as in Patent Document 4, a mask layer having regular openings is provided on the upper surface of the support substrate 10, and the upper surface of the support substrate 10 is etched using the mask layer as a mask to make the upper surface of the support substrate 10 uneven.

[0035] As shown in FIG. 2(b), the intermediate layer 12 is formed on the support substrate 10 by, for example, CVD (Chemical Vapor Deposition), sputtering, or vacuum deposition. The upper surface of the intermediate layer 12 is rough or uneven. The thickness of the intermediate layer 12 is T2'. The thickness T2' is an average thickness. As shown in FIG. 2(c), the upper surface of the intermediate layer 12 is polished to flatten it. For example, CMP (Chemical Mechanical Polishing) is used to polish the upper surface of the intermediate layer 12. As a result, the thickness of the intermediate layer 12 becomes T2.

[0036] As shown in Fig. 2(d), an intermediate layer 13 is formed on the intermediate layer 12. For example, a CVD method, a sputtering method, or a vacuum deposition method is used to form the intermediate layer 12. The thickness of the intermediate layer 13 is T3. As shown in Fig. 2(e), the upper surface of the intermediate layer 13 and the lower surface of the piezoelectric substrate 14 are irradiated with atoms, ions, etc. (arrow 55). This activates the upper surface of the intermediate layer 13 and the lower surface of the piezoelectric substrate 14.

[0037] As shown in Fig. 3(a), the upper surface of the intermediate layer 13 is brought into contact with the lower surface of the piezoelectric substrate 14, and the upper surface of the intermediate layer 13 and the lower surface of the piezoelectric substrate 14 are directly bonded to each other at room temperature. As shown in Fig. 3(b), the upper surface of the piezoelectric substrate 14 is flattened, for example, by CMP. This results in a thickness of the piezoelectric substrate 14 of T4. A wafer 28 is completed in which the piezoelectric substrate 14 is laminated on the support substrate 10. As shown in Fig. 3(c), a metal film 16 is formed on the piezoelectric substrate 14, thereby forming an IDT 22 and a reflector 24 on the piezoelectric substrate 14.

[0038] 4(a) to 4(c) are schematic diagrams showing a method of bonding substrates in Example 1. As shown in FIG. 4(a), the intermediate layer 13 has an intermediate layer 13a and an amorphous layer 13b. When the intermediate layer 13a is polycrystalline aluminum oxide, the amorphous layer 13b has atoms 50 which are aluminum atoms and oxygen atoms. When the intermediate layer 13a is polycrystalline aluminum oxynitride, the amorphous layer 13b has atoms 50 which are aluminum atoms, nitrogen atoms, and oxygen atoms. As shown by arrow 55, atoms 54 or ions are irradiated onto the upper surface of the intermediate layer 13 in a vacuum. The region irradiated with the atoms 54 or ions is the amorphous layer 13b, and has atoms 50 and the irradiated atoms 54.

[0039] As shown in FIG. 4(b), the piezoelectric substrate 14 has a piezoelectric layer 14a and an amorphous layer 14b. The piezoelectric substrate 14a is a single crystal piezoelectric substrate, and in the case of a lithium tantalate substrate, it has atoms 52 which are tantalum atoms, lithium atoms, and oxygen atoms, and in the case of a lithium niobate substrate, it has atoms which are niobium atoms, lithium atoms, and oxygen atoms. As indicated by arrow 55, atoms 54 or ions are irradiated onto the lower surface of the piezoelectric substrate 14 in a vacuum. The region irradiated with the atoms 54 or ions is the amorphous layer 14b, and has atoms 52 and the irradiated atoms 54.

[0040] In Fig. 4(a) and Fig. 4(b), the atoms 54 are inert elements (e.g., rare gas elements) such as argon (Ar), xenon (Xe), or krypton (Kr). The atoms 54 or ions are irradiated as an ion beam, a neutralized beam, or plasma. As a result, unbonded dangling bonds are formed on the upper surface of the amorphous layer 13b and the lower surface of the amorphous layer 14b (i.e., the upper surface of the amorphous layer 13b and the lower surface of the amorphous layer 14b are activated). When argon ions are used, for example, a surface activated bonding (SAB) device may be used.

[0041] As shown in FIG. 4(c), while maintaining a vacuum, the support substrate 10 and the piezoelectric substrate 14 are pressed as indicated by the arrow 56 to bond the amorphous layers 13b and 14b together. At this time, the dangling bonds formed on the surfaces of the amorphous layers 13b and 14b bond with each other to form a strong bond. This bonds the intermediate layer 13 and the piezoelectric substrate 14 together. This bonding is performed at room temperature (for example, 100° C. or lower and −20° C. or higher, preferably 80° C. or lower and 0° C. or higher), so that thermal stress can be suppressed. Whether or not bonding is performed at room temperature can be confirmed by checking the temperature dependency of the residual stress. In other words, the residual stress is smallest at the bonding temperature.

[0042] The amorphous layer 13b is mainly composed of the constituent elements of the intermediate layer 13 and contains an element for surface activation (e.g., argon). The amorphous layer 14b is mainly composed of the constituent elements of the piezoelectric substrate 14 and contains an element for surface activation (e.g., argon). When the intermediate layer 13 is an aluminum oxide film, the amorphous layer 13b is mainly composed of aluminum and oxygen and contains an element for surface activation (e.g., argon). When the intermediate layer 13 is an aluminum oxide nitride film, the amorphous layer 13b is mainly composed of aluminum, nitrogen and oxygen and contains an element for surface activation (e.g., argon). When the piezoelectric substrate 14 is a lithium tantalate substrate, the amorphous layer 14b is mainly composed of tantalum, lithium and oxygen and contains an element for surface activation (e.g., argon). When the piezoelectric substrate 14 is a lithium niobate substrate, the amorphous layer 14b is mainly composed of niobium, lithium and oxygen and contains an element for surface activation (e.g., argon).

[0043] The total thickness of the amorphous layers 13b and 14b is preferably greater than 0 nm, and more preferably 0.5 nm or more. This can improve the bonding between the intermediate layer 13 and the piezoelectric substrate 14. The total thickness of the amorphous layers 13b and 14b is preferably 10 nm or less, and more preferably 5 nm or less. This can suppress deterioration of the characteristics of the acoustic wave resonator.

[0044] [Experiment 1] 2(a) to 3(b) in Example 1 were carried out to fabricate the wafer 28. The method of fabricating the wafer 28 in Experiment 1 is as follows. In FIG. 2(a), a sapphire substrate having an irregular rough surface with an arithmetic mean roughness Ra of about 150 nm as the upper surface is prepared as the support substrate 10. The size of the support substrate 10 is 4 inches. In FIG. 2(b), an aluminum oxide layer is formed as the intermediate layer 12 on the support substrate 10 by using a sputtering method. At this time, the arithmetic mean roughness Ra of the upper surface of the intermediate layer 12 is 15 nm to 27 nm. As shown in FIG. 2(c), the upper surface of the intermediate layer 12 is flattened by using a CMP method. This results in a thickness T2 of the intermediate layer 12. At this time, the arithmetic mean roughness Ra of the upper surface of the intermediate layer 12 is about 0.2 nm. In FIG. 2(d), an aluminum nitride oxide layer having a thickness T3 is formed as the intermediate layer 13 on the intermediate layer 12 by using a sputtering method. In Fig. 2(e), argon is irradiated onto the lower surface of piezoelectric substrate 14 and the upper surface of intermediate layer 13 to activate the lower surface of piezoelectric substrate 14 and the upper surface of intermediate layer 13. In Fig. 3(a), the lower surface of piezoelectric substrate 14 and the upper surface of intermediate layer 13 are bonded at room temperature. In Fig. 3(b), the upper surface of piezoelectric substrate 14 is polished using the CMP method to make the thickness of piezoelectric substrate 14 T4.

[0045] Figures 5(a) and 5(b) are diagrams showing AFM images of the upper surface of the intermediate layer in the wafer manufacturing method in Example 1. Figure 5(a) is an AFM image of the upper surface of intermediate layer 12 in Figure 2(b), and Figure 5(b) is an AFM image of the upper surface of intermediate layer 13 in Figure 2(d). Thicknesses T2' and T3 of intermediate layers 12 and 13 are 10 μm and 40 nm.

[0046] As shown in FIG. 5(a), crystal grains 35 can be observed on the upper surface of the intermediate layer 12. The grain size of the crystal grains 35 is 100 nm to 2 μm. The average grain size of the crystal grains 35 is calculated as follows. The number of crystal grains 35 in the 10 μm×10 μm image of FIG. 5(a) is counted. The crystal grains 35 on the periphery of the image are counted as 1 / 2. The average area s of the crystal grains 35, s=S / N, can be calculated by dividing the area S (e.g., 10 μm×10 μm) by the number N of the crystal grains 35. Assuming that the cross section of the crystal grains 35 is circular and the average grain size of the crystal grains 35 is r, s=π×(r / 2)2 From this, the average grain size r of the crystal grains 35 can be calculated. In the image of FIG. 5(a), the average grain size r of the crystal grains is 1629 nm.

[0047] As shown in Fig. 5(b), the grain size of the crystal grains 35 on the upper surface of the intermediate layer 13 is very small. The grain size of the crystal grains 35 is 2 nm to 100 nm. The average grain size of the crystal grains 35 calculated from an enlarged 0.1 µm x 0.1 µm image of Fig. 5(b) in a similar manner to Fig. 5(a) is 17 nm.

[0048] Figures 6(a) to 6(c) are diagrams showing AFM images of the upper surface of the intermediate layer in the manufacturing method of the wafer in Example 1. Figures 6(a) to 6(c) are AFM images of the upper surface of the intermediate layer 12 in Figure 2(b) when the thickness T2' of the intermediate layer 12 is 4 μm, 6 μm, and 10 μm, respectively. The method of forming the intermediate layer 12 is the same as that shown in Figure 5(a). As shown in Figures 6(a) to 6(c), as the thickness T2' of the intermediate layer 12 increases, the grain size of the crystal grains 35 tends to increase.

[0049] [Comparative Example 1: Experiment 2] As Comparative Example 1, in Fig. 2(c), the upper surface of the intermediate layer 12 was polished by about 2 µm to form an intermediate layer 12 with a thickness T2 of 10 µm. A wafer was produced in which the intermediate layer 13 in Fig. 2(d) was not formed and a piezoelectric substrate 14 was directly bonded onto the intermediate layer 12. The other manufacturing methods for the wafer were the same as those in Figs. 2(a) to 3(b) of Example 1.

[0050] 7(a) and 7(b) are diagrams showing AFM images of the upper surface of the intermediate layer in the manufacturing method of the wafer in Comparative Example 1. Fig. 7(a) is an AFM image of the upper surface of the intermediate layer 12 in Fig. 2(b), and Fig. 7(b) is an AFM image of the upper surface of the intermediate layer 12 in Fig. 2(c). As shown in Fig. 7(a), crystal grains with a grain size of 1 μm to 2 μm are observed on the upper surface of the intermediate layer 12 before CMP, and the unevenness of the upper surface is large. As shown in Fig. 7(b), the unevenness of the upper surface is reduced by polishing the upper surface of the intermediate layer 12 by the CMP method.

[0051] 8(a) and 8(b) are schematic plan views of a wafer in the wafer manufacturing method in Comparative Example 1. FIG. 8(a) is a schematic plan view of the wafer in FIG. 3(b) after the piezoelectric substrate 14 has been polished. As shown in FIG. 8(a), in the wafer after the piezoelectric substrate 14 is bonded, the intermediate layer 12 and the piezoelectric substrate 14 appear to be bonded. As shown in FIG. 8(b), when the top surface of the piezoelectric substrate 14 is polished so that the thickness T4 of the piezoelectric substrate 14 becomes equal to or less than the wavelength λ, vortex-shaped peeling of the piezoelectric substrate 14 is observed on the front surface of the wafer 28.

[0052] Thus, in Comparative Example 1, even if the grain size of the crystal grains 35 of the intermediate layer 12 is large and the upper surface of the intermediate layer 12 is highly uneven as shown in FIG. 7(a), the upper surface of the intermediate layer 12 is flattened by planarizing the upper surface of the intermediate layer 12 using the CMP method as shown in FIG. 7(b). As shown in FIG. 8(a), it appears that the piezoelectric substrate 14 is directly bonded onto the intermediate layer 12. However, as shown in FIG. 8(b), when the piezoelectric substrate 14 is polished, the piezoelectric substrate 14 peels off from the intermediate layer 12. Thus, when the crystal grains 35 of the intermediate layer 12 are large, the bonding strength between the intermediate layer 12 and the piezoelectric substrate 14 decreases even if the upper surface of the intermediate layer 12 is flattened.

[0053] [Experiment 3] To investigate the reason why the crystal grains in intermediate layer 12 become larger, intermediate layer 12 was formed on support substrate 10 by sputtering, and the upper surface of intermediate layer 12 was observed with an AFM, for cases where the upper surface of support substrate 10 was a rough surface and a mirror surface. When the upper surface of support substrate 10 was a rough surface, the arithmetic mean roughness Ra was approximately 150 nm. When the upper surface of support substrate 10 was a mirror surface, the arithmetic mean roughness Ra was 0.1 nm or less.

[0054] 9(a) to 9(c) are AFM images of the upper surface of the intermediate layer in Experiment 3. The upper surface of the support substrate 10 is a rough surface. In FIGS. 9(a) to 9(c), the thickness T2' of the intermediate layer 12 is 4 μm, 6 μm, and 10 μm, respectively. As shown in FIGS. 9(a) to 9(c), the grain size of the crystal grains 35 is 1 μm or more in all wafers with the thickness T2' of the intermediate layer 12.

[0055] Figures 10(a) to 10(c) are AFM images of the upper surface of the intermediate layer in experiment 3. The upper surface of the support substrate 10 is a mirror surface. In Figures 10(a) to 10(c), the thickness T2' of the intermediate layer 12 is 4 μm, 6 μm, and 10 μm, respectively. As shown in Figures 10(a) to 10(c), the grain size of the crystal grains 35 is 400 nm or less in all wafers with the thickness T2' of the intermediate layer 12. It appears that the grain size of the crystal grains 35 increases as the thickness T2' increases.

[0056] As in experiment 3, crystal grains 35 in intermediate layer 12 become large when the upper surface of support substrate 10 is rough or uneven. Also, as shown in Figures 6(a) to 6(c), the grain size of crystal grains 35 increases as thickness T2' of intermediate layer 12 increases. As in experiment 2, when crystal grains 35 in intermediate layer 12 are large, the bonding strength decreases when piezoelectric substrate 14 is directly bonded onto intermediate layer 12, even if the upper surface of intermediate layer 12 is flattened using the CPM method.

[0057] [Experiment 4] In the wafer manufacturing method of Example 1, the thickness T2' of the intermediate layer 12 was changed to 4 μm, 6 μm, and 10 μm. The thickness T3 of the intermediate layer 13 was changed to 10 nm, 20 nm, and 40 nm. The thickness T4 of the piezoelectric substrate 14 was set to 1.2 μm. The amount of polishing [μm] using the CMP method in FIG. 2(c) was changed to 1.3 μm, 2.0 μm, and 2.5 μm. In FIG. 3(b), peeling of the piezoelectric substrate 14 in the wafer 28 was observed.

[0058] Table 1 shows the degree of peeling of the piezoelectric substrate 14 in the first experiment. [Table 1]

[0059] The degree of peeling was expressed as "A," "B," "C," and "D." "A" indicates that no peeling of the piezoelectric substrate 14 was observed more than 5 mm inward from the outer periphery of the wafer 28. "B" indicates that no peeling of the piezoelectric substrate 14 was observed more than 15 mm inward from the outer periphery of the wafer 28. "C" indicates that no peeling of the piezoelectric substrate 14 was observed more than 30 mm inward from the outer periphery of the wafer 28. "D" indicates that peeling of the piezoelectric substrate 14 was observed over the entire surface of the wafer 28. The degree of peeling worsens from "A" to "D." The peeling in Figure 8(b) of Experiment 2 corresponds to "D."

[0060] As shown in Table 1, in most cases, peeling of the piezoelectric substrate 14 is improved from Fig. 8(b) of Experiment 2. Peeling of the piezoelectric substrate 14 is improved when the thickness T2 of the intermediate layer 12 is thin and the thickness T3 of the intermediate layer 13 is thick.

[0061] As shown in FIG. 2(b), when the intermediate layer 12 (first intermediate layer) is formed on a support substrate having an uneven surface, the average grain size of the crystal grains 35 becomes 100 nm or more. As shown in FIG. 2(c), the surface of the intermediate layer 12 is flattened. As shown in Comparative Example 1 of Experiment 2, when the piezoelectric substrate 14 is directly bonded on the intermediate layer 12 in this state, the bonding strength of the piezoelectric substrate 14 decreases. Therefore, in Example 1, as shown in FIG. 2(d), an intermediate layer 13 (second intermediate layer) having an average grain size of less than 100 nm and thinner than the intermediate layer 12 is formed on the surface of the intermediate layer 12. As shown in FIG. 2(e) and FIG. 3(a), the piezoelectric substrate 14 is directly bonded on the intermediate layer 13. This allows the manufacture of a wafer having a high bonding strength between the intermediate layer 12 and the piezoelectric substrate 14.

[0062] When wafer 28 is manufactured in this manner, interface 30 between support substrate 10 and intermediate layer 12 in the wafer and acoustic wave device is a rough or uneven surface. The roughness of interface 32 between intermediate layers 12 and 13 is less than the roughness of interface 30. The roughness of interface 34 between intermediate layer 13 and piezoelectric substrate 14 is less than the roughness of interface 30.

[0063] The average grain size of the crystal grains 35 can be determined as follows. An AFM image, a SEM (Scanning Electron Microscope) image, or a TEM (Transmission Electron Microscope) image containing 10 or more, preferably 20 or more, crystal grains is obtained. The image is preferably an image in a planar direction. In the obtained image, the area S of the image is divided by the number N of the crystal grains 35 to determine the average area s of the crystal grains 35, ie, s=S / N. s=π×(r / 2) 2 The value of r that satisfies the above equation can be taken as the average particle size.

[0064] If the average grain size of crystal grains 35 in intermediate layer 12 becomes large, the bonding strength between piezoelectric substrate 14 and intermediate layer 12 decreases, and therefore intermediate layer 13 is provided. From this viewpoint, the average grain size of crystal grains 35 in intermediate layer 12 is preferably 200 nm or more, more preferably 500 nm or more, and even more preferably 1000 nm or more. If the average grain size of crystal grains 35 in intermediate layer 12 becomes too large, it becomes difficult to flatten the upper surface of intermediate layer 12. From this viewpoint, the average grain size of crystal grains 35 in intermediate layer 12 is preferably 10 μm or less, and more preferably 5 μm or less.

[0065] As the average grain size of the crystal grains in intermediate layer 13 increases, the bonding strength between piezoelectric substrate 14 and intermediate layer 13 decreases. From this viewpoint, the average grain size of the crystal grains in intermediate layer 13 is preferably 50 nm or less, and more preferably 20 nm or less. The average grain size of the crystal grains in intermediate layer 13 is preferably 1 / 10 or less, more preferably 1 / 20 or less, and even more preferably 1 / 50 or less of the average grain size of crystal grains 35 in intermediate layer 12.

[0066] If the arithmetic mean roughness Ra of the interface 30 is large, the crystal grains 35 of the intermediate layer 12 become large, and the piezoelectric substrate 14 becomes more likely to peel off from the intermediate layer 12, which leads to the provision of the intermediate layer 13. From this viewpoint, the arithmetic mean roughness Ra of the interface 30 is 10 nm or more, and preferably 100 nm or more. If the arithmetic mean roughness Ra of the interface 30 is large, it becomes difficult to form the intermediate layer 12. From this viewpoint, the arithmetic mean roughness Ra of the interface 30 is preferably 1 μm or less.

[0067] In order to increase the bonding strength between the piezoelectric substrate 14 and the intermediate layer 13, the arithmetic mean roughness Ra of the interfaces 32 and 34 is preferably 1 nm or less, more preferably 0.5 nm or less, and even more preferably 0.2 nm or less.

[0068] The surface roughness of the interfaces 30, 32, and 34 can be calculated by measuring the surface roughness of the support substrate 10 and the intermediate layers 12 and 13 during the manufacturing process by an AFM method or the like. The roughness of the interfaces 30, 32, and 34 in the wafer and the acoustic wave device can be compared using cross-sectional SEM images or cross-sectional TEM images.

[0069] When the process includes a step of directly bonding the piezoelectric substrate 14 onto the intermediate layer 12 using a surface activation method, the piezoelectric substrate 14 is likely to peel off from the intermediate layer 12. Therefore, it is preferable to provide the intermediate layer 13.

[0070] When wafer 28 is manufactured in this manner, in the wafer and acoustic wave device, piezoelectric substrate 14 has non-crystalline layer 14b (amorphous layer) at the interface with intermediate layer 13, as shown in FIG. 4(c). Amorphous layer 14b is mainly composed of the constituent elements of piezoelectric substrate 14. Intermediate layer 13 may have non-crystalline layer 13b at the interface with piezoelectric substrate 14. Amorphous layer 13b is mainly composed of the constituent elements of intermediate layer 13.

[0071] In order to increase the bonding strength with the piezoelectric substrate 14, the intermediate layer 13 is mainly composed of aluminum oxide or aluminum nitride oxide. In order to increase the bonding strength between the intermediate layers 12 and 13 and to increase the sound velocity of the elastic wave compared to the piezoelectric substrate 14, the intermediate layer 12 is mainly composed of aluminum oxide or aluminum nitride oxide. When a certain layer is mainly composed of a certain element, it is acceptable to intentionally or unintentionally contain impurities, and for example, the concentration of a certain element in a certain layer is 50 atomic % or more, 80 atomic % or more, or 90 atomic % or more. When the intermediate layers 12 and 13 are mainly composed of aluminum oxide, the sum of the aluminum concentration and the oxygen concentration in the intermediate layers 12 and 13 is 50 atomic % or more, 80 atomic % or more, or 90 atomic % or more. In addition, the aluminum concentration and the oxygen concentration in the intermediate layers 12 and 13 are 10 atomic % or more, or 20 atomic % or more, respectively. When intermediate layers 12 and 13 are mainly composed of aluminum oxynitride, the sum of the aluminum concentration, nitrogen concentration, and oxygen concentration in intermediate layers 12 and 13 is 50 atomic % or more, 80 atomic % or more, or 90 atomic % or more. Also, the aluminum concentration, nitrogen concentration, and oxygen concentration in intermediate layers 12 and 13 are each 10 atomic % or more or 20 atomic % or more.

[0072] As shown in Table 1, from the viewpoint of bonding strength, the intermediate layer 12 is preferably thin. The thickness T2 of the intermediate layer 12 is preferably, for example, 10 μm or less, and more preferably 6 μm or less. From the viewpoint of suppressing spurious, T2 is preferably twice (1λ) or more the average pitch D of the electrode fingers 18, and more preferably three times (1.5λ) or more. As shown in Table 1, from the viewpoint of bonding strength, the intermediate layer 13 is preferably thick. The thickness T3 of the intermediate layer 13 is preferably, for example, 20 nm or more, and more preferably 40 nm or more. When the thickness T3 is thick, the grain size near the interface 34 becomes large, and the bonding strength between the intermediate layer 13 and the piezoelectric substrate 14 becomes small. From this viewpoint, the thickness T3 is preferably 1 μm or less, and more preferably 100 nm or less. The thickness T3 is preferably 0.1 times or less the thickness T2, and more preferably 0.05 times or less.

[0073] In order to confine the energy of the elastic waves in the piezoelectric substrate 14, the thickness T4 of the piezoelectric substrate 14 is preferably 2 times (1λ) or less of the average pitch D of the electrode fingers 18 of the comb-shaped electrode 20, more preferably 1.6 times (0.8λ) or less, and even more preferably 1.2 times (0.6λ) or less. If the piezoelectric substrate 14 is too thin, elastic waves cannot be excited. From this perspective, the thickness T4 is preferably 0.2 times or more. The average pitch of the electrode fingers 18 can be calculated by dividing the width of the IDT 22 in the X direction by the number of electrode fingers 18. EXAMPLES

[0074] FIG. 11(a) is a circuit diagram of a filter according to a second embodiment. As shown in FIG. 11(a), one or more series resonators S1 to S3 are connected in series between an input terminal Tin and an output terminal Tout. One or more parallel resonators P1 and P2 are connected in parallel between the input terminal Tin and the output terminal Tout. The acoustic wave resonator of the first embodiment can be used for at least one of the one or more series resonators S1 to S3 and the one or more parallel resonators P1 and P2. The number of resonators of the ladder filter can be set as appropriate. The filter may be a multimode filter.

[0075] [Modification 1 of Example 2] FIG. 11(b) is a circuit diagram of a duplexer according to a first modified example of the second embodiment. As shown in FIG. 11(b), a transmission filter 40 is connected between a common terminal Ant and a transmission terminal Tx. A reception filter 42 is connected between the common terminal Ant and a reception terminal Rx. The transmission filter 40 passes a signal in a transmission band among high-frequency signals input from the transmission terminal Tx to the common terminal Ant as a transmission signal, and suppresses signals of other frequencies. The reception filter 42 passes a signal in a reception band among high-frequency signals input from the common terminal Ant to the reception terminal Rx as a reception signal, and suppresses signals of other frequencies. At least one of the transmission filter 40 and the reception filter 42 can be the filter of the second embodiment.

[0076] Although a duplexer has been described as an example of a multiplexer, a triplexer or a quadplexer may also be used.

[0077] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0078] 10 Support substrate 12, 13 Middle class 13b, 14b Amorphous layer 14 Piezoelectric substrate 18 electrode fingers 20 comb electrode 22 IDT 26 Elastic Wave Resonator 28 Wafers

Claims

1. A support substrate; a first intermediate layer provided on the support substrate, the first intermediate layer having crystal grains with an average grain size of 100 nm or more; a second intermediate layer provided on the first intermediate layer, the roughness of the interface with the first intermediate layer being smaller than the roughness of the interface between the support substrate and the first intermediate layer, the second intermediate layer being thinner than the first intermediate layer, and the second intermediate layer having an average grain size of less than 100 nm; a piezoelectric substrate directly bonded onto the second intermediate layer; A pair of comb-shaped electrodes provided on the piezoelectric substrate; 1. An acoustic wave device comprising:

2. The acoustic wave device according to claim 1 , wherein the piezoelectric substrate has an amorphous layer at an interface with the second intermediate layer.

3. The acoustic wave device according to claim 1 or 2, wherein the arithmetic mean roughness between the support substrate and the first intermediate layer is 10 nm or more, and the arithmetic mean roughness between the first intermediate layer and the second intermediate layer is 1 nm or less.

4. The acoustic wave device according to claim 1 , wherein the second intermediate layer has a thickness equal to or less than 0.1 times the thickness of the first intermediate layer.

5. The acoustic wave device according to claim 1 , wherein the thickness of the piezoelectric substrate is equal to or smaller than twice the average pitch of the electrode fingers of the pair of comb-shaped electrodes.

6. The acoustic wave device according to claim 1 , wherein the second intermediate layer is mainly composed of aluminum oxide or aluminum oxynitride.

7. The acoustic wave device according to claim 6 , wherein the first intermediate layer is mainly composed of aluminum oxide or aluminum oxynitride.

8. The acoustic wave device according to claim 1 , wherein the piezoelectric substrate is a lithium tantalate substrate or a lithium niobate substrate.

9. A filter comprising an acoustic wave device according to any one of claims 1 to 8.

10. A multiplexer including a filter according to claim 9.

11. A support substrate; a first intermediate layer provided on the support substrate, the first intermediate layer having crystal grains with an average grain size of 100 nm or more; a second intermediate layer provided on the first intermediate layer, the roughness of the interface with the first intermediate layer being smaller than the roughness of the interface between the support substrate and the first intermediate layer, the second intermediate layer being thinner than the first intermediate layer, and the second intermediate layer having an average grain size of less than 100 nm; a piezoelectric substrate directly bonded onto the second intermediate layer; A wafer comprising:

12. forming a first intermediate layer having an average crystal grain size of 100 nm or more on a support substrate; planarizing a surface of the first intermediate layer; forming a second intermediate layer on a surface of the first intermediate layer, the second intermediate layer having an interface roughness with the first intermediate layer smaller than an interface roughness between the support substrate and the first intermediate layer, being thinner than the first intermediate layer, and having an average crystal grain size of less than 100 nm; directly bonding a piezoelectric substrate onto the second intermediate layer; A method for manufacturing a wafer comprising the steps of:

13. The method for manufacturing a wafer according to claim 12 , wherein the step of directly bonding the piezoelectric substrate onto the second intermediate layer includes the step of directly bonding the piezoelectric substrate onto the second intermediate layer by using a surface activation method.

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