Portable device, envelope tracking system, and method for amplifying radio frequency signals in a portable device - Patents.com

Abstract

To provide a power amplifier with adaptive bias for an envelope tracking application which manages the power of a power amplifier's RF signal transmission to extend the battery life and / or provide an appropriate transmit power level.SOLUTION: An envelope tracking system includes a power amplifier 250 that receives power from a power amplifier supply voltage VPA and amplifies a radio frequency (RF) signal, and an envelope tracker that generates a power amplifier supply voltage PA on the basis of the envelope of the RF signal, and the power amplifier includes a field effect transistor (FET) 231 that amplifies the RF signal, and a current mirror 232 including an input unit that receives a reference current IREF and an output unit connected to the power amplifier supply voltage VPA, and the internal voltage of the current mirror is used to bias the gate of the FET 231, such that the FET is compensated for changes in the power amplifier supply voltage VPA resulting from the envelope tracking.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to electronic systems, and more particularly to power amplifiers for use in radio frequency (RF) electronic equipment. [Background technology]

[0002] Power amplifiers are used in radio frequency (RF) communication systems to amplify RF signals for transmission via an antenna. It is important to manage the power of RF signal transmissions to extend battery life and / or provide adequate transmission power levels.

[0003] Examples of RF communication systems having one or more power amplifiers include, but are not limited to, mobile phones, tablets, base stations, network access points, customer premises equipment (CPE), laptops, and wearable electronic devices. For example, in wireless devices that communicate using cellular standards, wireless local area network (WLAN) standards, and / or any other suitable communication standards, power amplifiers can be used for RF signal amplification. The RF signals may have frequencies in the range of about 30 kHz to 300 GHz, such as in the range of about 410 MHz to about 7.125 GHz for fifth generation (5G) cellular communications in Frequency Range 1 (FR1), or in the range of about 24.250 GHz to about 52.600 GHz for Frequency Range 2 (FR2) of 5G communications standards. Summary of the Invention

[0004] In certain embodiments, the present disclosure relates to a portable device including a transceiver configured to generate a radio frequency signal, a power management system including an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to an envelope of the radio frequency signal, and a front-end system including a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage, the power amplifier including a current mirror having an input configured to receive a reference current and an output electrically connected to the power amplifier supply voltage, and a field effect transistor configured to amplify the radio frequency signal, the field effect transistor having a gate biased based on an internal voltage of the current mirror.

[0005] In various embodiments, the internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage and decreases in response to an increase in the power amplifier supply voltage.

[0006] In a number of embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor.

[0007] In some embodiments, the power amplifier further includes a choke inductor electrically connected between the power amplifier supply voltage and the drain of the field effect transistor.

[0008] In some embodiments, the current mirror is a Wilson current mirror.

[0009] In various embodiments, the power amplifier further includes a buffer configured to buffer an internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor. According to a number of embodiments, the buffer includes a first depletion mode transistor and a second depletion mode transistor configured to provide a zero shift in the buffering.

[0010] In some embodiments, the current mirror includes a first mirror transistor having a drain configured to output an internal voltage, a second mirror transistor, a third mirror transistor, and a fourth mirror transistor, the third mirror transistor and the first mirror transistor being connected in series between an input of the current mirror and a ground voltage, and the fourth mirror transistor and the second mirror transistor being connected in series between an output of the current mirror and a ground voltage. According to a number of embodiments, the gate of the first mirror transistor is connected to the gate of the second mirror transistor, and the gate of the third mirror transistor is connected to the gate of the fourth mirror transistor. According to various embodiments, the drain of the second mirror transistor is connected to the gate of the second mirror transistor, and the drain of the third mirror transistor is connected to the gate of the third mirror transistor.

[0011] In some embodiments, the power amplifier further includes a current source configured to generate a reference current.

[0012] In some embodiments, the envelope tracker includes a DC / DC converter configured to output a plurality of regulated voltages, a modulator configured to generate a modulator output voltage at an output based on the plurality of regulated voltages and the envelope of the radio frequency signal, and a modulator output filter coupled between the output of the modulator and a power amplifier supply voltage.

[0013] In various embodiments, the envelope tracker includes a DC / DC converter and an error amplifier configured to operate in parallel with each other to generate the power amplifier supply voltage.

[0014] In certain embodiments, the present disclosure relates to an envelope tracking system including an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to an envelope of a radio frequency signal, and a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage, the power amplifier including a current mirror having an input configured to receive a reference current and an output electrically connected to the power amplifier supply voltage, and a field effect transistor configured to amplify the radio frequency signal, the field effect transistor having a gate biased based on an internal voltage of the current mirror.

[0015] In various embodiments, the internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage and decreases in response to an increase in the power amplifier supply voltage.

[0016] In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor.

[0017] In some embodiments, the power amplifier further includes a choke inductor electrically connected between the power amplifier supply voltage and the drain of the field effect transistor.

[0018] In various embodiments, the current mirror is a Wilson current mirror.

[0019] In some embodiments, the power amplifier further includes a buffer configured to buffer an internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor. According to a number of embodiments, the buffer includes a first depletion mode transistor and a second depletion mode transistor configured to provide a zero shift to the buffering.

[0020] In some embodiments, the current mirror includes a first mirror transistor having a drain configured to output an internal voltage, a second mirror transistor, a third mirror transistor, and a fourth mirror transistor, the third mirror transistor and the first mirror transistor being connected in series between an input of the current mirror and a ground voltage, and the fourth mirror transistor and the second mirror transistor being connected in series between an output of the current mirror and a ground voltage. According to a number of embodiments, the gate of the first mirror transistor is connected to the gate of the second mirror transistor, and the gate of the third mirror transistor is connected to the gate of the fourth mirror transistor. In various embodiments, the drain of the second mirror transistor is connected to the gate of the second mirror transistor, and the drain of the third mirror transistor is connected to the gate of the third mirror transistor.

[0021] In some embodiments, the power amplifier further includes a current source configured to generate a reference current.

[0022] In some embodiments, the envelope tracker includes a DC / DC converter configured to output a plurality of regulated voltages, a modulator configured to generate a modulator output voltage at an output based on the plurality of regulated voltages and the envelope of the radio frequency signal, and a modulator output filter coupled between the output of the modulator and a power amplifier supply voltage.

[0023] In some embodiments, the envelope tracker includes a DC / DC converter and an error amplifier configured to operate in parallel with each other to generate the power amplifier supply voltage.

[0024] In certain embodiments, the present disclosure relates to a method of radio frequency signal amplification in a mobile device, the method including: generating a power amplifier supply voltage using an envelope tracker, the power amplifier supply voltage varying relative to an envelope of a radio frequency signal, powering a power amplifier using the power amplifier supply voltage, amplifying the radio frequency signal using a field effect transistor of the power amplifier, and generating a gate bias voltage for the field effect transistor using an internal voltage of a current mirror of the power amplifier, providing a reference current to an input of the current mirror and providing the power amplifier supply voltage to an output of the current mirror.

[0025] In various embodiments, the method includes increasing an internal voltage of the current mirror in response to a decrease in the power amplifier supply voltage, and decreasing an internal voltage of the current mirror in response to an increase in the power amplifier supply voltage.

[0026] In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor.

[0027] In a number of embodiments, the method further includes providing a power amplifier supply voltage to the drain of the field effect transistor using a choke inductor.

[0028] In some embodiments, the current mirror is a Wilson current mirror.

[0029] In various embodiments, the method further includes buffering an internal voltage of the current mirror to generate a gate bias voltage of the field effect transistor.

[0030] In a number of embodiments, the method further includes generating the reference current using a current source.

[0031] In some embodiments, generating the power amplifier supply voltage includes outputting a plurality of regulated voltages from a DC / DC converter, generating a modulator output voltage using a modulator based on the plurality of regulated voltages and an envelope of the radio frequency signal, and filtering the modulator output voltage using a modulator output filter to generate the power amplifier supply voltage.

[0032] In some embodiments, generating the power amplifier supply voltage includes tracking the envelope using a DC / DC converter and an error amplifier operating in parallel. [Brief description of the drawings]

[0033] [Figure 1] FIG. 2 is a schematic diagram of an embodiment of a mobile device. [Diagram 2] FIG. 1 is a schematic diagram of an embodiment of a transmission system for transmitting a radio frequency (RF) signal from a mobile device. [Diagram 3] FIG. 1 is a schematic diagram of a power amplifier according to an embodiment. [Figure 4A-4D] FIGURE 4A is a graph of an example of power gain versus output power for a power amplifier without adaptive bias; FIGURE 4B is a graph of an example of power gain versus output power for a power amplifier with adaptive bias; FIGURE 4C is a graph of an example of quiescent drain current versus supply voltage for a power amplifier without adaptive bias; and FIGURE 4D is a graph of an example of quiescent drain current versus supply voltage for a power amplifier with adaptive bias. [Diagram 5] FIG. 13 is a schematic diagram of a power amplifier according to another embodiment. [Figures 6A-6D] FIG 6A is a graph of an example of amplitude distortion versus load power for a power amplifier with adaptive bias but no buffer; FIG 6B is a graph of an example of amplitude distortion versus load power for a power amplifier with adaptive bias and a buffer; FIG 6C is a graph of an example of phase distortion versus load power for a power amplifier with adaptive bias but no buffer; and FIG 6D is a graph of an example of phase distortion versus load power for a power amplifier with adaptive bias and a buffer. [Figure 7A-7B] 7A and 7B are graphs of an example of drain current versus drain voltage for a short-channel metal-oxide-semiconductor (MOS) transistor, respectively. [Figure 8A-8B] Figure 8A is an example graph of power amplifier supply voltage versus time. Figure 8B is another example graph of power amplifier supply voltage versus time. [Figure 9A] FIG. 1 is a schematic diagram of an envelope tracking system according to an embodiment. [Figure 9B] FIG. 4 is a schematic diagram of an envelope tracking system according to another embodiment; [Figure 10] FIG. 4 is a schematic diagram of an envelope tracking system according to another embodiment; [Figure 11A-11B] Fig. 11A is a schematic diagram of one embodiment of a packaged module, and Fig. 11B is a schematic diagram of a cross section of the packaged module taken along line 11B-11B in Fig. 11A. [Figure 12] FIG. 2 is a schematic diagram of an embodiment of a phone board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The following detailed description of certain embodiments represents various descriptions of specific embodiments. However, the innovation described herein may be embodied in many different ways, as defined and covered by, for example, the claims. In this description, reference is made to the drawings, in which like reference numbers may indicate identical or functionally similar elements. It is understood that the elements depicted in the drawings are not necessarily drawn to scale. It is further understood that a given embodiment may include more elements than are shown in the drawings and / or may include a subset of the elements depicted in the drawings. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings.

[0035] 1 is a schematic diagram of an example of a mobile device 100. The mobile device 100 includes a baseband system 1, a transceiver 2, a front-end system 3, an antenna 4, a power management system 5, a memory 6, a user interface 7 and a battery 8.

[0036] The mobile device 100 may be used to communicate using a wide variety of communication technologies, including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth® and ZigBee®), WMAN (e.g., WiMax), and / or GPS technologies.

[0037] The transceiver 2 generates RF signals for transmission and processes incoming RF signals received from the antenna 4. It will be appreciated that various functions associated with transmitting and receiving RF signals may be accomplished by one or more components collectively represented in Figure 1 as the transceiver 2. In one example, separate components (e.g., separate circuits or dies) may be provided to handle certain types of RF signals.

[0038] The front-end system 3 assists in conditioning signals transmitted to and / or received from the antenna 4. In the illustrated embodiment, the front-end system 3 includes a power amplifier (PA) 11, a low noise amplifier (LNA) 12, a filter 13, a switch 14, and a duplexer 15. However, other implementations are possible.

[0039] For example, the front-end system 3 may provide a number of functions including, but not limited to, signal amplification for transmission, amplification of received signals, signal filtering, switching between different bands, switching between different power modes, switching between transmit and receive modes, duplexing of signals, multiplexing of signals (e.g., diplexing or triplexing), or any combination thereof.

[0040] In certain implementations, the mobile device 100 supports carrier aggregation, providing flexibility to increase peak data rates. Carrier aggregation can be used for both frequency division duplexing (FDD) and time division duplexing (TDD) and can be used to aggregate multiple carriers or channels. Carrier aggregation includes contiguous aggregation, where adjacent carriers within the same operating frequency band are aggregated. Carrier aggregation can also be non-contiguous and include frequency separated carriers within a common band and / or in different bands.

[0041] Antenna 4 may include antennas used for a wide variety of types of communication. For example, antenna 4 may include antennas associated with transmitting and / or receiving signals associated with a wide variety of frequencies and communication standards.

[0042] In certain implementations, antenna 4 supports MIMO and / or switched diversity communications. For example, MIMO communications uses multiple antennas to communicate multiple data streams over a single radio frequency channel. MIMO communications benefits from higher signal-to-noise ratios, improved coding, and / or reduced signal interference due to spatial multiplexing differences in the wireless environment. Switched diversity refers to communications in which a particular antenna is selected to operate at a particular time. For example, a switch can be used to select a particular antenna from a group of antennas based on various factors such as observed bit error rates and / or signal strength indicators.

[0043] The mobile device 100 may operate with beamforming in certain implementations. For example, the front-end system 3 may include a phase shifter whose variable phase is controlled by the transceiver 2. Additionally, the phase shifter is controlled to provide beamforming and directivity for the transmission and / or reception of signals using the antenna 4. For example, in the context of signal transmission, the phase of the transmit signal provided to the antenna 4 is controlled such that the signals radiated from the antenna 4 combine using constructive and destructive interference to generate an aggregate transmit signal that exhibits a beam-like quality of signal strength propagating in a given direction. In the context of signal reception, the phase is controlled such that more signal energy is received when the signal is arriving at the antenna 4 from a particular direction. In certain implementations, the antenna 4 includes one or more arrays of multiple antenna elements to enhance beamforming.

[0044] The baseband system 1 is coupled to a user interface 7 to facilitate processing of various user inputs and outputs (I / O) such as voice and data. The baseband system 1 provides a digital representation of a transmit signal to the transceiver 2 which the transceiver 2 processes to generate an RF signal for transmission. The baseband system 1 also processes a digital representation of a receive signal provided by the transceiver 2. As shown in FIG. 1, the baseband system 1 is coupled to a memory 6 to facilitate operation of the mobile device 100.

[0045] The memory 6 may be used for a wide variety of purposes, such as storing data and / or instructions to facilitate operation of the portable device 100 and / or to provide storage of user information.

[0046] The power management system 5 provides a number of power management functions for the portable device 100. The power management system 5 of Figure 1 includes an envelope tracker 60. As shown in Figure 1, the power management system 5 receives a battery voltage from a battery 8. The battery 8 may be any suitable battery for use in the portable device 100, including, for example, a lithium ion battery.

[0047] 1 illustrates an example of an RF communication system that may include a power amplifier implemented in accordance with one or more aspects of the present disclosure, however, the teachings herein are applicable to RF communication systems implemented in a wide variety of manners.

[0048] 2 is a schematic diagram of an embodiment of a transmission system 130 for transmitting an RF signal from a mobile device. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital pre-distortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital computation (CORDIC) circuit 122, a shaping circuit 123, a digital-to-analog converter 124, and a reconstruction filter 125.

[0049] Transmitter system 130 of Figure 2 illustrates one example of an RF communication system that may include a power amplifier implemented in accordance with one or more aspects of the present disclosure, although the teachings herein are applicable to RF communication systems implemented in a wide variety of manners.

[0050] The base-band processor 107 operates to generate I and Q signals corresponding to signal components of a sinusoidal wave or signal of a desired amplitude, frequency and phase. For example, the I signal is used to represent the in-phase component of the sine wave and the Q signal is used to represent the quadrature component of the sine wave. These may be equivalent representations of sine waves. In certain implementations, the I and Q signals are provided to the I / Q modulator 110 in digital format. The base-band processor 107 may be any suitable processor configured to process base-band signals. For example, the base-band processor 107 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof.

[0051] The signal delay circuit 108 delays the envelope signal and the RF signal RF IN The signal delay circuit 108 provides an adjustable delay to the I and Q signals to help control the relative alignment with the I and Q signals. The amount of delay provided by the signal delay circuit 108 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112.

[0052] The DPD circuit 109 operates to provide digital shaping to the delayed I and Q signals from the signal delay circuit 108 to generate digitally predistorted I and Q signals. In the illustrated embodiment, the DPD provided by the DPD circuit 109 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112. The DPD circuit 109 serves to reduce distortion and / or increase the efficiency of the power amplifier 103.

[0053] The I / Q modulator 110 receives the digitally predistorted I and Q signals, which are converted into an RF signal RF IN For example, the I / Q modulator 110 may include a DAC configured to convert the I and Q signals to an analog format, a mixer to upconvert the I and Q signals to a radio frequency, and a signal combiner to combine the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier 103. In certain implementations, the I / Q modulator 110 may include one or more filters configured to filter the frequency content of the signal being processed.

[0054] The envelope delay circuit 121 delays the I and Q signals from the baseband processor 107. Additionally, a CORDIC circuit 122 processes the delayed I and Q signals to generate an RF signal RF IN 2 shows an implementation using a CORDIC circuit 122, the envelope signal may be obtained in other manners.

[0055] The shaping circuit 123 operates to shape the digital envelope signal to improve the performance of the transmission system 130. In certain implementations, the shaping circuit 123 includes a shaping table that maps each level of the digital envelope signal to a corresponding shaped envelope signal level. The shaping of the envelope can help control the linearity, distortion, and / or efficiency of the power amplifier 103.

[0056] In the illustrated embodiment, the shaped envelope signal is a digital signal that is converted to an analog envelope signal by DAC 124. Additionally, the analog envelope signal is filtered by reconstruction filter 125 to generate an envelope signal suitable for use by envelope tracker 102. In certain implementations, reconstruction filter 125 includes a low-pass filter.

[0057] Continuing to refer to FIG. 2, the envelope tracker 102 receives the envelope signal from the reconstruction filter 125 and also receives the battery voltage V from the battery 101. BATT and uses the envelope signal to generate an RF signal, IN The power amplifier supply voltage V for the power amplifier 103 varies in relation to the envelope of PA The power amplifier 103 outputs the RF signal RF IN , and transmits an amplified RF signal RF to an antenna 106 via a diplexing switching circuit 105 in this example. OUT Gives.

[0058] Directional coupler 104 is disposed between the output of power amplifier 103 and the input of duplexing switching circuit 105. This allows for measuring the output power of power amplifier 103 without including the insertion loss of duplexing switching circuit 105. The detected output signal from directional coupler 104 is provided to observation receiver 111. Observation receiver 111 includes a mixer that downconverts I and Q signal components of the detected output signal, and a DAC that generates I and Q observation signals from the downconverted signal.

[0059] The intermodulation detection circuit 112 determines intermodulation products between the I and Q observed signals and the I and Q signals from the baseband processor 107. Additionally, the intermodulation detection circuit 112 determines the intermodulation products between the envelope signal and the RF signal RF by controlling the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108. IN Controls the alignment relative to the

[0060] By including a feedback path from the output of the power amplifier 103 and the baseband, the I and Q signals can be dynamically adjusted to optimize the operation of the transmit system 130. For example, configuring the transmit system 130 in this manner can help provide power control, compensate for transmitter impairments, and / or perform DPD.

[0061] Although shown as a single stage, the power amplifier 103 may include one or more stages. Additionally, RF communication systems, such as mobile devices, may include multiple power amplifiers. In such implementations, separate envelope trackers may be provided for different power amplifiers and / or one or more shared envelope trackers may be used.

[0062] Adaptive bias for power amplifiers operating with envelope tracking

[0063] Envelope tracking is a technique that can be used to increase the power added efficiency (PAE) of a power amplifier by effectively controlling the voltage level of the power amplifier supply voltage in relation to the envelope of the RF signal amplified by the power amplifier. That is, if the envelope of the RF signal increases, the voltage supplied to the power amplifier may increase. Similarly, if the envelope of the RF signal decreases, the voltage supplied to the power amplifier decreases, reducing power consumption.

[0064] In one example, the envelope tracker includes a DC / DC converter operating in combination with an error amplifier to generate a power amplifier supply voltage based on the envelope signal. For example, the DC / DC converter and the error amplifier can be electrically connected in parallel with each other, and the DC / DC converter can track a low frequency component of the envelope signal while the error amplifier can track a high frequency component of the envelope signal. For example, the switching frequency of the DC / DC converter can be reduced to be lower than a maximum frequency component of the envelope signal, and the error amplifier can operate to smooth gaps in the output of the DC / DC converter to generate the power amplifier supply voltage. In certain implementations, the DC / DC converter and the error amplifier can be coupled via a coupler.

[0065] In another example, the envelope tracker includes a multi-output boost switch that generates regulated voltages at different voltage levels, a bank of switches that controls selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate the power amplifier supply voltage.

[0066] A power amplifier with adaptive bias for envelope tracking applications is provided herein. In certain embodiments, the envelope tracking system includes a power amplifier for amplifying an RF signal, the power amplifier receiving power from a power amplifier supply voltage, and an envelope tracker for generating a power amplifier supply voltage based on the envelope of the RF signal. The power amplifier includes a field effect transistor (FET) for amplifying the RF signal, and a current mirror including an input receiving a reference current and an output connected to the power amplifier supply voltage. An internal voltage of the current mirror is used to bias the gate of the FET such that the FET is compensated for changes in the power amplifier supply voltage resulting from envelope tracking.

[0067] Implementing adaptive bias in a power amplifier compensates for non-idealities in the power amplifier's FETs. For example, such adaptive bias helps compensate for channel length modulation and / or drain-induced barrier lowering that would otherwise result in high variations in RF gain versus power amplifier supply voltage.

[0068] In certain implementations, the FETs are implemented as short-channel metal-oxide-semiconductor (MOS) transistors. Although short-channel MOS transistors suffer from a certain number of transistor non-idealities, adaptive biasing provides compensation that allows short-channel MOS transistors to be used in a power amplifier without significantly degrading the performance of the power amplifier. In certain applications, it is desirable to implement a power amplifier using short-channel MOS transistors because short-channel MOS transistors are low cost and / or can be fabricated in processes that allow high integration.

[0069] In certain implementations, a buffer is further included to buffer the internal voltage of the current mirror to generate the gate bias voltage of the FET. The inclusion of the buffer can improve the bandwidth and speed up the bias transient response of the power amplifier, thereby improving the amplitude and phase distortion.

[0070] Current mirrors can be implemented in a wide variety of ways. In certain implementations, the current mirror is implemented as a Wilson current mirror. For example, the current mirror can be implemented using n-type field effect transistors (NFETs) arranged as a four-transistor Wilson current mirror. For example, the drain-source voltage of the first NFET of a four-transistor Wilson mirror increases as the voltage at the output decreases, making it well suited to increasing the gain of a power amplifier as the power amplifier supply voltage decreases.

[0071] 3 is a schematic diagram of a power amplifier 250 according to one embodiment. The power amplifier 250 includes an NFET 231, a Wilson current mirror 232, an input DC blocking capacitor 233, an output DC blocking capacitor 234, a choke inductor 235, and a reference current source 236.

[0072] Although FIG. 3 depicts one embodiment of a power amplifier with adaptive biasing, the teachings herein are applicable to power amplifiers implemented in a wide variety of ways.

[0073] The power amplifier 250 receives an RF input signal RF at an RF input terminal. IN and receiving an amplified RF output signal RF OUT to the RF output terminal. In the illustrated embodiment, an input DC blocking capacitor 233 is connected between the RF input terminal and the gate of NFET 231 to allow biasing of the gate voltage of NFET 231 independent of the DC voltage of the RF input terminal. Additionally, an output DC blocking capacitor 234 is connected between the drain of NFET 231 and the RF output terminal to decouple the drain voltage of NFET 231 from the DC voltage of the RF output terminal.

[0074] As shown in FIG. 3, a choke inductor 235 couples the power amplifier supply voltage V PA The power amplifier supply voltage V PA may be generated by an envelope tracker, including but not limited to any of the envelope trackers disclosed herein.

[0075] NFET 231 is connected to the RF input signal RF IN is amplified to produce an RF output signal, RF OUT Additionally, the gate of NFET 231 is biased by an internal voltage of Wilson current mirror 232. Furthermore, the drain of NFET 231 receives the power amplifier supply voltage V from choke inductor 235 while the source of NFET 231 receives ground. PAIn certain implementations, NFET 231 is implemented as an n-type metal-oxide semiconductor (NMOS) transistor. For example, NFET 231 may be a short-channel NMOS transistor.

[0076] The Wilson current mirror 232 receives a reference current I from a reference current source 236. REF and an input for receiving the power amplifier supply voltage V PA The Wilson current mirror 232 includes a first current mirror NFET 241, a second current mirror NFET 242, a third current mirror NFET 243, and a fourth current mirror NFET 244.

[0077] 3, the first current mirror NFET 241 and the second current mirror 242 each include a source connected to ground. Additionally, the gate of the first current mirror NFET 241 is connected to the gate and drain of the second current mirror NFET 242 and to the source of the fourth current mirror NFET 244. Additionally, the output of the Wilson current mirror 232 is connected to the drain of the fourth current mirror NFET 244, while the input of the Wilson current mirror 232 is connected to the gate of the fourth current mirror NFET 244 and to the gate and drain of the third current mirror NFET 243. Furthermore, the drain of the first current mirror NFET 241 and the drain of the third current mirror NFET 243 are connected to each other.

[0078] In the illustrated embodiment, an internal voltage of Wilson current mirror 232 is applied to the gate of NFET 231 to provide adaptive bias. The internal voltage corresponds to the drain voltage of first current mirror NFET 241 in this embodiment.

[0079] The Wilson current mirror 232 receives a reference current I REF Due to envelope tracking, the power amplifier supply voltage V PAAs V changes, the drain voltage of the first current mirror NFET 241 also changes so that the output current tracks the input current. As a result of adjusting the Wilson current mirror 232, the power amplifier supply voltage V PA As decreases, the drain-source voltage of the first current source NFET 241 increases.

[0080] The drain voltage of the first current mirror NFET 241 is the power amplifier supply voltage V PA is well suited to increasing the gain of a power amplifier as the power amplifier supply voltage V PA That is, Wilson current mirror 232 provides an adaptive bias to NFET 231 to compensate for gain variations resulting from power supply variations. Such adaptive bias is well suited to compensate for short channel effects (e.g., channel length modulation and / or drain induced barrier lowering) when NFET 231 is implemented as a short channel NMOS transistor.

[0081] FIG. 4A is a graph of an example of power gain versus output power for a power amplifier without adaptive bias.

[0082] FIG. 4B is a graph of an example of power gain versus output power for a power amplifier with adaptive bias.

[0083] As shown by comparing FIGS. 4A and 4B, adaptive biasing reduces the gain variation (eg, from about 15 dB to about 3 dB in this example).

[0084] FIG. 4C is a graph of an example of quiescent drain current versus supply voltage for a power amplifier without adaptive bias.

[0085] FIG. 4D is a graph of an example of quiescent drain current versus supply voltage for a power amplifier with adaptive bias.

[0086] As shown by comparing FIG. 4C with FIG. 4D, adaptive biasing reduces the variation in quiescent drain current (eg, from about 12× to about 1.25× in this example).

[0087] 5 is a schematic diagram of a power amplifier 280 according to another embodiment of the present invention. The power amplifier 280 includes an NFET 231, a Wilson current mirror 232, an input DC blocking capacitor 233, an output DC blocking capacitor 234, a choke inductor 235, a reference current source 270, and a buffer 270.

[0088] Power amplifier 280 of FIG. 5 is similar to power amplifier 250 of FIG. 3, except that power amplifier 280 further includes a buffer 270 that buffers the drain voltage of first current mirror NFET 241 to generate the gate bias voltage for NFET 231.

[0089] In the illustrated embodiment, buffer 270 is implemented as a zero-shift buffer. The zero-shift buffer includes a first depletion-mode (d-mode) FET 271 and a second d-mode FET 272, which may be, for example, junction field-effect transistors (JFETs) or Schottky-gate FETs. The drain of the first d-mode FET 271 is coupled to the battery voltage V BATT while the gate of the 1d-mode FET 271 receives the internal voltage of the Wilson current mirror 232. Additionally, the gate and source of the 2d-mode FET 272 are connected to ground while the drain of the 2d-mode FET 272 is connected to the source of the 1d-mode FET 271 at a node that outputs a gate bias voltage to bias the NFET 231 of the power amplifier.

[0090] By including buffer 270, increased bandwidth and improved transient response of the power amplifier bias circuit is achieved.

[0091] FIG. 6A is a graph of an example of amplitude distortion versus load power for a power amplifier with adaptive bias but no buffer.

[0092] FIG. 6B is a graph of an example of amplitude distortion versus load power for an adaptively biased and buffered power amplifier.

[0093] As shown by comparing Figures 6A and 6B, the use of a buffer in combination with adaptive bias reduces amplitude distortion (AM / AM).

[0094] FIG. 6C is a graph of an example of phase distortion versus load power for a power amplifier with adaptive bias but no buffer.

[0095] FIG. 6D is a graph of an example of phase distortion versus load power for an adaptively biased and buffered power amplifier.

[0096] Combining a buffer with adaptive bias reduces phase distortion (AM / PM), as shown by comparing Figures 6C and 6D.

[0097] 7A is an example graph of drain current versus drain voltage for a short-channel MOS transistor. Various plots of drain current versus drain voltage at different gate-source voltages for a short-channel MOS transistor are depicted. Included are plots both without considering channel length modulation (dashed plot) and with considering channel length modulation (solid plot).

[0098] 7B is a graph of an example of drain current versus gate voltage for a short-channel MOS transistor illustrating an example of a transistor threshold voltage shift resulting from drain-induced barrier lowering.

[0099] 8A and 8B show two examples of power amplifier supply voltage versus time.

[0100] 8A, a graph 447 shows an example of the voltage of an RF signal 441 and a power amplifier supply voltage 443 versus time. The RF signal 441 has an envelope 442.

[0101] It can be important that the power amplifier supply voltage 443 of the power amplifier has a voltage greater than that of the RF signal 441. For example, powering the power amplifier using a power amplifier supply voltage having an amplitude less than that of the RF signal may clip the RF signal, resulting in signal distortion and / or other problems. That is, it can be important to keep the power amplifier supply voltage 443 greater than the envelope 442. However, it is desirable to reduce the voltage difference between the power amplifier supply voltage 443 and the envelope 442 of the RF signal 441, because the area between the power amplifier supply voltage 443 and the envelope 442 may represent lost energy that may reduce battery life and increase heat generated in the wireless device.

[0102] In Figure 8B, graph 448 shows an example of the voltage of RF signal 441 and power amplifier supply voltage 444 versus time. In contrast to power amplifier supply voltage 443 in Figure 8A, power amplifier supply voltage 444 in Figure 8B varies with respect to envelope 442 of RF signal 441. Because the area between power amplifier supply voltage 444 and envelope 442 in Figure 8B is smaller than the area between power amplifier supply voltage 443 and envelope 442 in Figure 8A, graph 448 in Figure 8B can be associated with a more energy efficient power amplifier.

[0103] 9A is a schematic diagram of an envelope tracking system 500 according to one embodiment. The envelope tracking system 500 includes a power amplifier 501 and an envelope tracker 502. The power amplifier 501 amplifies a radio frequency signal 503.

[0104] The envelope tracker 502 receives an envelope signal 504 that corresponds to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 502 receives a power amplifier supply voltage V PA Causes the following to occur.

[0105] The illustrated envelope tracker 502 includes a DC / DC converter 511 and an error amplifier 512, which are coupled together to derive a power amplifier supply voltage V based on the envelope signal 504. PA In the illustrated embodiment, the output of the DC / DC converter 511 and the output of the error amplifier 512 are combined using a combiner 515.

[0106] Envelope tracker 502 of FIG. 9A illustrates an example of analog envelope tracking in which switching regulators operate in parallel with each other to track the envelope of an RF signal.

[0107] 9B is a schematic diagram of an envelope tracking system 540 according to another embodiment. The envelope tracking system 540 includes a power amplifier 501 and an envelope tracker 532. The power amplifier 501 amplifies a radio frequency signal 503.

[0108] The envelope tracker 532 receives an envelope signal 504 that corresponds to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 532 receives a power amplifier supply voltage V PA Causes the following to occur.

[0109] The illustrated envelope tracker 532 includes a multi-level switching circuit 535. In one implementation, the multi-level switching circuit includes a multi-output DC / DC converter that generates regulated voltages at different voltage levels, a number of switches that control the selection of the appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switches to generate the power amplifier supply voltage.

[0110] Envelope tracker 532 of FIG. 9B illustrates an example of MLS envelope tracking.

[0111] 10 is a schematic diagram of an envelope tracking system according to another embodiment. The envelope tracking system 600 includes a power amplifier 501 and an envelope tracker 602. The power amplifier 501 amplifies a radio frequency signal 503.

[0112] The envelope tracker 602 receives an envelope signal corresponding to the envelope of the radio frequency signal 503. In this example, the envelope signal is differential. Additionally, the envelope tracker 602 receives a power amplifier supply voltage V that supplies power to the power amplifier 501. PA Causes the following to occur.

[0113] The illustrated envelope tracker 602 includes an envelope amplifier 611, a first comparator 621, a second comparator 622, a third comparator 623, a coding and dithering circuit 624, a multi-output boost switch 625, a filter 626, a switch bank 627, and a capacitor bank 630. The capacitor bank 630 includes a first capacitor 631, a second capacitor 632, and a third capacitor 633. Additionally, the switch bank 627 includes a first switch 641, a second switch 642, and a third switch 643.

[0114] The envelope amplifier 611 amplifies the envelope signal and provides the amplified envelope signal to a first comparator 621-3 comparator 623. The first comparator 621-3 comparator 623 compare the amplified envelope signal with a first threshold T1, a second threshold T2 and a third threshold T3, respectively. The results of the comparisons are provided to a coding and dithering circuit 624. The coding and dithering circuit 624 processes the results to control the selection of switches in a switch bank 627. The coding and dithering circuit 624 can use coding and / or dithering while activating the switches to reduce artifacts resulting from opening and closing the switches.

[0115] Although an example having three comparators is shown, more or less comparators may be used. Additionally, one may choose to omit the coding and dithering circuit 624 and control the switch bank in other manners. In a first example, coding is used but dithering is not used. In a second example, dithering is used but coding is not used. In a third example, neither coding nor dithering is used.

[0116] The multi-output boost switch 625 is BATT The first regulated voltage V is based on the DC / DC conversion MLS1 , the second regulated voltage V MLS2 and the third regulated voltage V MLS3 Although an example is shown having three regulated voltages, the multi-output boost switch 625 can generate more or fewer regulated voltages. In certain implementations, at least a portion of these regulated voltages may be generated using a voltage that is less than the battery voltage V BATT In some configurations, one or more of these regulated voltages are boosted relative to the battery voltage V BATT is the buck voltage, which has a lower voltage than

[0117] Capacitor bank 630 helps stabilize the regulated voltage produced by multi-output boost switch 625. For example, capacitors 631-633 act as decoupling capacitors.

[0118] Filter 626 processes the output of switch bank 627 to generate the power amplifier supply voltage V PA By controlling the selection of switches 641-643 over time based on the envelope signal, a power amplifier supply voltage V that tracks the envelope signal is generated. PA occurs.

[0119] Fig. 11A is a schematic diagram of one embodiment of a packaged module 800. Fig. 11B is a schematic diagram of a cross section of the packaged module 800 taken along line 11B-11B in Fig. 11A.

[0120] Packaged module 800 includes an IC or die 801, a surface mount component 803, wire bonds 808, a package substrate 820, and an encapsulation structure 840. The package substrate 820 includes a pad 806 formed from a conductor disposed thereon. Additionally, die 801 includes a pad 804, and wire bonds 808 are used to electrically connect pad 804 of die 801 to pad 806 of package substrate 820.

[0121] Die 801 includes a power amplifier 846, which may be implemented according to any of the embodiments herein.

[0122] Package substrate 820 may be configured to receive die 801 and multiple components, such as surface mount components 803, which may include, for example, surface mount capacitors and / or inductors.

[0123] As shown in FIG. 11B, the packaged module 800 is shown to include a number of contact pads 832 disposed on a side of the packaged module 800 opposite the side used to attach the die 801. Configuring the packaged module 800 in this manner aids in connecting the packaged module 800 to a circuit board, such as a phone board of a wireless device. Examples of the contact pads 832 may be configured to provide RF signals, bias signals, power low voltages, and / or power high voltages to the die 801 and / or surface mounted components 803. As shown in FIG. 11B, electrical connection between the contact pads 832 and the die 801 may be facilitated by connections 833 through the package substrate 820. The connections 833 may represent electrical paths formed through the package substrate 820, such as connections associated with vias and conductors of a multi-layer laminate package substrate.

[0124] In some embodiments, packaged module 800 may also include one or more packaging structures, for example, to provide protection and / or facilitate handling of packaged module 800. Such packaging structures may include an overmold or encapsulation structure 840 formed to cover package substrate 820 and the components and die disposed thereon.

[0125] It will be understood that although packaged module 800 is described in the context of wire bond based electrical connections, one or more features of the present disclosure may also be implemented in other package configurations including, for example, a flip chip configuration.

[0126] Figure 12 is a schematic diagram of one embodiment of a phone board 900. The phone board 900 includes the module 800 shown in Figures 11A and 11B attached herewith. The phone board 900 may include additional components and structures, although not shown in Figure 12 for purposes of clarity.

[0127] application

[0128] Some of the above described embodiments have been given examples related to wireless devices or mobile phones, however, the principles and advantages of those embodiments can be used in any other system or apparatus requiring a power amplifier.

[0129] Such envelope trackers may be implemented in a variety of electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of such consumer electronic products, electronic test equipment, and the like. Examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuits of optical or other communication networks, and disk driver circuits. Consumer electronic products may include, but are not limited to, mobile phones, telephones, televisions, computer monitors, computers, handheld computers, personal digital assistants (PDAs), microwave ovens, refrigerators, automobiles, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, MP3 players, radios, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washer / dryers, copiers, facsimile machines, scanners, multifunction peripheral devices, watches, clocks, and the like. Additionally, electronic devices may include unfinished products.

[0130] summary

[0131] Throughout this specification and the claims, unless the context clearly indicates otherwise, terms such as "comprises" and the like are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to an exclusive or exhaustive sense. The word "coupled," as generally used herein, refers to two or more elements that may be either directly connected or connected through one or more intermediate elements. Similarly, the word "connected," as generally used herein, refers to two or more elements that may be either directly connected or connected through one or more intermediate elements. In addition, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portion of this application. Where the context permits, terms in the above detailed description using the singular or plural number may also include the plural or singular number, respectively. The words "or" and "or," referring to a list of two or more items, cover all of the following interpretations of that word: any item in that list, all items in that list, and any combination of items in that list.

[0132] Additionally, conditional language used herein, such as, among others, "can," "could," "may," "might," "for example," "such as," and the like, is generally intended to convey that certain embodiments include certain features, elements, and / or conditions while other embodiments do not, unless specifically stated otherwise or understood otherwise by the context of use. That is, such conditional language is generally not intended to imply that the features, elements, and / or conditions are in any manner required for one or more embodiments, or that one or more embodiments necessarily include logic that, with or without the author's input or prompting, determines whether or not those features, elements, and / or conditions are included in or performed in any specific embodiment.

[0133] The above detailed description of embodiments of the present invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. Although specific embodiments of the present invention and examples thereof have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the present invention. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines or use systems having blocks with steps in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks may be shown to occur in series, these processes or blocks may instead occur in parallel or at different times.

[0134] The teachings of the invention provided herein are not necessarily limited to the system described above, but may be applied to other systems. Elements and acts of various embodiments described above may be combined to provide further embodiments.

[0135] Although several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. It is intended that the appended claims and their equivalents cover such forms or modifications that fall within the scope and spirit of the present disclosure.

Claims

1. 1. A mobile device comprising: a transceiver configured to generate a radio frequency signal; a power management system including an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to an envelope of the radio frequency signal; a front-end system including a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage; Including, The power amplifier includes: a current mirror including an input configured to receive a reference current and an output electrically connected to the power amplifier supply voltage; a field effect transistor configured to amplify the radio frequency signal and having a gate biased based on an internal voltage of the current mirror; Including, A portable device, wherein an internal voltage of the current mirror is operable to increase in response to a decrease in the power amplifier supply voltage and to decrease in response to an increase in the power amplifier supply voltage.

2. The portable device of claim 1 , wherein the field effect transistor is a short channel metal oxide semiconductor transistor.

3. 2. The portable device of claim 1, wherein the power amplifier further comprises a choke inductor electrically connected between a node providing the power amplifier supply voltage and a drain of the field effect transistor.

4. The portable device of claim 1 , wherein the current mirror is a Wilson current mirror.

5. The portable device of claim 1 , wherein the power amplifier further comprises a buffer configured to buffer an internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor.

6. The current mirror includes: a first mirror transistor having a drain configured to output the internal voltage; A second mirror transistor; and A third mirror transistor; and A fourth mirror transistor; Including, the third mirror transistor and the first mirror transistor are connected in series between an input of the current mirror and a ground voltage; 2. The portable device of claim 1, wherein the fourth mirror transistor and the second mirror transistor are connected in series between an output of the current mirror and the ground voltage.

7. a gate of the first mirror transistor is connected to a gate of the second mirror transistor; The portable device of claim 6 , wherein a gate of the third mirror transistor is connected to a gate of the fourth mirror transistor.

8. the drain of the second mirror transistor is connected to the gate of the second mirror transistor; The portable device of claim 7 , wherein the drain of the third mirror transistor is connected to the gate of the third mirror transistor.

9. The portable device of claim 1 , wherein the power amplifier further comprises a current source configured to generate the reference current.

10. A portable device, comprising: a transceiver configured to generate a radio frequency signal; a power management system including an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to an envelope of the radio frequency signal; a front-end system including a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage; Including, The power amplifier includes: a current mirror including an input configured to receive a reference current and an output electrically connected to the power amplifier supply voltage; a field effect transistor configured to amplify the radio frequency signal and having a gate biased based on an internal voltage of the current mirror; a buffer configured to buffer an internal voltage of the current mirror to generate a gate bias voltage of the field effect transistor; Including, The buffer includes a first depletion mode transistor and a second depletion mode transistor configured to provide a zero shift in buffering.

11. 1. An envelope tracking system comprising: an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to an envelope of the radio frequency signal; a power amplifier configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage; Including, The power amplifier includes: a current mirror including an input configured to receive a reference current and an output electrically connected to the power amplifier supply voltage; a field effect transistor configured to amplify the radio frequency signal and having a gate biased based on an internal voltage of the current mirror; Including, The current mirror includes: a first mirror transistor having a drain configured to output the internal voltage; A second mirror transistor; and A third mirror transistor; and A fourth mirror transistor; Including, the third mirror transistor and the first mirror transistor are connected in series between an input of the current mirror and a ground voltage; The fourth mirror transistor and the second mirror transistor are connected in series between the output of the current mirror and the ground voltage.

12. 12. The envelope tracking system of claim 11, wherein an internal voltage of the current mirror increases in response to a decrease in the power amplifier supply voltage and decreases in response to an increase in the power amplifier supply voltage.

13. 12. The envelope tracking system of claim 11, wherein the field effect transistor is a short channel metal oxide semiconductor transistor.

14. 12. The envelope tracking system of claim 11, wherein the current mirror is a Wilson current mirror.

15. 12. The envelope tracking system of claim 11, wherein the power amplifier further comprises a buffer configured to buffer an internal voltage of the current mirror to generate a gate bias voltage for the field effect transistor.

16. The gate of the first mirror transistor is connected to the gate of the second mirror transistor; The envelope tracking system of claim 11 , wherein a gate of the third mirror transistor is connected to a gate of the fourth mirror transistor.

17. The drain of the second mirror transistor is connected to the gate of the second mirror transistor; The envelope tracking system of claim 11 , wherein the drain of the third mirror transistor is connected to the gate of the third mirror transistor.

18. 1. A method of radio frequency signal amplification in a mobile device, comprising: generating a power amplifier supply voltage that varies in relation to an envelope of the radio frequency signal using an envelope tracker; powering a power amplifier using the power amplifier supply voltage; amplifying the radio frequency signal using a field effect transistor of the power amplifier; generating a gate bias voltage for the field effect transistor using an internal voltage of a current mirror of the power amplifier, providing a reference current at an input of the current mirror and providing the power amplifier supply voltage at an output of the current mirror; increasing an internal voltage of the current mirror in response to a decrease in the power amplifier supply voltage; decreasing an internal voltage of the current mirror in response to an increase in the power amplifier supply voltage; A method comprising:

19. 20. The method of claim 18, further comprising buffering an internal voltage of the current mirror to generate a gate bias voltage of the field effect transistor.

20. The method of claim 19, wherein buffering the internal voltage includes using a first depletion mode transistor and a second depletion mode transistor to provide a zero shift in the buffering.

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