Semiconductor integrated circuit, semiconductor memory device, memory system, and frequency generation method

Abstract

To change a signal frequency in a relatively short time.SOLUTION: A semiconductor integrated circuit of an embodiment comprises: a first oscillator which generates a signal of a first frequency based on a control signal; a control signal generation circuit which constitutes a feedback loop with the first oscillator and generates the control signal when an output signal of the first oscillator is supplied via a path to the feedback loop; and a second oscillator which generates a signal of a second frequency based on the control signal and outputs the generated signal to an output terminal outside the path to the feedback loop.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor integrated circuit, a semiconductor memory device, a memory system, and a frequency generation method. [Background technology]

[0002] In various communication systems, the communication speed can be increased by increasing the operating frequency or making the operating frequency variable. For example, in an interface circuit in a memory system that employs a semiconductor memory or other semiconductor storage device, it may be possible to write and read data at high speed by optimizing the operating frequency by making it variable.

[0003] However, the time required to change the signal frequency is relatively long, and as a result, it is difficult to sufficiently increase the communication speed of the system. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special table 2015-504635 publication [Patent Document 2] U.S. Patent No. 7,439,816 [Patent Document 3] US Patent Application Publication No. 2019 / 363674 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present embodiment is to provide a semiconductor integrated circuit, a semiconductor memory device, a memory system, and a frequency generating method that are capable of changing a signal frequency in a relatively short time. [Means for solving the problem]

[0006] The semiconductor integrated circuit of an embodiment includes a first oscillator that generates a signal of a first frequency based on a control signal, a control signal generating circuit that forms a feedback loop with the first oscillator and generates the control signal when an output signal of the first oscillator is supplied via a path to the feedback loop, and a second oscillator that generates a signal of a second frequency based on the control signal and outputs the generated signal to an output terminal outside the path to the feedback loop. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram showing a clock generation circuit configured using a semiconductor integrated circuit according to the embodiment. [Diagram 2] FIG. 2 is a block diagram showing a memory system including the semiconductor integrated circuit of FIG. [Diagram 3] FIG. 1 is a block diagram showing a configuration of a communication system. [Figure 4] FIG. 1 is an explanatory diagram for explaining an increase in communication speed by making the frequency variable and setting an optimal frequency for the system. [Diagram 5] FIG. 1 is a block diagram showing a comparative example of a clock generation circuit. [Figure 6] FIG. 11 is a waveform diagram showing a change in output frequency when the frequency is changed in a comparative example, with the horizontal axis representing time and the vertical axis representing output frequency. [Figure 7] 4 is a waveform diagram showing a change in output frequency when the frequency is changed, with the horizontal axis representing time and the vertical axis representing output frequency. [Figure 8] FIG. 4 is a block diagram showing a second embodiment of the present invention. [Figure 9] FIG. 9 is a circuit diagram showing an example of a specific configuration of the frequency measurement circuit 41 of FIG. 8. [Figure 10] 10 is a timing chart for explaining the operation of the circuit shown in FIG. [Figure 11] 9 is a flowchart for explaining the operation of the circuit shown in FIG. 8 . [Figure 12] FIG. 9 is an explanatory diagram for explaining the operation of the circuit shown in FIG. 8 . [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. 4 is a circuit diagram showing an example of an OSC that can be used in each embodiment. [Figure 16] FIG. 11 is a circuit diagram showing an example of another OSC that can be used in each embodiment. [Figure 17] FIG. 4 is a circuit diagram showing a specific example of a VIC circuit that can be used in each embodiment. [Figure 18] 18 is a circuit diagram showing an example of frequency multiplication when the OSC circuit of FIG. 16 and the VIC circuit of FIG. 17 are employed. [Figure 19] 18 is a circuit diagram showing an example of frequency multiplication when the OSC circuit of FIG. 16 and the VIC circuit of FIG. 17 are employed. [Figure 20] FIG. 4 is an explanatory diagram for explaining a frequency change due to frequency multiplication. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0009] The semiconductor integrated circuit of this embodiment employs a signal generating circuit that oscillates at a stable frequency by a feedback loop, and uses a signal generated by the signal generating circuit to change the output frequency by a circuit that does not form a feedback loop, thereby enabling a frequency change in a relatively short time. Note that, in this embodiment, an example of application to a clock generating circuit will be described, but it is also possible to apply the present invention to an interface circuit or a PLL (Phase Locked Loop) circuit that uses a clock generating circuit. Also, in this embodiment, an example of application to an interface circuit employed in a memory system will be described as an interface circuit, but it may be applied to other interface circuits or circuits other than an interface circuit.

[0010] (faster) Figures 3 and 4 are diagrams for explaining how to increase the communication speed by making the frequency variable and setting an optimal frequency for the system. Figure 3 is a block diagram showing the configuration of a communication system, and Figure 4 is an explanatory diagram showing the communication speed (communication frequency) in the communication system of Figure 3.

[0011] 3 and 4 are based on the assumption that data is transmitted from system X to system Y, and further, data is transmitted from system Y to system Z.

[0012] 3, system X has a clock generation circuit 1X and an interface circuit (hereinafter referred to as an I / F circuit) 2X. The clock generation circuit 1X generates a clock as an output signal and provides it to the I / F circuit 2X. The I / F circuit 2X transmits data to be transmitted from system X to system Y in synchronization with the clock generated by the clock generation circuit 1X.

[0013] System Y has a clock generation circuit 1Y, I / F circuits 2Ya, 2Yb, and a data storage 3. The I / F circuit 2Ya receives data from the I / F circuit 2X and provides it to the data storage 3 for storage. The clock generation circuit 1Y generates a clock as an output signal and provides it to the I / F circuit 2Yb. The I / F circuit 2Yb transmits data read from the data storage 3 to system Z in synchronization with the clock generated by the clock generation circuit 1Y. System Z has an I / F circuit 2Z, and the I / F circuit 2Z receives data from the I / F circuit 2Yb.

[0014] The maximum operating frequency between System Y and System Z is determined by the maximum operating frequency of the I / F circuit 2Yb of System Y and the maximum operating frequency of the I / F circuit 2Z of System Z. Now, let the frequency of the output signal of the clock generation circuit 1X (clock frequency) be FX, and the frequency of the output signal of the clock generation circuit 1Y (clock frequency) be FY. Data transmission from System X to System Y is performed in synchronization with the clock having the frequency FX, and data transmission from System Y to System Z is performed in synchronization with the clock having the frequency FY. The actual communication frequency between System Y and System Z is restricted by the output (clock) frequency FY of the clock generation circuit 1Y.

[0015] Assume the case where FY < FX, that is, the amount of data sent from System X to System Y is larger than the amount of data sent from System Y to System Z in a certain period of time. In this case, if the bus widths between the I / F circuit 2X and the I / F circuit 2Ya and between the I / F circuit 2Yb and the I / F circuit 2Z are the same, communication can be realized if all the difference between the amount of data received by System Y and the amount of data transmitted by System Y during the communication period can be stored in the data storage 3. However, if the capacity of the data storage 3 is small, the data storage 3 may overflow depending on the difference in the amount of transmitted and received data, and communication cannot be realized. Considering reducing the capacity of the data storage 3 to reduce the chip area of System Y, basically FY ≧ FX needs to hold.

[0016] Figure 4 is an explanatory diagram showing the relationship between FX, FY and the communication speed of the entire communication system. The upper part of Figure 4 shows an example when FY is fixed, and the lower part of Figure 4 shows an example when FY is variable. Figure 4 takes the communication speed on the vertical axis, shows the communication speed between Systems X and Y on the left side, and the communication speed between Systems Y and Z on the right side.

[0017] (When FY is fixed) Now, let FYmax be the maximum value of the clock frequency FY that can be generated in the clock generation circuit 1Y. In other words, FYmax is the maximum communication frequency that provides the theoretical maximum value of the communication speed between system Y and system Z. FY varies by ±Δ[Hz] due to the influence of temperature, power supply voltage fluctuation, manufacturing process, trimming accuracy, etc. Therefore, the maximum frequency that can be generated in the clock generation circuit 1Y is set to FYmax-Δ (dashed line in the upper right of Figure 4), and the maximum communication frequency that can be used in actual communication from system Y to system Z is FYmax-2Δ (bold line).

[0018] When FY≧FX, even if the frequency FX that can be generated in the clock generation circuit 1X is higher than the frequency FY that can be generated in the clock generation circuit 1Y, the maximum communication frequency FXmax allowed for the entire system is limited to FXmax≦FYmax-2Δ.

[0019] (When FY is variable) Suppose that the clock frequency (output frequency) of the clock generation circuit 1Y is FYmax-Δ and the output frequency FX of the clock generation circuit 1X is FX≦FYmax-Δ, and then the frequency of FX increases and changes to FX>FYmax-Δ. The lower part of FIG. 4 assumes the state after such a frequency change. In this case, data transmission is possible by increasing FY in accordance with the change in FX. The level change of the bold line in the system YZ communication speed in FIG. 4 indicates such a change in FY. In this case, by changing the output clock frequency of the clock generation circuit 1X to FYmax, the maximum communication frequency FXmax allowed for the entire system becomes FXmax=FYmax. In this way, by making FY variable, the maximum communication frequency allowed for the entire system can be increased.

[0020] Incidentally, in the example at the bottom of Fig. 4, during the period until the output frequency of the clock generation circuit 1Y changes from FYmax-Δ to FYmax, an amount of data corresponding to the frequency difference between FX and FY is stored in the data storage 3. If FY does not change to FYmax before the data storage 3 overflows, communication cannot be realized. In other words, in order to realize communication, it is necessary to sufficiently shorten the time required for frequency switching so that the small-capacity data storage 3 does not overflow.

[0021] (Comparative example of clock generation circuit) FIG. 5 is a block diagram showing a comparative example of a clock generation circuit.

[0022] 5, the clock generation circuit 1 is composed of a bias circuit 4, a frequency-to-voltage conversion (FVC) circuit 5, an amplifier 6, a low-pass filter (LPF) 7, a voltage-to-current conversion (VIC) circuit 8, and an oscillator (OSC) 9. A reference voltage VB and a reference current IB are supplied to terminals I1 and I2 of the clock generation circuit 1, respectively.

[0023] The bias circuit 4 generates a bias current corresponding to the reference current IB supplied to the terminal I2, and supplies the generated bias current to the FVC circuit 5. The FVC circuit 5 converts the frequency of the oscillation output from the OSC 9 (described later) into a voltage using the bias current from the bias circuit 4, and outputs the converted voltage to the amplifier 6. The FVC circuit 5 may be configured using, for example, a capacitor (not shown). For example, the FVC circuit 5 may charge and discharge a capacitor using the bias current supplied from the bias circuit 4 for a period corresponding to the output of the OSC 9, and output the terminal voltage of the capacitor as the voltage conversion result.

[0024] A reference voltage VB is also applied to the amplifier 6 from the terminal I1. The amplifier 6 outputs a voltage that is the difference between the reference voltage VB and the output voltage of the FVC circuit 5 to the LPF 7. The LPF 7 averages the output of the amplifier 6 and supplies it to the FVC circuit 5. The VIC circuit 8 as a first current source is connected to a power supply line that supplies a power supply voltage, and converts the output voltage of the LPF 7 into a current and supplies it to the OSC 9. The VIC circuit 8 can be configured, for example, by a PMOS transistor having a source connected to the power supply line, a gate to which the output of the LPF 7 is applied, and a drain connected to the OSC 9.

[0025] The first oscillator OSC9 can be configured, for example, by a ring oscillator. The OSC9 oscillates at a frequency according to the input current, and outputs a clock (CLK) as an output signal from an output terminal O. The OSC9 also feeds back the generated clock to the FVC circuit 5.

[0026] When the frequency of the output clock of OSC9 is higher than the reference frequency corresponding to the reference voltage VB, the output voltage of the FVC circuit 5 becomes higher than the reference voltage VB, and the output voltage of the amplifier 6 becomes large. As a result, the current supplied from the VIC circuit 8 to OSC9 becomes smaller, and the frequency of the output clock of OSC9 decreases.

[0027] Conversely, when the frequency of the output clock of OSC9 is lower than the reference frequency corresponding to the reference voltage VB, the output voltage of the FVC circuit 5 becomes lower than the reference voltage VB, and the output voltage of the amplifier 6 becomes smaller. As a result, the current supplied to OSC9 from the VIC circuit 8 becomes larger, and the frequency of the output clock of OSC9 increases. Thus, the output clock frequency of OSC9 coincides with the reference frequency corresponding to the reference voltage VB.

[0028] Thus, the clock generation circuit 1 includes a feedback (FB) loop (broken line arrow) that is configured by the bias circuit 4, FVC circuit 5, amplifier 6, LPF 7, VIC circuit 8, and OSC 9. This FB loop causes the output clock frequency of OSC 9 to converge to a specified frequency. In other words, once the FB loop is locked (stabilized), it is possible to maintain the output clock frequency at the specified frequency even if fluctuations in the power supply voltage, temperature, etc. occur.

[0029] Incidentally, in order to change the frequency of the output clock of the clock generation circuit 1, it is necessary to change the settings of the reference voltage VB and reference current IB related to the FB loop, and to change the circuit settings of the bias circuit 4, FVC circuit 5, VIC circuit 8, and OSC9, which are indicated by diagonal arrows in Fig. 4. For example, the output clock frequency of the VIC circuit 8 can be changed by using multiple PMOS transistors and changing the number of connected PMOS transistors. For example, the output clock frequency of the OSC9 can be changed by changing the number of inverter stages that make up the ring oscillator.

[0030] However, such a setting change causes a disturbance to the FB loop, which is operating stably, and makes the FB loop unstable. The FB loop has a loop band limited by the LPF 7 to enable stable loop control, and it takes a relatively long time to re-stabilize the unstable FB loop. As a result, after the setting change is made to change the clock frequency of the clock generation circuit 1, it takes a relatively long time for the clock frequency of the clock generation circuit 1 to stabilize at a desired frequency.

[0031] Figure 6 is a waveform diagram showing this state, with time on the horizontal axis and output frequency on the vertical axis. As shown in Figure 6, if a setting change is made to change the output frequency at timing t1, the FB loop becomes unstable, the output frequency fluctuates, and the desired frequency is reached at timing t2, a relatively long time later.

[0032] 3 and 4, if a clock generation circuit 1Y having the same configuration as the clock generation circuit 1 is used, FX>FY may remain for a relatively long time after the frequency is changed. For this reason, in the systems of Figures 3 and 4, if the maximum communication frequency allowable for the system is increased, the capacity of the data storage 3 must be made sufficiently large.

[0033] It is also possible to prepare two circuits similar to the comparative example in Fig. 5, use one circuit to detect the set value and the other circuit to output the clock, and set the set value detected by one circuit to the other circuit. However, even in this case, it takes a relatively long time for the FB loop of the other circuit to stabilize when the frequency is changed.

[0034] (composition) Therefore, in this embodiment, an FB loop is adopted, and a circuit that generates an output clock without being affected by the FB loop is adopted.

[0035] Fig. 1 is a block diagram showing a clock generating circuit configured by a semiconductor integrated circuit according to this embodiment, and Fig. 2 is a block diagram showing a memory system including the semiconductor integrated circuit of Fig. 1.

[0036] The memory system in Fig. 2 includes a memory controller 21 and a semiconductor memory device 30. The semiconductor memory device 30 includes a memory interface (I / F) circuit 31 and a semiconductor memory 37. The memory controller 21 corresponds to system X in Fig. 3, the memory I / F circuit 31 corresponds to system Y, and the semiconductor memory 37 corresponds to system Z. The data transmission shown in Fig. 3 and Fig. 4 corresponds to, for example, the case where data from the memory controller 21 is stored in the semiconductor memory 37.

[0037] (Memory system configuration) The memory controller 21 and the semiconductor memory 37 are connected by an I / F circuit 31. The memory I / F circuit 31 and the semiconductor memory 37 are packaged as a semiconductor memory device 30. Although Fig. 1 shows an example in which one memory I / F circuit 31 and one semiconductor memory 37 are provided in the semiconductor memory device 30, one memory I / F circuit 31 may be provided with m (m is an integer of 2 or more) semiconductor memories 37, and one memory controller 21 may be provided with n (n is an integer of 2 or more) memory I / F circuits 31.

[0038] For example, multiple power supplies such as 1.2V, 1.8V, and 3.3V may be adopted for the memory controller 21. On the other hand, a power supply of, for example, 1.2V may be adopted for the semiconductor memory 37. Even in such a case, by adopting the memory I / F circuit 31, data transmission between the memory controller 21 and the semiconductor memory 37 can be made possible regardless of the difference between these power supply voltages. Furthermore, for example, the memory I / F circuit 31 enables effective data transmission even in cases where the memory controller 21 and the semiconductor memory 37 adopt different protocols.

[0039] The memory system can be connected to a host (not shown). The host is, for example, an electronic device such as a personal computer, a mobile terminal, an in-vehicle device, or a server. In response to a request from the host, the memory system stores user data (hereinafter simply referred to as data) from the host in each semiconductor memory 37, reads data stored in each semiconductor memory 37, and outputs the data to the host. Specifically, the memory system can write data to each semiconductor memory 37 in response to a write request from the host, and read data from each semiconductor memory 37 in response to a read request from the host.

[0040] The memory system may be a Universal Flash Storage (UFS) device or the like in which a memory controller 21, a plurality of memory I / F circuits 31, and a semiconductor memory 37 are configured as one package, or may be a Solid State Drive (SSD) or the like.

[0041] 2, the memory controller 21 controls writing of data to the semiconductor memory 37 in response to a write request from the host. The memory controller 21 also controls reading of data from the semiconductor memory 37 in response to a read request from the host. The memory controller 21 may control writing and reading of data to the semiconductor memory 37 on its own initiative, rather than in response to a request from the host.

[0042] The host and the memory controller 21 are connected via a predetermined interface. For example, various interfaces such as an eMMC (embedded Multi Media Card) parallel interface, a PCIe (Peripheral Component Interconnect-Express) serial expansion interface, and an M-PHY high-speed serial interface are adopted as this interface.

[0043] The memory controller 21 includes a CPU (Central Processing Unit) (not shown) and controls the process of writing user data and the like to each semiconductor memory 37 and the process of reading user data from each semiconductor memory 37 based on instructions from the CPU. When the CPU of the memory controller 21 receives a request from the host, it performs control according to the request. For example, the CPU of the memory controller 21 instructs the memory I / F circuit 31 to write user data to each semiconductor memory 37 in accordance with the request from the host. Also, the CPU of the memory controller 21 instructs the memory I / F circuit 31 to read user data from each semiconductor memory 37 in accordance with the request from the host.

[0044] 2, the memory controller 21 includes a clock generation circuit 22 and an I / F circuit 23 having the same configurations as the clock generation circuit 1X and the I / F circuit 2X, respectively, in Fig. 3. Also, the memory I / F circuit 31 includes I / F circuits 33, 34 and a data storage 35 having the same configurations as the I / F circuits 2Ya, 2Yb and the data storage 3, respectively, in Fig. 3. The semiconductor memory 37 includes an I / F circuit 38 having the same configuration as the I / F circuit 2Z in Fig. 3.

[0045] In this embodiment, the memory I / F circuit 31 employs the clock generation circuit 10 shown in Fig. 1 as the clock generation circuit 1Y in Fig. 3. The memory I / F circuit 31 also includes a control circuit 32 and a memory 36 that enable settings of the clock generation circuit 10 to be changed. The control circuit 32 may be configured by a processor using a CPU, an FPGA (Field Programmable Gate Array), or the like, may operate according to a program stored in a memory (not shown) to control each part, or may realize some or all of the functions by a hardware electronic circuit.

[0046] If the clock frequency generated by the clock generation circuit 22 is FX and the clock frequency generated by the clock generation circuit 10 is FY, the control circuit 32 controls the frequency of the output clock of the clock generation circuit 10 so that the frequency FY of the output clock of the clock generation circuit 10 satisfies FX≦FY. The clock generation circuit 10 employed in this embodiment can change FY to a frequency corresponding to FX in an extremely short time after the frequency FX is changed.

[0047] (Clock generation circuit) Next, the configuration of the clock generation circuit 10 will be described with reference to Fig. 1. Note that in Fig. 1, the same components as those in Fig. 5 are given the same reference numerals, and duplicated descriptions of the same configuration will be omitted.

[0048] The clock generation circuit 10 includes a bias circuit 4, an FVC circuit 5, an amplifier 6, an LPF 7, a VIC circuit 8, and an OSC 9. A reference voltage VB and a reference current IB are supplied to terminals I1 and I2 of the clock generation circuit 1, respectively. In the clock generation circuit 10, the bias circuit 4, the FVC circuit 5, the amplifier 6, the LPF 7, the VIC circuit 8, and the OSC 9 form an FB loop. The bias circuit 4, the FVC circuit 5, the amplifier 6, and the LPF 7 form a control signal generation circuit.

[0049] In this embodiment, the oscillation clock from OSC 9 is fed back to the FVC circuit 5 but is not output to the output terminal O.

[0050] In this embodiment, the clock generation circuit 10 includes a VIC circuit 11 and an OSC12 that do not constitute an FB loop, in addition to these circuits that constitute the FB loop. The output of the LPF7 is given to the VIC circuit 11. The VIC circuit 11 as a second current source is connected to a power supply line that supplies a power supply voltage, and converts the output voltage of the LPF7, which is a control signal for the FB loop, into a current and supplies it to the OSC12. The VIC circuit 11 can be configured, for example, by one or more PMOS transistors whose sources are connected to the power supply line, whose gates are applied with the output of the LPF7, and whose drains are connected to the OSC12. The OSC12 as a second oscillator can be configured, for example, by a ring oscillator. The OSC12 oscillates at a frequency according to the input current, and outputs a clock (CLK) from an output terminal O as an output signal. Note that the OSC12 does not constitute an FB loop, and the output of the OSC12 is not fed back to the FVC circuit 5.

[0051] The VIC circuit 11 may be configured to be able to change the conversion characteristics of the voltage-current conversion. For example, the VIC circuit 11 may be configured using a plurality of PMOS transistors, and the number of PMOS transistors used for the voltage-current conversion may be made changeable, thereby making the conversion characteristics of the voltage-current conversion changeable. For example, a switch is provided between the source of each PMOS transistor and the power supply line, and between the drain and OSC 12, and the number of switches to be turned on is controlled, thereby making it possible to change the conversion characteristics of the voltage-current conversion.

[0052] Furthermore, the current-frequency conversion characteristics of OSC 12 may be changeable. For example, if OSC 12 is configured as a ring oscillator made up of multiple inverters, the number of stages of connected inverters may be changeable, or the capacitance of the capacitor that configures the ring oscillator may be made variable, thereby making it possible to change the voltage-current conversion characteristics.

[0053] In this embodiment, when changing the output clock frequency, the settings of the reference voltage VB, reference current IB, bias circuit 4, FVC circuit 5, VIC circuit 8, and OSC9 that affect the FB loop are not changed, and the settings of at least one of the VIC circuits 11 and OSC12 that do not constitute the FB loop are changed. Since feedback control using the output of OSC12 is not performed, changing the settings of at least one of the VIC circuits 11 and OSC12 does not cause a disturbance to the FB loop.

[0054] The control circuit 32 changes the frequency of the output clock from OSC12 by changing the setting of at least one of the VIC circuit 11 and OSC12. Note that the memory 36 stores setting information for setting FY. The control circuit 32 reads the setting information from the memory 36, and changes the setting of at least one of the VIC circuit 11 and OSC12 based on the read setting information. For example, the control circuit 32 may obtain setting information for each output clock frequency from OSC12 when that frequency is obtained while changing the setting of at least one of the VIC circuit 11 and OSC12, and store the obtained setting information in advance in the memory 36.

[0055] In this embodiment, the VIC circuit 8 and the VIC circuit 11 are configured to obtain the same characteristics. For example, the VIC circuit 8 and the VIC circuit 11 are configured in close proximity to each other on the layout of the semiconductor integrated circuit. Also, the OSC9 and the OSC12 are configured to obtain the same characteristics. For example, the OSC9 and the OSC12 are configured in close proximity to each other on the layout of the semiconductor integrated circuit. As a result, it is considered that when a change in temperature or power supply voltage occurs, the VIC circuit 8 and the VIC circuit 11 will have the same characteristic change, and the OSC9 and the OSC12 will have the same characteristic change. Therefore, when a desired frequency can be obtained from the OSC9 by loop control of the FB loop, regardless of the change in temperature or power supply voltage, it is considered that a desired frequency can also be obtained from the OSC12, regardless of the change in temperature or power supply voltage.

[0056] Next, the operation of the embodiment configured as above will be described with reference to Fig. 7. Fig. 7 is a waveform diagram showing the change in output frequency when the frequency is changed, with the horizontal axis representing time and the vertical axis representing output frequency.

[0057] When the power is turned on, the OSC9 of the clock generation circuit 10 starts oscillating at a predetermined frequency. The bias circuit 4 supplies the FVC circuit 5 with a current corresponding to the reference current IB input via the input terminal I1, for example, a multiplied current. The FVC circuit 5 converts the frequency of the output of the OSC9 into a voltage using the reference current IB and outputs it to the amplifier 6. The amplifier 6 outputs a voltage according to the difference between the output voltage of the FVC circuit 5 and the reference voltage VB input via the input terminal I2 to the LPF 7. The LPF 7 averages the output of the amplifier 6 and supplies it to the VIC circuit 8. The VIC circuit 8 supplies a current based on the output of the LPF 7 to the OSC9. In this way, the OSC9 generates a clock with a frequency according to the current from the LPF 7. This FB loop causes the frequency of the clock generated by the OSC9 to converge to a desired frequency.

[0058] In this embodiment, the output of LPF 7 is supplied not only to VIC circuit 8 but also to VIC circuit 11. By matching the characteristics of VIC circuit 8 and VIC circuit 11, VIC circuit 11 supplies OSC12 with a current similar to the current that VIC circuit 8 supplies to OSC9. Furthermore, by matching the characteristics of OSC9 and OSC12, OSC12 generates a clock with the same frequency as OSC9. OSC12 outputs the generated clock (CLK) from output terminal O. The output signal of OSC12 is supplied to I / F circuit 34 as the output of clock generation circuit 10.

[0059] With the output of the clock generation circuit 10 in a stable state, data transmission is started between the memory controller 21 and the semiconductor memory 37. That is, the clock generation circuit 22 of the memory controller 21 generates a clock having a frequency FX and provides it to the I / F circuit 23, and the I / F circuit 23 transmits data from the memory controller 21 to the memory I / F circuit 31 in synchronization with the clock generated by the clock generation circuit 22.

[0060] The I / F circuit 33 of the memory I / F circuit 31 receives data from the I / F circuit 23 and provides it to the data storage 35. The data storage 35 outputs the data received by the I / F circuit 33 to the I / F circuit 34 while storing the data. The I / F circuit 34 is provided with a clock having a frequency FY from the clock generation circuit 10, and outputs data read from the data storage 35 to the semiconductor memory 37 in synchronization with this clock. The I / F circuit 38 of the semiconductor memory 37 receives the data transmitted from the I / F circuit 34.

[0061] In this data transmission, FX≦FY is set, and data from memory controller 21 is reliably transmitted to semiconductor memory 37. For example, even if temperature fluctuations or power supply voltage fluctuations occur, fluctuations in the clock frequency of OSC9 are minimal due to the FB loop that constitutes clock generation circuit 10, and OSC9 continues to output a clock of approximately the desired frequency. VIC circuit 11 supplies a current according to the output of LPF 7 to OSC12, and OSC12 continues to output a clock of the desired frequency, just like OSC9.

[0062] Here, it is assumed that the frequency FX of the clock generated by the clock generation circuit 22 changes and becomes a higher frequency than FY before the change. The control circuit 32 is provided with information about the frequency FX of the clock generated by the clock generation circuit 22, and when FX changes, the control circuit 32 changes the setting value of the clock generation circuit 10 so as to increase the frequency of the clock generated by the clock generation circuit 10 in response to the change in FX.

[0063] That is, the control circuit 32 changes the frequency of the clock generated by the OSC12 by changing the setting of at least one of the VIC circuit 11 and the OSC12 constituting the clock generating circuit 10. The VIC circuit 11 and the OSC12 do not constitute a FB loop, and even if the setting values ​​of the VIC circuit 11 and the OSC12 are changed, no disturbance occurs in the FB loop, and the clock frequency from the OSC12 changes to the desired frequency in a sufficiently short time. For example, in the clock generating circuit of the comparative example, it took about several μs for the frequency to be stabilized at the desired frequency after the frequency change due to the band limit of the FB loop, whereas in the clock generating circuit 10 of this embodiment, it is assumed that the time required from the start of the frequency change until the frequency is stabilized at the desired frequency is about several n seconds to several tens of n seconds.

[0064] FIG. 7 shows this state, and when the setting of at least one of the VIC circuit 11 and the OSC 12 is changed at timing t3, the output frequency of the OSC 12 reaches the desired frequency after a relatively short frequency conversion time.

[0065] As a result, the increase in the amount of data that the data storage 35 must hold is relatively small, and even if a data storage 35 with a relatively small capacity is used, data communication from the memory controller 21 to the semiconductor memory 37 can be continued.

[0066] In this manner, in this embodiment, a feedback loop is utilized to generate a signal with a stable frequency, and an oscillator that does not form a feedback loop and does not disturb the feedback loop is utilized to change the output frequency, making it possible to change the frequency in a relatively short time (high speed) regardless of the loop bandwidth of the feedback loop. As a result, when this embodiment is used as a clock generation circuit of an interface circuit that relays data, not only can the maximum communication frequency be maximized by changing the frequency, but also the capacity of the buffer that stores data can be reduced by the difference in the amount of transmission data due to the difference in communication frequency.

[0067] Second embodiment Fig. 8 is a block diagram showing a second embodiment of the present invention. In Fig. 8, the same components as those in Fig. 1 are given the same reference numerals and the description thereof will be omitted. This embodiment makes it possible to accurately change the frequency to a desired frequency when changing the frequency.

[0068] In the first embodiment, in order to generate a clock of a desired frequency after the frequency change, the setting information for setting at least one of the VIC circuit 11 and the OSC 12 is stored in the memory 36. In the present embodiment, it is possible to sequentially obtain setting information for setting at least one of the VIC circuit 11 and the OSC 12 when changing the frequency according to the desired frequency.

[0069] The embodiment of FIG. 8 differs from the embodiment of FIG. 1 in that a frequency measurement circuit 41, a control logic circuit 42, and switches SW1 and SW2 are added. A clock (CLK) appearing at an output terminal O is output as an output signal and is also supplied to the frequency measurement circuit 41 via the switch SW1. A reference clock RECLK is also input to the frequency measurement circuit 41 via the switch SW2. The frequency measurement circuit 41 is controlled by the control circuit 32 (not shown) to measure the frequency or period of the clock CLK input via the switch SW1 and the frequency or period of the reference clock RECLK input via the switch SW2, and outputs the measurement results to the control logic circuit 42. The switches SW1 and SW2 are controlled to be turned on and off by the control circuit 32.

[0070] Fig. 9 is a circuit diagram showing an example of a specific configuration of the frequency measurement circuit 41 of Fig. 8. In Fig. 9, the frequency measurement circuit 41 is configured by a TDC (Time-to-Digital Converter) circuit. Fig. 10 is a timing chart for explaining the operation of the circuit shown in Fig. 9.

[0071] The frequency measurement circuit 41 has a plurality of cascaded delay elements D0 to Dn-1 (hereinafter, when no distinction is made between them, they will be collectively referred to as delay element D) and phase detectors F0 to Fn-1 (hereinafter, when no distinction is made between them, they will be collectively referred to as phase detector F) to which the outputs clk0 to clkn-1 of the delay elements D0 to Dn-1 are respectively provided. A clock clk_ref is input to the first-stage delay element D0, and this clock clk_ref passes through the delay elements D in sequence while being delayed by the delay elements D0 to Dn-1. Figure 10 shows the clock clk_ref and the outputs clk0 to clkn-1 of the delay elements D0 to Dn-1.

[0072] These outputs clk0 to clkn-1 are respectively provided to phase detectors F0 to Fn-1. The phase detectors F0 to Fn-1 take in and output the outputs clk0 to clkn-1 at the rising edge of the second clock clk_ref. In the example of FIG. 10, at the rising edge of the second clock clk_ref, the output of the delay element D through which the first clock clk_ref has not passed is at a low level (hereinafter referred to as an L level), and the output of the phase detector F to which the output of these delay elements D is provided is also at an L level. Furthermore, at the rising edge of the second clock clk_ref, the output of the most recent delay element D among the delay elements D through which the first clock clk_ref has passed is at a high level (hereinafter referred to as an H level), and the output of the phase detector F to which the output of this delay element D is provided is also at an H level.

[0073] In the example of FIG. 10, the clock clk_ref passes through delay elements D up to the mth stage, but does not pass through the delay element D at the (m+1)th stage. That is, one period of the clock clk_ref corresponds to the delay time of delay elements D for m+1 stages. The outputs q0 to qn-1 of the phase detectors F0 to Fn-1 are provided to a decoder 41a. The decoder 41a determines the period of the clock clk_ref from the outputs q0 to qn-1 of the phase detectors F0 to Fn-1. The decoder 41a outputs the determined period to the control logic circuit 42 as a measurement result.

[0074] The control logic circuit 42 is controlled by the control circuit 32 to obtain a frequency difference or a period difference between the clock CLK and the reference clock RECLK based on the measurement result from the frequency measurement circuit 41, and performs logic calculations to obtain setting information to be set for at least one of the VIC circuit 11 and OSC12 according to the obtained frequency difference or period difference. That is, the control logic circuit 42 obtains setting information for matching the frequency of the clock CLK from the OSC12 with the frequency of the reference clock RECLK. The control logic circuit 42 outputs the obtained setting information to the control circuit 32. The control circuit 32 changes the setting of at least one of the VIC circuit 11 and OSC12 based on the setting information obtained by the control logic circuit 42.

[0075] The other configuration is similar to that of the first embodiment.

[0076] Next, the operation of the embodiment configured in this manner will be described with reference to the flow chart of Fig. 11 and the explanatory diagram of Fig. 12. The upper part of Fig. 12 is a graph showing changes in the frequency of the clock CLK, with the horizontal axis representing time and the vertical axis representing output frequency, while the lower part of Fig. 12 shows the clock CLK and the reference clock RECLK, with the same time axis as the upper part on the horizontal axis and the vertical axis representing level, as well as the processing time of the frequency measurement circuit 41 and the control logic circuit 42. In the following description, the frequency measurement circuit 41 will be described as measuring the period, but it may also measure the frequency.

[0077] After power-on, the clock CLK is input to the frequency measurement circuit 41 via the switch SW1, and the reference clock RECLK is input to the frequency measurement circuit 41 via the switch SW2. The frequency measurement circuit 41 measures the period of the clock CLK (hereinafter referred to as the CLK period) (S1), then measures the period of the reference clock RECLK (hereinafter referred to as the RECLK period), and outputs these measurement results to the control logic circuit 42. The control logic circuit 42 determines whether these periods match, that is, whether the frequencies of the clock CLK and the reference clock RECLK match, and if they do not match, obtains setting information for matching the frequency of the clock CLK to the frequency of the reference clock RECLK and outputs it to the control circuit 32 (S4). The control circuit 32 sets at least one of the VIC circuit 11 and the OSC 12 based on the setting information (S5).

[0078] Fig. 12 shows the change in frequency of the clock CLK after a stable frequency of the clock CLK is output from OSC12 of the clock generation circuit 10 after power is turned on. After the clock CLK stabilizes, the period of the CLK and the period of the RECLK are assumed to match at the start timing of the time axis in Fig. 12. Then, immediately after the start timing of the time axis in Fig. 12, the frequency of the reference clock RECLK becomes lower than the previous frequency.

[0079] 12, in a predetermined 1 CLK period of the clock CLK, the switch SW1 is turned on and the clock CLK is supplied to the frequency measurement circuit 41, and the period (CLK period) is measured by the frequency measurement circuit 41. In 1 RECLK period, for example, 1.5 CLK periods after the frequency measurement period of this clock CLK, the switch SW2 is turned on and the clock RECLK is supplied to the frequency measurement circuit 41, and the period (RECLK period) is measured by the frequency measurement circuit 41.

[0080] Then, for example, 2.5 RECLK periods from the end of the frequency measurement period of the reference clock RECLK, logic calculation is performed by the control logic circuit 42, and the setting information, which is the calculation result, is supplied to the control circuit 32. The control circuit 32 changes the setting value of at least one of the VIC circuit 11 and the OSC 12 based on the setting information, for example, 1.5 RECLK periods from timing t4 after the end of the logic calculation period of the setting information. This setting change ends at timing t5, 1.5 RECLK periods after timing t4. That is, in the example of FIG. 12, the period required from timing t4 when the frequency starts to change to timing t5 when it changes to the desired frequency is, for example, 1.5 RECLK periods. If the frequency of the clock CLK cannot be made to match the frequency of the reference clock RECLK by one setting change, the processes of S1 to S5 are repeated to make the frequency of the clock CLK match the frequency of the reference clock RECLK. If the frequencies of the clock CLK and the reference clock RECLK are relatively close to each other, it is considered that the frequencies can be made to match by one setting change.

[0081] For example, by supplying the clock generated by the clock generation circuit 22 in Fig. 2 to the frequency measurement circuit 41 as the reference clock RECLK, it is possible to generate a clock having the same frequency as the frequency FX of the output clock of the clock generation circuit 22 from OSC12. Then, the frequency of the output clock of OSC12 can be changed in a relatively short time in accordance with the change in frequency FX. In the example of Fig. 12, it takes 9 CLK periods from measurement to frequency change, but if it is known in advance that FX will be changed, it is possible to change FY in an extremely short time after FX is changed, as shown in the frequency conversion time of Fig. 12, by generating the reference clock RECLK corresponding to the changed FX before FX is changed.

[0082] In this manner, in this embodiment, the clock frequency generated by OSC 12 can be made to coincide with the frequency of the reference clock, and the frequency can be changed in a short period of time in response to changes in the frequency of the reference clock.

[0083] In the above description, the frequency measurement circuit 41 has been described as measuring the clock period in one cycle of the clock, but it is also possible to measure the clock period in half a cycle of the clock. In this case, the frequency accuracy is degraded, but it is possible to change the frequency of the output clock in an even shorter time. Also, for example, by first measuring the clock period in a half cycle and then measuring the clock period in one cycle halfway through, it is possible to achieve a good balance between frequency accuracy and high speed.

[0084] (Modification) Figures 13 and 14 are block diagrams showing modified examples. In Figures 13 and 14, the same components as in Figure 8 are given the same reference numerals and their explanation will be omitted.

[0085] 13 differs from the embodiment in FIG. 8 in that an N-divider 45 is added. The N-divider 45 divides the clock CLK input via switch SW1 and the reference clock RECLK input via switch SW2 by N, and provides the divided clock to the frequency measurement circuit 41.

[0086] With this configuration, the frequency measurement circuit 41 only needs to measure the periods of the clock CLK and the reference clock RECLK that have been divided by N. This makes it possible to improve the frequency measurement accuracy of the frequency measurement circuit 41 compared to the case where the periods of the clock CLK and the reference clock RECLK are directly measured.

[0087] In this case, since the measurement time of the period in frequency measurement circuit 41 becomes longer by N times the frequency division number, it is better to set the frequency division number according to the system to which the embodiment is applied and determine the measurement time and frequency measurement accuracy.

[0088] The modified example of Fig. 14 differs from the embodiment of Fig. 8 in that N dividers 45 and 46 are added. N divider 45 divides clock CLK by N, and provides the divided clock to frequency measurement circuit 41 via switch SW1. In addition, N divider 46 divides reference clock RECLK by N, and provides the divided clock to frequency measurement circuit 41 via switch SW2.

[0089] The modification of Fig. 14 differs from the modification of Fig. 13 in that the frequency division number for the clock CLK and the frequency division number for the reference clock RECLK can be set separately. Other effects are the same as those of Fig. 13.

[0090] (Third embodiment) 15 to 20 show a third embodiment. This embodiment shows specific circuits that can be used as the VIC circuit 11 and the OSC 12.

[0091] (OSC example 1) FIG. 15 shows an example of a specific configuration of an OSC that can be used in each of the above embodiments.

[0092] FIG. 15 shows a ring oscillator composed of three stages of inverters I1, I2, and I3 (hereinafter, referred to as inverter I when there is no need to distinguish between them). The inverter I has a differential configuration and has a non-inverting input terminal IP, an inverting input terminal IN, a non-inverting output terminal OP, and an inverting output terminal ON. The inverter I has inverters IN1, IN2, IN3, and IN4. The inverter IN1 inverts a signal input to the non-inverting input terminal IP and outputs it to the non-inverting output terminal OP. The inverter IN2 inverts a signal input to the inverting input terminal IN and outputs it to the inverting output terminal ON. When averaged over a relatively long time, the inverters I1 to I3 are each given 1 / 3 of the current from the VIC circuit 11.

[0093] Inverter IN4 inverts the output of inverter IN1 and supplies it to the output terminal of inverter IN2, and inverter IN3 inverts the output of inverter IN2 and supplies it to the output terminal of inverter IN1. Inverter I performs differential operation due to the latch circuit formed by inverters IN3 and IN4. Mutually inverted input signals are input to the non-inverting input terminal IP and the inverting input terminal IN, respectively, and each inverter I inverts these input signals and outputs them from the non-inverting output terminal OP and the inverting output terminal ON.

[0094] The signal output from the output terminal OP,ON of inverter I1 is provided to the input terminal IP,IN of inverter I2, inverted by inverter I2 and output from the output terminal OP,ON of inverter I2. The signal output from the output terminal OP,ON of inverter I2 is provided to the input terminal IP,IN of inverter I3, inverted by inverter I3 and output from the output terminal OP,ON of inverter I3. The signal output from the output terminal OP,ON of inverter I3 is provided to the input terminal IP,IN of inverter I1, inverted by inverter I1 and output from the output terminal OP,ON of inverter I1.

[0095] In this embodiment, trimming circuits IS1P, IS2P, IS3P (hereinafter, when there is no need to distinguish between them, they will be referred to as trimming circuits ISP) for adjusting the oscillation frequency are connected to the non-inverting input terminals IP of the inverters I1, I2, I3, respectively. Also, trimming circuits IS1N, IS2N, IS3N (hereinafter, when there is no need to distinguish between them, they will be referred to as trimming circuits ISN) for adjusting the oscillation frequency are connected to the inverting input terminals IN of the inverters I1, I2, I3, respectively. The trimming circuits IS1P, IS2P, IS3P, IS1N, IS2N, IS3N have the same configuration.

[0096] The trimming circuit ISP has a plurality of switches T1, T2, ..., Tn and a plurality of capacitors C1, C2, ..., Cn. The switch T1 and the capacitor C1 are connected in series between the non-inverting input terminal IP and a reference potential point. Similarly, the switch Tm (m is 1 to n) and the capacitor Cm are connected in series between the non-inverting input terminal IP and a reference potential point.

[0097] The trimming circuit ISN has a plurality of switches T1, T2, ..., Tn and a plurality of capacitors C1, C2, ..., Cn. The switch T1 and the capacitor C1 are connected in series between the non-inverting input terminal IN and a reference potential point. Similarly, the switch Tm (m is 1 to n) and the capacitor Cm are connected in series between the non-inverting input terminal IN and a reference potential point.

[0098] The switches T1, T2, ..., Tn are controlled to be turned on and off by a control circuit 32. The control circuit 32 controls the switches T1, T2, ..., Tn to be turned on and off based on setting information stored in the memory 36 or setting information from the control logic circuit 42. When the switches T1, T2, ..., Tn are turned on, the capacitors C1, C2, ..., Cn connected to the turned-on switches are connected between the non-inverting input terminal IP or the inverting input terminal IN and the reference potential point. Hereinafter, the capacitance obtained by one or more capacitors connected between the non-inverting input terminal IP or the inverting input terminal IN and the reference potential point by the switches T1, T2, ..., Tn being turned on is referred to as the capacitance between the non-inverting input terminal IP and the inverting input terminal IN and the reference potential point.

[0099] In the OSC configured in this manner, oscillation occurs at an oscillation frequency based on the delay time of the inverter I and the number of stages of the inverter I. Furthermore, the oscillation frequency is adjusted by the capacitance between the non-inverting input terminal IP and the inverting input terminal IN and the reference potential point. The control circuit 32 simultaneously turns on or off all the switches Tm (m is 1 to n) of the trimming circuits ISP and ISN. For example, the oscillation frequency is adjusted by adjusting the number of switches to be turned on among the switches T1, T2, ..., Tn.

[0100] 15, the larger the current supplied from the VIC circuit 11, the shorter the time required to charge the capacitance between the non-inverting input terminal IP and the inverting input terminal IN and the reference potential point, and the higher the oscillation clock frequency. Conversely, the smaller the current supplied from the VIC circuit 11, the longer the time required to charge the capacitance between the non-inverting input terminal IP and the inverting input terminal IN and the reference potential point, and the lower the oscillation clock frequency. Also, the smaller the capacitance between the non-inverting input terminal IP and the inverting input terminal IN and the reference potential point, the shorter the time required for charging, and the higher the oscillation clock frequency, and the larger the capacitance between the non-inverting input terminal IP and the inverting input terminal IN and the reference potential point, the longer the time required for charging, and the lower the oscillation clock frequency.

[0101] 15, the oscillation clock frequency can be changed by controlling the on / off of the switches T1, T2, ..., Tn of the trimming circuits ISP, ISN based on the setting information by the control circuit 32. This makes it possible to change the frequency in a short time without disturbing the FB loop.

[0102] Although the example of FIG. 15 shows a three-stage inverter configuration, any number of stages may be used, and the frequency of the oscillation clock can be changed in a short time by switching the capacitance of each terminal.

[0103] (OSC example 2) Fig. 16 is a circuit diagram showing another OSC that can be used in each of the above embodiments. In Fig. 16, the same components as in Fig. 15 are given the same reference numerals and their explanations are omitted. In this modification, the oscillation clock frequency is changed by changing the number of inverter stages that make up the ring oscillator.

[0104] The configurations of inverters I1, I2, and I3 in Fig. 16 are similar to the configurations of inverters I1, I2, and I3 in Fig. 15. The configurations of inverters I4, I5, and I6 in Fig. 16 are similar to the configurations of inverters I1, I2, and I3 in Fig. 15. The inverters I4, I5, and I6 are cascade-connected to the inverters I1, I2, and I3.

[0105] In this modification, the non-inverting output terminal OP of the inverter I3 is connected to the non-inverting input terminal IP of the inverter I1 via the switch SW3, and the inverting output terminal ON of the inverter I3 is connected to the inverting input terminal IN of the inverter I1 via the switch SW4. The non-inverting output terminal OP of the inverter I6 is connected to the non-inverting input terminal IP of the inverter I1 via the switch SW5, and the inverting output terminal ON of the inverter I6 is connected to the inverting input terminal IN of the inverter I1 via the switch SW6.

[0106] The switches SW3 to SW6 are controlled to be turned on and off by the control circuit 32. Based on setting information, the control circuit 32 simultaneously turns on the switches SW3 and SW4 and simultaneously turns off the switches SW5 and SW6, or simultaneously turns off the switches SW3 and SW4 and simultaneously turns on the switches SW5 and SW6.

[0107] When the control circuit 32 simultaneously turns on the switches SW3 and SW4 and simultaneously turns off the switches SW5 and SW6, the OSC in Fig. 16 has a three-stage configuration with inverters I1, I2, and I3. When the control circuit 32 simultaneously turns off the switches SW3 and SW4 and simultaneously turns on the switches SW5 and SW6, the OSC in Fig. 16 has a six-stage configuration with inverters I1, I2, I3, I4, I5, and I6.

[0108] In the OSC configured in this manner, the oscillation frequency changes depending on whether the number of inverters I is three or six. The control circuit 32 simultaneously turns on the switches SW3 and SW4 and simultaneously turns off the switches SW5 and SW6 to configure a three-stage oscillator. From this state, the control circuit 32 simultaneously turns off the switches SW3 and SW4 and simultaneously turns on the switches SW5 and SW6, changing the OSC in FIG. 16 to a six-stage oscillator and decreasing the oscillation clock frequency.

[0109] 16, the oscillation clock frequency can be changed by controlling the on / off of the switches SW3 to SW6 based on the setting information by the control circuit 32. This makes it possible to change the frequency in a short time without disturbing the FB loop.

[0110] Although the example of FIG. 16 shows an example in which the number of steps is changed to two steps, the number of steps can be changed to any number of steps by increasing the number of steps.

[0111] (VIC circuit) FIG. 17 is a circuit diagram showing a specific example of the VIC circuit 11 that can be used in each of the above embodiments.

[0112] A resistor R0 and a current path of a PMOS transistor M0 are connected in series between a power supply line that generates a voltage VCC and a current supply line OSCV. The source of the transistor M0 is connected to the power supply line via the resistor R0, the drain is connected to the current supply line OSCV, and the gate is supplied with a voltage VG from the LPF 7. The transistor M0 generates a drain current according to the voltage VG and supplies the generated current to OSC12 via the current supply line OSCV.

[0113] In this embodiment, a resistor R1, a current path of a PMOS transistor M1, and a PMOS transistor SW1A are connected in series between a power supply line generating a voltage VCC and a current supply line OSCV. A plurality of systems are provided with configurations similar to those of the resistor R1 and the transistors M1 and SW1A. In general, a resistor Rm (m is 1 to N), a current path of a PMOS transistor Mm, and a PMOS transistor SWmA are connected in series between a power supply line generating a voltage VCC and a current supply line OSCV. The source of the transistor Mm is connected to the power supply line via the resistor Rm, the drain is connected to the source of the transistor SWmA, and the voltage VG is supplied to the gate. The drain of the transistor SWmA is connected to the current supply line OSCV, and a control signal from the control circuit 32 is supplied to the gate.

[0114] Between the source of the transistor SWmA and the reference potential point, the current path of the transistor SWmB and the resistor RmB are connected in series. The source of the transistor SWmB is connected to the source of the transistor SWmA, the drain is connected to the reference potential point via the resistor RmB, and a control signal is supplied to the gate of the transistor SWmB from the control circuit 32. The control circuit 32 generates the control signal based on setting information to control the on / off of the transistors SW1A-SWNA and SW1B-SWNB.

[0115] A trimming circuit 51 is configured with resistors R1-RN, R1B-RNB, and transistors M1-MN, SW1A-SWNA, and SW1B-SWNB. The transistors M1-MN generate drain currents according to the voltage VG. The drain currents generated by the transistors M1-MN are supplied to OSC12 via the transistors SW1A-SWNA and the current supply line OSCV, respectively. Therefore, by the control circuit 32 controlling the on / off of the transistors SW1A-SWNA, it is possible to change the amount of current supplied to OSC12 and change the oscillation clock frequency of OSC12.

[0116] Incidentally, when changing the current supplied to OSC12 via the current supply line OSCV, it is necessary to configure the circuit so that the voltage VG is not changed. If the voltage VG is changed, a disturbance is applied to the FB loop, and a long time is required for the frequency to stabilize. Therefore, in this embodiment, the control circuit 32 turns on and off the transistors SWmA and SWmB complementarily. That is, when one of the transistors SWmA and SWmB is on, the other is off. As a result, the drain current generated in the transistors M1 to MN flows to the current supply line OSCV side via the transistor SWmA, or flows to the reference potential point via the transistor SWmB.

[0117] In other words, even if the destination of the drain current generated in the transistors M1 to MN changes, the transistors M1 to MN always pass the drain current. The current flowing through the transistors M1 to MN does not change. Therefore, the voltage across the resistors R1 to RN and the gate-source voltage Vgs of the transistors M1 to MN do not change, so the voltage VG does not fluctuate and no disturbance is caused to the FB loop.

[0118] In this manner, in this embodiment, the amount of current supplied to the OSC 12 can be changed, and the output frequency of the OSC 12 can be changed in a short period of time, without disturbing the FB loop.

[0119] Although resistor elements are used as the resistors R1B to RNB, they can be realized without using resistors.

[0120] (Multiplication) 18 and 19 are circuit diagrams showing an example of frequency multiplication when the OSC circuit in FIG. 16 and the VIC circuit in FIG. 17 are employed.

[0121] 18 and 19 show examples in which VIC circuits 8A, OSC9A, VIC circuits 11A and OSC12A are used as the VIC circuits 8, OSC9, VIC circuits 11 and OSC12 in FIG. 1, respectively. The VIC circuit 8A includes a resistor R00 and a current path of a PMOS transistor M00, which are connected in series between a power supply line generating a voltage VCC and a current supply line OSCV1. The source of the transistor M00 is connected to the power supply line via the resistor R00, the drain is connected to OSC9A via the current supply line OSCV1, and the gate is supplied with a voltage VG from the LPF 7. The transistor M00 generates a drain current according to the voltage VG, and supplies the generated drain current to OSC9A via the current supply line OSCV1.

[0122] The VIC circuit 11A is similar to the trimming circuit 51 in FIG. 17 except that one system of resistors R1, R1B and transistors M1, SW1A, and SW1B is used.

[0123] OSC9A is composed of cascaded inverters I1 to I6. The configuration of the inverters I1 to I6 is the same as that of the inverters I1 to I6 in Fig. 16, but in OSC9A, the switches SW3 to SW6 are omitted from the configuration in Fig. 16, the non-inverting output terminal OP of the inverter I6 is connected to the non-inverting input terminal IP of the inverter I1, and the inverting output terminal ON of the inverter I6 is connected to the inverting input terminal IN of the inverter I1.

[0124] The configuration of the OSC 12A is the same as that shown in FIG.

[0125] FIG. 18 shows that the control circuit 32 sets the transistor SW1A of the VIC circuit 11A to on and the transistor SW1B to off, and also sets SW3 and SW4 of the OSC 12A to off and SW5 and SW6 to on.

[0126] Now, assume that the drain current of transistor M00 in VIC circuit 8A is 6×IA. This drain current is supplied to each of inverters I1-I6 in OSC9A via current supply line OSCV1. As a result, each of inverters I1-I6 in OSC9 is supplied with a current amount IA, averaged over a relatively long period of time.

[0127] On the other hand, suppose that the drain current of transistor M0 in VIC circuit 11A is 3×IA, and the drain current of transistor M1 is 3×IA. In this case, because transistor SW1A is on, the current supplied from VIC circuit 11A to current supply line OSCV2 is 6×IA. As a result, the inverters I1 to I6 in OSC12 are each supplied with the current IA, averaged over a relatively long period of time.

[0128] If OSC9A and OSC12A have the same characteristics, then the oscillation frequency of OSC9A and the oscillation frequency of OSC12A will be the same.

[0129] FIG. 19 shows that the control circuit 32 sets the transistor SW1A of the VIC circuit 11A to OFF and the transistor SW1B to ON, and also sets SW3 and SW4 of the OSC 12A to ON and SW5 and SW6 to OFF.

[0130] Even if the control circuit 32 changes the settings of the VIC circuit 11A and OSC12A, it does not affect the FB loop, so the voltage VG does not change, the amount of current supplied to each inverter I1 to I6 of OSC9A remains IA, and the oscillation frequency of OSC9A does not change. Meanwhile, since the transistor SW1A is turned off and the transistor SW1B is turned on, the drain current of the transistor M1 flows to the reference potential point. Therefore, the amount of current supplied from the VIC circuit 11A to OSC12A via the current supply line OSCV2 becomes 1 / 2 of the amount in FIG. 18, 3×IA.

[0131] OSC12A has a three-stage configuration because switches SW5 and SW6 are off and switches SW3 and SW4 are on. Therefore, as in the case of Fig. 18, an amount of current IA is supplied to each of the inverters I1 to I3 of OSC12A when averaged over a relatively long period of time. Therefore, the amount of delay of each of the inverters I1 to I3 of OSC12A is the same as in Fig. 18, and because the number of stages has been halved, the oscillation frequency of OSC12A is twice as high as in the state of Fig. 18.

[0132] 18 and 19, the oscillation frequency can be multiplied by one control of the control circuit 32. Although the examples of Fig. 18 and 19 show an example of doubling the frequency, it is possible to change the oscillation frequency to any desired multiplication factor X / Y by setting the initial number of steps in OSC 12 to X and the number of steps after the setting change to Y, and multiplying the current generated in VIC circuit 11A by X / Y.

[0133] 2 and 3, after FY is stabilized, data transmission is started from system X or memory controller 21. Therefore, in order to reduce power consumption until data transmission is started from system X or memory controller 21, it is better to set the initial value of FY to a relatively low frequency. In this case, however, the difference between FY and FX may become relatively large, and it is considered that the trimming process shown in FIG. 11 takes a relatively long time. In such a case, if the frequency can be multiplied by X / Y in one control as shown in FIG. 18 and FIG. 19, the frequency can be changed to the desired frequency in a relatively short time.

[0134] FIG. 20 is an explanatory diagram showing such control, which is illustrated in the same manner as FIG.

[0135] In FIG. 20, the vertical axis indicates communication speed, with the left side indicating the communication speed between the memory controller 21 and the memory I / F circuit 31 and the right side indicating the communication speed between the memory I / F circuit 31 and the semiconductor memory 37.

[0136] The initial value of FY is a frequency that is sufficiently lower than FX used in actual communication. Immediately after startup, FY is set to this initial value. When communication begins, FX is changed to FYmax. The control circuit 32 increases FY to FYmax. In this case, by configuring the VIC circuit 11 and OSC 12 in the same manner as in Figures 18 and 19, the control circuit 32 increases FY to X / Y times the initial value in one control. Next, the control circuit 32 increases FY to FYmax in accordance with the trimming process of Figure 11.

[0137] In this way, by performing the control shown in Fig. 12, even if FY is initially set to a sufficiently low frequency, it is possible to change FY to a desired frequency in a relatively short time. This reduces power consumption and enables reliable data transmission by changing the frequency in a short time.

[0138] The present invention is not limited to the above embodiment, and various modifications can be made in the implementation stage without departing from the gist of the invention. In addition, the above embodiment includes inventions at various stages, and various inventions can be extracted by appropriate combinations of the disclosed multiple constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, if the problem described in the "Problem to be Solved by the Invention" column can be solved and the effect described in the "Effect of the Invention" column can be obtained, the configuration from which the constituent elements are deleted can be extracted as the invention. [Explanation of symbols]

[0139] 1...clock generation circuit, 4...bias circuit, 5...FVC circuit, 6...amplifier, 7...LPF, 8...VIC circuit, 9...OSC, 10...clock generation circuit, 11...VIC circuit, 12...OSC, 21...memory controller, 22...clock generation circuit, 23, 33, 34, 38...I / F circuit, 31...memory I / F circuit, 32...control circuit, 35...data storage, 36...memory, 37...semiconductor memory device

Claims

1. a first oscillator for generating a signal at a first frequency based on a control signal; a control signal generating circuit that forms a feedback loop together with the first oscillator and receives an output signal of the first oscillator via a path to the feedback loop to generate the control signal; a second oscillator that generates a signal at a second frequency based on the control signal and outputs the generated signal to an output terminal outside the path to the feedback loop; a frequency measurement circuit that receives the output signal of the second oscillator and a reference signal having a reference frequency and measures the frequency of the input signal; a control logic circuit that determines setting information for making the second frequency coincide with the reference frequency based on a measurement result by the frequency measurement circuit; a control circuit for changing a frequency of a signal generated by the second oscillator based on the setting information; A semiconductor integrated circuit comprising:

2. a first current source that generates a current based on the control signal and provides the current to the first oscillator; a second current source that generates a current based on the control signal and provides the current to the second oscillator; The semiconductor integrated circuit according to claim 1 , further comprising:

3. A semiconductor integrated circuit as described in claim 1, wherein the control circuit changes the setting of the second oscillator based on the setting information.

4. A semiconductor integrated circuit as described in claim 2, wherein the control circuit changes the settings of at least one of the second current source and the second oscillator based on the setting information.

5. a second current source having a plurality of transistors each generating a current based on the control signal, the second current source supplying a current generated by a transistor based on the setting information among the currents generated by the plurality of transistors to the second oscillator; the second oscillator is configured by cascade-connecting a plurality of inverters each of which is supplied with a current from the second current source, and the number of stages of the inverters to be connected is controllable by the setting information; The control circuit changes a setting of at least one of the second current source and the second oscillator based on the setting information.

2. The semiconductor integrated circuit according to claim 1.

6. The control circuit multiplies the current generated in the second current source by n (n is an integer of 2 or more) based on the setting information, and multiplies the number of stages of the inverters constituting the second oscillator by n.

6. The semiconductor integrated circuit according to claim 5.

7. a control signal generating circuit that forms a feedback loop together with the first oscillator and that generates the control signal when an output signal of the first oscillator is supplied via a path to the feedback loop; a second oscillator that generates a signal of a second frequency based on the control signal and outputs the generated signal to an output terminal outside the path to the feedback loop; a frequency measuring circuit that receives an output signal of the second oscillator and a reference signal of a reference frequency and measures a frequency of the input signal; a control logic circuit that determines setting information for matching the second frequency with the reference frequency based on a measurement result by the frequency measuring circuit; and a control circuit that changes the frequency of the signal generated by the second oscillator based on the setting information; a semiconductor memory for receiving data transmitted by the memory interface circuit; A semiconductor memory device comprising:

8. a memory controller that transmits data in synchronization with a clock generated by a first clock generating circuit; a control signal generating circuit that forms a feedback loop together with the first oscillator and that generates the control signal when an output signal of the first oscillator is supplied via a path to the feedback loop; a second oscillator that generates a signal of a second frequency based on the control signal and outputs the generated signal to an output terminal outside the path to the feedback loop; a frequency measuring circuit that receives an output signal of the second oscillator and a reference signal of a reference frequency and measures a frequency of the input signal; a control logic circuit that determines setting information for matching the second frequency with the reference frequency based on a measurement result by the frequency measuring circuit; and a control circuit that changes the frequency of the signal generated by the second oscillator based on the setting information; a semiconductor memory for receiving data transmitted by the memory interface circuit; A memory system comprising:

9. generating a first signal at a first frequency based on a control signal obtained by a feedback loop, and the generated first signal is fed back via a path to the feedback loop to generate the control signal; generating a second signal at a second frequency based on the control signal, and outputting the generated second signal to an output terminal outside a path to the feedback loop; the second signal and a reference signal having a reference frequency are input, and the frequency of the input signal is measured; determining setting information for matching the second frequency with the reference frequency based on a measurement result; changing a frequency of the second signal based on the setting information; Frequency generation method.

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