Semiconductor Device

Abstract

To provide a semiconductor device in which required circuit functions are combined to be formed into one chip on a high voltage side and a level shift operation having a high power supply voltage variation removal ratio from low voltage to high voltage can be performed.SOLUTION: The semiconductor device includes: a constant current generating circuit portion; a first current mirror circuit portion that uses a constant current as an input current to generate a first mirror current as a mirror current; a level shift circuit portion that includes a clamp transistor in which the first mirror current flows between a drain and a source and a power supply voltage of the constant current generating circuit portion is applied to a base and a transistor which is connected in series with the clamp transistor and in which the first mirror current flows; a second current mirror circuit portion in which a transistor serves an input stage and a transistor through which a second mirror current, which is a duplicate of the first mirror current, flows serves an output stage; and an error absorption circuit portion that is connected to a terminal outputting the second mirror current of the transistor in the output stage of the second current mirror circuit portion.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device on the high-voltage side in a mild hybrid system, for example. [Background technology]

[0002] Power conversion devices such as inverters for mild hybrid systems use a gate driver on the high-voltage side. The gate driver includes a protection circuit that detects a short circuit / overcurrent in a power semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) when a short circuit occurs, and protects the power semiconductor device.

[0003] For example, Patent Document 1 discloses an IGBT, which is a power semiconductor device that drives a motor, and a gate driver that drives the IGBT, on the high-voltage side. Also, typically, a current detection circuit that detects the current flowing through the motor is provided on the high-voltage side. Furthermore, in order to make the voltage applied to the current detection circuit as a power source as low as possible and to make the voltage between the input signal and the ground voltage as low as possible, the output voltage of the IGBT has conventionally been used as the ground voltage of the current detection circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-5422 A Summary of the Invention [Problem to be solved by the invention]

[0005] Despite the circuit innovations described above, the high-voltage side requires an IGBT to drive the motor, a gate driver to drive the IGBT, and a current detection circuit to detect the current flowing through the motor, all of which are required separately, resulting in a large mounting area. In addition, the high-voltage side requires high-voltage circuits because grounds with various potentials are mixed, and these high-voltage circuits tend to require a large mounting area. Furthermore, when the IGBT switches, a high power supply rejection ratio is required, and additional circuits may be required.

[0006] The present invention has been made in view of the above. One of its objectives is to provide a semiconductor device that combines the required circuit functions on the high voltage side into a single chip, and that is capable of performing level shift operation with a high power supply voltage fluctuation rejection ratio from low voltage to high voltage by using a level shift circuit, an error absorbing circuit, etc. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A typical example of the invention disclosed in the present application can be briefly outlined as follows: A typical semiconductor device includes a constant current generating circuit, a first current mirror circuit that receives a constant current output by the constant current generating circuit as an input current and generates a first mirror current as a mirror current, a clamp transistor through which the first mirror current flows between its drain and source and to which the power supply voltage of the constant current generating circuit is applied, and a level shift circuit that includes a transistor connected in series with the clamp transistor and through which the first mirror current flows, a second current mirror circuit that uses a transistor as an input stage and a transistor as an output stage through which a second mirror current that is a copy of the first mirror current flows, and an error absorbing circuit that has a capacitance corresponding to the parasitic capacitance of the clamp transistor that is connected to a terminal that outputs the second mirror current of the transistor in the output stage of the second current mirror circuit. Effect of the Invention

[0008] According to one embodiment, it is possible to provide a semiconductor device that combines the required circuit functions on the high-voltage side into a single chip, and that is capable of level shifting operation with a high power supply voltage fluctuation rejection ratio from low voltage to high voltage by using a level shift circuit, an error absorbing circuit, etc. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram for explaining an outline of the operation of a system including an example of a semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a circuit diagram illustrating a part of an example of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram of the semiconductor device according to the first embodiment including components not shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing the semiconductor device according to the first embodiment on a transistor basis. [Diagram 5] FIG. 5 shows an example of an experimental result of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 shows an example of an experimental result of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a circuit diagram illustrating an example of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a circuit diagram illustrating an example of the semiconductor device according to the third embodiment. [Figure 9] FIG. 9 is a circuit diagram illustrating an example of a semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is related to the other as a partial or complete modification, detail, supplementary explanation, etc. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number, etc.

[0011] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be obviously not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Furthermore, although not particularly limited, the circuit elements constituting each functional block of the embodiment are formed on a semiconductor substrate such as single crystal silicon by known integrated circuit technology such as CMOS (complementary metal oxide semiconductor).

[0013] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. In all drawings for explaining the embodiment, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. Furthermore, the dimensional ratios in the drawings are exaggerated for the convenience of explanation, and may differ from the actual ratios.

[0014] (Embodiment 1) FIG. 1 is a block diagram for explaining an outline of the operation of a system including a semiconductor device according to the first embodiment. The system in FIG. 1 shows an on-vehicle mild hybrid system as an example. A motor M1 in FIG. 1 is a three-phase motor that auxiliarily moves a vehicle. FIG. 1 shows one phase as a representative of the three phases. The left side of FIG. 1 is a low-voltage region via an insulating layer IL, and 12 volts (V) is shown as an example of the low voltage. However, the battery B3 in the low-voltage region is not limited to 12V. For example, the voltage of the battery B3 may be 16V or the like.

[0015] The 12V domain region, which indicates a low-voltage region, is a circuit region controlled by a low-voltage battery, for example, a 12V battery B3. A power management integrated circuit (PMIC) 210 generates a power supply voltage required for circuits used in the 12V domain region. For example, the PMIC 210 in the 12V domain region can generate a voltage of 5V as a power supply voltage for the controller 220.

[0016] 1 is a high-voltage area, and shows an area controlled by a battery B2 of 48 volts (V) (maximum approximately 70 V) as an example of a high voltage through an insulating layer IL. The high-voltage area is a circuit area equipped with a high-voltage battery, for example, a battery B2 of 48 volts (V) (maximum approximately 70 V), to drive a motor M1 for auxiliary movement of a car.

[0017] The high voltage region includes a gate driver unit (GDU) 110, a current detection unit (CSU) 120 that detects the current flowing through the motor M1, the motor M1, and drive transistors 131 and 132 that generate a switching voltage for driving the motor M1. The GDU 110 and CSU 120 are integrated into a single chip, and include a level shift circuit section 125 (described later) and further include an error absorption circuit, resulting in a semiconductor device 100 that is capable of level shifting operation with a high power supply voltage fluctuation rejection ratio from low voltage to high voltage.

[0018] The GDU 110 generates a drive pulse for alternately switching the drive transistors 131 and 132 that drive the motor M1. The GDU 110 includes buffers 111 and 112, an inverter 113, and a level shifter 114. A pulse signal output from the controller 220 is input to the inverter 113 and the level shifter 114 via the buffer 111. The output pulse of the inverter 113 is input to the gate of the drive transistor 132. When the output pulse is high, the drive transistor 132 is turned ON, and the drain of the drive transistor 132 is electrically connected to the absolute ground. When the output pulse is low, the drive transistor 132 is turned OFF, and the drain of the drive transistor 132 becomes the voltage of the source of the drive transistor 131.

[0019] The GDU 110 applies a voltage lower than the high voltage of the battery B2 as the power supply voltage VL. For example, the power supply voltage VL is 5V, but the value of the power supply voltage VL is not limited to 5V. The power supply voltage of a general-purpose IC can be adopted as the power supply voltage VL. The power supply voltage VL can also be set to a voltage value between 3V and 6V.

[0020] The level shifter 114 is used to increase the voltage applied to the gate of the drive transistor 131 in order to switch the drive transistor 131. The increased voltage value can be determined by the output voltage of the battery B2 and the electrical characteristics of the drive transistor 131, etc. The output signal of the level shifter 114 is input to the buffer 112, and the output pulse of the buffer 112 is input to the gate of the drive transistor 132. Since the output pulse of the buffer 112 and the output pulse of the inverter 113 are in an inverted relationship, the ON / OFF of the drive transistor 131 and the drive transistor 132 are also in an inverted relationship on the time axis. That is, when the drive transistor 131 is OFF, the drive transistor 132 is ON as described above, and no current flows through the motor M1. Also, when the drive transistor 131 is ON, the drive transistor 132 is OFF, and a current flows through the motor M1 via the battery B2. By switching the drive transistor 131 and the drive transistor 132 in this way, the motor M1 rotates, and a vehicle or the like on which the motor M1 is mounted can move.

[0021] The CSU 120 has a function of detecting the current flowing through the motor M1 as a voltage and outputting the detected voltage to the controller 220. The current flowing through the motor M1 flows through a resistor R1, so a detection voltage is generated across the resistor R1. The detection voltage is converted from an analog signal to a digital signal by an AD converter (not shown) via an amplifier 121, and the converted digital signal is input to the controller 220, which monitors the driving state of the motor M1. The controller 220 outputs the above-mentioned pulse signal to the buffer 111 based on the driving state of the motor M1.

[0022] The CSU 120 includes a BGR (Band Gap Reference) circuit unit 124, an IREF circuit unit 123, an LDO (Low Drop Out) circuit unit 122, and a level shift circuit unit 125 in order to supply a stable power supply to the amplifier 121. The amplifier 121 detects the voltage generated in the resistor R1, and therefore may process a voltage ranging from the bootstrap voltage VBST to the floating ground FGND. Therefore, it is preferable that the bootstrap voltage VBST and the floating ground FGND are also input to the power supply voltage of the amplifier 121. It is also preferable to provide an LDO circuit unit 122 in order to reduce the voltage drop from the bootstrap voltage VBST. The LDO circuit unit 122 of this embodiment will be described later. Furthermore, it is preferable to connect an IREF circuit unit 123 that generates a constant current for generating a reference voltage for the LDO circuit unit 122 to the LDO circuit unit 122. The IREF circuit unit 123 of this embodiment will also be described later. It is also preferable to provide a BGR circuit unit 124 that generates a constant voltage for generating a constant current generated in the IREF circuit unit 123. Since the BGR circuit is a known technique, detailed description thereof will be omitted. In addition, it is preferable to provide a level shift circuit unit 125 that shifts the difference in power supply voltage applied to the IREF circuit unit 123 and the LDO circuit unit 122.

[0023] Since the BGR circuit section 124, the IREF circuit section 123, and the LDO circuit section 122 are electrically connected to the amplifier 121, it is considered that unnecessary circuit parts are not required by supplying the bootstrap voltage VBST as a power supply voltage. However, as described above, since the bootstrap voltage VBST is a high voltage, the BGR circuit section 124 and the IREF circuit section 123 to which the bootstrap voltage VBST is applied become high-voltage circuits, and therefore occupy a large area on the semiconductor chip. Therefore, even if the current detection unit (CSU) 120 and the gate driver unit (GDU) 110 are integrated into one chip, it will have the opposite effect on reducing the overall area.

[0024] Therefore, in this embodiment, the area of ​​the single chip in which the CSU 120 and the GDU 110 are integrated into a single chip is reduced by applying a low voltage to the power supply voltage of the BGR circuit unit 124 and the IREF circuit unit 123 by the level shift circuit unit 125. In Fig. 1, an example of a low voltage is the power supply voltage VL of the buffer 111 and the inverter 113. Also, the power supply voltage VL may be a voltage of 3 to 6 V, but is not limited to this voltage.

[0025] Furthermore, the LDO circuit section 122 is provided with the error absorbing circuit section described above, but this is not shown in FIG. 1, and the error absorbing circuit section will be described in detail from FIG. 3 onwards.

[0026] FIG. 2 is a circuit diagram showing a detailed circuit configuration in which the LDO circuit unit 122 is not provided with an error absorbing circuit unit in the semiconductor device according to this embodiment. FIG. 2 omits the low voltage region through the insulating layer IL in FIG. 1. In FIG. 2, the IREF circuit unit 123 and the level shift circuit unit 125 including transistors Tr3, Tr4, and Tr5 are present between the BGR circuit unit 124 and the LDO circuit unit 122. Since the GDU 110 has been described in detail in FIG. 1, a duplicated description will be omitted. Also, the motor M1 is simplified and shown using an inductance L1 for one phase. Also, the circuit diagram is shown assuming that the power supply voltage applied as a low voltage to the power supplies of the BGR circuit unit 124 and the REF circuit unit 123 is 5V.

[0027] The IREF circuit unit 123 outputs a constant current Is using the constant voltage output from the BGR circuit unit 124. The principle of generating the constant current of the IREF circuit unit 123 is a known technology, so detailed description will be omitted. The current Is flows through a first current mirror circuit unit 125_1 composed of a transistor Tr1 whose gate and drain are shorted and a transistor TR2. Therefore, the current Is also flows through the transistor TR2 as a mirror current. That is, the current Is also flows through the transistors Tr3, Tr4, and Tr5. Note that the withstand voltage of the transistor Tr3>>the withstand voltage of the transistor Tr4>the withstand voltage of the transistor Tr5. As an example, the withstand voltage of the transistor Tr3 is preferably equal to or higher than the voltage of the battery B2, and the withstand voltage of the transistor Tr5 is preferably equal to or higher than the voltage of the battery B1. If the transistor Tr3 has a high withstand voltage and the gate voltage of the transistor Tr3 is low, the voltage of the source of the transistor Tr3 is (low voltage (5V)-gate threshold voltage), so that the transistor Tr3 functions as a clamp transistor. Therefore, it is possible to design the BGR circuit unit 124 and the REF circuit unit 123 in a low-voltage region. Note that by forming a cascode current mirror circuit using transistors Tr4 and Tr5, it is possible to improve the accuracy of the copy current flowing through the LDO circuit unit 122. As an example, the withstand voltage of transistor Tr3 is 100V, and the withstand voltage of transistor Tr5 is 100V, but the withstand voltages of transistors Tr3 and Tr5 are not limited to these voltages.

[0028] However, the parasitic capacitance CD3 on the drain side of the transistor Tr3, which has a high breakdown voltage, also becomes large, so that the current Isub flowing through the parasitic capacitance CD3 also becomes large. When the current Isub becomes large, the current Isub flows through the current Is, so that the fluctuation of the output voltage of the level-shifted LDO circuit unit 122 becomes large, and the output of the amplifier 121 becomes unstable, and the controller 220 cannot accurately detect the driving current of the motor M1. Therefore, in this embodiment, a dummy transistor that copies the transistor Tr3 is provided in the LDO circuit unit 122, so that the current Isub that flows through the current Is flows through the parasitic capacitance of the dummy transistor. The dummy transistor will be described in detail in the description of FIG. 3 below. The dummy transistor is an example of the error absorbing circuit unit described above. For example, a capacitor whose capacitance value is the parasitic capacitance of the dummy transistor can also be an example of the error absorbing circuit unit. A parasitic capacitance CS3 is also formed in the transistor Tr3, but since the source voltage of the transistor Tr3 is a low voltage, the magnitude of the current flowing through the parasitic capacitance CS3, which has a capacitance value close to that of the parasitic capacitance CD3, is smaller than the current flowing through the parasitic capacitance CD3. Therefore, the following description will focus on the current Isub.

[0029] The second current mirror circuit portion 125_1 has transistors Tr4 and Tr5 as an input stage, and has two output stages for the input stage. The first output stage of the second current mirror circuit portion 125_1 includes transistors Tr6 and Tr7, and the second output stage includes transistors Tr8 and Tr9, and (current Is+current Isub) flows as a mirror current in each output stage.

[0030] Furthermore, the current Isub, which is a transformer current causing an error, is applied to the mirror current Is of the first current mirror circuit section 125_1, and a fluctuating current flows through the LDO circuit section 122, so that the power supply voltage applied to the amplifier 121 fluctuates like Vsupply1. When the power supply voltage applied to the amplifier 121 fluctuates, the output of the amplifier 121 also fluctuates, so an error absorbing circuit section that absorbs the current Isub is required.

[0031] FIG. 3 is a circuit diagram in which dummy transistors Tr10 and Tr11, which are copies of the transistor Tr3, are provided as an error absorbing circuit in the LDO circuit 122. The current Is+Isub flowing through the transistors Tr4 and Tr5 flows through the transistors Tr6 and Tr7 which constitute the output stage of the second current mirror circuit. Similarly, the current Is+Isub flowing through the transistors Tr4 and Tr5 flows through the transistors Tr8 and Tr9 which constitute the output stage of the second current mirror circuit. The power supply voltage of the operational amplifier OP1 is supplied by the current flowing through the transistors Tr8 and Tr9. Therefore, as described above, when the current flowing through the transistors Tr8 and Tr9 fluctuates, the power supply voltage of the operational amplifier OP1 also fluctuates, and the output voltage of the operational amplifier OP1 is affected (for example, it fluctuates like Vsupply1 in FIG. 2). In addition, the reference voltage of the operational amplifier OP1 is formed by the current flowing through the transistors Tr6 and Tr7. Therefore, when the current flowing through the transistors Tr6 and Tr7 fluctuates, the reference voltage fluctuates, affecting the output voltage of the operational amplifier OP1 (for example, fluctuating like Vsupply1 in FIG. 2).

[0032] Therefore, a dummy transistor Tr10 is provided as an error absorbing circuit section for absorbing the current Isub. Parasitic capacitances CD10 and CS10 are formed in the dummy transistor Tr10. Therefore, the drain of the dummy transistor Tr10 is electrically connected to the source of the transistor Tr9 and the drain of the transistor Tr8, and the gate and source of the dummy transistor Tr10 are electrically connected to the drain of the transistor Tr9. Then, most of the current Isub is absorbed by the parasitic capacitance CS10 as a current Isub_replica.

[0033] Similarly, a dummy transistor Tr11 is provided as an error absorbing circuit section for absorbing the current Isub. The dummy transistor Tr11 has parasitic capacitances CD11 and CS11. The drain of the dummy transistor Tr11 is electrically connected to the source of the transistor Tr7 and the drain of the transistor Tr6, and the gate and source of the dummy transistor Tr11 are electrically connected to the drain of the transistor Tr7. Then, most of the current Isub is absorbed by the parasitic capacitance CS11 as a current Isub_replica.

[0034] Due to the parasitic capacitances CS10 and CS11, the output voltage of the LDO circuit section 122 becomes a voltage Vsupply2 that fluctuates less than the voltage Vsupply1.

[0035] Fig. 4 is a circuit diagram showing the inside of the operational amplifier OP1 of Fig. 3. The operational amplifier OP1 includes transistors Tr17, Tr18, Tr19, and Tr20 constituting a differential input stage, transistor Tr15 constituting a gain stage, transistor Tr16 constituting an output stage, transistors Tr12 and Tr13 supplying a constant current, and a dummy transistor Tr14. The current Isub is absorbed by parasitic capacitances CD14 and CS14 formed in the dummy transistor Tr14. Most of the current Isub is absorbed by the parasitic capacitance CS14 as a current Isub_replica.

[0036] According to the first embodiment, it is possible to provide a semiconductor device that combines the required circuit functions on the high voltage side into a single chip, and that is capable of level shifting operation with a high power supply voltage fluctuation rejection ratio from low voltage to high voltage by using a level shift circuit and an error absorbing circuit.

[0037] (Experimental Example 1) 5 shows the results of measuring the currents of each part in the semiconductor device constructed according to this embodiment when a dummy transistor is not formed and when a dummy transistor is formed. In FIG. 5, a pulse waveform in which the floating ground FGND is switched between 0V and the bootstrap voltage is shown. At the rising edge of the pulse waveform of the floating ground FGND, a spike-like current is generated in the current Is on both positive and negative sides due to the floating inductance component of the circuit. Also, at the falling edge of the pulse waveform of the floating ground FGND, a spike-like current is generated in the current Is on both positive and negative sides due to the floating inductance component of the circuit.

[0038] The current (Is+Isub: solid line) is a waveform in which, in addition to the above-mentioned Is, a pulse-shaped current Isub for charging and discharging the parasitic capacitance CD3 is added. The current Isub occurs for about 1.750 μs (values ​​of t1 and t2), and has a current value of about 8.4 μA. It is also confirmed that a current Isub_replica having an equivalent current value to the current Isub flows in the parasitic capacitance of the dummy transistor for a period equivalent to that of the current Isub. As a result of the current Isub_replica flowing, as shown by the current Iout (dashed line), the fluctuation period is shortened to about 0.005 μs, and the fluctuating current value is reduced to about 3.5 μA. The current Iout is a current flowing through the resistor R2 to generate the reference voltage in FIG. 3.

[0039] (Experimental Example 2) FIG. 6 shows the results of measuring the current of each part as a voltage when the dummy transistor is not formed and when the dummy transistor is formed in the semiconductor device configured according to this embodiment. As in FIG. 5, the upper part of FIG. 6 shows a pulse waveform in which the floating ground FGND is switched between 0V and the bootstrap voltage. The LDO output fluctuation indicates the fluctuation of the output voltage of the LDO circuit part 122. The LDO output fluctuation when the dummy transistor is not formed shows a peak value of about 152 mV. However, the LDO output fluctuation when the dummy transistor is formed shows a peak value of about 17 mV. That is, when the full scale of the output voltage of the amplifier 121 is 1 V and the PSRR is −20 dB, the output fluctuation when the dummy transistor is not formed is about 1.5%, and the output fluctuation when the dummy transistor is formed is about 0.17%. Since the output fluctuation is less than 0.3% in the specifications of the amplifier 121, it is possible to satisfy the output fluctuation specification of the amplifier 121 by forming the dummy transistor.

[0040] As described above, according to the first embodiment, required circuit functions are combined into one chip on the high voltage side, and a level shift circuit section and an error absorbing circuit section are provided, making it possible to provide a semiconductor device capable of level shift operation with a high power supply rejection ratio from low voltage to high voltage.

[0041] (Embodiment 2) In the first embodiment, the dummy transistor is electrically connected in parallel with the transistor forming the output stage of the second current mirror circuit. That is, the drain and source of the dummy transistor are connected in parallel with the source and drain of the transistor forming the output stage of the second current mirror circuit. However, in the second embodiment, the three terminals of the drain, gate, and source of the dummy transistor are connected to each other, and are connected to the output terminal (drain or source) of the transistor forming the output stage of the second current mirror circuit, as shown in FIG. 7. By connecting the three terminals of the drain, gate, and source of the dummy transistor, the parasitic capacitance of the drain side of the dummy transistor and the parasitic capacitance of the source side of the dummy transistor are added together, so that the area of ​​the dummy transistor can be reduced. For example, even if the formation area of ​​the dummy transistor in the second embodiment is half that of the dummy transistor in the first embodiment, the same output fluctuation as in the first embodiment can be realized.

[0042] 7 shows a configuration in which the drain, gate, and source terminals of a dummy transistor Tr10, which is an error absorbing circuit, are connected to each other, and the drain is connected to the output terminal of a transistor Tr9, which forms the output stage of a second current mirror circuit. Also, the drain, gate, and source terminals of a dummy transistor Tr11 are connected to each other, and the drain is connected to the output terminal of a transistor Tr9, which forms the output stage of a second current mirror circuit. A capacitor C9 has a capacitance obtained by adding together a parasitic capacitance CS11 on the source side and a parasitic capacitance CD11 on the drain side of the dummy transistor Tr11. Also, a capacitor C10 has a capacitance obtained by adding together a parasitic capacitance CS10 on the source side and a parasitic capacitance CD10 on the drain side of the dummy transistor Tr10.

[0043] According to the configuration of the second embodiment, the parasitic capacitance of the drain side of the dummy transistor that constitutes the error absorbing circuit section is added to the parasitic capacitance of the source side of the dummy transistor. Therefore, it is possible to reduce the area of ​​the dummy transistor. For example, even if the formation area of ​​the dummy transistor of the second embodiment is half that of the dummy transistor of the first embodiment, it is possible to realize the same output fluctuation as that of the first embodiment.

[0044] (Embodiment 3) The third embodiment is an embodiment in which the LDO circuit unit 122 of the first and second embodiments is applied to a current-controlled pre-driver circuit unit 126. Since the fluctuation range of the output current of the output stage of the current mirror circuit of the pre-driver circuit unit 126 is sufficiently small, the fluctuation of the current flowing into the gate of the drive transistor Tr16 is small, and the slew rate of the drive transistor Tr16 can be improved.

[0045] (Embodiment 4) The fourth embodiment is shown in Fig. 9. The fourth embodiment shows a configuration in which the first current mirror circuit section 125_1 includes sub-first current mirror circuit sections 125_1_1 and 125_1_2, and the second current mirror circuit section 125_2 includes sub-second current mirror circuit sections 125_2_1 and 125_2_2. Note that in Fig. 9, the sub-first current mirror circuit section 125_1_1 shows only the transistor Tr16 of the output stage, and the sub-first current mirror circuit section 125_1_2 shows only the transistor Tr17 of the output stage.

[0046] The level shift circuit section 125-1 also includes a transistor Tr18 which is a clamp transistor electrically connected in series to the transistor Tr16 in the output stage of the sub-first current mirror circuit section 125_1_1. Similarly, the level shift circuit section 125-2 includes a transistor Tr19 which is a clamp transistor electrically connected in series to the transistor Tr17 in the output stage of the sub-first current mirror circuit section 125_1_2.

[0047] Furthermore, the level shift circuit section 125-1 includes transistors Tr20 and Tr22 electrically connected in series to transistor Tr18, which is a clamp transistor, and through which a sub-first mirror current, which is a mirror current of the sub-first current mirror circuit section 125_1_1, flows. The transistors Tr20 and Tr22 form an input stage of the sub-second current mirror circuit section 125_2_1. The level shift circuit section 125-2 includes transistors Tr21 and Tr23 electrically connected in series to transistor Tr19, which is a clamp transistor, and through which a sub-first mirror current, which is a mirror current of the sub-first current mirror circuit section 125_1_2, flows. The transistors Tr21 and Tr23 form an input stage of the sub-second current mirror circuit section 125_2_2.

[0048] The output stage of the sub second current mirror circuit section 125_2_1 is formed by transistors Tr24 and Tr26 connected in series. A transistor Tr28, which is a dummy transistor serving as an error absorbing circuit section, is formed at the output end (drain in FIG. 9) of the transistor Tr26, which supplies the sub second current, which is the mirror current of the sub second current mirror circuit section 125_2_1, to the next stage. The transistor Tr28 is a dummy transistor having the same structure as the transistor Tr18, which is a clamp transistor.

[0049] An output stage of the sub second current mirror circuit section 125_2_2 is formed by transistors Tr25 and Tr27 connected in series. A transistor Tr29, which is a dummy transistor serving as an error absorbing circuit section, is formed at the output end (drain in FIG. 9) of the transistor Tr27, which supplies a sub second current, which is a mirror current of the sub second current mirror circuit section 125_2_2, to the next stage. The transistor Tr29 is a dummy transistor having the same structure as the transistor Tr19, which is a clamp transistor.

[0050] According to the fourth embodiment, the level shift circuit section and the error absorbing circuit section of the present disclosure can be applied to a two-stage cascode current mirror circuit.

[0051] The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention. For example, the above embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those having all of the configurations described. In addition, it is possible to add, delete, or replace part of the configuration of the above embodiments with other configurations. [Explanation of symbols]

[0052] 100 Semiconductor device 123 Constant current generating circuit section 125_1 First current mirror circuit Tr3, Tr18, Tr19 Clamp transistors 125 Level shift circuit section 125_2 Second current mirror circuit Tr10, Tr11, Tr14, Tr28, Tr29 Dummy transistors (error absorption circuit section) 125_1_1, 125_1_2 Sub 1st current mirror circuit section 125_2_1, 125_2_2 Sub 2nd current mirror circuit section

Claims

1. A constant current generating circuit unit; a first current mirror circuit section that uses the constant current output from the constant current generating circuit section as an input current and generates a first mirror current as a mirror current; a clamp transistor through which the first mirror current flows between its drain and source and to which a power supply voltage of the constant current generating circuit is applied, and a level shift circuit section including a transistor connected in series to the clamp transistor and through which the first mirror current flows; a second current mirror circuit section having the transistor as an input stage and a transistor through which a second mirror current obtained by replicating the first mirror current flows as an output stage; an error absorbing circuit section having a capacitance corresponding to a parasitic capacitance of the clamp transistor connected to a terminal that outputs the second mirror current of the output stage transistor of the second current mirror circuit section.

2. 2. The semiconductor device according to claim 1, wherein the input stage transistors and the output stage transistors of the second current mirror circuit section are configured by electrically connecting in series a plurality of transistors having different withstand voltages, and the input stage transistors and the output stage transistors are configured by connecting a plurality of transistors having the same electrical characteristics opposite each other.

3. 2. The semiconductor device according to claim 1, wherein the error absorbing circuit section is a parasitic capacitance of a dummy transistor that is a copy of the clamp transistor, and the dummy transistor having a gate-source short-circuited is formed as the error absorbing circuit section.

4. 4. The semiconductor device according to claim 3, wherein the dummy transistor is electrically connected in parallel to a terminal for inputting the second mirror current of the transistor in the output stage and a terminal for outputting the second mirror current.

5. The semiconductor device according to claim 3 , wherein the dummy transistor has a drain-source short-circuited.

6. 2. The semiconductor device according to claim 1, wherein an output stage of the second current mirror circuit includes a plurality of transistors, the transistors of the plurality of output stages being electrically connected to each other in parallel, and the error absorbing circuit is connected to a terminal that outputs the second mirror current of each of the transistors of the output stages.

7. the first current mirror circuit unit includes a plurality of sub first current mirror circuit units, the level shift circuit section includes a plurality of clamp transistors electrically connected in series to the transistors constituting the output stages of the plurality of sub-first current mirror circuit sections, and a plurality of transistors electrically connected in series to the clamp transistors, through which a sub-first mirror current, which is a mirror current of the sub-first current mirror circuit section, flows; the second current mirror circuit unit includes a plurality of sub second current mirror circuit units having a transistor as an input stage through which a sub first mirror current, which is a mirror current of the sub first current mirror circuit unit, flows; 2. The semiconductor device according to claim 1, wherein the error absorbing circuit section is provided at each output end of a transistor that outputs a sub-second mirror current that is a mirror current of the sub-second current mirror circuit section.

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