Digital Controller for High-Performance Multiphase VRM with Current Balancing and Near-Ideal Transient Response

Abstract

A mixed-signal controller for controlling a multi-phase average current-mode voltage regulator having an output connected to a load, comprising: a digital voltage sampling ADC for converting an output voltage signal from an analog to a digital representation; a digital current sampling ADC for converting an inductor current from an analog to a digital representation; a digital compensator for generating a current reference signal based on a digital voltage error signal and generating a duty cycle command signal based on the digital current error signal; a multi-phase digital pulse-width modulator (DPWM) for generating a pulse-width modulated signal (per phase) to thereby control the current and output voltage per phase supplied to the load; an analog front-end, wherein a single-ended signal is used for steady-state control via ADC measurement and the single-ended output voltage is used for transient detection and output voltage extreme value detection during transients; a transient suppression unit (TSU) for generating gate signals supplied to gates of transistors in the converter during transient events; a phase count optimizer (PCO) unit for generating enable / disable control signals for each phase PWM output tri-state buffer; and an AVP unit for generating a voltage reference signal for a voltage loop compensator.

Description

[Technical field]

[0001] The present invention relates to the field of voltage regulator modules (VRMs). More particularly, the present invention relates to a digital controller for high performance multi-phase VRMs with current balancing and near-ideal transient response. [Background technology]

[0002] With the popularity of cloud computing, datacenter power consumption has increased significantly [1]. Datacenters typically use a large number of CPUs and double data rate (DDR) memory modules, each of which requires a highly regulated DC voltage under extremely strict requirements and specifications. Formed by the recent Open Computing Project (OCP) standardization [2], the power processing chain for datacenter applications has a 48Vdc unregulated bus as the main source, which is downstreamed to the load in a two-stage converter architecture. The first stage is a 48V to 12V converter that provides a 12V bus. The second stage is a high-performance 12V to 1.xV voltage regulator module (VRM) back-end converter, which is typically implemented using a multi-phase buck architecture. This is done to satisfy the load in terms of power quality requirements, especially to ensure a tightly regulated supply under bursty, rapid and continuous load transient conditions. Multiphase interleaved buck VRM (MPVRM) enables low-voltage high-current operation [3]-[5] characterized by high power density, high conversion efficiency [6]-

[11] and fast dynamic response

[12] -

[16] . MPVRM can eventually be used to relax passive component requirements or to further increase computing power. Traditional setups of multiphase interleaved buck converters use multiple phases in parallel to deliver power to the load. Typically, a single controller IC is employed to monitor the operation of all power stages. This allows for better synchronization of signals, data collection with higher signal-to-noise ratio, and PCB area savings.

[0003] Single-phase controllers are mostly realized using analog implementations due to the cost vs. performance trade-off. In multi-phase applications, especially VRM applications, digital control has taken the lead. This is mainly due to the fact that modern controllers require not only performance characteristics, but also flexibility, plug-and-play and programmability capabilities, some housekeeping, communication and telemetry functions. However, the additional penalty of implementing a digital controller core is a non-negligible factor due to the extreme hardware requirements to achieve performance goals such as high base clock frequency, overall silicon area, power consumption acquisition and control resolution. These are the result of the control architecture, the implementation of the internal control blocks, peripheral units, etc.

[0004] In the majority of MPVRM voltage modes, control schemes with linear compensation are applied to facilitate regulation

[17] -

[22] . Paralleling and voltage positioning are achieved by droop control methods

[23] -

[29] , and per-phase current information is usually used either for sharing purposes or for data collection

[30] -

[32] . Acceleration of control bandwidth is facilitated by switching or transitioning between linear controllers, i.e., by adjusting the compensator coefficients according to the load conditions

[33] -

[39] . Although versions of per-phase current information are available for controllers, current-programmed mode control techniques have been excluded from commercial use so far.

[0005] Paralleling multiple power stages operating in-phase or out-of-phase introduces several challenges, ranging from current and thermal distribution as a result of different physical layouts to generating different voltages even with the same control. Since the phases are distributed over a significant portion of the PCB, fine-grained traces and interfaces are essential to carry the power, as well as the control signals from the individual phases to the centralized controller and vice versa. In such applications, regulation of the currents per phase reduces the system complexity considerably. However, capturing the instantaneous inductor current and manipulating the phase operation accordingly may be practically prohibitive, both from the sensing and control standpoints. Here, the advantages of the Average Current-Mode (ACM) control approach are becoming more evident

[40] -

[43] , especially if it can be realized without additional hardware penalty. In the ACM approach, some of the building blocks are identical for both the voltage and current loops, and therefore, by using the same hardware, a significant reduction in resources can be achieved.

[0006] It is therefore an object of the present invention to provide a new all-digital controller for high performance multi-phase buck VRM that includes a current balancing module that enables even load distribution between phases.

[0007] Another object of the present invention is to present in detail a novel controller implementation that enables time-optimal transient recovery in a multiphase regulator.

[0008] Other objects and advantages of the present invention will become apparent as the description proceeds. Summary of the Invention

[0009] 1. A mixed signal controller for controlling a multiphase average current mode voltage regulator having an output connected to a load, comprising: a. a delay line (DL) based digital voltage sampling analog-to-digital converter (ADC) configured to obtain samples of an output voltage signal and convert the output voltage signal from analog to digital; b. a delay line (DL) based digital current sampling ADC configured to obtain samples of inductor current per phase and convert the inductor current from analog to digital; c. A digital compensator for voltage regulation, comprising: a digital voltage error signal v generated by a voltage loop; e a digital compensator configured to receive as an input the digital voltage error signal and generate a current reference signal based on the digital voltage error signal; d. A digital compensator for current regulation having as input a current error signal i e a digital compensator receiving the digital current error signal and generating a duty ratio command signal based on the digital current error signal; e. A DL-based multi-phase digital pulse width modulator (DPWM) that receives as input the duty cycle command signals for each phase and generates pulse width modulated signals (per phase) that are supplied to gates of transistors of the converter, thereby controlling the current and output voltage per phase supplied to the load; f. an analog front end that receives differential measurements of output voltage and inductor current per phase, where each signal is converted to single-ended form, whereby the single-ended signal is used for steady state control via ADC measurement, and the single-ended output voltage is used for transient detection and output voltage extreme detection during transients; g. a transient suppression unit (TSU) receiving as an input a digital indication signal from said analog front end and generating gating signals provided to gates of transistors of said converter during a transient event, thereby controlling the current and voltage provided to said load during said transient event; h. a Phase Counting Optimizer (PCO) unit that receives the digital current reference signal as an input and generates enable / disable control signals for each phase PWM output tri-state buffer; i. an active voltage positioning (AVP) unit that receives as an input the digital current reference signal and generates a voltage reference signal for the voltage loop compensator; A controller comprising:

[0010] The controller may be implemented using standard CMOS components.

[0011] The digital voltage-sampling ADC and the digital current-sampling ADC can be based on standard cell technology without modification.

[0012] The digital current reference compensator and each phase digital duty ratio compensator may be a first-order compensator.

[0013] Whenever the voltage loop is broken, each loop and each phase can be regulated with a single state variable.

[0014] The controller may have an outer voltage loop and an inner current loop for each phase having a different bandwidth.

[0015] The multi-phase DPWM is a. A single DL ring oscillator that generates the clock signals for the PWM logic per phase; b. a duty cycle logic block that receives as inputs a digital duty cycle command and the DL Ring output and generates a pulse width modulated signal that controls the gate of the transistor; It can be provided with:

[0016] The control signals for the gates are synchronized for interleaved operation and out of sync for non-interleaved operation.

[0017] The TSU is a. a state machine based logic block that generates gating signals provided to gates of phase transistors of the converter during a transient event; b. Fault protection logic for fast TSU operation termination and return to DPWM operation; c. a handoff estimation block that receives a pre-transient current reference signal and a duty cycle command and generates estimated post-transient values ​​for said current reference signal and duty cycle command; It can be provided with:

[0018] The PCO is a. a low pass filter LPF that receives the current reference signal and generates a moving average of the current reference signal based on the current reference signal; b. a state machine based logic block that receives the average current reference signal and the transient notification signal and generates a controlled enable / disable signal for each of the phases; It can be provided with:

[0019] The AVP is a. a reference calculation block that receives the average current reference signal generated by the PCO and generates the digital reference voltage signal for the voltage compensator; b. a transient compensation block that receives a step estimate of current from said TSU following a transient event and generates a compensation signal for said calculation block; It can be provided with:

[0020] The active number of phases can be optimized by PCO by the following steps: a. When power is turned on, all phases are turned on; b. monitoring the average current reference signal at the voltage compensator output to determine the optimal number of phases; c. taking over the current reference signal of the particular phase to be shut down / turned on and issuing an associated enable signal to the output buffer; d. determining the optimal number of phases by monitoring the average current reference signal at the voltage compensator output; e. Setting all phases to active mode during the transient event and returning to step b above.

[0021] 1. A method for voltage regulation in a mixed signal hybrid ACM controller architecture, comprising: a. during steady state operation of the ACM controller, simultaneously measuring the output voltage and average inductor current per phase once for each active phase during a switching cycle and in synchronization with the interleaved operation of a multi-phase digital pulse width modulator (DPWM) that controls the current and output voltage per phase delivered to a load; b. Using the measured output voltage, a voltage error v e generating [n]; c. calculating a current reference signal using a voltage compensator; d. Using the calculated current reference signal and the inductor current measurement, a current error signal i e generating a per-phase current compensator for generating a particular phase duty cycle command d[n]; e. receiving a duty cycle command d[n] by multi-phase DPWM and generating a steady gating signal; f. sensing a transient start time and a transient direction (load or unload) by a transient detection sensor if a transient event occurs during steady state operation; g. upon detecting a transient event, using the PCO to activate all available phases and allowing the TSU to control the transient gate signal to start counting T0; h. depending on the transient direction, the TSU turning on all phases using low side transistors for unload transients and using high side transistors for load transients; i. continuing step g. above until an output voltage extreme is measured by an extreme value detection sensor, and the TSU stopping the T0 counter, and resuming the steady state control if an output voltage extreme is not detected; j. generating remaining gate signal timing by the TSU based on the counter value of T0 and an average duty cycle value D, and a correction signal of a handoff procedure is calculated based on T0 and fed back to the steady state controller; k. completing a gating sequence by the TSU according to the values ​​generated in step i.; l. When the gate sequence of the TSU is completed, the control of the gate signal is transferred to the ACM controller, and phase synchronization by the DPWM is resumed, and steady-state operation is started according to step a. above. [Brief description of the drawings]

[0022] The above and other features and advantages of the present invention will be better understood from the following illustrative and non-limiting detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings, in which: [Figure 1] Showing a simplified schematic diagram of a multi-phase step-down system; [Diagram 2] Shows a schematic diagram of the sensing scheme for multi-phase controller operation; [Figure 3A]Dual loop current control ACM step-down VRM; [Figure 3B] The equivalent diagram of dual-loop ACM step-down VRM is shown; [Figure 4] Showing active voltage positioning VID curves required for high end loads; [Diagram 5] A conceptual block diagram of a multi-phase step-down ACM control system is shown; [Figure 6] The multi-phase ACM controller timing sequence diagram of the key block during steady operation is shown; [Figure 7] Presents the load transient recovery of a four-phase interleaved buck converter controlled by a linear compensation scheme; [Figure 8] Showing large signal compensation waveforms during loading and unloading transient events; [Figure 9A] Shown is a large signal compensated sensor with transient detection sensor; [Figure 9B] Shown is a large signal compensated sensor with an output voltage extreme value detector (minimum); [Figure 10] Demonstrates phase synchronization during transient rise; [Figure 11] Showing state space trajectories of multiphase step-down during loading and unloading transients; [Figure 12] Showing system governor block diagram; [Figure 13] Show programmable piecewise linear AVP function; [Figure 14] Shows an example of AVP function for minimum deviation control recovery; [Figure 15] Showing PCO operation in monitored phase shedding procedure during steady state; [Figure 16] Shows a single DL multi-phase DPWM module with built-in soft start unit; [Figure 17] Demonstrating small signal compensator operation during a 16A→88A loading transient event; [Figure 18] Demonstrating large signal compensator operation during a 16A→88A loading transient event; [Figure 19] Demonstrating small signal compensator operation during an 88A → 24A unload transient event; [Figure 20] Demonstrating the operation of the large signal compensator during an 88A → 24A unload transient event; [Figure 21] The phase shedding procedure is shown under steady operation of 20A load, the controller goes from 4 phase to 2 phase, and from 2 phase to single phase; [Figure 22] Demonstrating full hybrid controller operation including phase shedding and AVP functionality during a 5A⇔85A load step; [Diagram 23] Multi-phase VRM thermal images are shown under 90A steady-state load conditions: (a) voltage mode with unbalanced phase currents; (b) ACM operation with inherent current sharing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present invention proposes a digital or mixed signal (having digital and analog parts) current programmed control for multi-phase buck VRM for high performance loads that regulates the output voltage with high precision, maintains current sharing of all phases for the entire operating range, and realizes optimal transient recovery for load transients. These are made possible by a hybrid controller architecture that facilitates per-phase average current control (ACM) for steady-state operation and a state-space based transient oriented controller that performs time-optimal or minimum deviation recovery for loading and unloading transients. Active voltage positioning (AVP) as well as phase shedding algorithms (i.e., reducing the number of active switches to reduce the number of active phases when the load current decreases below a certain limit, thereby reducing switching losses) are incorporated to cover all the features required to supply modern high-end loads. In addition to the high-end analog interface developed for accurate acquisition of control signals, the digital core IP blocks (compensation, sharing, droop, etc.) and peripheral units (HRDPWM, ADC) are realized by combinatorial asynchronous logic with all standard cells using HDL for direct synthesis for IC implementation. The resulting compact controller (implemented on an FPGA with a total logic element count of 1700 elements for four phases) has been tested and successfully verified experimentally on Intel-qualified hardware. The experimental prototype features a four-phase 12V to 1.xV buck VRM driving an array of seven DDR4 load modules, and has demonstrated time-optimal recovery while accommodating a 100A load transient event with a transition speed of 2000A / μs.

[0024] The objective of this invention is to introduce a new all-digital controller for high performance multi-phase buck VRM as shown in Figure 1. The new controller has a current balancing module that allows for even load sharing among phases. The outer voltage regulation loop encompasses linear compensation for steady state and small deviations along with a large signal transient suppression unit to mitigate large changes in load. Additionally, a high level system governor oversees the tasks of phase balancing, synchronization, load sharing, AVP, and phase shedding. A further objective of this invention is to present in detail a new controller implementation that allows for time optimal transient recovery in multi-phase regulators.

[0025] Proposed controller architecture and operating principle The multi-phase buck VRM controller developed in this invention and exemplarily presented in FIG. 1 consists of two main control units: a small-signal ACM controller and a large-signal transient suppression unit (TSU) that are integrated together in a hybrid controller architecture

[44] -

[53] . Each controller is designed to perform well within its control law operation. The TSU is designed to accommodate large load changes and utilizes a nonlinear, state variable based recovery pattern to achieve the best possible transition from one load condition to another. This small-signal controller is structured around a current-programmed linear compensation scheme and operates with fixed frequency PWM. Doing so allows for a simpler design of the power stage and, more importantly, high steady-state accuracy can be achieved along with high static efficiency and good thermal distribution between phases, which is important in the context of multiphase converters. Forming this type of hybrid controller structure provides flexibility and separates tasks between compensators. Load transients are repaired in a time-optimal or minimum deviation pattern, taking advantage of the parallelization of phases to hasten the recovery process. The design of the small-signal linear compensator encompasses minimum dc error, accuracy, and current sharing. This configuration simplifies the design, while at the same time the steady-state features are preserved and a significant improvement in transient mitigation is achieved by the TSU. It should be noted that by defining the task of the transient controller to bring the state variables from the old state to the neighborhood of the new state while regulating the task of the linear controller, the problem of controller stability is essentially solved and can be checked by conventional tools such as Nyquist or phasemargirtest

[53] -

[56] .

[0026] Figure 2 shows a schematic of the sensing diagram required to facilitate a hybrid controller. This is a key interface for any high performance VRM, and especially in multi-phase applications. It is important to have reliable circuit parameters for issues of accuracy, fast timing, sensitivity to changes, and response to noise and other disturbances. As can be seen from Figure 2, the embodiment used in the present invention is to use differential acquisition of state variable signals. This compensates for the distance from the measurement point to the controller front end. Once the signals are acquired, they are further manipulated according to the required task (regulation, detection, information, etc.). The average readings, i.e. one sample per cycle readings such as information of the output voltage and the current of each phase, are processed by the steady state controller. The continuous signal information of the output voltage is further manipulated by the TSU.

[0027] The fundamental challenge of multi-phase architectures is the parallelability of multiple power stages and the need to properly distribute effort among them while maintaining a well-regulated voltage at the output. This requires some form of current or load sharing protocol. In the present invention, an average current program mode (ACM) control for the operation of the steady-state compensation scheme is used, as seen in FIG. 3A. Under the assumption that the control bandwidth of the current loop is sufficiently wider than that of the output voltage, each individual power stage feeding the output capacitance can be treated as a controlled current source, as in FIG. 3B. This allows the parallelization of multiple converter phases, easy regulation of phase currents, and therefore current sharing. Equal currents ultimately result in thermal distribution between phases at no additional cost, which is important for multi-phase applications.

[0028] An additional important feature of multiphase controllers, required by loads due to thermal limitations when operating at high currents

[57] , is active voltage positioning (AVP). load (t) as a function of the target v outA typical falling curve representing the (t) level is shown in Figure 4. The output voltage decreases as a linear function of the load current, V VID defines the nominal output voltage under no load condition, and V min I max Droop control is implemented by shifting down the target reference voltage as the load increases and can be expressed as: v ref =V VID -R VID i sum [n] (1) v ref [n] is the voltage loop reference, V VID and R VID is the desired V VID User-selected AVP parameters to fit the curve, I sum [n] is the digital value of the total converter current. Note that to avoid oscillations at the output, and because the droop is only concerned with the steady-state voltage level, its bandwidth is significantly lower than the response of the voltage control loop.

[0029] The working principle of the ACM controller is explained using Figures 5 and 6, which respectively show a conceptual block diagram of the ACM controller and its timing sequence diagram during steady-state operation. Since the present invention focuses on an all-digital implementation of the controller, the explanation is carried out using a sample data domain representation. The voltage loop is driven by the error signal v given by equation (2): e Based on [n], a digital reference v for the inner current loop c Create [n]: v c [n]=v ref [n]-v out [n] (2) v ref [n] is the reference generated in the AVP, and v out [n] is the sampled output voltage. Then, the current error signal i e [n] is the sampled average inductor current of each phase, i L [n] is calculated for each phase. The current error signal i e[n] is used as input for a current loop compensator which generates a duty command d[n] for the DPWM module to form a pulse width modulated signal c(t).

[0030] In the classical approach to ACM control, v out [n] and i L [n] (Fig. 5) samples consecutively to save power and area. Moreover, it is common practice to place the sampling events away from the switching actions to increase the measurement signal-to-noise ratio. However, in interleaved multiphase systems, the switching events are virtually distributed along the entire switching cycle Ts and become more frequent with the number of phases, limiting the suitable time slots for data acquisition. To overcome this obstacle, the present invention synchronizes the measurements per phase and configures a unified data acquisition sequence, which has the advantage of increasing the number of allowed interleaved phases, limited only by the acquisition time. The ADC hardware realization in the present invention is performed by delay lines and combinational circuits as previously described in

[58] , so that the hardware penalty per phase is negligible.

[0031] Figure 6 shows the timing sequence diagram of the ACM controller. out [n] and i L Both [n] are sampled simultaneously. To take advantage of the extended bandwidth options of polyphase operation, the reference v c [n] signal is updated by the voltage loop compensator and the associated phase duty command d n [n] is generated by each current loop and updated to its DPWM port at the start of each phase. out [n] and i L By simultaneously sampling [n] at fixed positions within Ts, the timing logic of Figure 6 can be replicated and adapted to accommodate any number of phases, limited by the data acquisition capabilities of the controller hardware.

[0032] Small load changes, defined within the range of the inductor current ripple (approximately 30% of the rated current), do not trigger the operation of the TSU, but are regulated through steady-state compensation. Figure 7 shows a typical response of a linear controller to a loading transient in four-phase operation (results obtained from a PSIM simulation). At point t step Before the controller is in steady state, each phase is low t step In the load is changed, each phase is I high The magnified box in Figure 7 shows that the load step occurs between two adjacent phase switching cycles. The small signal compensator must transmit t update In the small signal compensator, the ACM architecture responds to a transient event as soon as the next upcoming phase period begins, a much faster response than the traditional practice where the controller waits for a full switching cycle to complete. During the transient period and under any transient condition, the ACM architecture of the small signal compensator maintains current sharing between the phases, reducing the current sharing convergence time to zero, and the output current is fully shared when the system returns to steady state operation.

[0033] Large signal compensation method The hybrid controller architecture facilitates a large-signal recovery pattern to suppress extreme transient events that exceed the tuning capability of linear, small-signal compensators. The limitations of a transient-oriented controller are effectively the slew rate imposed by the passive components and the system delays (detection, computation, etc.)

[48] ,

[59] -

[62] . A typical waveform of the transient recovery is shown in Figure 8 (obtained by PSIM simulation) when the load is I low and I high , and a subsequent unloading transient event, which respectively vary between values ​​of . Details of the transient and extreme detection sensor as used in the present invention are shown in Fig. 9 and are based on

[43] .

[0034] Before the first transient event, the output voltage is V th-H and V th-L (FIG. 9A) and is controlled by the steady-state controller. load At this time, the load is I high , the output voltage drops and CMPL is triggered. By this point, the steady-state controller operation stops and the large signal compensator takes over control of the gating output, forcing on all available phases. The duration between the start of the transient and the point of charge balance (T0) is measured using a counter. The charge balance point appears as an extreme point in the output voltage. Assuming that T0 is achieved by the controller, the remainder of the operation can be completed in a single on-off switching cycle to fully recover to its nominal value, as demonstrated in

[44] -

[49] . In the unique case of a loading transient, where a small inductor significantly increases the total system current slew rate, producing a faster transient response and virtually no voltage drop at the output, a minimum deviation approach can be implemented instead of a full TOC operation. Beyond this point, control is returned to the steady-state controller, which maintains operation at the new steady-state condition.

[0035] Contrary to loading transient events, unloading transients are a more challenging task due to the low current slew rate which extends the transient recovery time. The result of current slew rate mismatch is shown in Figure 8, where the unloading transient v max Voltage overshoot caused by voltage undershoot v min Since the output voltage is much larger than the nominal value, a longer off-time is required to restore the output voltage to its nominal value. In some cases, the output capacitor is actively discharged by the multi-phase VRM as the inductor current goes negative, further inducing the transient relaxation process. The capacitor current i shown in Figure 8 cap It is also possible to demonstrate the difference between the two transients. Loading Transient Q loss The charge loss during the unloading transient case isinj This is because it recovers more quickly than

[0036] The current rise / fall phase in large signal compensation can be achieved with different levels of phase synchronization during the transient. Figure 10 shows three options for the rise start with and without phase synchronization, each with its advantages and disadvantages. The first option in Figure 10(a) maintains phase synchronization while also dealing with the transient with the closest phase available at the time of detection, in which case the dashed phase continues its on state immediately upon transient detection. The second option in Figure 10(b) is to maintain perfect phase synchronization during the transient, when each phase is turned on at the beginning of its next cycle. The third option is to turn on all available phases as soon as the transient event is detected, which results in the worst phase synchronization, but nevertheless the transient performance is better compared to the first two options. When examining the current sharing attributes during the transient time, the latter option maintains good current sharing, while the worst current mismatch depends on the size of the current ripple.

[0037] The method described in Figure 10(c) is chosen for its fastest transient performance as well as current sharing attributes. Another benefit of this approach is that during a transient event, the system can be treated as one single-phase buck, effectively increasing the bandwidth and reducing the effective inductance L. eq The goal is to obtain L eq =L ind / N (N represents the number of active phases).

[0038] If we treat the multi-phase converter as a single-phase buck, we can easily extract the state space trajectories as shown in Figure 11. The dashed lines mark the OFF-state trajectories, while the ON-state trajectories are rendered as vertical straight lines, due to the small size of the inductors and large output capacitors. low and I highA loading transient between two steady currents, I, is shown in FIG. 11 by the thick dashed line, and the loading transient can be completed in a single on-cycle, during which the output voltage remains substantially constant, and thus full TOC operation can be reduced to a minimal excursion regime without extended recovery times. high and I low The unloading transient reaction between the I and I starts with a long off state that can be completed with a negative inductor current, followed by a short on state, bringing the system to I in as short a time as possible. low The behavior of both the loading and unloading transients is experimentally verified in the following description.

[0039] Advanced management features and implementation aspects To accommodate high performance loads, performed by hybrid architectures and with additional features such as AVP, phase shedding / addition, and fault management in addition to the regulation requirements described in the previous section, modern multi-phase controllers are required. In the present invention, the additional features are implemented by a system governor unit shown in Figure 12. The system governor regulates the input voltage v in [n], output voltage v out [n], temperature temp[n], voltage loop output v C Collect [n] system variables.

[0040] AVP function implementation A linear AVP function (as shown above) can be realized in an analog controller with relatively moderate design effort, while implementing more complex functions such as piecewise linear or nonlinear functions can dramatically increase the complexity of the controller design. Digital control, as used in state-of-the-art MPVRM controllers, can be utilized to implement complex AVP functions, as shown in Figure 13, reducing the design complexity and providing real-time calibration of the AVP function. The digital AVP function realized in the present invention is shown in Figure 13. At low load conditions, the load current is at the bottom threshold i s The output voltage remains constant until if Up to a load current of i, the output voltage is constant due to the output impedance R AVP Follow the instructions. f Larger load current to maximum load current I max The output voltage remains constant until V min It is.

[0041] Despite their advantages over analog-implemented AVP units, digital AVP units can encounter resolution issues where the minimum output voltage step is limited by the voltage ADC sampling resolution. ref The unit change in [n] is v out The smooth load line profile in Figure 13 is realized discretely since the AVP profile is translated into small steps of (t). Enhancing the ADC resolution to solve the AVP profile discretization is limited by the system PWM resolution to prevent limit cycle oscillations. Filtering the AVP results improves noise immunity and profile discretization while minimizing the impact on the bandwidth of the AVP function.

[0042] Traditional AVP operating bandwidth is typically relatively low relative to the voltage loop compensator bandwidth, which is implemented to prevent unwanted voltage oscillations between the loops and ensure tight voltage regulation during steady state operation. However, in modern MPVRMs, the load is capable of fast and large transients that require ensuring that the nonlinear solution always maintains the load line profile of Figure 13. Figure 14 illustrates the nonlinear operation of the AVP unit during a large unloading transient event. Ideally, once the minimum deviation transient mitigation is complete, the output voltage, as dictated by the AVP unit, will be brought down to its desired post-transient level (V post Because transient events can be extremely short due to the small inductor values ​​used in high performance MPVRMs, the load current step size can be difficult to obtain from the relatively slow steady state measurements, and therefore the time of nonlinear relaxation action T0 is used to accurately estimate the current step and adjust v accordingly. ref [n] can be changed.

[0043] Phase Count Optimizer In the present invention, as shown in FIG. 1, the output of the outer current loop is the inner current loop reference v c Extract the load current from [n]. v c The value of [n] is fed to a digital LPF (implemented as a moving average) to ensure that singular calculation or sampling errors do not trigger the Phase Count Optimizer (PCO). The phase shedding and summing procedure for efficiency is a relatively slow process, so the delay caused by the filtering stage is negligible. The filtered result is the input to a look-up table (LUT) that optimizes the filter for a given v c This LUT can be reprogrammed to accommodate changes in power stages or to account for drift in component values ​​due to aging and temperature.

[0044] In case of load shedding, a phase shedding procedure implemented by the PCO is initiated to optimize the converter efficiency. For simplicity, the procedure is described for a 2 to 1 transition, but it applies for any other phase shedding transition. As can be seen in Figure 15, before the number of active phases changes, a current balancing is performed by the ACM control scheme. Initially, the reference to the inner current loop of the shedding phase is v shed [n], and the remaining phases operate in the original double-loop configuration. shed [n] is v c [n]-1 is equal to N sh It gradually decreases with each switching period. The inner current loop of the shedding phase remains active, so its inductor current is monitored, allowing the current ramp down v shed[n]. The remaining phases operating in a dual loop configuration increase their current to compensate for the shed phase, as shown in Figure 15. This results in a gentle phase shedding scheme without voltage deviations or current spikes. shed When [n] reaches zero, the shedding phase is turned off completely by the controller. The duration of each step can be varied, but must be long enough to allow the remaining phases to ramp up their current, as shown in Figure 15. For an increase in load demand, a similar procedure is performed in which the inner loop reference of the added phase is gradually increased every Nsh switching cycles. Since the existing phase operates in a dual loop configuration, its current is adjusted to compensate for the increased current delivered to the load and maintain tight voltage regulation. shed [n] is v c Once [n] or more is reached, the phase addition process is complete, which means that the currents in both phases are equal.

[0045] Besides optimizing steady-state efficiency, the PCO also functions during transient events. Upon transient detection, the linear controller is bypassed and the drive signal to the power switches is generated by the nonlinear controller. Thus, upon transient detection, the PCO sets the maximum number of phases to reduce the transient duration by multiplying the effective current slew rate. This action in turn ensures the best achievable transient performance of the nonlinear TSU. After completion of the transient event, the PCO reverts to steady-state operation, branching, or adding phases depending on the load conditions.

[0046] Post-transient handoff procedures The transition from a nonlinear controller operation performing TOC or minimum deviation control to a small signal based linear controller is called Hand-off. It involves a series of adjustments performed by the TSU on the reference control signal and on the duty cycle commands of the different phases. The hand-off procedure from the nonlinear control operation in a lossless converter can be performed by assigning a pre-transient control value. But in practice, additional settling transients may occur if the post-transient control signals (both internal and external) are not modified to compensate for losses in the system. In the present invention, an ACM control scheme is realized for steady state operation (Error! Reference source not found), and therefore the inner current loop v c Both the reference to [n], as well as all duty cycle commands, are modified based on the duration and polarity of the transient event. Once the handoff procedure is initiated, the controller operates open-loop for a single switching cycle with the modified duty cycle before closed-loop operation is resumed.

[0047] In transient detection, the duty cycle D0[n] of the leading phase, the current loop reference v co [n] is sampled and stored in a dedicated register. In case of a loading transient, the modified duty cycle, D tr is calculated as follows:

[0048]

number

[0049] For unload transients, do the following:

[0050]

number

[0051] k is a proportionality constant derived during the design process, and T0 is the duration of the transient relaxation period estimated by the TSU. By performing a current sweep test of the multiphase converter, the full load range operation is verified and duty cycle values ​​are stored in the system for a wide range of load conditions. These values ​​are plotted as a function of the load current and extrapolated to a linear curve with a slope equal to k. The inner current loop reference is also a sampled v co and is updated to take into account the load step information stored as T0. Once closed-loop operation resumes, fine adjustments are made to the duty cycle command by the steady-state controller to achieve accurate current balance and maintain steady-state operation.

[0052] Multi-phase DL-DPWM module The practical implementation of a multi-phase system is subject to imbalance between different phases that will affect the current sharing quality. A DPWM model based on multiple DL realization, especially on an FPGA custom-designed module, can introduce non-identical PWM signals for two different phases under the same duty command. As shown in Figure 16, the single DL multi-phase DPWM realized in this invention generates PWM signals for all phases based on a single DL ring oscillator. Given a duty command d[n], the DL ring oscillator and duty cycle logic are used to generate c n A (t) signal is generated. The single DL design negates the system sensitivity to both composition and silicon level differences between multiple modules. In a multi-phase system, with very small inductors and very large output capacitances, the soft start unit is essential to prevent any start-up current or voltage overshoot and bring the system to the steady state threshold. The soft start unit is built into the DPWM module (Figure 16) and provides a power good indication after the soft start process is completed.

[0053] Simulation and Experimental Verification of a Multiphase Buck Converter The operation of the multi-phase buck VRM controller has been verified using a 12V to 1.xV 4-phase multi-phase buck converter. An experimental prototype with all analog front-end peripherals has been built and tested. The converter parameters are given in Table I. Each DDR4 module capable of sourcing or sinking up to 14A and the gating signal pattern is generated by a signal generator that is asynchronous to the controller operation. The load slew rate used in the experiments is 2000A / μs. The digital hybrid controller architecture, system governor and custom-made peripherals like DL-ADC and single delay line multi-phase PWM are fully implemented on Cyclone V FPGA. The converter parameters are given in Table I below.

[0054] [Table 1]

[0055] FIG. 17 shows the transient response of the small signal compensator for a load transient event from 16A to 88A. L1 and i L2 represent the inductor currents of phase 1 and phase 2, respectively, which step up from an average current of 4A to 22A in response to the load change. The voltage at the load point is v out , which shows a maximum voltage excursion of 350 mV and a complete recovery period after 220 μs. The small signal controller maintains current sharing between the phases during the entire transient relaxation period.

[0056] In FIG. 18, the large signal compensation scheme is activated to mitigate a load transient event from 16 A to 88 A. Here, the controller detects a 30 mV voltage v out A minimum deviation recovery profile was achieved with a steady-state recovery within 12μs. The TSU operation demonstrates excellent current sharing during the transient and transition to the steady-state controller.

[0057] As shown in Figure 19 (small signal compensation) and Figure 20 (TSU), an unloading transient case is demonstrated with a load step from 88 A to 24 A. The overshoot obtained with the linear compensation scheme was measured at 360 mV and recovered within 300 μs, while the transient directional recovery was 43 mV with a recovery time of 7 μs.

[0058] Figure 21 shows the phase shedding capability of the controller during steady state operation. At a constant load of 20A, the controller adjusts the number of active phases from 4 to 1, thereby improving the VRM efficiency. The shedding process is divided into two steps, as indicated by the shedding indicator. In the first step, the controller sheds phases 2 and 4, and in the second step, phase 3 is dropped as well. The impact of the shedding process on the output voltage is negligible due to the controlled shedding process described above, resulting in a maximum voltage deviation measured to be less than 20mV.

[0059] The complete operation of all implemented controls is shown in Figure 22, where the DDR emulation module is switched from 5A to 85A. During a load transient event, the PCO transitions from 1 to 4 phases of operation and the AVP unit commands a 160mV drop in output voltage according to the 2mΩ load line function. In the reverse unloading case, the AVP unit restores the output voltage to its original position. After the transient suppression is complete, the steady-state phase shedding process is implemented and phases 2, 4, and 3 are shed during the 5A load operation.

[0060] A thermal performance comparison between the voltage mode control scheme without active current balancing and the ACM control with inherent per-phase current balancing is shown in Figure 23. When the difference in heat distribution is tested at 90A steady-state operation, the voltage mode control (Figure 23(a)) results in a difference of 2.5°C between 2 and 4 phases. The ACM control (Figure 23(b)) improves the heat sharing, achieving a difference of 0.7°C between phase 2 and phase 4.

[0061] The above examples and explanations are of course provided for illustrative purposes only and are not intended to limit the invention in any manner. As will be appreciated by those skilled in the art, the present invention can be implemented in a wide variety of ways, using two or more techniques from the techniques described above, all without exceeding the scope of the present invention.

Claims

1. 1. A mixed signal controller for controlling a multiphase average current mode voltage regulator having an output connected to a load, comprising: a. a delay line (DL) based digital voltage sampling analog to digital converter (ADC) configured to obtain samples of an output voltage signal and convert the output voltage signal from analog to digital; b. A delay line (DL) based digital current sampling ADC configured to obtain samples of inductor currents per phase and convert the inductor currents from analog to digital; c. A digital voltage compensator for voltage regulation, comprising: ｅ a digital voltage compensator configured to receive as an input, d. A digital current compensator for current regulation, having as input a digital current error signal i ｅ a digital current compensator receiving the digital current error signal and generating a duty ratio command signal based on the digital current error signal; e. A DL-based multi-phase digital pulse width modulator (DPWM) that receives as input the duty cycle command signal for each phase and generates pulse width modulated signals (per phase) that are supplied to the gates of the converter transistors, thereby controlling the current and output voltage per phase supplied to the load; f. An analog front end that receives differential measurements of the output voltage and inductor current per phase, where each signal is converted to a single-ended form, whereby the single-ended signal is used for steady state control via ADC measurements, and the single-ended output voltage is used for transient detection and output voltage extreme detection during transients; g. a transient suppression unit (TSU) receiving as an input a digital indication signal from said analog front end and generating gating signals provided to gates of transistors of said converter during a transient event, thereby controlling the current and voltage provided to said load during said transient event; h. a Phase Count Optimizer (PCO) unit that receives as an input the digital current reference signal and generates enable / disable control signals for each phase PWM output tri-state buffer; i. an active voltage positioning (AVP) unit that receives as an input the digital current reference signal and generates a voltage reference signal for the voltage loop compensator; A controller comprising:

2. The controller of claim 1 , wherein the controller is implemented using standard CMOS components.

3. The controller of claim 1 , wherein the digital voltage-sampling ADC and the digital current-sampling ADC are based on standard cell technology without modification.

4. The controller of claim 1 , wherein the digital current compensator and the per-phase digital duty ratio compensator are first order compensators.

5. The controller of claim 1 , wherein whenever the voltage loop is broken, each loop and each phase is regulated with a single state variable.

6. The controller of claim 1 , wherein the controller comprises an outer voltage loop and an inner current loop per phase having different bandwidths.

7. The multi-phase DPWM includes: a. A single DL ring oscillator that generates the clock signals for the PWM logic per phase; b. a duty cycle logic block that receives as inputs a digital duty cycle command and the DL ring output and generates a pulse width modulated signal that controls the gate of the transistor; Equipped with The control signals of the gates are synchronized for interleaved operation and out of sync for non-interleaved operation. The controller of claim 1 .

8. The TSU is a. a state machine based logic block that generates gating signals that are provided to the gates of the phase transistors of the converter during a transient event; b. Fault protection logic for fast TSU termination and return to DPWM operation; c. a handoff estimation block that receives a pre-transient current reference signal and a duty cycle command and generates estimated post-transient values ​​for the current reference signal and the duty cycle command; The controller of claim 1 .

9. The PCO is a. a low pass filter LPF that receives the current reference signal and generates a moving average of the current reference signal based on the current reference signal; b. a state machine based logic block that receives the average value of the current reference signal and a transient notification signal and generates a controlled enable / disable signal for each of the phases; Equipped with The controller of claim 1 .

10. The AVP is a. a reference calculation block that receives the average value of the current reference signal generated by the PCO and generates a digital reference voltage signal for the digital voltage compensator; b. a transient correction block that receives a step estimate of current from the TSU following a transient event and generates a correction signal for the calculation block; Equipped with The controller of claim 1 .

11. The number of active phases is determined by the PCO. a. turning on all phases when power is turned on; b. monitoring the average value of the digital current reference signal at the output of the digital voltage compensator to determine an optimal number of phases; c. taking over the current reference signal of the particular phase to be shut down / turned on and issuing an associated enable signal to the output buffer; d. determining the optimal number of phases by monitoring the average value of the digital current reference signal at the output of the digital voltage compensator; e. During the transient event, setting all phases to active mode and returning to step b above; Optimized by 2. The digital hybrid average current mode voltage regulator controller of claim 1.

12. 1. A method for voltage regulation in a mixed-signal hybrid ACM controller architecture, comprising: a. during steady state operation of the ACM controller, simultaneously measuring the output voltage and average inductor current per phase once for each active phase during a switching cycle and in synchronization with the interleaved operation of a multi-phase digital pulse width modulator (DPWM) that controls the current and output voltage per phase delivered to a load; b. Using the measured output voltage, a voltage error v e generating [n]; c. calculating a current reference signal using a voltage compensator; d. Using the calculated current reference signal and the inductor current measurement, a digital current error signal i e generating a current error signal d[n], the current error signal being used by a per-phase current compensator to generate a particular phase duty cycle command d[n]; e. receiving a multi-phase DPWM duty cycle command d[n] and generating a steady-state gating signal; f. sensing the transient start time and the transient direction (loading or unloading) by a transient detection sensor if a transient event occurs during steady state operation; g. When a transient event is detected, the PCO is used to activate all available phases, and the TSU controls the transient gate signal to activate the T ０ enabling counting to begin; h) depending on the transient direction, the TSU turns on all phases using low side transistors for unloading transients and high side transistors for loading transients; i. Continue step g. above until an output voltage extreme is measured by the extreme value detection sensor, and the TSU ０ stopping the counter and resuming said steady state control if no output voltage extreme is detected; j. Said T ０ The remaining gate signal timing is generated by the TSU based on the counter value of T and the average duty cycle value D, and the correction signal for the handoff procedure is T ０ and feeding back to the steady state controller; k. completing a gating sequence by said TSU according to the values ​​generated in step i. above; l. upon completion of the TSU gating sequence, transferring control of the gating signals to the ACM controller and resuming phase synchronization using the DPWM to commence steady-state operation according to step a. above; The method according to claim 1,

13. The multi-phase DPWM includes: a. A single DL ring oscillator that generates the clock signals for the PWM logic per phase; b. a duty cycle logic block that receives as input a digital duty cycle command and the DL Ring output and generates a pulse width modulated signal that controls the gate of the low side transistor and the gate of the high side transistor; Equipped with The control signals of the gates are synchronized for interleaved operation and out of sync for non-interleaved operation.

13. The method of claim 12.

14. The TSU is a. a state machine based logic block that generates gating signals that are supplied to the gates of the phase transistors of the converter during a transient event; b. Fault protection logic for fast TSU termination and return to DPWM operation; c. a handoff estimation block that receives a pre-transient current reference signal and a duty cycle command and generates estimated post-transient values ​​for the current reference signal and the duty cycle command; 13. The method of claim 12.

15. The PCO is a. a low pass filter LPF that receives the current reference signal and generates a moving average of the current reference signal based on the current reference signal; b. a state machine based logic block that receives the average value of the current reference signal and a transient notification signal and generates a controlled enable / disable signal for each of the phases; Equipped with 13. The method of claim 12.

16. The number of active phases is determined by the PCO. a. turning on all phases when power is turned on; b. monitoring an average value of the digital current reference signal at the output of the voltage compensator to determine an optimal number of phases; c. taking over the digital current reference signal of the particular phase to be shut down / turned on and issuing an associated enable signal to the output buffer; d. determining the optimal number of phases by monitoring the average value of the digital current reference signal at the output of the voltage compensator; e. During the transient event, setting all phases to active mode and returning to step b above; Optimized by 13. The method of claim 12.

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