Method for manufacturing back-illuminated optical sensor with improved detection parameters

Abstract

The present invention relates to a method for fabricating a backside illuminated (BSI) CMOS optical sensor, and more particularly to a method for reducing crosstalk and improving photon detection efficiency (PDE) in a backside illuminated (BSI) CMOS optical sensor. In particular, the claimed method includes the steps of creating isolation structures between adjacent detector elements of a pixel array of the BSI CMOS optical sensor to isolate all adjacent detector elements from each other, and creating a common voltage backside application structure for all detector elements of the pixel array to connect all detector elements to a common voltage bias.

Description

[Technical field]

[0001] The present invention relates generally to methods for fabricating backside illuminated (BSI) optical sensors, and more particularly to methods for fabricating BSI optical sensors having improved detection parameters such as reduced crosstalk and increased photon detection efficiency (PDE). In particular, the present invention provides a method for isolating the detection elements of a BSI optical sensor that is compatible with the possibility of applying a common voltage bias to the detection elements. [Background technology]

[0002] Optical sensors have reached a level of miniaturization and detection accuracy that makes them suitable for use in many fields.

[0003] For example, optical sensors are currently used in autonomous driving systems such as ADAS (Advanced Driver Assistance Systems) to provide distance measurements. Among this type of optical sensors are so-called time-of-flight (TOF) devices, which are designed to detect the distance of an object by measuring the time it takes for an electromagnetic wave (such as a laser pulse) to return from the object. TOF devices employ a very sensitive detection element, being a single-photon avalanche diode (SPAD). The main components of a SPAD are an avalanche photodiode (Geiger mode) operated above its breakdown voltage, a quenching resistor, a first electrode (cathode) and a second electrode (anode). Electron-hole pairs generated by photons incident on the photodiode region (such as a reverse-biased p-n junction) can be biased above the breakdown voltage (multiplication region) and cause an avalanche due to a multiplication process by impact ionization in the space charge region of the photodiode. In this way, a macroscopic current is generated in response to the flow of incident photons.

[0004] The use of SPADs is not limited to the automotive market, but has been widely adopted in other markets such as the medical market. SPAD arrays (often referred to as silicon photomultipliers or SiPMs) have replaced photomultiplier tube (PMT) technology in photon counting applications such as Positron Emission Tomography (PET) technology, and have been adopted to observe metabolic processes in the body. The implementation of SPAD technology in CMOS technology further enhances the advantages of SiPM technology, offering high dynamic range photon counting with picosecond timing.

[0005] Referring again to the automotive market, LIDAR (Light Detection and Ranging) technology uses near-infrared (NIR) light detection, for example, to measure the time of flight of emitted laser pulses. To be sensitive to the NIR wavelength range, a SPAD array optical sensor must have a photodetection efficiency (PDE) of more than 10% in the 850-910 nm range of the electromagnetic spectrum. This is very difficult to achieve with conventional front-side illuminated (FSI) CMOS optical sensors, due to the deep penetration distance of NIR photons and their deep absorption in the semiconductor substrate (e.g., silicon substrate), with the consequence that the generated electron / hole pairs are less likely to be collected in the avalanche photodiode region. Conversely, it can be achieved with back-side illuminated (BSI) CMOS optical sensors, which are configured to place all detector elements close to the back surface where the incident photons impinge, and for this reason, most generated electron / hole pairs are more likely to be collected in the avalanche photodiode region.

[0006] The main drawback that occurs in SPAD arrays is the crosstalk between adjacent detector elements. Crosstalk can occur due to a pseudo avalanche of one detector element caused by the avalanche of another detector element, generating a pseudo output current pulse even in the absence of light (dark current). In order to limit the presence of photons moving from one SPAD to an adjacent SPAD, potentially causing a secondary avalanche (crosstalk) and, as a result, the dark count rate (DCR), it is necessary to isolate the individual detector elements from each other. Different isolation structures can be used. In general, the isolation structure can be made in the form of a trench etched from the front side into the substrate adjacent to the detector element area. Once the trench is formed, it is usually filled with a dielectric. For example, according to US Pat. No. 9,741,759, the trench isolation structure has the form of a deep trench isolation (DTI) structure made from the back side towards the front side of the semiconductor substrate. According to the same US patent, the trench isolation structure is filled with a first isolation material conformally formed on the inner wall of the trench and a second conductive material conformally formed to fill the interior of the trench isolation structure. Furthermore, according to the same US patent, the trench isolation structure can be voltaged by connecting a voltage application device to the trench isolation structure. Usually, with this type of isolation, a problem occurs because the trench isolation structure isolates the detector elements from each other, making it impossible to connect all the detector elements to a common voltage bias. For example, in the case of SiPMs, each detector element (SPAD) has an anode electrode connected to a specific potential (e.g., ground potential) in order to be reverse biased across the junction. If the SPADs are isolated from each other, there is no way to connect the SPAD anode electrodes to a common potential. The only way to overcome this problem is to bias each SPAD individually, for example, by adding a single contact to connect each SPAD to the same potential, but this uses additional space in the array layout, reduces the fill factor, defined as the ratio of the detector area to the total area of ​​the detector elements, and reduces the photon detection efficiency (PDE).

[0007] It would therefore be desirable to provide a BSI optical sensor with improved performance parameters, such as reduced crosstalk and increased photodetection efficiency (PDE), without affecting the fill factor. Summary of the Invention [Problem to be solved by the invention]

[0008] A general object of the present invention is therefore to overcome the aforementioned technical problems that arise when trying to reduce crosstalk by implementing an optical isolation structure that isolates the sensing elements of an optical sensor from each other, thus prohibiting each sensing element from being connected to a common voltage bias.

[0009] Moreover, it is a specific object of the present invention to provide a method for manufacturing a back-side illuminated (BSI) CMOS optical sensor with improved detection parameters, said method including the step of creating an isolation structure between adjacent detection elements while all detection elements maintain connection to a common voltage bias. [Means for solving the problem]

[0010] These and other objects are achieved by the present invention, in that it relates to a method for manufacturing an optical sensor, as defined in the appended claims.

[0011] According to a first embodiment of the present invention, a method for manufacturing a back-side illuminated (BSI) CMOS optical sensor includes the following steps. forming an isolation structure surrounding each detection element of the pixel array in the form of a trench grid structure, the isolation structure consisting of a first isolation structure (e.g., a shallow trench isolation (STI) structure, a LOCOS isolation structure, or a buried region) created from the front surface of the optical sensor and a deep trench isolation (DTI) structure etched from the back surface of the optical sensor, and landing correspondingly on the bottom surface of the first isolation structure on the front side after thinning the silicon substrate from the back side; filling the backside DTI structure with a first insulating material and a second opaque material (e.g., metal) suitable for reducing crosstalk; backside planarizing the back surface of the optical sensor to expose a silicon surface corresponding to each sensing element; Depositing an additional low resistance layer on the backside surface to connect the exposed silicon surfaces and provide a common voltage application structure for all sensing elements of the pixel array. Preferably, the additional low resistance layer consists of an amorphous silicon material, which has the advantage of filtering UV and visible light, making it possible to detect only NIR light. According to a second embodiment of the present invention, a method for manufacturing a back-side illuminated (BSI) CMOS optical sensor includes the following steps. forming an isolation structure surrounding each detector element of the pixel array in the form of a staggered line of trenches, each line of trenches consisting of trench portions separated by gaps, filled with silicon substrate and staggered with respect to trench portions belonging to parallel lines of trenches; the isolation structure comprises a first isolation structure (e.g., a shallow trench isolation (STI) structure, or a LOCOS isolation structure, or an implanted region) created from the front side surface of the optical sensor and a second deep trench isolation structure (DTI) etched from the thinned back side surface of the optical sensor, landing corresponding to a bottom surface of the first isolation structure on the front side; filling the backside DTI structure with an opaque material suitable for reducing crosstalk; planarizing the backside surface of the optical sensor to expose a silicon backside surface corresponding to each sensing element and corresponding to a silicon gap, the exposed silicon backside surface providing a common voltage application structure for all sensing elements of the pixel array.

[0012] For a better understanding of the present invention, preferred embodiments, which are intended purely by way of example and should not be construed as limiting, will now be described with reference to the accompanying drawings (not to scale): [Brief description of the drawings]

[0013] [Figure 1] 1 shows a schematic diagram of a pixel array of a known semiconductor optical sensor, in which detector elements are connected in parallel to a common voltage bias; [Diagram 2] 1 shows a schematic diagram of a pixel array of a known semiconductor optical sensor, where detector elements are separated by isolation structures (solid bars); [Diagram 3] FIG. 1 shows a schematic diagram of a pixel array of a known semiconductor optical sensor, where detector elements are separated by isolation structures (solid bars) and connected to a common voltage bias via a single contact included in each detector element. [Figure 4] 1 shows a cross-section of a semiconductor BSI optical sensor obtained by the claimed method according to a first embodiment. [Diagram 5] 2 shows a flow chart illustrating a method for manufacturing a semiconductor BSI optical sensor according to a first embodiment. [Figure 6] 5 shows a top view and a cross section of a semiconductor BSI optical sensor obtained according to the claimed method according to a second embodiment. [Figure 7] 4 shows a flow chart illustrating a method for manufacturing a semiconductor BSI optical sensor according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The following discussion is presented to enable those skilled in the art to make and use the present invention. Various modifications to the embodiments will be readily apparent to those skilled in the art without departing from the scope of the invention as claimed. Thus, the present invention is not intended to be limited to the embodiments shown and described, but is to be accorded the widest scope consistent with the principles and features disclosed herein and defined in the appended claims.

[0015] As discussed in detail below, one aspect of the invention provides a method for fabricating a BSI optical sensor in which all sensing elements (e.g., SPADs) of a pixel array (e.g., SiPM) are separated by an isolation structure to reduce crosstalk, with the single elements being connected to a common voltage application structure provided from the backside of the optical sensor in a manner that does not affect the fill factor.

[0016] 1-3 show schematic diagrams of three different pixel arrays of an optical sensor, each consisting of a number of detector elements designed according to known layouts.

[0017] For example, the schematic diagram shown in FIG. 1 shows a pixel array 100 of an optical sensor implemented in CMOS technology, including a plurality of sensing elements 110 (e.g., SPADs), arranged in a two-dimensional matrix, with a first electrode (110a) connected to a potential V1 and a second electrode (110b) connected to a common potential node V2 (115). In particular, each sensing element is configured to include a photodiode active area (110c). In its simplest form, this is realized with a pn (or np) reverse-biased junction, so that the carrier charge (such as electron / hole pairs) in the n (or p) region is reduced. Thus, an incident photon generates an electron / hole pair that is collected by the depletion region of the photodiode. The pn junction is reverse-biased above the breakdown voltage, so that the electron (and hole) acquires enough energy before being collected to create another pair and start an avalanche process, amplifying the signal generated by the incident single photon. To stop the avalanche process, a quenching resistor 120 is used. In this way, each incident photon can be detected, resulting in a strong current pulse of a few nanoseconds duration. In a standard approach, a potential V1 is applied to each first electrode in succession, while a potential V2 (e.g. ground potential) is applied simultaneously to all second electrodes. Thus, all detector elements of the pixel array are connected in parallel to a common voltage bias V1-V2.

[0018] To isolate the SPADs from one another for the purpose of reducing crosstalk, a standard practice is to use trench isolation structures (solid bars 230 in FIG. 2) filled with a conductive material (such as a metal) or other opaque material. As shown in FIG. 2, the formation of a trench isolation structure provides optical isolation, but at the same time electrically isolates the sensing elements from one another, making it impossible to connect all the sensing elements to a common potential V2.

[0019] 3 shows a standard method used to overcome this problem. According to this method, an additional contact 310 is added to each detector element to continuously apply a potential V2 (e.g., ground potential) to each second electrode of each detector element. The addition of contact 310 to each detector element requires the use of more silicon space in the pixel array layout, thus reducing the fill factor and therefore the PDE.

[0020] To overcome the aforementioned problems, the proposed solution provides a method for manufacturing a BSI optical sensor according to the first and second embodiments.

[0021] For a better understanding of the invention, Fig. 4 shows an example of an optical sensor obtained according to a first preferred embodiment of the proposed method, in particular, Fig. 4 shows a cross-sectional view of a BSI optical sensor 400 at certain steps of the manufacturing process, including: a front side (FS) surface 410 and a back side (BS) surface 411; a semiconductor substrate (e.g., a silicon substrate) 401 having a first surface 401a and a second surface 401b facing each other; at least a first sensing element 402a and a second sensing element 402b formed in the semiconductor substrate 401 and separated by a front-side isolation structure (e.g., a shallow trench isolation (STI) structure) 403; a front side voltage application device 404 electrically connected from the FS surface 401a of the semiconductor substrate to the at least first or second detection element; an insulating layer 406 formed as multiple layers and including at least a first interconnect layer 407 and a metal contact 408; a carrier semiconductor substrate 409 attached to a front surface 510 of the optical sensor; a backside deep trench isolation (DTI) structure 405 surrounding at least one and a second sensing element and etched from the BS surface 401b and landing on the underside of the FS isolation structure 403, the DTI structure being filled with a first insulating material 405a (e.g., silicon oxide) covering the trench sidewalls and bottom and a second conductive material 405b (e.g., tungsten) filling the inside of the DTI structure; An additional low resistance layer 412 (eg, an amorphous silicon layer) is deposited on the BS surface 401b and connects at least the first and second sensing elements 402a and 402b from the semiconductor second surface.

[0022] According to a first preferred embodiment of the present invention, the BSI optical sensor 400 is manufactured according to the manufacturing process steps shown in Flowchart A of FIG. According to this preferred embodiment, the manufacturing process comprises the following manufacturing steps: 501) Perform a standard CMOS front side fabrication process including steps of fabricating a FS isolation structure (e.g., shallow trench isolation (STI)), multiple interconnect layers, and multiple contact / via structures disposed in the multi-layer isolation structure. 502) Attach a carrier wafer to a front surface of said multi-layer isolation structure. 503) Partially thin the semiconductor substrate from the backside surface. 504) Form BSI Deep Trench Isolation (DTI) structures from the backside by photo / etch process steps that land on the underside of the grid-shaped FS isolation structures surrounding each detector element area. 505) Deposit a first isolation layer covering the trench sidewalls and bottom wall of the DTI structure and a second conductive material, such as W, Ti / W, or Aluminum, filling the interior of the BSIDTI structure. 506) Planarize the backside surface (e.g., by chemical mechanical polishing, CMP) to remove all excess conductive material on the backside surface, form a low resistivity layer by depositing an amorphous silicon layer, dope (e.g., implant) said amorphous silicon layer to convert it to a low resistivity layer, and anneal it (e.g., thermal laser annealing, LTA, or microwave annealing, or other method that does not affect the underlying layers). Finally, a suitable ARC layer can be applied over the low resistivity layer to improve the transmittance of near infrared (NIR) radiation.

[0023] The advantages of the present invention are clear from the above. In particular, it is important to highlight the fact that in the above method, at least the first and second detector elements of the optical sensor pixel array (e.g., SPAD array) are all connected to the same backside potential (e.g., ground potential) by contacting a low-resistance layer (not shown in FIG. 4) with only one or very few contacts disposed on the front side of the optical sensor. It is also advantageous to use an amorphous silicon layer as an additional low-resistance material, since it helps to filter UV / visible light in the case of near-infrared (NIR) light detection.

[0024] According to a second embodiment of the present invention, a BSI deep trench isolation (DTI) structure is fabricated in the form of staggered lines of trenches to ensure optical isolation between adjacent detector elements of a pixel array while maintaining electrical continuity between said detector elements. For better understanding, FIG. 6 shows an example of a BSI optical sensor obtained according to the second embodiment of the proposed method. In particular, the upper part of FIG. 6 represents a top view of a BSI optical sensor 600, and the lower part represents a cross-sectional view of the BSI optical sensor 600 cut along the BB′ direction, as displayed at the top of FIG. 6. The optical sensor obtained according to this second embodiment includes: Front side FS surface 610 and back side BS surface 611; a semiconductor substrate 601 having a first surface 601a and a second surface 601b facing each other; at least a first sensing element 602a and a second sensing element 602b formed in the semiconductor substrate and separated by a FS isolation structure (e.g., a shallow trench isolation (STI) structure) 603; a front-side voltage application device 604 electrically connected from the FS surface 601a of the semiconductor substrate to the at least first or second detection element; an insulating layer 606 formed as multiple layers and including at least a first interconnect layer 607 and a metal contact 608; a carrier semiconductor substrate 609 attached to a front surface 610 of the optical sensor; A backside BS deep trench isolation (DTI) structure surrounding at least one and a second sensing element and made in the form of staggered lines of trenches 605 and etched from the backside surface 601b and landing on the underside of the FS isolation structure 603, the DTI structure being filled with a first insulating material 605a (e.g., silicon oxide) covering the sidewalls and bottom of the trench and a second conductive material 605b (e.g., W, Ti / W or aluminum) filling the interior of the DTI structure.

[0025] According to a second embodiment of the present invention, the BSI optical sensor 600 is manufactured according to the manufacturing process steps illustrated by Flowchart B of FIG. According to this method, the manufacturing process includes the following manufacturing steps: 701) Performing a standard front side fabrication process including forming a FS isolation structure (e.g., a shallow trench isolation structure (STI)) and multiple contact / via structures and multiple interconnect layers disposed in the multi-layer isolation structure; 702) attaching a carrier wafer to a front surface of the multi-layer isolation structure; 703) Partially removing silicon substrate from backside silicon surface; 704) forming a BSI deep trench isolation (DTI) structure from the backside by a photo / etch process step landing on the bottom surface of the FS isolation structure, the DTI structure having the form of staggered lines of trenches, separated by gaps, surrounding each detector element area; 705) depositing a first isolation layer covering the sidewalls and bottom wall of the trench of the DTI structure and a second conductive material, such as Ti / W or Aluminum, filling the interior of the BSIDTI structure; 706) Planarizing the backside surface (e.g., by chemical mechanical planarization (CMP)) and removing any excess conductive layer on the backside surface.

[0026] The advantages of the invention are clear from the above. In particular, it is important to highlight that the proposed solution consists in configuring a backside deep trench isolation structure in the form of staggered lines of trenches running parallel to each other and surrounding adjacent detector elements. Said staggered lines of trenches consist of trench portions separated by gaps filled with silicon substrate in order to guarantee electrical continuity between detector elements of a pixel array (e.g. a SPAD array) through the silicon gaps and at the same time create an optical barrier against crosstalk. According to the above-mentioned method, the exposed silicon substrate in the photodiode area serves as the second electrode of the detector elements, allowing a common potential to be applied to each second electrode (Figure 7).

[0027] Finally, it will be apparent that numerous modifications and variations can be made to the present invention, all of which are within the scope of the invention as defined in the appended claims.

Claims

1. 1. A method for fabricating a back-side illuminated (BSI) CMOS optical sensor with improved crosstalk and increased photon detection efficiency (PDE), comprising: providing a semiconductor wafer having a semiconductor substrate (401), a first surface (401a) and a second surface (401b) opposed to each other; performing a standard CMOS front side fabrication process, including forming at least a first sensing element (402a) and a second sensing element (402b) in the semiconductor substrate (401) between the first and second surfaces; forming at least one insulating layer (406) on said first surface of said semiconductor substrate (401), as well as at least a first interconnect layer (407) and at least one metal contact (408), said at least first interconnect layer and said at least one metal contact being embedded in said at least one insulating layer; providing a carrier semiconductor substrate (409) and attaching said carrier semiconductor substrate (409) to said at least one insulating layer; thinning the semiconductor wafer by removing material from the second surface (401b) of the semiconductor substrate (401); forming a backside deep trench isolation (DTI) structure (405) in the semiconductor substrate (401) surrounding the at least first and second sensing elements, the DTI structure extending from the thinned second surface; filling the DTI structure with a first insulating material (405a) covering the sidewalls and bottom of the trench and filling the inside of the deep trench isolation (DTI) structure with a second conductive material (405b); planarizing the semiconductor wafer from the thinned second surface to expose the semiconductor substrate (401) in the area of ​​at least the first and second detector elements; forming a common voltage application structure from the thinned second surface in contact with the deep trench isolation (DTI) structure and the semiconductor substrate (401) in at least the first and second sensing elements.

2. The method of claim 1 , wherein the deep trench isolation (DTI) structure (405) has the form of a trench grid structure surrounding the at least first and second sensing elements.

3. The method of claim 2, wherein the step of forming a common voltage application structure from the thinned second surface includes the step of forming a low resistance layer (412) on the thinned second surface connecting the trench grid structure and the semiconductor substrate (401) in the at least first and second detection elements.

4. forming the low resistance layer (412) on the thinned second surface, A process step of depositing an amorphous silicon layer; a process step of doping said amorphous silicon layer by an implantation process; 4. The method of claim 3, comprising the process step of annealing said amorphous silicon layer by thermal laser annealing (LTA), or microwave annealing, or other methodology that does not affect underlying layers.

5. 2. The method of claim 1, wherein the deep trench isolation (DTI) structure (405) has the form of staggered lines of trenches, each line of trenches consisting of trench portions separated by gaps filled with semiconductor substrate, the trench portions belonging to one line of trenches being staggered with respect to trench portions belonging to a parallel line of trenches.

6. The method of claim 5 , wherein the gaps between the trench portions are configured to provide a common voltage application structure to the at least first and second sensing elements from the thinned second surface.

7. 7. The method of claim 1, wherein the first insulating material (405a) is silicon oxide.

8. The method of any one of claims 1 to 7, wherein the second conductive material (405b) is an opaque material.

9. The method of claim 8, wherein the opaque material (405b) is made of metal.

10. The method of claim 9 , wherein the metal is selected from the set consisting of titanium, titanium nitride, tungsten, and aluminum.

11. 2. The method of claim 1, wherein the standard CMOS front side fabrication process further comprises forming a first isolation structure in the semiconductor substrate (401) surrounding the at least first and second detection elements, the first isolation structure extending from the first surface of the semiconductor substrate (401).

12. 12. The method of claim 11, wherein the first isolation structure formed in the semiconductor substrate (401) surrounding the at least first and second sensing elements is a shallow trench isolation (STI) structure.

13. 12. The method of claim 11, wherein the first isolation structure formed in the semiconductor substrate (401) surrounding the at least first and second detector elements is a LOCOS structure.

14. The method of claim 11 , wherein the first isolation structure formed in the semiconductor substrate (401) surrounding the at least first and second sensing elements is a buried region.

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