Digital-to-analog conversion circuit, display device, electronic device

Abstract

To reduce a circuit area of each of a plurality of selection units that selects a voltage to be outputted from among a plurality of voltages.SOLUTION: A column DAC circuit of a signal output circuit is a digital analog conversion unit that has a decoder 3022 to which a digital signal (image data 3023) composed of a plurality of bits is input, a voltage output unit that outputs a plurality of voltages differing in a value, and an output line that is provided so as to correspond to the decoder. The decoder has an arithmetic circuit SEL2A that accepts a digital signal as input, with two or bits inputted thereto, and a unit selection circuit 3024A to which a logical operation result of the arithmetic circuit is inputted, the unit selection circuit including a voltage selection unit to which a voltage of the voltage output unit is inputted, a switch SW that connects the output line and the voltage selection unit together, and selection means SEL1A to which the logical operation result of the arithmetic circuit is inputted and that controls the switch, the selection means controlling the switch according to the logical operation result of the arithmetic circuit.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a digital-to-analog conversion circuit that converts a digital signal into an analog signal, and to a display device and electronic equipment that include the digital-to-analog conversion circuit. [Background technology]

[0002] 2. Description of the Related Art Digital-to-analog conversion circuits are known that include a digital-to-analog conversion unit (hereinafter, sometimes abbreviated as DAC) that converts an input digital signal into an analog signal.

[0003] Various DAC configurations have been proposed, but the DAC configuration described in Patent Document 1 includes a plurality of selection circuits to which different voltages are input. Each of the selection circuits includes a logic circuit 813A to which a multi-bit signal is input, and a switch 812A. The on / off state of switch 812A is controlled by the output of logic circuit 813A. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-270858 A Summary of the Invention [Problem to be solved by the invention]

[0005] Although Patent Document 1 examines ways to reduce the circuit area of ​​the DAC, it does not sufficiently examine ways to reduce the circuit area of ​​the logic circuit that controls switch 812A.

[0006] The present invention solves the problem of reducing the circuit area of ​​each of a plurality of selection sections that selects a voltage to be output from a plurality of voltages. [Means for solving the problem]

[0007] The present invention has been made in view of the above problems, and one aspect of the present invention is a digital signal processing apparatus for a multi-bit digital signal input. 、 a decoder; a voltage output unit for outputting a plurality of voltages having different values; an output line provided corresponding to the decoder; A digital-to-analog conversion circuit having a decoder, teeth a first arithmetic circuit to which the digital signal is input and to which two or more bits are input; ,before The logical operation result of the first operation circuit is input. R A selection unit, teeth, The voltage of the voltage output unit is input. R A voltage selection unit and the output line and a switch that connects the voltage selection unit to the first arithmetic circuit, and a selection means that receives as input the logical operation result of the first arithmetic circuit and controls the switch, wherein the selection means controls the switch based on the logical operation result of the first arithmetic circuit. Effect of the Invention

[0008] According to the present invention, it is possible to reduce the circuit area of ​​each of a plurality of selection sections that selects a voltage to be output from a plurality of voltages. [Brief description of the drawings]

[0009] [Figure 1] Schematic diagram showing the configuration of a display device [Diagram 2] Diagram showing the configuration of the column DAC circuit [Diagram 3] Diagram showing the configuration of the column DAC circuit [Figure 4] Diagram showing the configuration of the column DAC circuit [Diagram 5] Diagram showing the configuration of the column DAC circuit [Figure 6] Diagram showing the configuration of the column DAC circuit [Figure 7] Diagram showing the configuration of electronic devices DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings.

[0011] In the following embodiments, the description will be focused on a display device having a digital-analog conversion circuit with a digital-analog conversion unit. However, the present invention is not limited to the display device, and can be generally applied to a digital-analog conversion circuit that converts a digital signal into an analog signal.

[0012] (First embodiment) 1 is a schematic diagram showing one form of a display device according to this embodiment. A pixel array 100 has a plurality of pixels 101 arranged across a plurality of rows and a plurality of columns (two-dimensionally). A control signal is input to each pixel 101 from a vertical scanning circuit 200 via a scanning line 210, and a luminance signal voltage (analog signal) is input from a signal output circuit 300 via an output line 310. The vertical scanning circuit 200 and the signal output circuit 300 are controlled by a control circuit 400. The pixel 101 includes a light-emitting diode (light-emitting element) and emits light with an amount of light corresponding to the input luminance signal voltage.

[0013] The signal output circuit 300 has a horizontal scanning circuit 301, a column DAC circuit 302, and a column driver circuit 303. Image data scanned by the horizontal scanning circuit 301 and input to each column is converted into an analog signal voltage by the column DAC circuit 302, and a luminance signal voltage corresponding to the analog signal voltage is output by the column driver circuit 303.

[0014] 2 shows the configuration of the column DAC circuit 302. The column DAC circuit 302 has a reference voltage generating means 3021 (voltage output section) and a decoder 3022 provided for each column. m (m is a natural number) reference voltages Vref are generated and commonly wired to the decoders 3022 for each of the multiple columns. The connection relationship of the decoders 3022 for each column is switched according to the m-bit image data 3023 scanned by the horizontal scanning circuit 301 and input to each column. mA corresponding one of the reference voltages Vref is output to the column driver circuit 303 as an analog signal corresponding to the image data.

[0015] A reference embodiment will be described with reference to FIG. 2. In FIG. 2, the column-by-column decoder 3022 is a 2 m The unit selection circuit 3024 has unit selection circuits 3024 (circuit blocks), and each unit selection circuit 3024 is composed of a switch SW and a selection means SEL1. The switch SW has two signal terminals and one control terminal. The switch SW switches between outputting and not outputting the voltage input to the signal terminal to the output line 310 in accordance with a signal input to the control terminal. One of the signal terminals is m Each of the switches SW is connected to a corresponding one of the reference voltages Vref, the other is connected to an output terminal of a decoder 3022 for each column, and the control terminal is connected to a selection means SEL1. When a signal is input to the control terminal, the two signal terminals are switched between conductive and non-conductive depending on the signal level. The selection means SEL1 inputs image data 3023 and its inverted signal, and controls the switch SW to be in a conductive state when desired data is input, and to be in a non-conductive state when other data is input. When the image data 3023 changes and the connection of the decoder 3022 for each column is switched accordingly, only two switches SW in each column are switched between conductive and non-conductive (one from conductive to non-conductive, the other from non-conductive to conductive).

[0016] In the configuration of FIG. 2(b), the selection means SEL1, which is the selection section, has 16 switches.

[0017] This embodiment will be described with reference to FIG.

[0018] Description of the contents that overlap with the description given with reference to FIG. 2 will be omitted.

[0019] In FIG. 3(a), the column-by-column decoder 3022 mThe unit selection circuit 3024A has one unit selection circuit 3024A and a second selection means SEL2A (arithmetic circuit). The second selection means SEL2A has a plurality of groups Gr1 to 4. Of the input data, a two-bit signal is input to each of the plurality of groups Gr1 to 4. Then, each of the plurality of groups Gr1 to 4 outputs four signals by performing a logical operation on the two-bit input signal. (2 inputs, 4 outputs)

[0020] Of the four signals output from each of the multiple groups Gr1 to Gr4, only one signal will be Hi depending on the signal value of each of the four-bit signals input. Note that, although the signals input to the multiple groups Gr are 2-bit here, they may be of more than one bit. When a 3-bit signal is input, eight signals will be output. In other words, the relationship between the number of input signals and the number of output signals for each of the multiple groups Gr is n inputs 2 n This is the output.

[0021] Each unit selection circuit 3024A is composed of a switch SW and a selection means SEL1A. The second selection means SEL2A inputs image data 3023 and outputs a signal 3023A for controlling the unit selection circuit 3024A to the corresponding transmission line 3100. A part of the signal 3023A, which is a result of logical operation of the input data, is input to each of the multiple selection means SEL1A. The multiple selection means SEL1 are connected so that one of the four signals output from each of the multiple groups Gr1 to Gr4 is input. The selection means SEL1 controls the conduction / non-conduction of the corresponding switch SW.

[0022] In this embodiment, the number of switches required to configure the selection means SEL1A can be reduced by converting the image data 3023 into a signal 3023A by the second selection means SEL2A. For example, when the image data is 8 bits and 256 unit selection circuits 3024 are arranged per column, the selection means SEL1 has 16 switches in FIG. 2, whereas the selection means SEL1A has 8 switches in FIG. 3. In this way, this embodiment can reduce the number of switches in the selection section. The multiple selection means SEL, including the selection means SEL1, are arranged in two rows and two columns, respectively. mIn this embodiment, since the number of switches in the selection means SEL can be reduced, it can be said that this brings about a remarkable effect in reducing the circuit area of ​​the column DAC circuit 302.

[0023] A level conversion circuit for converting the signal level of the signal 3023A may be provided between the second selection means SEL2A and the multiple selection means SEL. This level conversion circuit preferably converts the input Hi signal into a signal with a larger amplitude. On the other hand, the voltage of the input Lo signal is not converted. This makes the output voltage range larger than the voltage range input to the level conversion circuit. This allows the voltage handled by the circuit in the previous stage of the level conversion circuit (such as the second selection means SEL2A) to be reduced. This allows the withstand voltage performance required for the circuit in the previous stage of the level conversion circuit to be reduced, allowing it to be configured with smaller elements. This allows the circuit area of ​​the digital-to-analog conversion section to be reduced.

[0024] Second embodiment The second embodiment will be described with reference to Figures 4(a) and 4(b). Descriptions of the same parts as in the first embodiment will be omitted.

[0025] In this embodiment, the column decoder 3022 is m Each of the unit selection circuits 3024C has a switch SW, a selection means SEL1C, and a 1-bit subDAC 3026. mTwo voltages, which are one corresponding voltage group, out of the reference voltages Vref are input. Then, one of them is output to one end of the signal terminal of the switch SW depending on the value of the least significant bit of the image data 3023. The second selection means SEL2C receives a signal of a bit other than the least significant bit of the image data 3023, and outputs a signal 3023C for controlling the unit selection circuit 3024C. A part of the signals 3023C output from the multiple groups Gr1 to 3 is input to each of the multiple selection means SEL1C. Each of the multiple selection means SEL1C controls the conduction / non-conduction of the corresponding switch SW.

[0026] In this embodiment, by providing the subDAC3026, the number of unit selection circuits 3024C per column can be reduced to 1 / 2 compared to the first embodiment. In addition, by providing the second selection means SEL2C, the number of switches of the first selection means SEL1C can be reduced. This allows the circuit area of ​​the column DAC circuit 302 to be reduced.

[0027] Third embodiment This embodiment will be described with reference to Figures 5(a) and 5(b). Descriptions of the same parts as in the second embodiment will be omitted.

[0028] In this embodiment, the column-by-column decoder 3022 m The unit selection circuit 3024D has 1 / 4 unit selection circuits 3024D and a second selection means SEL2D. Each unit selection circuit 3024D has a switch SW, a selection means SEL1D, and a 2-bit subDAC 3026'. The second selection means SEL2C receives bits other than the lowest 2 bits of the image data 3023, and outputs a signal 3023D for controlling the unit selection circuit 3024D. Each of the multiple selection means SEL1D receives the signal 3023D and controls the conduction / non-conduction of the corresponding switch SW. The subDAC 3026' has 2 mFour of the reference voltages Vref corresponding to each column are input, and one of them is output to one end of the signal terminal of the switch SW. Also, a third selection means SEL2D' is further provided for each column. The third selection means SEL2D' receives the lower two bits of the image data 3023 and outputs a signal 3023D' for controlling a plurality of subDACs 3026'.

[0029] In this embodiment, by making the subDAC 3026' 2 bits, the number of unit selection circuits 3024D per column can be reduced to 1 / 4 of that in the first embodiment. In addition, by having the second selection means SEL2D', the number of switches in the first selection means SEL1D can be reduced. This allows the circuit area of ​​the column DAC circuit 302 to be reduced.

[0030] (Fourth embodiment) This embodiment will be described with reference to FIG. 6(a) and FIG. 6(b). In this embodiment, the column decoder 3022 has two m Each of the unit selection circuits 3024E includes a switch SW, a dummy switch DSW provided at each of two signal terminals of the switch SW, and a selection means SEL1E. The dummy switch DSW has two signal terminals shorted, and a signal in phase opposite to that of the switch SW is input to the control terminal.

[0031] In this embodiment, the switch SW and the dummy switch DSW are formed of, for example, MOS transistors. In addition, since signals of opposite phases are input to the control terminals of the switch SW and the dummy switch DSW, the switching noise generated by the switch SW and the switching noise generated by the dummy switch DSW are also opposite phases. In other words, the switching noises cancel each other out, and the apparent amount of noise can be reduced. For this reason, this is more preferable in terms of the linearity of the column DAC circuit 302.

[0032] It is preferable to design the dummy switch DSW so that it emits the same amount of noise as the switching noise emitted by the switch SW toward each signal terminal. For example, if the total amount of switching noise emitted by the switch SW is 1 and 0.5 is output to each of the two signal terminals, each of the two dummy switches DSW is designed so that the total amount of switching noise it emits is 0.5. This makes it possible to reduce the apparent amount of noise.

[0033] Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to these embodiments, and the above-described embodiments can be modified and combined as appropriate without departing from the gist of the present invention.

[0034] The display device 10 as described above can be incorporated into various electronic devices. Examples of such electronic devices include cameras, computers, mobile terminals, and in-vehicle display devices. The electronic devices can include, for example, the display device 10 and a control unit that controls the driving of the display device 10.

[0035] Here, an embodiment in which the above-mentioned display device 10 is applied to a display unit of a digital camera will be described with reference to Fig. 7. Lens unit 901 is an imaging optical system that forms an optical image of a subject on image sensor 905, and includes a focus lens, a variable magnification lens, an aperture, etc. Drive of the focus lens position, variable magnification lens position, aperture aperture diameter, etc. in lens unit 901 is controlled by control unit 909 via lens driving device 902.

[0036] A mechanical shutter 903 is disposed between the lens unit 901 and the image sensor 905, and its drive is controlled by a control unit 909 via a shutter driving device 904. The image sensor 905 converts an optical image formed by a plurality of pixels at the lens unit 901 into an image signal. A signal processing unit 906 performs A / D conversion, demosaic processing, white balance adjustment processing, encoding processing, etc. on the image signal output from the image sensor 905.

[0037] A timing generation unit 907 outputs various timing signals to the image sensor 905 and the signal processing unit 906. The control unit 909 has, for example, a memory (ROM, RAM) and a microprocessor (CPU), and realizes various functions of the digital camera by loading a program stored in the ROM into the RAM and having the CPU execute the program to control each unit. The functions realized by the control unit 909 include auto focus detection (AF) and automatic exposure control (AE).

[0038] The memory unit 908 is used by the control unit 909 and the signal processing unit 906 to temporarily store image signals and as a working area. The medium I / F unit 910 is an interface for reading and writing to a recording medium 911, which is, for example, a removable memory card. The display unit 912 displays captured images and various information about the digital camera. The display unit 10 described above can be used for the display unit 912. The display unit 10 mounted on the digital camera as the display unit 912 is driven by the control unit 909 and displays images and various information. The operation unit 913 is a user interface, such as a power switch, release button, menu button, etc., for the user to give instructions and settings to the digital camera.

[0039] Next, the operation of the digital camera during shooting will be described. When the power is turned on, the camera enters a shooting standby state. The control unit 909 starts a display process for displaying images and various information on the display unit 912 (display device 10). When a shooting preparation command (e.g., half-pressing the release button of the operation unit 913) is input in the shooting standby state, the control unit 909 starts a focus detection process.

[0040] Then, the control unit 909 determines the amount and direction of movement of the focus lens of the lens unit 901 from the obtained defocus amount and direction, and drives the focus lens via the lens driving device 902 to adjust the focus of the imaging optical system. After driving, focus detection based on the contrast evaluation value may be further performed as necessary to fine-tune the focus lens position.

[0041] Thereafter, when an instruction to start shooting (for example, pressing the release button all the way down) is input, the control unit 909 executes a shooting operation for recording, and the obtained image signal is processed by the signal processing unit 906 and stored in the memory unit 908. The control unit 909 then records the image signal stored in the memory unit 908 in a recording medium 911 via a medium control I / F unit 910. At this time, the control unit 909 may also drive a display unit 912 (display device 10) to display the shot image. The control unit 909 may also output the image signal from an external I / F unit (not shown) to an external device such as a computer. [Explanation of symbols]

[0042] 300 Signal output circuit 302 Column DAC circuit (digital-to-analog conversion section) 310 Signal Line 3100 Transmission Line

Claims

1. a decoder to which a multi-bit digital signal is input; A voltage output unit that outputs a plurality of voltages having different values; an output line provided corresponding to the decoder, The decoder comprises: a first arithmetic circuit to which the digital signal is input and to which two or more bits are input, and a selection section to which a logical operation result of the first arithmetic circuit is input, The selection unit is a voltage selection unit to which the voltage of the voltage output unit is input; a switch that connects the output line and the voltage selection unit; a selection means for receiving the logical operation result of the first operation circuit and controlling the switch; 2. A digital-to-analog conversion circuit, wherein the selection means controls the switch based on a logical operation result of the first arithmetic circuit.

2. The decoder further comprises a second arithmetic circuit; 2. The digital-to-analog conversion circuit according to claim 1, wherein the voltage selection section outputs a voltage based on a result of the calculation by the second calculation circuit.

3. 3. The digital-to-analog conversion circuit according to claim 2, wherein the voltage selection section has a plurality of third switches, and the plurality of third switches are controlled by a logical operation result of the second operation circuit.

4. a level conversion circuit between the first arithmetic circuit and the plurality of selection units; 4. The digital-to-analog converter circuit according to claim 1, wherein the level conversion circuit increases the amplitude of the first signal output by the first arithmetic circuit.

5. 5. The digital-to-analog converter circuit according to claim 4, wherein the level converter circuit does not convert a second signal different from the first signal output by the first arithmetic circuit.

6. 6. The digital-to-analog conversion circuit according to claim 5, wherein the first signal is a Hi signal and the second signal is a Lo signal.

7. the selection unit further includes a first dummy switch, 7. The digital-to-analog converter circuit according to claim 1, wherein the first dummy switch is electrically connected between the switch and the voltage output section.

8. The selection unit further includes a second dummy switch, 8. The digital-to-analog converter circuit according to claim 1, wherein the second dummy switch is electrically connected between the switch and the output line.

9. The multi-bit digital signal is divided into a plurality of groups; a plurality of transmission lines for transmitting the logical operation results of the first operation circuit; 9. The digital-to-analog conversion circuit according to claim 1, wherein the plurality of transmission lines are provided such that a plurality of transmission lines correspond to each of the plurality of groups.

10. 10. The digital-to-analog conversion circuit according to claim 9, wherein one of the plurality of transmission lines corresponding to one of the plurality of groups is connected to one of the plurality of selection sections, and the other one is connected to another one of the plurality of selection sections.

11. A digital-to-analog conversion circuit according to any one of claims 1 to 10; A plurality of pixels arranged across a plurality of rows and a plurality of columns; A display device comprising a plurality of the decoders, each of which corresponds to one of the columns.

12. 12. The display device according to claim 11, wherein each of the plurality of pixels has a light emitting diode that emits light with an amount of light corresponding to an analog signal input to the pixel.

13. A display device according to claim 11 or 12, A control unit that controls driving of the display device; Electronic equipment, including

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