Butt joint flex circuit board interconnects and methods of manufacture thereof

Abstract

An interconnect for connecting flex circuit boards in classical and / or quantum computing systems may include a first flex circuit board having a removed portion exposing one or more signal lines and a second flex circuit board having a removed portion exposing one or more other signal lines. The flex circuit boards may be aligned at the removed portion to form signal trace gaps near the exposed signal lines. The exposed signal lines of the first flex circuit board may be bonded to the exposed signal lines of the second flex circuit board. A ground support layer may be bonded to the first flex circuit board and the second flex circuit board along the same side. An insulating plate at least partially covering the signal trace gaps may be bonded to the first flex circuit board and / or the second flex circuit board on the opposite side of the ground support layer.

Description

[Technical field]

[0001] Claiming priority This application claims the benefit of priority to U.S. Provisional Application No. 63 / 079,267, filed September 16, 2020, and entitled “Butt Joint Flex Circuit Board Mating,” which is incorporated herein by reference.

[0002] The present disclosure relates generally to interconnects that can be used, for example, in classical and quantum computing systems. [Background technology]

[0003] Quantum computing is a computational method that exploits quantum effects such as superposition of basis states and entanglement to perform certain calculations more efficiently than classical digital computers. In contrast to digital computers, which store and manipulate information in the form of bits such as "1" or "0", quantum computing systems can manipulate information using quantum bits ("qubits"). A qubit can refer to a quantum device that allows for the superposition of multiple states, e.g., data in both "0" and "1" states, and / or the superposition of data itself in multiple states. According to conventional terminology, the superposition of "0" and "1" states in a quantum system can be represented, for example, as a|0〉+b|1〉. The "0" and "1" states of a digital computer are analogous to the |0〉 and |1〉 basis states of a qubit, respectively. Summary of the Invention [Means for solving the problem]

[0004] Aspects and advantages of embodiments of the disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned by practice of the embodiments.

[0005] One exemplary embodiment of the present disclosure is directed to an interconnect for connecting multiple flex circuit boards. The interconnect comprises a first flex circuit board including a first ground plane, a first dielectric layer, a first set of one or more signal lines, a second dielectric layer, and a second ground plane, the first flex circuit board having a removed portion exposing at least one signal line in the first set of one or more signal lines. The interconnect also comprises a second flex circuit board including a third ground plane, a third dielectric layer, a second set of one or more signal lines, a fourth dielectric layer, and a fourth ground plane, the second flex circuit board having a removed portion exposing at least one signal line in the second set of one or more signal lines. The removed portion of the first flex circuit board and the removed portion of the second flex circuit board are aligned to form a signal trace gap. A solder bridge is coupled to at least one signal line in the first set of one or more signal lines and at least one signal line in the second set of one or more signal lines in the signal trace gap. An insulating plate is coupled to at least one of the first ground plane of the first flex circuit board and the third ground plane of the second flex circuit board, at least partially covering the signal trace gap.

[0006] These and other features, aspects, and advantages of various embodiments of the present disclosure will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the relevant principles.

[0007] A detailed discussion of the embodiments, directed to those skilled in the art, is set forth in the specification, which refers to the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates an exemplary flex circuit board interconnect according to an example of the present disclosure. [Diagram 2]FIG. 1 illustrates a top view scan of an exemplary flex circuit board interconnect according to an example of the present disclosure. [Diagram 3] FIG. 2 illustrates a flow diagram of an exemplary method for generating interconnects according to an example of the present disclosure. [Figure 4] FIG. 1 illustrates a block diagram of an exemplary quantum computing system according to examples of the present disclosure. [Diagram 5] FIG. 1 illustrates an exemplary quantum computing system according to an example of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Exemplary aspects of the present disclosure are directed to making and using specialized butt joint interconnects capable of connecting various types of circuit boards, including, but not limited to, flexible and semi-flexible circuit boards used in conventional computing systems, quantum computing systems, and other types of electronic devices (such as automobiles, aircraft, satellites, medical equipment, smartphones, wearable devices, etc.). A circuit board generally refers to a material with printed circuits or integrated circuits used to connect electronic components and devices. A flex circuit board may include a circuit board that provides, in whole or in part, at least some structural flexibility.

[0010] Flex circuits may be used in a variety of electronic devices, for example, where flexibility and space savings are difficult or impossible to achieve with rigid circuit boards. Although flex circuits offer advantages over rigid circuit boards, connecting flex circuits can be problematic. For example, the inherent flexibility of flex circuits increases the risk of damage from movement and loss of structural support during handling and use. Furthermore, repairing or replacing a damaged flex circuit board can be inconvenient and costly. Thus, the present disclosure describes new and improved methods of making and using butt joints to interconnect flex circuit boards.

[0011] According to an exemplary aspect of the present disclosure, a butt joint interconnect for interconnecting multiple circuit boards, such as flex circuit boards, may include a first flex circuit board having a removed portion exposing one or more signal lines and a second flex circuit board having a removed portion exposing one or more signal lines. The flex circuit boards may be aligned with the exposed signal lines at an edge of the removed portion, forming a signal trace gap between the flex circuit boards. A ground support layer may extend at least partially across one side of the aligned flex circuit boards. A solder bridge may be used to connect the exposed signal lines of the aligned flex circuit boards. Additionally, an insulating plate may cover the trace signal gap formed by the removed portion of the aligned flex circuit boards on the opposite side of the ground support layer over the solder bridge. In some examples, one or more of the ground planes may include a superconducting material that exhibits superconductivity at a temperature of less than about 3 Kelvin, such as less than about 1 Kelvin, such as less than about 20 milliKelvin.

[0012] Exemplary aspects of the present disclosure are directed to methods of manufacturing wiring structures for interconnecting various types of circuit boards, for example in computing systems, quantum computing systems, and various types of electronic devices (such as automobiles, aircraft, satellites, medical devices, smartphones, wearable devices, etc.). The method may include, for example, obtaining a first circuit board and removing a portion of the first circuit board exposing at least one signal line of the first circuit board, obtaining a second circuit board and removing a portion of the second circuit board exposing at least one signal line of the second circuit board, aligning a side of the removed portion of the first circuit board with a side of the removed portion of the second circuit board to form a signal trace gap between the flex circuit boards near the exposed signal line of each board, bonding a ground support layer at least partially across one side of each of the aligned circuit boards, connecting the exposed signal lines of the aligned circuit boards using a solder bridge or another type of connecting material, and bonding an insulating plate to the circuit boards on the opposite side of the ground support layer covering the trace signal gap and the connected signal line. Additionally, the one or more ground planes may include a superconducting material that exhibits superconductivity at a temperature of less than about 3 Kelvin, such as less than about 1 Kelvin, such as less than about 20 milliKelvin. Such superconducting ground planes may be used, for example, in superconducting quantum computing systems that operate significantly faster than classical computing systems.

[0013] Aspects of the present disclosure provide many technical effects and advantages. For example, various examples of interconnects described in this disclosure provide reinforcement and increased durability when interconnecting flex circuit boards that may flex, bend, or twist to conform to a final assembly. For example, the flex circuit board interconnects described herein protect against and reduce the likelihood of damage during installation, deployment, use, and maintenance of various types of conventional computing systems, quantum computing systems, consumer devices, industrial equipment, aerospace equipment, and the like. Thus, these new and improved flex circuit board interconnects provide increased reliability and resiliency compared to conventional interconnects, thereby reducing damage, repairs, replacements, downtime, and costs associated with various types of systems, devices, and equipment that rely on flex circuit boards.

[0014] As used herein, a "flex circuit board" refers to a substrate that includes at least one substantially planar substrate (e.g., a layered substrate) or other support on which one or more signal lines are formed or otherwise disposed and that is flexible in at least one plane. Flexibility refers to the ability to deform without breaking. For example, a rectangular flex circuit board may be flexible along the largest surface of the rectangular flex circuit board. A rectangular flex circuit board may be flexible and / or rigid along at least a portion of its edges. Flexibility may be achieved as a property of the material from which the flex circuit board and / or layers of the flex circuit board are formed (e.g., metals such as copper, copper alloys, niobium, aluminum, dielectric materials, non-metals, polymers, rubbers, etc.), by hinges and / or segmentation of the flex circuit board (e.g., hinges and / or segmentation of rigid portions), and / or in any other suitable manner. The substrate may be strictly planar (e.g., having a substantially linear cross-section across its length and width) and / or may be approximately planar in the sense that in at least one cross-section the substrate is curved, wrinkled, or otherwise non-linear, but overall represents a shape having a depth that is significantly less (e.g., less than about 10%) than its length and width.

[0015] As used herein, the terms "about" or "approximately" when used in conjunction with a stated numerical value are intended to refer to within 10% of the stated numerical value.

[0016] Exemplary embodiments of the present disclosure will now be discussed in more detail with reference to the drawings. Aspects of the present disclosure will be discussed with reference to flex circuit board interconnects in quantum computing systems for purposes of illustration and discussion. Those skilled in the art will appreciate, using the disclosure provided herein, that the interconnects may be used in other applications without departing from the scope of the present disclosure.

[0017] 1 illustrates a diagram of an exemplary flex circuit butt joint according to an exemplary embodiment of the present disclosure. In the example, flex circuit butt joint 100 includes a first flex circuit board 102, a second flex circuit board 106, a ground support layer 140, a solder connection 150, a solder bridge 160, an insulating plate 170, a solder connection 180, and a solder connection 182.

[0018] The first flex circuit board 102 includes a removed portion 104, a ground plane 120, a dielectric layer 122, a signal line 124, a dielectric layer 126, and a ground plane 128. In one example, the removed portion 104 of the first flex circuit board 102 exposes some or all of the signal line 124. In some examples, the removed portion 104 is a pocket etched or otherwise created in an edge or side of the first flex circuit board 102 that exposes the signal line 124 for butt-connecting with a signal line of another board (e.g., an exposed signal line 134 of the second flex circuit board 106).

[0019] The second flex circuit board 106 includes a removed portion 108, a ground plane 130, a dielectric layer 132, a signal line 134, a dielectric layer 136, and a ground plane 138. In one example, the removed portion 108 of the first flex circuit board 102 exposes some or all of the signal line 134. In some examples, the removed portion 108 is a pocket etched or otherwise created in an edge or side of the second flex circuit board 106 that exposes the signal line 134, for example, to butt-connect with a signal line 124 of the first flex circuit board 102 or another board.

[0020] In one example, the first flex circuit board 102 and the second flex circuit board 106 are aligned such that the removed portion 104 of the first flex circuit board 102 and the removed portion 108 of the second flex circuit board 106 face or oppose one another. For example, the first flex circuit board 102 and the second flex circuit board 106 can be substantially aligned such that the removed portion 104 and the removed portion 108 form a signal trace gap 110.

[0021] In one example, signal trace gap 110 generally represents an area of ​​physical space where signal line 124 is exposed relative to removed portion 104 of first flex circuit board 102 and signal line 134 is exposed relative to removed portion 108 of second flex circuit board 106. Thus, signal trace gap 110 may generally be an area formed when removed portion 104 of first flex circuit board 102 and removed portion 108 of second flex circuit board 106 are positioned in relative proximity to one another.

[0022] In one example, a side or edge of the first flex circuit board 102 corresponding to the removed portion 104 is aligned proximate to a side or edge of the second flex circuit board 106 corresponding to the removed portion 108. In some examples, the removed portion 104 of the first flex circuit board 102 and the removed portion 108 of the second flex circuit board 106 can be positioned such that the first flex circuit board 102 and the second flex circuit board 106 are in contact or in contact with each other near the signal trace gap 110. In some examples, the first flex circuit board 102 and the second flex circuit board 106 may not be in contact or may alternatively remain relatively or proximate to each other. In some examples, one or more exposed signal lines 124 contact or are in contact with one or more exposed signal lines 134 near the signal trace gap 110, for example, when the first flex circuit board 102 and the second flex circuit board 106 are in contact or in contact.

[0023] In one example, the solder bridge 160 connects one or more exposed signal lines 124 to one or more exposed signal lines 134 near the signal trace gap 110. For example, the solder bridge 160 can connect the exposed signal lines 124, either in contact or not in contact with the exposed signal lines 134, either when the first flex circuit board 102 and the second flex circuit board 106 are in contact or not in contact. The solder bridge 160 can generally be any type of connecting substance or layer, such as, for example, a solder bridge, or a connecting material that joins different objects or elements together.

[0024] In one example, the solder bridge 160 includes one or more conductive materials that allow currents, pulses, signals, and / or other types of communication to pass across or through the signal line 124 and the signal line 134, and vice versa. In some examples, the solder bridge 160 may be comprised of one or more conductive metals, including but not limited to silver, copper, gold, aluminum, and the like. In some examples, the solder bridge 160 may be comprised of one or more superconducting materials that become superconducting under certain conditions, such as, for example, at temperatures less than about 3 Kelvin, such as less than about 1 Kelvin, such as less than about 20 milliKelvin. In some examples, the solder bridge 160 may include one or more conductive adhesives, for example, in addition to or instead of a solder material. The conductive adhesive may generally include a conductive adhesive, paste, or glue. Such a conductive adhesive may include one or more conductive materials and / or one or more materials that become superconducting under certain conditions.

[0025] The ground support layer 140 is coupled to the ground plane 128 of the first flex circuit board 102 and the ground plane 138 of the second flex circuit board 106 via solder connections 150. In one example, the ground support layer 140 extends at least partially across the first flex circuit board 102 and at least partially across the second flex circuit board 106. The ground support layer 140 may be coupled to an exterior portion of the first flex circuit board 102 and an exterior portion of the second flex circuit board 106, for example, to couple and support adjacent flex circuit boards. In one example, the solder connections 150 may be one or more solder or adhesive connections coupling the ground support layer 140 to the first flex circuit board 102 and the second flex circuit board 106.

[0026] The insulating plate 170 is coupled to the ground plane 120 of the first flex circuit board 102 via solder connections 180 and is coupled to the ground plane 130 of the second flex circuit board 106 via solder connections 182. In one example, the insulating plate 170 extends at least partially across the first flex circuit board 102 and at least partially across the second flex circuit board 106, covering the signal trace gap 110 on the opposite side of the ground support layer 140. In some examples, the insulating plate 170 covers the signal trace gap 110, the signal line 124 near the removed portion 104 of the first flex circuit board 102, the solder bridge 160 (if present), and the signal line 134 near the removed portion 108 of the second flex circuit board 106. In some examples, the insulating plate 170 can be coupled to one or both of the first flex circuit board 102 and / or the second flex circuit board 106. The flex circuit butt joint 100 may also include an insulating plate 170 with or without the use of a ground support layer 140 .

[0027] In one example, the flex circuit butt joint 100 may be configured without the ground support layer 140 and the insulating plate 170, with at least one of the ground support layer 140 or the insulating plate 170, or with both the ground support layer 140 and the insulating plate 170, for example. In some examples, one or more of the ground support layer 140 and / or the insulating plate 170 may be constructed of copper. In some examples, the insulating plate 170 may have one or more holes cut before, during, and / or after circuit board bonding, for example to provide access to the signal lines 124, 134 near the signal trace gap 110.

[0028] In some examples, the flex circuit butt joint 100 is used to join two separate flex circuit boards together. In some examples, the flex circuit butt joint 100 can join one flex circuit board with another type of circuit board, such as a rigid circuit board. Additionally, examples of the present disclosure can be used to join any two separate flexible or rigid circuit boards together. Various examples of the flex circuit butt joint 100 can be used to connect different flex and other types of circuit boards used in and / or in conjunction with quantum computing systems, classical computing systems, such as interconnects used to couple and operate quantum and classical computing systems. In various examples, any number of flex circuit boards and / or other types of boards can each be joined or coupled in series one after the other using, for example, multiple different flex circuit butt joint 100 interconnects. For example, the second flex circuit board 106 may be joined to a third circuit board (not shown) via a flex circuit butt joint which may be joined to a fourth circuit board (not shown) via another flex circuit butt joint, etc.

[0029] FIG. 2 depicts a diagram showing a top scan of an exemplary flex circuit butt joint according to an example of the present disclosure.

[0030] As an example, a top view 200 of an exemplary flex circuit butt joint includes a first flex circuit board 102, a second flex circuit board 106, an insulating plate 170, and an oval shaped cavity 210 representing an island of solder (e.g., solder bridge 160) connecting signal traces (e.g., signal line 124 of the first flex circuit board 102 and signal line 134 of the second flex circuit board 106). The insulating plate 170 is coupled to the first flex circuit board 102 via solder connections 220 and is also coupled to the second flex circuit board 106 via solder connections 222.

[0031] 3 illustrates a flow diagram of an exemplary method for generating a wiring structure for a quantum computing system according to an example of the present disclosure. While FIG. 3 illustrates, by way of example, steps performed in a particular order for purposes of illustration and discussion, the method of the present disclosure is not limited to the order or arrangement specifically depicted. Thus, various steps of method 300 may be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present disclosure.

[0032] At 302, a first flex circuit board 102 is obtained. For example, the first flex circuit board 102 may each include a first ground plane 120, a first dielectric layer 122, one or more signal lines 124, a second dielectric layer 126, and a second ground plane 128. In some examples, one or more of the ground planes 120 and / or 128 may be composed of a conductive material. For example, one or more of the ground planes 120 and / or 128 may include a superconducting material that is superconducting under certain conditions, such as a temperature of less than about 1 Kelvin, such as less than about 20 milliKelvin, or less than about 3 Kelvin.

[0033] In one example, the first flex circuit board 102 is obtained in an original or unaltered state with neither the removed portion 104 nor the signal lines 124 exposed. The first flex circuit board 102 may also be obtained with some type of removed portion 104 that may or may not expose the signal lines 124. In some examples, the first flex circuit board 102 may also be cleaned to improve solder adhesion.

[0034] At 304, a second flex circuit board 106 is obtained. For example, the second flex circuit board 106 may each include a first ground plane 130, a first dielectric layer 132, one or more signal lines 134, a second dielectric layer 136, and a second ground plane 138. In some examples, one or more of the ground planes 130 and / or 138 may be composed of a conductive material. For example, one or more of the ground planes 130 and / or 138 may include a superconducting material that is superconducting under certain conditions, such as a temperature of less than about 3 Kelvin, such as less than about 1 Kelvin, such as less than about 20 milliKelvin.

[0035] In one example, the second flex circuit board 106 is obtained in an original or unaltered state with no portions 108 removed and no signal lines 134 exposed. The second flex circuit board 106 may also be obtained with some type of removed portions 108 that may or may not expose signal lines 134. In some examples, the second flex circuit board 106 may also be cleaned to improve solder adhesion.

[0036] At 306, a portion of the first flex circuit board 102 is removed to expose one or more signal lines 124 at the removed portion 104 of the first flex circuit board 102. In one example, a portion of the first flex circuit board 102 is removed to create the removed portion 104 and expose the one or more signal lines 124. In some examples, a portion of the first flex circuit board 102 may be removed to enlarge or modify an existing removed portion (e.g., a partially removed portion), for example, to adjust the size of the removed portion 104 and / or to expose or further expose the signal lines 124. In one example, ablation or any other type of vaporization, erosion, or physical removal process may be used to create or modify the removed portion 104 of the first flex circuit board 102.

[0037] At 308, a portion of the second flex circuit board 106 is removed to expose one or more signal lines 134 at the removed portion 108 of the second flex circuit board 106. In one example, a portion of the second flex circuit board 106 is removed to create the removed portion 108 and expose the one or more signal lines 134. In some examples, a portion of the second flex circuit board 106 may be removed to enlarge or modify an existing removed portion (e.g., a partially removed portion), e.g., to adjust the size of the removed portion 108 and / or to expose or further expose the signal lines 134. In one example, ablation or any other type of vaporization, erosion, or physical removal process may be used to create or modify the removed portion 108 of the second flex circuit board 106.

[0038] In one example, ablation can be performed to create or modify the removed portion 104 of the first flex circuit board 102 and / or the removed portion 108 of the second flex circuit board 106. For example, ablation can be performed to remove material from the first flex circuit board 102 to create or enlarge the removed portion 104 and / or expose the signal line 124. Similarly, ablation can be performed to remove material from the second flex circuit board 106 to create or enlarge the removed portion 108 and / or expose the signal line 134. In general, ablation can be performed using a laser, a chemical, heat, physical removal (e.g., chipping, cutting, etc.), and / or any other type of removal process. Also, in general, material can be removed using one or more other types of removal processes.

[0039] In some examples, ablation (e.g., by a laser) is used to cut cavities in the top ground plane layer (e.g., ground plane 120) and top dielectric layer (e.g., dielectric layer 122) of the first flex circuit board to expose the signal line 124, and / or in the top ground plane layer (e.g., ground plane 130) and top dielectric layer (e.g., dielectric layer 132) of the second flex circuit board 106 to expose the signal line 134. In some examples, the dielectric layer or layers may be comprised of Kapton or other materials. In some examples, one or more of 306 and / or 308 may not be performed, for example, if the respective flex circuit boards already include removed portions that expose one or more signal lines.

[0040] At 310, the removed portion 104 of the first flex circuit board 102 and the removed portion 108 of the second flex circuit board 106 are aligned to form a signal trace gap 110. In one example, a side or edge of the first flex circuit board 102 corresponding to the removed portion 104 is aligned with a side or edge of the second flex circuit board 106 corresponding to the removed portion 108 such that the removed portions 104 and 108 face each other from opposite sides, e.g., symmetrically or substantially symmetrically. In some examples, a heated assembly jig may be used, for example, to align the first flex circuit board 102 with the second flex circuit board 106 and perform various steps of assembling the flex circuit butt joint 100.

[0041] In some examples, the first flex circuit board 102 and the second flex circuit board 106 are laterally aligned based on the alignment that forms the signal trace gap 110 and mate or butt each other near the removed portion 104 of the first flex circuit board 102 and the removed portion 108 of the second flex circuit board 106. In some examples, the exposed signal line 124 of the first flex circuit board 102 near the removed portion 104 contacts or is in contact with the exposed signal line 134 of the second flex circuit board 106 near the removed portion 108. In some examples, there may be an amount of space between the first flex circuit board 102 and the second flex circuit board 106 and / or the exposed signal line 124 near the removed portion 104 and the exposed signal line 134 near the removed portion 108.

[0042] At 312, a ground support layer 140 extending at least partially across the first flex circuit board 102 and at least partially across the second flex circuit board 106 is coupled to one side of the first flex circuit board 102 and also to one side of the second flex circuit board 106. In one example, the ground support layer 140 extends across one side of the first flex circuit board 102 and is coupled to an outer layer of the first flex circuit board 102, such as the ground plane 128. Continuing with this example, the ground support layer 140 further extends across one side of the second flex circuit board 106 and is coupled to an outer layer of the second flex circuit board 106, such as the ground plane 138. For example, the ground support layer 140 may be coupled to each of the first flex circuit board 102 and the second flex circuit board 106 when the flex circuit boards are aligned to form the signal trace gap 110. In one example, the ground support layer 140 is bonded to each of the first flex circuit board 102 and the second flex circuit board 106, and both flex circuit boards are stably held in a fixed or stable alignment, for example, via a heated or unheated assembly jig or other similar device.

[0043] In one example, the ground support layer 140 is coupled to each of the first flex circuit board 102 and the second flex circuit board 106 via a solder connection 150 on the opposite side of the signal trace gap 110. For example, the ground support layer 140 may be generally arranged to provide one or more of a ground connection and / or mechanical support for the first flex circuit board 102 and the second flex circuit board 106. In one example, the solder connection 150 may be one or more portions of solder and / or adhesive material that joins the ground support layer 140 to the first flex circuit board 102 and the second flex circuit board 106. In some examples, the flex circuit butt joint 100 may include the ground support layer 140 and an insulating plate 170. In some examples, the flex circuit butt joint 100 may include the ground support layer 140 without the use of an insulating plate 170.

[0044] At 314, at least one signal wire in the first set of one or more signal wires 124 and at least one signal wire in the second set of one or more signal wires 134 are coupled via a solder bridge 160 at the signal trace gap 110. In one example, the signal wire 124 may be exposed when the removed portion 104 is created by removing a portion of the first flex circuit board 102, and / or the signal wire 134 may be exposed when the removed portion 108 is created by removing a portion of the second flex circuit board 106. In one example, the solder bridge 160 connects the exposed signal wire 124 to the exposed signal wire 134 near the signal trace gap 110. In one example, the solder bridge 160 connects the exposed signal wire 124 and the signal wire 134. The solder bridge 160 does not contact the exposed signal wire 134 and can also connect the exposed signal wire 124 that is not contacting.

[0045] In one example, solder bridge 160 provides a connection across exposed signal wire 124 and exposed signal wire 134. For example, solder bridge 160 may be comprised of one or more conductive metals and / or superconducting materials that become superconducting under certain conditions (e.g., temperatures below about 1 Kelvin). In some examples, solder bridge 160 may generally include one or more conductive and / or superconducting adhesives, e.g., in addition to or in lieu of solder materials. Such conductive and / or superconducting adhesives may generally include conductive and / or superconducting glues, pastes, adhesives, and the like.

[0046] At 316, an insulating plate 170 at least partially covering the signal trace gap 110 is coupled to at least one of the first flex circuit board 102 and the second flex circuit board 106. In one example, the insulating plate 170 may extend partially or completely across the signal trace gap 110. For example, the insulating plate 170 may generally cover and protect the signal lines 124, 134, and the solder bridges 160 near the signal trace gap 110. In one example, the insulating plate 170 is coupled to the first flex circuit board 102 via solder connections 180 and / or to the second flex circuit board 106 via solder connections 182.

[0047] In various examples, the flex circuit butt joint 100 may include an insulating plate 170 with or without a ground support layer 140. In examples where the flex circuit butt joint 100 includes both an insulating plate 170 and a ground support layer 140, the insulating plate 170 and the ground support layer 140 are disposed on opposing sides. In some examples, for example, after initial assembly of one or more components of the flex circuit butt joint 100, a thermal reflow is performed on one or more solder connections and / or bridges. Additionally, heated components are generally allowed to cool prior to testing.

[0048] 4 illustrates a block diagram of an exemplary quantum computing system according to an example of the present disclosure. Quantum computing system 400 is an example of a system implemented as a classical or quantum computer program on one or more classical or quantum computing devices at one or more locations where the systems, components, and techniques described in this disclosure may be implemented. Quantum computing system 400 is an example that may be used to implement aspects of the present disclosure. Those skilled in the art will appreciate that other quantum computing structures or systems may be used using the examples provided herein without departing from the scope of the present disclosure.

[0049] Quantum computing system 400 includes quantum hardware 402 in data communication with one or more classical processors 404. For example, quantum hardware 402 may represent and / or manipulate information using qubits. Qubits may be or include any suitable quantum device that allows for a superposition of multiple states, such as data in both "0" and "1" states. By way of example, a qubit may be or include a unit of a superconducting material, such as a superconducting material that achieves superconductivity at a temperature below about 10 millikelvin (mK).

[0050] Quantum hardware 402 may include components for performing quantum computations. For example, quantum hardware 402 may include a quantum system 410, a controller 412, and a readout device 414 (e.g., a readout resonator). Quantum system 410 may include one or more multilevel quantum subsystems, such as a register of qubits. In some implementations, the multilevel quantum subsystems may include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, etc.

[0051] The classical processor 404 may be a binary processor, such as a processor that operates on data represented as a plurality of bits. As an example, a bit may be represented by a voltage difference between a low voltage (e.g., 0V) and a high voltage (e.g., 5V) at a reference point, such as a memory cell, a circuit node, or the like. The low voltage may be associated with a "0" state, and the high voltage may be associated with a "1" state. The classical processor 404 may be configured to control the quantum hardware 402 in addition to any other suitable functions of the classical processor 404. For example, the classical processor 404 may be coupled (e.g., by a signal line) to the quantum hardware 402 and / or configured to send control signals to perform quantum operations using the quantum hardware 402. As an example, the classical processor 404 may be configured (e.g., by a controller 412) to send control signals that implement quantum gate operations in the quantum hardware 402. Additionally and / or alternatively, classical processor 404 can be configured to send control signals (e.g., by a readout device 414, such as a readout resonator) that cause quantum hardware 402 to perform quantum state measurements and / or provide quantum state measurements to classical processor 404. For example, classical processor 404 can receive measurements of quantum system 410 that can be interpreted by classical processor 404.

[0052] There may be a variety of types of multi-level quantum subsystems utilized by quantum computing system 400. For example, in some cases it may be convenient to include one or more readout devices 414 (e.g., readout resonators) attached to one or more superconducting qubits, e.g., transmons, flux, gmons, xmons, or other qubits.

[0053] A quantum circuit can be constructed and applied to a register of qubits included in the quantum system 410 via multiple signal lines (e.g., signal lines 124, 134 in FIG. 1 ) coupled to one or more controllers 412. An exemplary controller 412 operating on the register of qubits can be used to implement a quantum logic gate or a circuit of quantum logic gates, such as a Hadamard gate, a controlled NOT (CNOT) gate, a controlled phase gate, a T-gate, a multi-qubit quantum gate, a coupler quantum gate, etc. The one or more controllers 412 can be configured to operate on the quantum system 410 through one or more respective control parameters (e.g., one or more physical control parameters 406). For example, in some implementations, the multi-level quantum subsystem can be a superconducting qubit, and the controller 412 can be configured to provide control pulses to the control lines (e.g., signal lines 124, 134 in FIG. 1 ) to generate a magnetic field to tune the frequency of the qubit.

[0054] The quantum hardware 402 may further include a readout device 414 (e.g., a readout resonator). Measurement results 408 obtained via the measurement device may be provided to the classical processor 404 for processing and analysis. In some examples, the quantum hardware 402 may include a quantum circuit, and the controller 412 and readout device may implement one or more quantum logic gates that operate on the quantum system 410 via physical control parameters (e.g., microwave pulses) sent via wires included in the quantum hardware 402. Further examples of controllers include arbitrary waveform generators from which DACs create signals.

[0055] The readout device 414 (e.g., a readout resonator) may be configured to perform quantum measurements on the quantum system 410 and send the measurement results 408 to the classical processor 404 (e.g., over signal lines 124, 134 in FIG. 1 ). Additionally, the quantum hardware 402 may be configured to receive data specifying values ​​of the physical control parameters 406 from the classical processor 404 (e.g., over signal lines 124, 134 in FIG. 1 ). The quantum hardware 402 may use the received values ​​of the physical control parameters 406 to update the operation of the controller 412 and the readout device 414 (e.g., a readout resonator) on the quantum system 410. For example, the quantum hardware 402 may receive data specifying new values ​​representing voltage strengths of one or more DACs included in the controller 412 and may update the operation of the DACs on the quantum system 410 accordingly. The classical processor 404 may be configured to initialize the quantum system 410 to an initial quantum state, for example, by sending data specifying an initial set of parameters 406 to the quantum hardware 402.

[0056] The readout device 414 (e.g., readout resonator) can utilize the difference in impedance between the |0〉 and |1〉 states of an element of the quantum system 410, such as a qubit, to measure the state of the element (e.g., a qubit). For example, the resonant frequency of the readout resonator can take different values ​​when the qubit is in state |0〉 or state |1〉 due to the nonlinearity of the qubit. Thus, microwave pulses reflected from the readout device 414 (e.g., readout resonator) carry amplitude and phase shifts that depend on the qubit state. In some examples, a Purcell filter can be used with the readout device 414 (e.g., readout resonator) to prevent microwave propagation at the qubit frequency.

[0057] The quantum computing system 400 includes a controller 412. The controller 412 can operate the quantum hardware 402. For example, the controller 412 can include a waveform generator configured to generate control pulses according to exemplary aspects of the present disclosure.

[0058] In some examples, the controller 412 may include a data processor and associated memory. The memory may include a computer program having instructions that, when executed by the data processor, cause the data processor to perform one or more operations, such as applying control signals to the qubits and / or tunable couplers.

[0059] The quantum hardware 402, such as, but not limited to, the quantum system 410, the controller 412, the readout device 414, and / or any other suitable components of the quantum hardware 402, may be disposed within a cryogenic cooling system (not shown). Additionally and / or alternatively, the classical processor 404 may be disposed outside of the cryogenic cooling system. For example, the cryogenic cooling system may be configured to cool the quantum hardware 402. Additionally and / or alternatively, the classical processor 404 is not cooled by a cryogenic cooling system. For example, the classical processor 404 may operate at a temperature near room temperature (e.g., about 300 Kelvin) and / or at a temperature of about 100 Kelvin, while the quantum hardware 402 may operate at a temperature near about absolute zero (e.g., less than about 20 milliKelvin) that may require cooling by a cryogenic cooling system to operate effectively.

[0060] The quantum computing system 400 may include signal lines (not shown). The signal lines may couple the classical processor 404 to the quantum hardware 402. For example, the classical processor 404 and the quantum hardware 402 may engage in signal communication, such as transmitting parameters 406 and / or measurement results 408 and / or any other suitable signals, such that the classical processor 404 may be coupled to the quantum hardware 402 by signal lines. For example, the signal lines may be or include any suitable physical communication coupling (e.g., one or more wires) configured to couple the quantum hardware 402 and the classical processor 404. In general, the signal lines may include physical connections to enable faster and / or more robust communication between the quantum hardware 402 and the classical processor 404. Additionally, the signal lines may be at least partially disposed within a cryogenic cooling system, for example, to provide coupling to the quantum hardware 402.

[0061] FIG. 5 illustrates an exemplary quantum computing system according to examples of the present disclosure. The quantum computing system 500 may include one or more classical processors 502 and quantum hardware 504 including one or more qubits. The quantum computing system 500 may include a chamber mount 508 configured to support the quantum hardware 504 and a vacuum chamber configured to receive the chamber mount 508 and place the quantum hardware 504 in a vacuum. The vacuum chamber can form a cooling gradient from an end of the vacuum chamber (e.g., cap 507) to the quantum hardware 504. For example, the vacuum chamber can form a cooling gradient from a first temperature, such as room temperature (e.g., about 300 Kelvin), to a second temperature, such as absolute zero or near absolute zero (e.g., about 10 milliKelvin), such as providing the quantum hardware 504 with a temperature at which the qubits experience superconductivity. In some embodiments, the cooling gradient can be formed by multiple cooling stages in which the temperature is gradually increased and / or decreased. As an example, the cooling stages can be stages of a stepwise cryogenic cooling system, such as a dilution refrigerator.

[0062] The quantum computing system 500 can include one or more signal lines between the classical processor 502 and the quantum hardware 504. According to an exemplary embodiment of the present disclosure, the quantum computing system 500 can include one or more flex circuit boards 506 including one or more signal lines. The flex circuit board 506 can be configured to transmit signals by one or more signal lines through a vacuum chamber to couple the one or more classical processors 502 to the quantum hardware 504. The flex circuit board 506 can include multiple signal lines and can provide significantly improved signal line density in addition to providing improved isolation, reduced thermal conductivity, and / or improved scalability. For example, the inclusion of a flex circuit board 506 according to an exemplary embodiment of the present disclosure to couple the classical processor 502 to the quantum hardware 504 can provide an infrastructure to reliably scale to the increasing number of qubits achieved in current quantum computing systems and / or anticipated in future quantum computing systems and / or future quantum computing systems.

[0063] In some embodiments, some or all of the flex circuit boards 506 may include at least one ground layer. The ground layer may form an outer surface of each flex circuit board 506, such as an outer surface along a maximum surface. In some embodiments, each flex circuit board 506 may include two ground layers, such as two parallel, spaced apart ground layers. For example, the two ground layers may form both maximum outer surfaces of each flex circuit board 506. The ground layer functions as an electrical insulation layer to isolate signal lines on one side of the ground layer from interfering signals on the other side of the ground layer (e.g., from signal lines on other layers, other substrates, the environment, etc.). For example, the ground layer may be coupled to ground and / or other suitable ground.

[0064] The ground layer may be or include any suitable electrically conductive material. In some embodiments, the ground layer may be or include a superconducting ground layer including a superconducting material, such as a superconducting material that achieves superconductivity at a temperature below about 1 Kelvin, such as about 0 Kelvin. By way of example, the ground layer may be or include niobium, tin, aluminum, molybdenum disulfide, BSCCO, and / or other suitable superconducting materials. Additionally and / or alternatively, the ground layer may be or include a material having high signal transmission performance characteristics, such as low resistance, low reflectivity, low distortion, such that the signal is not substantially altered by passing through the signal line. By way of example, the ground layer may be or include copper, gold, and / or other suitable materials having high signal transmission performance characteristics. Additionally and / or alternatively, the ground layer may be or include a material having desirable thermal properties, such as suitably high and / or low heat transfer, such as, for example, copper, copper alloys, thin superconducting materials, and the like.

[0065] In some embodiments, each flex circuit board 506 may include at least one dielectric layer. The dielectric layer may be or include any suitable dielectric material, such as a dielectric polymer. In some embodiments, the dielectric layer may be or include a flexible dielectric material. As an example, the dielectric layer may be or include a polyimide. At least a portion of the dielectric layer may be formed on or otherwise disposed proximate to at least a portion of an inner surface of a ground layer. For example, in some embodiments, an inner surface of the ground layer may be combined with an outer surface of the dielectric layer. Additionally, in some embodiments, the inner surfaces of two dielectric layers may be combined with a signal line disposed therebetween.

[0066] Each flex circuit board 506 may include one or more signal lines. The one or more signal lines may be disposed on a surface (e.g., an inner surface) of at least one dielectric layer. As an example, in some embodiments, the one or more signal lines may be disposed between opposing inner surfaces of two dielectric layers. The signal lines may be or include any suitable conductive material. In some embodiments, the signal lines may be or include superconducting signal lines including a superconducting material, such as a superconducting material that achieves superconductivity at a temperature below about 1 Kelvin, such as about 0 Kelvin. By way of example, the signal lines may be or include niobium, tin, aluminum, molybdenum disulfide, BSCCO, and / or other suitable superconducting materials. Additionally and / or alternatively, the signal lines may be or include a material having high signal transmission performance characteristics. By way of example, the signal lines may be or include copper, gold, and / or other suitable materials having high signal transmission performance characteristics. Additionally and / or alternatively, the signal wires may be or include materials having desirable thermal properties, such as, for example, copper, copper alloys, thin superconducting materials, etc.

[0067] In some embodiments, each flex circuit board 506 may include one or more vias. For example, the vias may extend through the ground layers, the dielectric layers, and / or the signal lines. The vias serve to improve isolation of the signal lines. Additionally and / or alternatively, the vias may serve to couple multiple ground layers and / or to transmit signals between layers of the flex circuit board. In some embodiments, the vias may be plated with a via plate that extends along the via. In some embodiments, the via plate may be or include a conductive material, such as copper.

[0068] For example, in some embodiments, the quantum computing system 500 may include quantum hardware 504 in data communication with one or more classical processors 502. For example, the quantum hardware 504 may represent and / or manipulate information using qubits. A qubit may be or include any suitable quantum device that allows for a superposition of multiple states, e.g., both "0" and "1" states. By way of example, a qubit may be or include a unit of a superconducting material, such as a superconducting material that achieves superconductivity at a temperature below at least about 100 millikelvin, and may require operation at low temperatures, such as below about 100 millikelvin. In some embodiments, the quantum computing system 500 may include one or more multilevel quantum subsystems, such as a register of qubits. In some embodiments, the multilevel quantum subsystem may include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, etc.

[0069] The classical processor 502 may be a binary processor, such as a processor that operates on data represented as a plurality of bits. As an example, a bit may be represented by a voltage difference between a low voltage (e.g., 0V) and a high voltage (e.g., 5V) at a reference point, such as a memory cell, a circuit node, or the like. The low voltage may be associated with a "0" state, and the high voltage may be associated with a "1" state. The classical processor 502 may be configured to control the quantum hardware 504 in addition to any other suitable functions of the classical processor 502. For example, the classical processor 502 may be coupled to the quantum hardware 504 (e.g., by signal lines included in the flex circuit board 506 according to an exemplary embodiment of the present disclosure) and / or configured to send control signals to perform quantum operations using the quantum hardware 504. As an example, the classical processor 502 may be configured to send control signals (e.g., by a controller) to perform quantum gate operations in the quantum hardware 504. Additionally and / or alternatively, classical processor 502 can be configured to send control signals (e.g., by a readout device) that cause quantum hardware 504 to perform quantum state measurements and / or provide quantum state measurements to classical processor 502. For example, classical processor 502 can receive measurements of the quantum system that can be interpreted by classical processor 502.

[0070] According to an exemplary aspect of the present disclosure, the quantum computing system 500 may include one or more flex circuit boards 506 including one or more signal lines. The classical processor 502 may be coupled to at least one first flex circuit board. For example, the classical processor 502 may be coupled to the first flex circuit board 514 by a classical flex interconnect 532. The classical flex interconnect 532 may convert from a classical signal transmission medium 512 (e.g., a coaxial cable) to the first flex circuit board 514.

[0071] As an example, the classical flex interconnect 532 may be or may include a compression interposer. The compression interposer may include an array (e.g., a two-dimensional array) of spring pads. A connector receiving a signal from the classical processor 502, such as via one or more coaxial cables 512 (e.g., one coaxial cable 512 per signal line), may be compressed against the compression interposer to form a signal communication between the spring pad and the connector (e.g., a coaxial cable). Each of the spring pads may be coupled to a signal line on the first flex circuit board 514 and may transmit a signal from the classical processor 502 (e.g., a coaxial cable) to the signal line. The compression interposer may enable connection of a signal transmission medium 512 having a relatively low spatial density, such as a coaxial cable, which may occupy a relatively large amount of space per cable, to a signal transmission medium having a relatively high spatial density, such as a signal line embedded in the first flex circuit board 514 provided according to an exemplary embodiment of the present disclosure. Additionally, compressive interposers can provide high isolation between signal lines and / or low reflectivity along the signal lines, suitable for quantum computing applications.

[0072] In some embodiments, the first flex circuit board 514 may be or include a first flex circuit board material in the ground layer and / or signal lines. The first flex circuit board material may be selected to provide high signal transfer performance characteristics. By way of example, the first flex circuit board material may be or include copper, brass, gold, and / or other suitable materials having high signal transfer performance characteristics. For example, the first flex circuit board 514 may include copper signal lines and / or ground layers to provide high signal transfer performance characteristics.

[0073] The first flex circuit board 514 can pass through an airtight seal 552 disposed at an end (e.g., entrance) of a vacuum chamber, such as the cap 507. For example, a flex circuit board (e.g., the first flex circuit board 514) can be configured to pass through the airtight seal 552 such that a first portion of the flex circuit board (e.g., the first flex circuit board 514) is disposed within the vacuum chamber and a second portion of the flex circuit board (e.g., the first flex circuit board 514) is disposed outside the vacuum chamber, while the airtight seal 552 forms a vacuum seal for the vacuum chamber. The airtight seal 552 can allow the first flex circuit board 514 to enter the vacuum chamber without (e.g., substantially) breaking the vacuum created by the vacuum chamber. As an example, the airtight seal 552 can include a mating seal for each first flex circuit board 514. The mating seal can receive the first flex circuit board 514 and form a vacuum seal with a surface of the first flex circuit board 514. Additionally, the hermetic seal 552 may include one or more seal slots configured to receive the mating seal and / or the first flex circuit board 514. For example, the mating seal may form a vacuum seal with the seal slot while allowing the first flex circuit board 514 to pass through the seal slot and into the vacuum chamber. In this manner, the flex circuit board 506 may enter the vacuum chamber without experiencing signal disruption due to damage to the circuit board, as the board may enter the vacuum chamber continuously. In some embodiments, the hermetic seal 552 may include a fastening system that secures the mating seal to the seal slot and / or forms a vacuum seal, such as, for example, screws, bolts, seal rings, O-rings, etc. In some embodiments, the hermetic seal 552 may form a vacuum seal without the need for adhesive materials (e.g., glue, resin, etc.), such that, for example, residual adhesive materials do not contaminate the flex circuit board 506.

[0074] The first flex circuit board 514 can be coupled to at least one second flex circuit board 516. The first flex circuit board 514 can be coupled to the second flex circuit board 516 by at least one flex-flex interconnect 534. For example, the flex-flex interconnect 534 can couple (structurally and / or electrically) a ground layer, a dielectric layer, and / or a signal line of the first flex circuit board 514 to the second flex circuit board 516. By way of example, the flex-flex interconnect 534 can be formed by soldering, welding, and / or fusing components of the first flex circuit board 514 to the second flex circuit board 516. The flex-flex interconnect 534 can be or include any suitable interconnection of the two flex circuit boards 506, such as a butt joint, an overlap joint, and / or any other suitable interconnection.

[0075] The second flex circuit board 516 may have a different material composition than at least the first flex circuit board 514. In some embodiments, the second flex circuit board 516 may be or include a second flex circuit board material in the ground layer and / or signal lines. The second flex circuit board material may be selected to provide high signal transfer performance characteristics and / or reduced thermal conductivity. By way of example, the second flex circuit board material may be or include a copper alloy and / or other suitable material having desirable thermal properties. For example, the second flex circuit board 516 may include a copper alloy signal line and / or ground layer to reduce thermal conductivity from the top of the vacuum chamber (e.g., the first circuit board 514) and / or to dissipate heat generated in subsequent components such as the surface mounted attenuator 554.

[0076] In some embodiments, the second flex circuit board 516 can be coupled to at least one surface mount attenuator board 518. For example, the second flex circuit board 516 can be coupled to the surface mount attenuator board 518 by at least one flex-flex interconnect 536. For example, the flex-flex interconnect 536 can couple (structurally and / or electrically) a ground layer, a dielectric layer, and / or a signal line of the second flex circuit board 516 to the surface mount attenuator board 518. By way of example, the flex-flex interconnect 536 can be formed by soldering, welding, and / or fusing components of the second flex circuit board 516 to the surface mount attenuator board 518. The flex-flex interconnect 536 can be or include any suitable interconnection of the two flex circuit boards 506, such as a butt joint, an overlap joint, and / or any other suitable interconnection.

[0077] The surface mount attenuator substrate 518 may be a flexible printed circuit board. In some embodiments, the surface mount attenuator substrate 518 may be or include surface mount attenuator substrate material in the ground layer and / or signal lines. The surface mount attenuator substrate material may be selected to provide high signal transfer performance characteristics. By way of example, the surface mount attenuator substrate material may be or include copper, brass, gold, and / or other suitable materials having high signal transfer performance characteristics. For example, the surface mount attenuator substrate may include copper signal lines and / or ground layers to provide high signal transfer performance characteristics.

[0078] The surface mount attenuator substrate 518 may include one or more surface mount attenuators 554. The surface mount attenuators 554 may be configured to attenuate or block thermal photon interference. In some embodiments, the surface mount attenuator substrate 518 and / or the surface mount attenuators 554 may be disposed at a sufficiently low temperature such that the surface mount attenuators 554 do not generate thermal photons. In some embodiments, the surface mount attenuators 554 may be disposed within an isolation plate. The isolation plate may be configured to isolate the one or more surface mount attenuators 554. The isolation plate may be attached to the surface mount attenuator substrate 518. In some embodiments, the isolation plate may be attached to a ground layer and / or grounded. The isolation plate may include one or more cavities configured to isolate a first surface mount attenuator from a second surface mount attenuator. For example, the cavity may surround the first surface mount attenuator in the direction of the second surface mount attenuator to block crosstalk between the attenuators.

[0079] The quantum computing system 500 may include at least one third flex circuit board 520. For example, the surface mount attenuator substrate 518 may be coupled to the third flex circuit board 520 by at least one flex-flex interconnect 538. For example, the flex-flex interconnect 538 may couple (structurally and / or electrically) a ground layer, a dielectric layer, and / or a signal line of the surface mount attenuator substrate 518 to the third flex circuit board 520. By way of example, the flex-flex interconnect 538 may be formed by soldering, welding, and / or fusing components of the surface mount attenuator substrate 518 to the third flex circuit board 520. The flex-flex interconnect 538 may be or include any suitable interconnection of the two flex circuit boards 506, such as a butt joint, an overlap joint, and / or any other suitable interconnection.

[0080] The third flex circuit board 520 can be placed at a point within the vacuum chamber where the cooling gradient is cold enough for some materials to exhibit superconductivity. For example, at least a portion of the third flex circuit board 520 can have a temperature below about 3 Kelvin.

[0081] In some embodiments, the third flex circuit board 520 may be or include the material of the third flex circuit board in the ground layer and / or signal lines. The material of the third flex circuit board 520 may be selected to be superconducting at a temperature at which at least a portion of the third flex circuit board 520 experiences superconductivity. By way of example, the material of the third flex circuit board 520 may be or include niobium, tin, aluminum, and / or other suitable superconducting materials. For example, the third flex circuit board 520 may include copper plated niobium signal lines and / or ground layers to provide superconductivity. For example, copper plating on a copper plated niobium substrate may be useful for interfacing with superconducting niobium that may provide improved signal transfer characteristics. In some embodiments, the copper plated niobium substrate may be formed by first applying a layer of niobium, then a thin layer of copper to prevent oxide formation, and then a thicker layer of copper.

[0082] In some embodiments, the third flex circuit board 520 may be coupled to at least one fourth flex circuit board 522. The third flex circuit board 520 may be coupled to the fourth flex circuit board 522 by at least one flex-flex interconnect 540. For example, the flex-flex interconnect 540 may couple (structurally and / or electrically) a ground layer, a dielectric layer, and / or a signal line of the third flex circuit board 520 to the fourth flex circuit board 522. By way of example, the flex-flex interconnect 540 may be formed by soldering, welding, and / or fusing components of the third flex circuit board 520 to the fourth flex circuit board 522. The flex-flex interconnect 540 may be or include any suitable interconnection of the two flex circuit boards 506, such as a butt joint, an overlap joint, and / or any other suitable interconnection.

[0083] The fourth flex circuit board 522 can couple the third flex circuit board 520 to the quantum hardware 504. For example, a connector 542 on an end of the fourth flex circuit board 522 can be attached to a port in signal communication with the quantum hardware 504. By way of example, the connector can be a T-junction connector, such as a T-junction connector including a superconducting material (e.g., tin). Additionally and / or alternatively, the connector 542 can be a planar spring array.

[0084] In some embodiments, the fourth flex circuit board 522 may be or include a fourth flex circuit board material for the ground layer and / or signal lines. The fourth flex circuit board 522 material may be selected to provide high signal transmission performance characteristics. By way of example, the fourth flex circuit board 522 material may be or include copper, brass, gold, and / or other suitable materials having high signal transmission performance characteristics. For example, the fourth flex circuit board 522 may include copper signal lines and / or ground layers to provide high signal transmission performance characteristics. Additionally and / or alternatively, the fourth flex circuit board 522 material may be selected to be superconducting at a temperature at which at least a portion of the fourth flex circuit board 522 experiences superconductivity. By way of example, the fourth flex circuit board 522 material may be or include niobium, tin, aluminum, and / or other suitable superconducting materials.

[0085] In some embodiments, the fourth flex circuit board 522 may be or include a filter 556, such as an XYZ and / or IR filter 556. For example, the filter 556 may be configured to reduce the effects of noise, thermal photons, and / or other potential interference sources. As an example, the filter 556 may include a cavity in the fourth flex circuit board 522 filled with a filter material, such as a particulate suspension, to provide XYZ / IR filtering. In some examples, the filter material may provide less attenuation for signals at a first frequency and more attenuation for signals at a second, higher frequency. For example, some filter materials provide substantially monotonically increasing attenuation with increasing signal frequency for at least a portion of a target frequency band. In some embodiments, aspects of the filter material may be configured for low-pass and / or band-pass operation.

[0086] In some embodiments, the filter 556 can be bounded by one or more boundaries of a cavity (e.g., a cavity in a dielectric material) in the fourth flex circuit board 522. For example, the cavity in the fourth flex circuit board 522 can be filled with a filter material (e.g., a magnetically loaded polymer). In some embodiments, the cavity can be filled (e.g., partially or completely) with the filter material via an access in the fourth flex circuit board 522 if the filter material is in any pourable, injectable, and / or moldable state (e.g., flowing particles, soft / plasticized material, gel, slurry, paste, foam, uncured thermoset, softened / molten thermoplastic, etc.). In some embodiments, the cavity can be filled with the filter material in a substantially solid state (e.g., by pressing into the cavity, etc.).

[0087] In one example, the control pulses may be transmitted over one or more signal lines (e.g., signal lines 124, 134). For example, the control pulses may be transmitted by one or more classical processors coupled to the signal lines. The control pulses may be or include classical (e.g., binary) computer-readable signal data, such as a voltage signal, and / or a signal implementable by a quantum computing device.

[0088] In one example, the control pulses are transmitted to one or more quantum computing devices via signal lines. For example, the control pulses may be transmitted by the signal lines through multiple cryogenic cooling stages. For example, the signal lines carrying the control pulses may be gradually cooled from a classical processor (e.g., room temperature and / or a temperature of about 100 Kelvin), through multiple cryogenic cooling stages, to a quantum computing device (e.g., a temperature of less than about 1 Kelvin, such as about 10 mK).

[0089] In one example, the control pulses may be applied to perform at least one quantum operation based at least in part on the control pulses. As an example, in some embodiments, the quantum operation may be or may include obtaining a state measurement of the quantum computing device. For example, the control pulses may instruct the quantum computing device to measure a quantum state and / or to decompose the quantum state into a basis state representation. Further, the measured quantum state may be transmitted (e.g., by a signal line) to a classical processor.

[0090] As another example, in some embodiments, the quantum operation may be or may include performing at least one quantum gate operation by and / or in a quantum computing device. For example, a control pulse may represent a microwave pulse applied to a quantum computing device (e.g., a qubit) to perform a quantum gating operation. Exemplary quantum gating operations include, but are not limited to, a Hadamard gate, a controlled NOT (CNOT) gate, a controlled phase gate, a T-gate, a multi-qubit quantum gate, a coupler quantum gate, and the like.

[0091] The implementations of the digital and / or quantum subject matter, and digital function operations and quantum operations described in this specification may be implemented in digital electronic circuitry, suitable quantum circuitry, including the structures disclosed herein and their structural equivalents, or, more generally, in quantum computing systems in tangibly implemented digital and / or quantum computer software or firmware, digital and / or quantum computer hardware, or one or more combinations thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer / computing system, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0092] Implementations of the digital and / or quantum subject matter described in this disclosure may be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded in a tangible, non-transitory storage medium for execution by or to control the operation of a data processing apparatus. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits / qubit structures, or one or more combinations thereof. Alternatively or additionally, the program instructions may be encoded in an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information that is generated to encode the digital and / or quantum information for transmission to a suitable receiving device for execution by a data processing apparatus.

[0093] The terms quantum information and quantum data refer to information or data carried by, held in, or stored in a quantum system, with the smallest important system being a qubit, i.e., a system that defines a unit of quantum information. The term "qubit" is understood to encompass all quantum systems that can be adequately approximated as a two-level system in the corresponding context. Such quantum systems may include, for example, multi-level systems having more than two levels. By way of example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified with the ground state and the first excited state, but it is understood that other setups are possible in which the computational states are identified with higher-level excited states (e.g., qudits).

[0094] The term "data processing apparatus" generally refers to digital and / or quantum data processing hardware and includes any kind of apparatus, device, and machine for processing digital and / or quantum data, including, by way of example, a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, or a plurality of digital and quantum processors or computers, and combinations thereof. The apparatus may also be or further include special-purpose logic circuits, such as, for example, an FPGA (field programmable gate array), or an ASIC (application specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus designed to simulate or generate information about a particular quantum system. In particular, a quantum simulator is a special-purpose quantum computer that does not have the capability to perform universal quantum computations. In addition to the hardware, the apparatus may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting a processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0095] A digital computer program, which may also be referred to or described as a program, software, software application, module, software module, script, or code, may be written in any form of programming language, including compiled or interpreted, or declarative or procedural, and may be deployed in any form, such as as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, software application, module, software module, script, or code, may be written in any form of programming language, including compiled or interpreted, or declarative or procedural, and may be converted to a suitable quantum programming language or written in a quantum programming language such as Quantum Computation Language (QCL), Quipper, Cirq, etc.

[0096] A digital and / or quantum computer program may correspond to a file in a file system, but this is not necessarily the case. A program may be stored in part of a file that holds other programs or data. For example, it may be stored in one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, subprograms, or portions of code. A digital and / or quantum computer program may be deployed to be executed on one digital or one quantum computer, or on multiple digital and / or quantum computers located at one site or distributed across multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can transmit quantum data using quantum systems such as qubits. In general, a digital data communication network cannot transmit quantum data, but a quantum data communication network can transmit both quantum data and digital data.

[0097] The processes and logic flows described herein may, as appropriate, be performed by one or more programmable digital and / or quantum computers executing one or more digital and / or quantum computer programs operating on one or more digital and / or quantum processors to perform functions by manipulating input digital and quantum data and generating outputs. The processes and logic flows may also be performed by, and an apparatus may be implemented as, special purpose logic circuitry, such as an FPGA or ASIC, or a quantum simulator, or a combination of special purpose logic circuitry or a quantum simulator and one or more programmed digital and / or quantum computers.

[0098] A system of one or more digital and / or quantum computers or processors being "configured" or "operable" to perform a particular operation or action means that the system has installed thereon software, firmware, hardware, or a combination thereof that, when in operation, causes the system to perform the operation or action. A system of one or more digital and / or quantum computer programs being configured to perform a particular operation or action means that the program or programs contain instructions that, when executed by a digital and / or quantum data processing device, cause such device to perform an operation or action. A quantum computer can receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform an operation or action.

[0099] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general-purpose or dedicated digital and / or quantum microprocessor or both, or on any other kind of central digital and / or quantum processing unit. In general, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from a read-only memory, a random access memory, or a quantum system suitable for transmitting quantum data, such as photons, or a combination thereof.

[0100] Some exemplary elements of a digital and / or quantum computer are a central processing unit for executing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and memory may be supplemented or incorporated by dedicated logic circuitry or a quantum simulator. In general, a digital and / or quantum computer also includes one or more mass storage devices for storing digital and / or quantum data, e.g., magnetic, magneto-optical, optical disks, or quantum systems suitable for storing quantum information, or is operatively coupled to receive digital and / or quantum data, or to transmit digital and / or quantum data, or both. However, a digital and / or quantum computer need not include such devices.

[0101] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memories, media, and memory devices, e.g., semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks (such as internal hard disks and removable disks), magneto-optical disks, CD-ROM and DVD-ROM disks, quantum systems such as trapped atoms and electrons, etc. Quantum memory is understood to be a device capable of storing quantum data with high fidelity and efficiency for long periods of time, e.g., light-matter interfacing where light is used for transmission and matter is used to store and preserve the quantum properties of the quantum data, such as superposition and quantum coherence.

[0102] Control of the various systems described in this specification, or portions thereof, may be implemented in a digital and / or quantum computer program product stored on one or more non-transitory machine-readable storage media and including instructions executable on one or more digital and / or quantum processing devices. Each of the systems described herein, or portions thereof, may be implemented as an apparatus, method, or electronic system that may include one or more digital and / or quantum processing devices and memory for storing executable instructions for performing the operations described in this specification.

[0103] Although the present disclosure includes many example implementation details, these should not be construed as limitations on the scope of the claims, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in the examples of the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable subcombination. Furthermore, although features may be described above as acting in a particular combination, and may even be initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0104] Similarly, although operations are shown in the figures in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the operations shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above implementations should not be understood as requiring such separation in all implementations, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.

[0105] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. [Explanation of symbols]

[0106] 100 flex circuit butt joint 102 first flex circuit board 104, 108 removed part 106 Second flex circuit board 110 Signal Trace Gap 120, 128, 130, 138 Ground plane 122, 126, 132, 136 Dielectric layers 124, 134 signal lines 140 Ground support layer 150, 180, 182, 220, 222 Solder joints 160 Solder Bridge 170 Insulating plate 210 Cavity 300 ways 400, 500 Quantum Computing System 402, 504 Quantum Hardware 404, 502 Classical Processors 406 Physical Control Parameter Values 408 Measurement results 410 Quantum Systems 412 Control device 414 Readout device 506 flex circuit board 507 Cap 508 Chamber Mount 512 Classical signal transmission media (coaxial cable) 514 First flex circuit board 516 Second flex circuit board 518 Surface Mount Attenuator Board 520 3rd flex circuit board 522 4th flex circuit board 532 Classic Flex Interconnect 536, 540 Flex-Flex Interconnects 542 Connector 552 Airtight Seal 554 Surface Mount Attenuator

Claims

1. 1. An interconnect for connecting a plurality of flex circuit boards, comprising: a first flex circuit board including a first ground plane, a first dielectric layer, a first set of one or more signal lines, a second dielectric layer, and a second ground plane, the first flex circuit board having a removed portion exposing at least one signal line in the first set of one or more signal lines; a second flex circuit board including a third ground plane, a third dielectric layer, a second set of one or more signal lines, a fourth dielectric layer, and a fourth ground plane, the second flex circuit board having a removed portion exposing at least one signal line in the second set of one or more signal lines, the removed portion of the first flex circuit board and the removed portion of the second flex circuit board being aligned to form a signal trace gap having a first surface; a solder bridge disposed within the signal trace gap coupling the at least one signal line in the first set of one or more signal lines and the at least one signal line in the second set of one or more signal lines; an insulating plate at least partially covering the signal trace gap such that the solder bridge is disposed between the insulating plate and the first surface of the signal trace gap, the insulating plate being coupled to at least one of the first ground plane of the first flex circuit board and the third ground plane of the second flex circuit board; An interconnection comprising:

2. a ground support layer extending at least partially across the second ground plane of the first flex circuit board and at least partially across the fourth ground plane of the second flex circuit board, the ground support layer being coupled to the second ground plane and the fourth ground plane; The interconnect of claim 1 further comprising:

3. 2. The interconnect of claim 1, wherein an edge of said removed portion of said first flex circuit board and an edge of said removed portion of said second flex circuit board contact one another.

4. 2. The interconnect of claim 1 , wherein one or more of the first ground plane, the second ground plane, the third ground plane, or the fourth ground plane comprises at least one superconducting material that is superconducting at a temperature below 1 Kelvin.

5. The interconnection of claim 1, wherein the at least one signal line in the first set of the one or more signal lines and the at least one signal line in the second set of the one or more signal lines are positioned on the first surface of the signal trace gap.

6. 1. An interconnect for connecting a plurality of circuit boards, comprising: a first circuit board including a first ground plane, a first dielectric layer, a first set of one or more signal lines, a second dielectric layer, and a second ground plane, the first circuit board having a removed portion exposing at least one signal line in the first set of one or more signal lines; a second circuit board including a third ground plane, a third dielectric layer, a second set of one or more signal lines, a fourth dielectric layer, and a fourth ground plane, the second circuit board having a removed portion exposing at least one signal line in the second set of one or more signal lines, the removed portion of the first circuit board and the removed portion of the second circuit board being aligned to form a signal trace gap having a first surface; a solder bridge disposed within the signal trace gap coupling the at least one signal line in the first set of one or more signal lines and the at least one signal line in the second set of one or more signal lines; an insulating plate at least partially covering the signal trace gap such that the solder bridge is disposed between the insulating plate and the first surface of the signal trace gap; a ground support layer extending at least partially across the second ground plane of the first circuit board and at least partially across the fourth ground plane of the second circuit board, the ground support layer being coupled to the second and fourth ground planes by a set of one or more solder connections; An interconnection comprising:

7. The interconnect of claim 6 , wherein the insulating plate is coupled to at least one of the first ground plane of the first circuit board and the third ground plane of the second circuit board.

8. 7. The interconnect of claim 6, wherein the insulating plate is coupled to at least one of the first ground plane of the first circuit board and the third ground plane of the second circuit board by a set of one or more solder connections.

9. The interconnect of claim 6 , wherein an edge of the removed portion of the first circuit board and an edge of the removed portion of the second circuit board are in contact.

10. 10. The interconnect of claim 9, wherein the at least one signal line of the first set of signal lines and the at least one signal line of the second set of signal lines are in contact.

11. The interconnect of claim 6 , wherein at least one of the first circuit board and the second circuit board is a flex circuit board.

12. 7. The interconnect of claim 6, wherein each ground plane of the first circuit board and each ground plane of the second circuit board are constructed of at least one superconducting material that is superconducting at a temperature below 3 Kelvin.

13. 7. The interconnect of claim 6, wherein the first circuit board and the second circuit board are flex circuit boards, and each ground plane of the first circuit board and each ground plane of the second circuit board are comprised of at least one superconducting material that is superconducting at a temperature below 3 Kelvin.

14. The interconnection of claim 6, wherein the at least one signal line in the first set of the one or more signal lines and the at least one signal line in the second set of the one or more signal lines are positioned on the first surface of the signal trace gap.

15. 1. A method for fabricating an interconnect structure for a quantum computing system, comprising: obtaining a first flex circuit board including a first ground plane, a first dielectric layer, a first set of one or more signal lines, a second dielectric layer, and a second ground plane; obtaining a second flex circuit board including a third ground plane, a third dielectric layer, a second set of one or more signal lines, a fourth dielectric layer, and a fourth ground plane; removing a portion of the first flex circuit board, thereby creating a removed portion of the first flex circuit board that exposes at least one signal line in the first set of signal lines; removing a portion of the second flex circuit board, thereby creating a removed portion of the second flex circuit board that exposes at least one signal line in the second set of signal lines; aligning the removed portion of the first flex circuit board with the removed portion of the second flex circuit board, thereby forming a signal trace gap having a first surface; coupling the at least one signal line in the first set of one or more signal lines to the at least one signal line in the second set of one or more signal lines at the signal trace gap via a solder bridge; coupling an insulating plate to the wiring structure such that the insulating plate at least partially covers the signal trace gap and the solder bridge is disposed between the insulating plate and the first surface of the signal trace gap; A method comprising:

16. coupling a ground support layer extending at least partially across the second ground plane of the first flex circuit board and at least partially across the fourth ground plane of the second flex circuit board, the ground support layer being coupled to the second and fourth ground planes by a respective set of one or more solder connections; The method of claim 15 further comprising:

17. 16. The method of claim 15, wherein coupling the insulating plate to the wiring structure comprises coupling the insulating plate to at least one of the first ground plane of the first flex circuit board and the third ground plane of the second flex circuit board.

18. 16. The method of claim 15, wherein the insulating plate is coupled to each of the first ground plane of the first flex circuit board and the third ground plane of the second flex circuit board by a set of one or more solder connections.

19. 16. The method of claim 15, wherein the step of removing a portion of the first flex circuit board or the step of removing a portion of the second flex circuit board comprises ablating the respective flex circuit board.

20. The method of claim 15 , wherein an edge of the removed portion of the first flex circuit board and an edge of the removed portion of the second flex circuit board contact one another.

21. The method of claim 15 , wherein the solder bridge is comprised of at least one superconducting material.

22. 16. The method of claim 15, wherein one or more of the ground planes are comprised of at least one superconducting material that is superconducting at a temperature below 3 Kelvin.

23. The method of claim 15, wherein the at least one signal line in the first set of the one or more signal lines and the at least one signal line in the second set of the one or more signal lines are positioned on the first surface of the signal trace gap.

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