Display device

Abstract

To provide a display device which reduces coloring when a background is visually confirmed in a peripheral region outside a display region.SOLUTION: The display device includes: a liquid crystal layer sealed between an array substrate and a counter substrate; and a light source arranged so that light enters a side surface of the array substrate or a side surface of the counter substrate. There is a net-like metal layer in the peripheral region outside the display region. In the peripheral region, the background of the counter substrate is visually confirmed from the array substrate and the background of the array substrate is visually confirmed from the counter substrate.SELECTED DRAWING: Figure 26

Description

[Technical field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] Patent Document 1 describes a display device including a first light-transmitting substrate, a second light-transmitting substrate arranged opposite the first light-transmitting substrate, a liquid crystal layer having a polymer-dispersed liquid crystal sealed between the first light-transmitting substrate and the second light-transmitting substrate, and at least one light-emitting unit arranged opposite at least one side surface of the first light-transmitting substrate and the second light-transmitting substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-021974 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the display device described in Patent Document 1, the background on the other side of the display panel can be seen from one side of the display panel. If the peripheral area outside the display area does not transmit light, the background cannot be seen, which may cause an uncomfortable feeling. Therefore, it is desirable to make the background on the other side of the display panel visible from one side of the display panel in the peripheral area outside the display area.

[0005] An object of the present invention is to provide a display device that reduces coloring that occurs when the background is viewed in a peripheral area outside the display area. [Means for solving the problem]

[0006] A display device according to one embodiment includes an array substrate, an opposing substrate, a liquid crystal layer between the array substrate and the opposing substrate, and a light source arranged to allow light to enter a side of the array substrate or a side of the opposing substrate, the array substrate having a plurality of signal lines spaced apart in a first direction and a plurality of scanning lines spaced apart in a second direction in a display region, a first peripheral region outside the display region having a plurality of first wirings to which a constant potential is supplied, and a second peripheral region on the opposite side of the display region to the first peripheral region having a plurality of second wirings connected to the scanning lines, the shape of the first wirings in the first peripheral region being a mirror image of the shape of the second wirings in the second peripheral region, and the first wirings are not connected to the scanning lines.

[0007] A display device according to another aspect includes an array substrate, a counter substrate, a liquid crystal layer between the array substrate and the counter substrate, and a light source arranged so that light enters a side of the array substrate or a side of the counter substrate, wherein the array substrate has a plurality of signal lines spaced apart in a first direction and a plurality of scanning lines spaced apart in a second direction in a display region, and a mesh-like metal layer is provided in a peripheral region outside the display region, and an incident direction from a first side closest to the light source to the opposing surface of the first side is non-orthogonal to a first side that constitutes the mesh of the metal layer, and the incident direction is non-orthogonal to a second side that constitutes the mesh and extends in a direction different from the first side. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view illustrating an example of a display device according to the present embodiment. [Diagram 2] FIG. 2 is a block diagram showing the display device of the first embodiment. [Diagram 3] FIG. 3 is a timing chart for explaining the timing at which the light source emits light in the field sequential method of the first embodiment. [Figure 4] FIG. 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrode and the scattering state of the pixel. [Diagram 5] FIG. 5 is a cross-sectional view showing an example of a cross section of the display device of FIG. [Figure 6] FIG. 6 is a plan view showing the plane of the display device of FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of the liquid crystal layer portion of FIG. [Figure 8] FIG. 8 is a cross-sectional view for explaining the non-scattering state in the liquid crystal layer. [Figure 9] FIG. 9 is a cross-sectional view for explaining a scattering state in a liquid crystal layer. [Figure 10] FIG. 10 is a plan view showing scanning lines, signal lines, and switching elements in a pixel. [Figure 11] FIG. 11 is a plan view showing a storage capacitor layer in a pixel. [Figure 12] FIG. 12 is a plan view showing the auxiliary metal layer and the opening region in a pixel. [Figure 13] FIG. 13 is a plan view showing a pixel electrode in a pixel. [Figure 14] FIG. 14 is a plan view showing a light-shielding layer in a pixel. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV' of FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI' of FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII' of FIG. [Figure 18] FIG. 18 is an explanatory diagram illustrating the relationship between a viewer viewing the background on the other surface side from one surface and the background. [Figure 19] FIG. 19 is an explanatory diagram illustrating an example in which a peripheral region is superimposed on a background. [Figure 20] FIG. 20 is a plan view for explaining the peripheral region of the first embodiment. [Figure 21] FIG. 21 is a plan view showing a schematic cross section taken along line XXI-XXI' in FIG. [Figure 22] FIG. 22 is a plan view for explaining the peripheral region of the second embodiment. [Diagram 23] FIG. 23 is an enlarged plan view illustrating a first portion of the peripheral region of the second embodiment. [Figure 24] FIG. 24 is an enlarged plan view illustrating a second portion of the peripheral region of the second embodiment. [Diagram 25] FIG. 25 is a plan view showing a schematic cross section taken along line XXV-XXV' in FIG. [Figure 26] FIG. 26 is an enlarged plan view illustrating a first portion of the peripheral region of the first modification of the second embodiment. [Figure 27] FIG. 27 is an enlarged plan view illustrating a first portion of the peripheral region of the second modification of the second embodiment. [Figure 28] FIG. 28 is an enlarged plan view illustrating a first portion of the peripheral region of the third modification of the second embodiment. [Figure 29] FIG. 29 is an enlarged plan view illustrating a second portion of the peripheral region of the third modification of the second embodiment. [Diagram 30] FIG. 30 is an enlarged plan view illustrating a first portion of the peripheral region of the fourth modification of the second embodiment. [Diagram 31] FIG. 31 is an enlarged plan view illustrating a second portion of the peripheral region of the fourth modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The form (embodiment) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited by the contents described in the following embodiments. The components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the disclosure are naturally included in the scope of the present disclosure. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present disclosure. In addition, in this specification and each figure, elements similar to those described above with respect to the previously mentioned figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] (Embodiment 1) Fig. 1 is a perspective view showing an example of a display device according to the present embodiment. Fig. 2 is a block diagram showing the display device of Fig. 1. Fig. 3 is a timing chart explaining the timing at which a light source emits light in a field sequential system.

[0011] 1, the display device 1 includes a display panel 2, a light source 3, and a drive circuit 4. Here, one direction in the plane of the display panel 2 is the PX direction, a direction perpendicular to the PX direction is the second direction PY, and a direction perpendicular to the PX-PY plane is the third direction PZ.

[0012] The display panel 2 includes an array substrate 10, a counter substrate 20, and a liquid crystal layer 50 (see FIG. 5). The counter substrate 20 faces the array substrate 10 in a direction perpendicular to the surface of the array substrate 10 (the PZ direction shown in FIG. 1). The liquid crystal layer 50 (see FIG. 5) is filled with a polymer dispersed liquid crystal LC (described later) between the array substrate 10, the counter substrate 20, and a sealing portion 18.

[0013] As shown in FIG. 1, the display panel 2 has a display area AA capable of displaying an image, and a peripheral area FR outside the display area AA. In the display area AA, a plurality of pixels Pix are arranged in a matrix. In this disclosure, a row refers to a pixel row having m pixels Pix arranged in one direction. Also, a column refers to a pixel column having n pixels Pix arranged in a direction perpendicular to the direction in which the rows are arranged. The values ​​of m and n are determined according to the display resolution in the vertical direction and the display resolution in the horizontal direction. Also, a plurality of scanning lines GL are wired for each row, and a plurality of signal lines SL are wired for each column.

[0014] The light source 3 includes a plurality of light-emitting units 31. As shown in Fig. 2, the light source control unit 32 is included in the drive circuit 4. The light source control unit 32 may be a circuit separate from the drive circuit 4. The light-emitting units 31 and the light source control unit 32 are electrically connected by wiring in the array substrate 10.

[0015] 1, the driving circuit 4 is fixed to the surface of the array substrate 10. As shown in Fig. 2, the driving circuit 4 includes a signal processing circuit 41, a pixel control circuit 42, a gate driving circuit 43, a source driving circuit 44, and a common potential driving circuit 45. The array substrate 10 has a larger area in the PX-PY plane than the counter substrate 20, and the driving circuit 4 is provided on the protruding portion of the array substrate 10 exposed from the counter substrate 20.

[0016] An input signal (such as an RGB signal) VS is input to the signal processing circuit 41 from an image output unit 91 of an external upper level control unit 9 via a flexible substrate 92.

[0017] The signal processing circuit 41 includes an input signal analysis unit 411, a storage unit 412, and a signal adjustment unit 413. The input signal analysis unit 411 generates a second input signal VCS based on a first input signal VS input from the outside.

[0018] The second input signal VCS is a signal that determines, based on the first input signal VS, what gradation value is to be given to each pixel Pix of the display panel 2. In other words, the second input signal VCS is a signal that includes gradation information related to the gradation value of each pixel Pix.

[0019] The signal adjustment unit 413 generates a third input signal VCSA from the second input signal VCS. The signal adjustment unit 413 sends the third input signal VCSA to the pixel control circuit 42, and sends a light source control signal LCSA to the light source control unit 32. The light source control signal LCSA is, for example, a signal including information on the amount of light of the light-emitting unit 31 that is set according to the input gradation value to the pixel Pix. For example, when a dark image is displayed, the amount of light of the light-emitting unit 31 is set to be small. When a bright image is displayed, the amount of light of the light-emitting unit 31 is set to be large.

[0020] The pixel control circuit 42 generates a horizontal drive signal HDS and a vertical drive signal VDS based on the third input signal VCSA. In this embodiment, since the pixel is driven by the field sequential method, the horizontal drive signal HDS and the vertical drive signal VDS are generated for each color that the light emitting unit 31 can emit.

[0021] The gate drive circuit 43 sequentially selects the scanning lines GL of the display panel 2 within one vertical scanning period based on the horizontal drive signal HDS. The order in which the scanning lines GL are selected is arbitrary. The gate drive circuit 43 and the scanning lines GL are electrically connected to each other by second wiring GPL arranged in the peripheral region FR (see FIG. 1) outside the display area AA.

[0022] The source drive circuit 44 supplies a gray scale signal corresponding to the output gray scale value of each pixel Pix to each signal line SL of the display panel 2 within one horizontal scanning period based on the vertical drive signal VDS.

[0023] In this embodiment, the display panel 2 is an active matrix panel, which has signal (source) lines SL extending in the second direction PY and scanning (gate) lines GL extending in the first direction PX in a plan view, and switching elements Tr are provided at the intersections of the signal lines SL and the scanning lines GL.

[0024] A thin film transistor is used as the switching element Tr. A bottom gate type transistor or a top gate type transistor may be used as the thin film transistor. Although a single gate thin film transistor is illustrated as the switching element Tr, a double gate transistor may be used. One of the source electrode and the drain electrode of the switching element Tr is connected to the signal line SL, the gate electrode is connected to the scanning line GL, and the other of the source electrode and the drain electrode is connected to one end of the capacitance of the polymer dispersed liquid crystal LC described later. One end of the capacitance of the polymer dispersed liquid crystal LC is connected to the switching element Tr via the pixel electrode PE, and the other end is connected to the common potential wiring COML via the common electrode CE. In addition, a storage capacitance HC is generated between the pixel electrode PE and the storage capacitance electrode IO electrically connected to the common potential wiring COML. In addition, the common potential wiring COML is supplied from a common potential driving circuit 45.

[0025] The light-emitting unit 31 includes a first color (e.g., red) light-emitting body 33R, a second color (e.g., green) light-emitting body 33G, and a third color (e.g., blue) light-emitting body 33B. The light source control unit 32 controls the first color light-emitting body 33R, the second color light-emitting body 33G, and the third color light-emitting body 33B to emit light in a time-division manner based on a light source control signal LCSA. In this manner, the first color light-emitting body 33R, the second color light-emitting body 33G, and the third color light-emitting body 33B are driven by a field sequential method.

[0026] 3, in the first subframe (first predetermined time) RF, the first color light emitter 33R emits light in the first color light emission period RON, and the pixels Pix selected in one vertical scanning period GateScan scatter the light to display. In the entire display panel 2, if the gradation signals corresponding to the output gradation values ​​of the pixels Pix are supplied to the signal lines SL described above to the pixels Pix selected in one vertical scanning period GateScan, only the first color is lit in the first color light emission period RON.

[0027] Next, in a second subframe (second predetermined time) GF, the second color light emitter 33G emits light in a second color light emission period GON, and the pixels Pix selected within one vertical scanning period GateScan scatter the light to display. In the entire display panel 2, if the pixels Pix selected within one vertical scanning period GateScan are supplied with grayscale signals corresponding to the output grayscale values ​​of the pixels Pix to the above-mentioned signal lines SL, only the second color is lit during the second color light emission period GON.

[0028] Furthermore, in a third subframe (third predetermined time) BF, the third color light emitter 33B emits light in the third color light emission period BON, and the pixels Pix selected within one vertical scanning period GateScan scatter the light to display. In the entire display panel 2, if the pixels Pix selected within one vertical scanning period GateScan are supplied with gradation signals corresponding to the output gradation values ​​of the pixels Pix to the above-mentioned signal lines SL, then only the third color is lit during the third color light emission period BON.

[0029] The human eye has a limited temporal resolution and an afterimage occurs, so that a composite image of three colors is recognized during one frame (1F). The field sequential method does not require a color filter and reduces absorption loss in the color filter, so that a high transmittance can be achieved. In the color filter method, one pixel is created by dividing the pixel Pix into sub-pixels for the first, second, and third colors, whereas the field sequential method does not require such sub-pixel division. It is also possible to further include a fourth sub-frame and emit a fourth color different from the first, second, and third colors.

[0030] FIG. 4 is an explanatory diagram showing the relationship between the voltage applied to a pixel electrode and the scattering state of a pixel. FIG. 5 is a cross-sectional view showing an example of a cross section of the display device of FIG. 1. FIG. 6 is a plan view showing a plane of the display device of FIG. 1. FIG. 5 is a V-V' cross section of FIG. 6. FIG. 7 is an enlarged cross-sectional view of a liquid crystal layer portion of FIG. 5. FIG. 8 is a cross-sectional view for explaining a non-scattering state in the liquid crystal layer. FIG. 9 is a cross-sectional view for explaining a scattering state in the liquid crystal layer.

[0031] If a grayscale signal corresponding to the output grayscale value of each pixel Pix selected within one vertical scanning period GateScan is supplied to each of the signal lines SL described above, the voltage applied to the pixel electrode PE changes according to the grayscale signal. When the voltage applied to the pixel electrode PE changes, the voltage between the pixel electrode PE and the common electrode CE changes. Then, as shown in FIG. 4, the scattering state of the liquid crystal layer 50 for each pixel Pix is ​​controlled according to the voltage applied to the pixel electrode PE, and the scattering ratio within the pixel Pix changes.

[0032] 4, when the voltage applied to the pixel electrode PE becomes equal to or higher than the saturation voltage Vsat, the change in the scattering ratio in the pixel Pix becomes small. Therefore, the drive circuit 4 changes the voltage applied to the pixel electrode PE in accordance with the vertical drive signal VDS in a voltage range Vdr lower than the saturation voltage Vsat.

[0033] 5 and 6, the array substrate 10 has a first main surface 10A, a second main surface 10B, a first side surface 10C, a second side surface 10D, a third side surface 10E, and a fourth side surface 10F. The first main surface 10A and the second main surface 10B are parallel planes. The first side surface 10C and the second side surface 10D are parallel planes. The third side surface 10E and the fourth side surface 10F are parallel planes.

[0034] 5 and 6, the counter substrate 20 has a first main surface 20A, a second main surface 20B, a first side surface 20C, a second side surface 20D, a third side surface 20E, and a fourth side surface 20F. The first main surface 20A and the second main surface 20B are parallel planes. The first side surface 20C and the second side surface 20D are parallel planes. The third side surface 20E and the fourth side surface 20F are parallel planes.

[0035] 5 and 6, the light source 3 faces the second side surface 20D of the counter substrate 20. The light source 3 is sometimes called a side light source. As shown in Fig. 5, the light source 3 irradiates the second side surface 20D of the counter substrate 20 with light source light L. The second side surface 20D of the counter substrate 20 facing the light source 3 serves as a light incident surface.

[0036] 5, the light source light L emitted from the light source 3 propagates in a direction (second direction PY) away from the second side surface 20D while being reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20. When the light source light L travels from the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20 to the outside, it travels from a medium with a large refractive index to a medium with a small refractive index. Therefore, if the angle of incidence of the light source light L on the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20 is larger than the critical angle, the light source light L is totally reflected by the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20.

[0037] As shown in Fig. 5, the light source light L propagating inside the array substrate 10 and the counter substrate 20 is scattered by the pixels Pix having liquid crystal in a scattering state, and the incident angle of the scattered light becomes smaller than the critical angle, so that emitted light 68, 68A is radiated to the outside from the first main surface 20A of the counter substrate 20 and the first main surface 10A of the array substrate 10, respectively. The emitted light 68, 68A radiated to the outside from the first main surface 20A of the counter substrate 20 and the first main surface 10A of the array substrate 10, respectively, is observed by an observer. Hereinafter, the polymer dispersed liquid crystal in a scattering state and the polymer dispersed liquid crystal in a non-scattering state will be described with reference to Figs. 7 to 9.

[0038] 7, a first alignment film AL1 is provided on the array substrate 10. A second alignment film AL2 is provided on the counter substrate 20. The first alignment film AL1 and the second alignment film AL2 are, for example, vertical alignment films.

[0039] A solution containing liquid crystal and a monomer is sealed between the array substrate 10 and the counter substrate 20. Next, in a state in which the monomer and liquid crystal are aligned by the first alignment film AL1 and the second alignment film AL2, the monomer is polymerized by ultraviolet light or heat to form a bulk 51. This forms a liquid crystal layer 50 having a reverse mode polymer dispersed liquid crystal LC in which the liquid crystal is dispersed in the gaps of a network of polymers formed in a mesh shape.

[0040] Thus, the polymer dispersed liquid crystal LC has a bulk 51 formed of a polymer and a plurality of particles 52 dispersed in the bulk 51. The particles 52 are formed of a liquid crystal. The bulk 51 and the particles 52 each have optical anisotropy.

[0041] The orientation of the liquid crystal contained in the particles 52 is controlled by the voltage difference between the pixel electrode PE and the common electrode CE. The orientation of the liquid crystal changes depending on the voltage applied to the pixel electrode PE. The change in the orientation of the liquid crystal changes the degree of scattering of light passing through the pixel Pix.

[0042] 8, when no voltage is applied between the pixel electrode PE and the common electrode CE, the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the particle 52 are oriented in the same direction. The optical axis Ax2 of the particle 52 is parallel to the PZ direction of the liquid crystal layer 50. The optical axis Ax1 of the bulk 51 is parallel to the PZ direction of the liquid crystal layer 50 regardless of the presence or absence of voltage.

[0043] The ordinary light refractive indexes of the bulk 51 and the particles 52 are equal to each other. When no voltage is applied between the pixel electrode PE and the common electrode CE, the difference in refractive index between the bulk 51 and the particles 52 is zero in all directions. The liquid crystal layer 50 is in a non-scattering state in which it does not scatter the light source light L. The light source light L propagates in a direction away from the light source 3 (light-emitting section 31) while being reflected by the first main surface 10A of the array substrate 10 and the first main surface 20A of the counter substrate 20. When the liquid crystal layer 50 is in a non-scattering state in which it does not scatter the light source light L, the background on the first main surface 20A side of the counter substrate 20 is visible from the first main surface 10A of the array substrate 10, and the background on the first main surface 10A side of the array substrate 10 is visible from the first main surface 20A of the counter substrate 20.

[0044] 9, between the pixel electrode PE and the common electrode CE to which a voltage is applied, the optical axis Ax2 of the particles 52 is tilted by the electric field generated between the pixel electrode PE and the common electrode CE. Since the optical axis Ax1 of the bulk 51 does not change due to the electric field, the optical axis Ax1 of the bulk 51 and the optical axis Ax2 of the particles 52 are oriented in different directions. In the pixel Pix having the pixel electrode PE to which a voltage is applied, the light source light L is scattered. As described above, a part of the scattered light source light L is emitted to the outside from the first main surface 10A of the array substrate 10 or the first main surface 20A of the counter substrate 20, and the light is observed by the observer.

[0045] In a pixel Pix having a pixel electrode PE to which no voltage is applied, the background on the first main surface 20A side of the counter substrate 20 is visible from the first main surface 10A of the array substrate 10, and the background on the first main surface 10A side of the array substrate 10 is visible from the first main surface 20A of the counter substrate 20. When the display device 1 of this embodiment receives a first input signal VS from the image output unit 91, a voltage is applied to the pixel electrode PE of the pixel Pix where an image is displayed, and an image based on the third input signal VCSA is visible together with the background. In this way, when the polymer dispersed liquid crystal is in a scattering state, an image is displayed in the display region.

[0046] An image displayed by light emitted to the outside after scattering the light source light L in a pixel Pix having a pixel electrode PE to which a voltage is applied is displayed superimposed on the background. In other words, the display device 1 of this embodiment displays an image superimposed on the background by combining the emitted light 68 or 68A with the background.

[0047] In one vertical scanning period GateScan shown in FIG. 3, the potential of each pixel electrode PE (see FIG. 7) to which the electric potential has been written must be held in at least one of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON, which follow each vertical scanning period GateScan. If the potential of each pixel electrode PE (see FIG. 7) to which the electric potential has been written cannot be held in at least one of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON, which follow each vertical scanning period GateScan, so-called flicker is likely to occur. In other words, in order to shorten one vertical scanning period GateScan, which is the selection time of the scanning line, and to improve visibility in driving by the so-called field sequential method, there is a demand for making it easier to hold the potential of each pixel electrode PE (see FIG. 7) to which the electric potential has been written in each of the first color light emission period RON, the second color light emission period GON, and the third color light emission period BON.

[0048] FIG. 10 is a plan view showing a scanning line, a signal line, and a switching element in a pixel. FIG. 11 is a plan view showing a storage capacitance layer in a pixel. FIG. 12 is a plan view showing an auxiliary metal layer and an opening region in a pixel. FIG. 13 is a plan view showing a pixel electrode in a pixel. FIG. 14 is a plan view showing a light-shielding layer in a pixel. FIG. 15 is a cross-sectional view taken along line XV-XV' in FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI' in FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII' in FIG. 14. As shown in FIGS. 1, 2, and 10, a plurality of signal lines SL and a plurality of scanning lines GL are provided in a lattice pattern in a plan view on the array substrate 10. In other words, one surface of the array substrate 10 includes a plurality of signal lines arranged at intervals in the first direction PX and a plurality of scanning lines arranged at intervals in the second direction PY.

[0049] As shown in Fig. 10, a region surrounded by adjacent scanning lines GL and adjacent signal lines SL is a pixel Pix. The pixel Pix is ​​provided with a pixel electrode PE and a switching element Tr. In this embodiment, the switching element Tr is a bottom-gate type thin film transistor. The switching element Tr has a semiconductor layer SC that overlaps, in a plan view, with a gate electrode GE that is electrically connected to the scanning line GL.

[0050] 10, the scanning lines GL are wirings made of a metal such as molybdenum (Mo) or aluminum (Al), a laminate of these, or an alloy of these, while the signal lines SL are wirings made of a metal such as aluminum or an alloy.

[0051] 10, the semiconductor layer SC is provided so as not to protrude from the gate electrode GE in a plan view, whereby the light source light L directed from the gate electrode GE side toward the semiconductor layer SC is reflected, making it difficult for light leakage to occur in the semiconductor layer SC.

[0052] 5 and 20, the light source light L emitted from the light source 3 is incident in the second direction PY. The incident direction is the direction from the second side surface 20D closest to the light source 3 to the first side surface 20C which is the opposing surface of the second side surface 20D. When the incident direction of the light source light L is the second direction PY, the length of the semiconductor layer SC in the first direction is smaller than the length of the semiconductor layer SC in the first direction PX. This reduces the length of the light source light L in the direction intersecting the incident direction, thereby reducing the effect of light leakage.

[0053] 10, the source electrode SE has two conductors, the same as those of the signal line SL, which are in the same layer as the signal line SL and extend from the signal line SL in a direction intersecting the signal line SL. As a result, the source electrode SE electrically connected to the signal line SL overlaps one end of the semiconductor layer SC in a plan view.

[0054] As shown in Fig. 10, a drain electrode DE is provided between the conductors of adjacent source electrodes SE in a planar view. The drain electrode DE overlaps with the semiconductor layer SC in a planar view. The portion that does not overlap with the source electrode SE and the drain electrode DE functions as a channel of the switching element Tr. As shown in Fig. 13, a contact electrode DEA electrically connected to the drain electrode DE is electrically connected to the pixel electrode PE through a contact hole CH.

[0055] 15, the array substrate 10 has a first light-transmissive base material 19 made of, for example, glass. The first light-transmissive base material 19 may be made of a resin such as polyethylene terephthalate as long as it has light-transmissive properties.

[0056] As shown in FIG. 15, on a first light-transmissive base material 19, the scanning lines GL (see FIG. 10) and the gate electrodes GE are provided.

[0057] 15, a first insulating layer 11 is provided to cover the scanning lines GL and the gate electrodes GE. The first insulating layer 11 is made of a transparent inorganic insulating material such as silicon nitride.

[0058] A semiconductor layer SC is laminated on the first insulating layer 11. The semiconductor layer SC is formed of, for example, amorphous silicon, but may be formed of polysilicon or an oxide semiconductor. When viewed from the same cross section, the length Lsc of the semiconductor layer SC is smaller than the length Lge of the gate electrode GE overlapping the semiconductor layer SC. This allows the gate electrode GE to block the light Ld1 propagating through the first light-transmitting base material 19. As a result, the switching element Tr of the first embodiment has reduced light leakage.

[0059] A source electrode SE and a signal line SL covering a portion of the semiconductor layer SC, and a drain electrode DE covering a portion of the semiconductor layer SC are provided on the first insulating layer 11. The drain electrode DE is made of the same material as the signal line SL. A second insulating layer 12 is provided on the semiconductor layer SC, the signal line SL, and the drain electrode DE. The second insulating layer 12 is formed of a transparent inorganic insulating material such as silicon nitride, for example, similar to the first insulating layer.

[0060] A third insulating layer is formed on the second insulating layer 12 to cover a part of the second insulating layer 12. The third insulating layer 13 is formed of an organic insulating material having light transmitting properties, such as an acrylic resin. The third insulating layer 13 has a thickness larger than other insulating films formed of inorganic materials.

[0061] As shown in FIG. 15, FIG. 16, and FIG. 17, there are regions where the third insulating layer 13 is present and regions where the third insulating layer 13 is not present. As shown in FIG. 16 and FIG. 17, the region where the third insulating layer 13 is present is above the scanning line GL and above the signal line SL. The third insulating layer 13 is in a lattice shape that covers the scanning line GL and the signal line SL along the scanning line GL and the signal line SL. Also, as shown in FIG. 15, the region where the third insulating layer 13 is present is above the semiconductor layer SC, that is, above the switching element Tr. Therefore, the switching element Tr, the scanning line GL, and the signal line SL are relatively far away from the storage capacitance electrode ITO, so that they are less susceptible to the common potential from the storage capacitance electrode ITO. Furthermore, in the array substrate 10, a region surrounded by the scanning line GL and the signal line SL has a region where the third insulating layer 13 is not present, and therefore a region where the thickness of the insulating layer is smaller than the thickness of the insulating layer that overlaps the signal line SL and the scanning line GL in a plan view is formed. In the region surrounded by the scanning lines GL and the signal lines SL, the light transmittance is relatively improved compared to the regions above the scanning lines GL and above the signal lines SL, and the light transmittance is improved.

[0062] As shown in Fig. 15, a metal layer TM is provided on the third insulating layer 13. The conductive metal layer TM is a metal such as molybdenum (Mo) or aluminum (Al), a laminate of these, or wiring of an alloy of these. As shown in Fig. 12, the metal layer TM is provided in an area overlapping the signal lines SL, the scanning lines GL, and the switching elements Tr in a plan view. This makes the metal layer TM lattice-shaped, and an opening AP surrounded by the metal layer TM is formed.

[0063] As shown in FIG. 15, a storage capacitance electrode IO is provided on the third insulating layer 13 and the metal layer TM. The storage capacitance electrode IO is made of a light-transmitting conductive material such as ITO (Indium Tin Oxide). The storage capacitance electrode IO is also called a third light-transmitting electrode. As shown in FIG. 11, the storage capacitance electrode IO has an area IOX surrounded by the scanning line GL and the signal line SL where there is no light-transmitting conductive material. The storage capacitance electrode IO is provided across a plurality of pixels Pix, straddling adjacent pixels Pix. The storage capacitance electrode IO has an area where the light-transmitting conductive material is present that overlaps the scanning line GL or the signal line SL and extends to the adjacent pixel Pix.

[0064] The storage capacitance electrode IO is in a lattice shape that covers the scanning lines GL and the signal lines SL along the scanning lines GL and the signal lines SL. This reduces the storage capacitance HC between the region IOX without the translucent conductive material and the pixel electrode PE, so that the storage capacitance HC is adjusted by the size of the region IOX without the translucent conductive material.

[0065] 12, a switching element Tr is provided that is connected to a scanning line GL and a signal line SL, and at least the switching element Tr is covered with a third insulating layer 13 that is an organic insulating layer, and a metal layer TM having an area larger than that of the switching element Tr is provided above the third insulating layer 13. This makes it possible to suppress light leakage from the switching element Tr.

[0066] More specifically, the array substrate 10 includes a third insulating layer 13, which is an organic insulating layer covering at least the switching element Tr, and a metal layer TM that is provided above the third insulating layer 13 and has an area larger than that of the switching element Tr. In the region surrounded by the scanning line GL and the signal line SL, there is a region whose thickness is smaller than that of the third insulating layer 13 that overlaps the scanning line GL and the signal line SL in a plan view. Therefore, a slope is formed in which the thickness of the third insulating layer 13 changes on the side closer to the light source 3 than the switching element Tr in a plan view. As shown in FIG. 5, the light source light L irradiated from the light source 3 is incident with the second direction PY as the incident direction. As shown in FIG. 15, the above-mentioned slope includes a first slope 13F of the third insulating layer 13 on the side where the light Lu of the light source light L is incident, and a second slope 13R of the third insulating layer 13 on the opposite side to the side where the light Lu is incident. 15, the first slope 13F of the third insulating layer 13 on the side where the light Lu is incident is covered with a metal layer TMt. Here, the metal layer TMt is made of the same material as the metal layer TM and is a tapered portion formed by extending the metal layer TM.

[0067] 15, light Lu arrives in the incident direction. The light Lu is a part of the light source light L that arrives from a side closer to the light source 3 than the switching element Tr. Here, the metal layer TMt blocks the light Lu, thereby reducing light leakage.

[0068] When the second inclined surface 13R is covered with a metal layer TM and the background of the counter substrate 20 is visible from the array substrate 10, the light Ld2 seen by the viewer may be reflected by the metal layer TM covering the second inclined surface 13R, and the reflected light may be visible to the viewer. In the first embodiment, there is no metal layer TM covering the second inclined surface 13R. Therefore, in the display device of the first embodiment, the reflected light that interferes with the viewer's visibility is reduced.

[0069] The metal layer TM may be on the storage capacitance electrode IO, and may be laminated with the storage capacitance electrode IO. The metal layer TM has a smaller electrical resistance than the storage capacitance electrode IO. This suppresses the variation in the potential of the storage capacitance electrode IO depending on the position of the pixel Pix in the display area AA.

[0070] As shown in FIG. 12, in a plan view, the width of the metal layer TM overlapping the signal line SL is greater than the width of the signal line SL. This prevents light reflected at the edge of the signal line SL from being emitted from the display panel 2. Here, the width of the metal layer TM and the width of the signal line SL are lengths in a direction intersecting the direction in which the signal line SL extends. In addition, the width of the metal layer TM overlapping the scanning line GL is greater than the width of the scanning line GL. Here, the width of the metal layer TM and the width of the scanning line GL are lengths in a direction intersecting the direction in which the scanning line GL extends.

[0071] 15, a fourth insulating layer 14 is provided on the storage capacitor electrode IO and the metal layer TM. The fourth insulating layer 14 is an inorganic insulating layer formed of a transparent inorganic insulating material such as silicon nitride.

[0072] As shown in Fig. 15, a pixel electrode PE is provided on the fourth insulating layer 14. The pixel electrode PE is made of a light-transmitting conductive material such as ITO. The pixel electrode PE is electrically connected to the contact electrode DEA via a contact hole CH provided in the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12. As shown in Fig. 13, the pixel electrode PE is partitioned for each pixel Pix. A first alignment film AL1 is provided on the pixel electrode PE.

[0073] As shown in FIG. 15, the counter substrate 20 has a second light-transmitting base material 29 made of, for example, glass. The second light-transmitting base material 29 may be a resin such as polyethylene terephthalate as long as it has light-transmitting properties. A common electrode CE is provided on the second light-transmitting base material 29. The common electrode CE is made of a light-transmitting conductive material such as ITO. A second alignment film AL2 is provided on the surface of the common electrode CE. The counter substrate 20 also has a light-shielding layer LS between the second light-transmitting base material 29 and the common electrode CE. The light-shielding layer LS is made of a black resin or metal material. A spacer PS is also formed between the array substrate 10 and the counter substrate 20, and the spacer PS is between the common electrode CE and the second alignment film AL2.

[0074] 12 and 16, in the display device of the first embodiment, a light-shielding layer GS, which is the same layer as the scanning lines GL, is provided at a position that extends along the signal lines SL and overlaps with a part of the signal lines SL. The light-shielding layer GS is made of the same material as the scanning lines GL. The light-shielding layer GS is not provided at the portion where the scanning lines GL and the signal lines SL intersect in a plan view.

[0075] As shown in Fig. 12, the light-shielding layer GS and the signal line SL are electrically connected by a contact hole CHG. This reduces the wiring resistance of the light-shielding layer GS and the signal line SL compared to the wiring resistance of only the signal line SL. As a result, the delay of the grayscale signal supplied to the signal line SL is suppressed. Note that the light-shielding layer GS and the signal line SL do not necessarily have to be connected without the contact hole CHG.

[0076] As shown in FIG. 16, the light-shielding layer GS is provided on the opposite side of the signal line SL to the metal layer TM. The width of the light-shielding layer GS is larger than the width of the signal line SL and smaller than the width of the metal layer TM. The width of the light-shielding layer GS, the width of the metal layer TM, and the width of the signal line SL are lengths in a direction intersecting the direction in which the signal line SL extends. In this way, since the light-shielding layer GS is wider than the signal line SL, it suppresses the reflected light reflected at the edge of the signal line SL from being emitted from the display panel 2. As a result, the visibility of images in the display device 1 is improved.

[0077] 14 and 15, a light-shielding layer LS is provided on the counter substrate 20. The light-shielding layer LS is provided in an area overlapping the signal lines SL, the scanning lines GL, and the switching elements Tr in a plan view.

[0078] 14, 15, 16, and 17, the light-shielding layer LS has a width greater than that of the metal layer TM. This prevents light reflected at edges of the signal lines SL, the scanning lines GL, and the metal layer TM from being emitted from the display panel 2. As a result, the visibility of images in the display device 1 is improved.

[0079] The contact holes CH and CHG are prone to diffuse reflection when struck by the light source light L. For this reason, the light shielding layer LS is provided in an area overlapping the contact holes CH and CHG in plan view.

[0080] As shown in FIG. 15, spacers SP are disposed between the array substrate 10 and the counter substrate 20 to improve the uniformity of the distance between the array substrate 10 and the counter substrate 20. As shown in FIG.

[0081] Fig. 18 is an explanatory diagram for explaining the relationship between a viewer viewing the background on the other side of one surface from one surface, and the background. Fig. 19 is an explanatory diagram for explaining an example in which a peripheral area is superimposed on the background. As shown in Fig. 18, when a viewer IB views the display device 1 from one side to the other, The background BS1 is visible through the display device 1. As shown in Fig. 19, if the first peripheral region FR1 outside the display area AA does not transmit light, the background BS1 will not be visible, which may cause an uncomfortable feeling. Therefore, the first peripheral region FR1 and the second peripheral region FR2 also allow the background BS1 on the other side of the display device 1 to be visible from one side of the display device 1.

[0082] FIG. 20 is a plan view for explaining the peripheral region of the first embodiment. FIG. 21 is a plan view showing a schematic cross section of XXI-XXI' in FIG. 20. The peripheral region FR shown in FIG. 1 has a first peripheral region FR1 and a second peripheral region FR2 shown in FIG. 20. The first peripheral region FR1 and the second peripheral region FR2 sandwich the display region AA in the first direction PX. The second wiring GPL is disposed in the second portion Q2 of the second peripheral region FR2. As shown in FIG. 2, the second wiring GPL electrically connects the gate driving circuit 43 of the driving circuit 4 and the scanning line GL. The second wiring GPL is formed in the same layer as the scanning line GL and is formed of the same material.

[0083] In the first embodiment, the first peripheral region FR1 does not have a wiring that electrically connects the gate drive circuit 43 and the scanning line GL. The second wiring GPL reduces the transmittance of the second peripheral region FR2. Here, if the transmittance of the first peripheral region FR1 and the transmittance of the second peripheral region FR2 are significantly different, the viewer may feel uncomfortable. Therefore, as shown in FIG. 20, in the display device 1 of the first embodiment, the first wiring DPL is arranged in the first portion Q1 of the first peripheral region FR1. As shown in FIG. 21, the first wiring DPL is formed in the same layer as the scanning line GL and is formed of the same material. Therefore, the transmittance of the first peripheral region FR1 and the transmittance of the second peripheral region FR2 are approximately the same.

[0084] The first wiring DPL is connected to the common potential drive circuit 45 shown in Fig. 2 and has approximately the same potential as the above-mentioned common potential wiring COML. This reduces noise generated in the display area AA. The first wiring DPL is not limited to the common potential, and may have any constant potential.

[0085] As shown in FIG. 21, the counter substrate 20 includes a light-shielding layer LS that covers at least a part of the signal line SL and the scanning line GL. In contrast, the light-shielding layer LS does not cover the first wiring DPL and the second wiring GPL. As a result, the light-shielding layer LS is not arranged in the first peripheral region FR1, so light is easily transmitted. However, the viewer is also more likely to notice the difference in contrast between the first peripheral region FR1 and the second peripheral region FR2. Therefore, as shown in FIG. 20, in the first embodiment, the shape of the first wiring DPL in the first peripheral region FR1 is a mirror image of the shape of the second wiring GPL in the second peripheral region FR2. As a result, the viewer is less likely to notice the difference in contrast between the first peripheral region FR1 and the second peripheral region FR2. In this way, the first wiring DPL is not connected to the scanning line GL, so it can be said to be a dummy wiring of the second wiring GPL.

[0086] As described above, the display device 1 includes the array substrate 10, the counter substrate 20, the liquid crystal layer 50, and the light source 3. The array substrate 10 includes a plurality of pixel electrodes PE, which are first translucent electrodes arranged for each pixel Pix. The array substrate 10 includes a plurality of signal lines SL spaced apart in the first direction PX and a plurality of scanning lines GL spaced apart in the second direction PY. The counter substrate 20 includes a common electrode CE, which is a second translucent electrode, at a position overlapping the pixel electrode PE in a plan view. The liquid crystal layer 50 includes a polymer-dispersed liquid crystal LC sealed between the array substrate 10 and the counter substrate 20. The light-emitting section 31 of the light source 3 emits light toward the side surface of the counter substrate 20 in the second direction PY. The incident direction of the light propagating through the array substrate 10 and the counter substrate 20 is the second direction. The light-emitting section 31 may emit light propagating through the array substrate 10 and the counter substrate 20 toward the side surface of the array substrate 10.

[0087] In the display area AA, the array substrate 10 has a plurality of signal lines SL spaced apart in the first direction PX and a plurality of scanning lines GL spaced apart in the second direction PY. A first peripheral area FR1 outside the display area AA has a plurality of first wirings DPL to which a constant potential is supplied. A second peripheral area FR2 on the opposite side of the display area AA to the first peripheral area FR1 has a plurality of second wirings GPL connected to the scanning lines GL. This allows the background BS1 to be viewed in the first peripheral area FR1 or the second peripheral area FR2 without any sense of incongruity when comparing the first peripheral area FR1 outside the display area AA with the second peripheral area FR2.

[0088] (Embodiment 2) Fig. 22 is a plan view for explaining the peripheral region of the second embodiment. Fig. 23 is a plan view for explaining an enlarged first portion of the peripheral region of the second embodiment. Fig. 24 is a plan view for explaining an enlarged second portion of the peripheral region of the second embodiment. Fig. 25 is a plan view showing a schematic cross section of XXV-XXV' in Fig. 23. The same components as those explained in the above-mentioned present embodiment are given the same reference numerals and redundant explanations will be omitted.

[0089] 22, the first wirings DPL are arranged in the first portion Q11 of the first peripheral region FR1. The second wirings GPL connected to the scanning lines GL are arranged in the second portion Q21 of the second peripheral region FR2.

[0090] As shown in Fig. 23, in the second embodiment, the first wiring DPL extends to have a first angle α with the second direction PY. The extending direction of the first wiring DPL is non-orthogonal to the second direction PY. In the second embodiment, as in the first embodiment, the incident direction of the light source light L is the second direction PY, so the extending direction of the first wiring DPL is non-orthogonal to the incident direction of the light source light L. If the first wiring DPL extends obliquely with respect to the second direction PY, the light source light L is reflected at the edge of the first wiring DPL in a direction different from the second direction PY, and is less noticeable.

[0091] In the first peripheral region FR1, a mesh-like metal layer FCM1 is located outside the region occupied by the first wiring DPL. The metal layer FCM1 is connected to the common potential driving circuit 45 shown in FIG. 2 and becomes a part of the above-mentioned common potential wiring COML. This reduces noise generated in the display region AA. The first wiring DPL is electrically connected to the metal layer FCM1 via the third wiring CPL. The third wiring CPL is arranged at intervals in the second direction PY. Adjacent third wiring CPLs should have an interval larger than the interval between adjacent scanning lines GL. This makes the third wiring CPL less noticeable and invisible.

[0092] As shown in FIG. 24, in the second embodiment, the second wiring GPL extends to have a second angle β with the second direction PY. The extension direction of the second wiring GPL is non-orthogonal to the second direction PY. In the second embodiment, as in the first embodiment, the incident direction of the light source light L is the second direction PY, so the extension direction of the second wiring GPL is non-orthogonal to the incident direction of the light source light L. If the second wiring GPL extends obliquely with respect to the second direction PY, the light source light L is reflected at the edge of the second wiring GPL in a direction different from the second direction PY and is less noticeable. In the second embodiment, the first angle α and the second angle β are the same. This makes it difficult for the viewer to notice the difference in contrast between the first peripheral region FR1 and the second peripheral region FR2.

[0093] In the second peripheral region FR2, a mesh-like metal layer FCM2 is present outside the region occupied by the second wiring GPL. The metal layer FCM2 is connected to the common potential drive circuit 45 shown in FIG. 2 and becomes a part of the above-mentioned common potential wiring COML. This reduces noise generated in the display region AA. At least one of the metal layers FCM1 and FCM2 is electrically connected to the common electrode CE of the counter substrate 20 via a conductive conductive pillar. The conductive pillar may also be a sealant containing conductive particles such as Au particles.

[0094] As shown in FIG. 25, the metal layer FCM1 is formed in the same layer as the first wiring DPL and is made of the same material as the first wiring DPL. The light-shielding layer LS does not cover the metal layer FCM1. As a result, the light-shielding layer LS is not arranged in the first peripheral region FR1, so light is easily transmitted through the first peripheral region FR1. Since the metal layer FCM1 is mesh-shaped, light is transmitted through the openings where there is no metal. Similarly, the metal layer FCM2 is formed in the same layer as the second wiring GPL and is made of the same material as the second wiring GPL. The light-shielding layer LS does not cover the metal layer FCM2. As a result, the light-shielding layer LS is not arranged in the second peripheral region FR2, so light is easily transmitted through the second peripheral region FR2.

[0095] 22, in the second embodiment, the shape of the metal layer FCM1 in the first peripheral region FR1 is a mirror image of the shape of the metal layer FCM2 in the second peripheral region FR2, making it difficult for a viewer to notice the difference in contrast between the first peripheral region FR1 and the second peripheral region FR2.

[0096] (Modification 1 of the second embodiment) 26 is an enlarged plan view illustrating a first portion of the peripheral region of Modification 1 of Embodiment 2. The same components as those described in the above embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0097] In the first modification of the second embodiment, as shown in FIG. 23, when the first side of the mesh-like metal layer FCM1 extends in the first direction PX, it is perpendicular to the incident direction of the light source light L. Then, as shown in FIG. 25, the light source light L hits the first side of the mesh-like metal layer FCM1, and reflected light is likely to occur. The reflected light reaches the viewer as diffracted light, and there is a possibility that the viewer recognizes partial coloring. Therefore, in the first modification of the second embodiment, the mesh-like metal layer FCM1 is made rhombic. And, the incident direction is non-orthogonal to the metal layer FCM1 of the first side constituting the mesh. Also, the incident direction is non-orthogonal to the metal layer FCM1 of the second side constituting the mesh and extending in a direction different from the first side. As a result, the reflected light is scattered, making it difficult for the viewer to recognize it. As a result, partial coloring of the first peripheral region FR1 is suppressed.

[0098] In the first modification of the second embodiment, the mesh-like metal layer FCM1 extends to have a third angle γ with the second direction PY. The third angle γ is larger than the first angle α. This makes it difficult for diffraction to occur due to interaction between the first wiring DPL and the mesh-like metal layer FCM1.

[0099] In the first modification of the second embodiment, the mesh-shaped metal layer FCM1 has been described as an example, but the same effect can be obtained by forming the metal layer FCM2 shown in FIG. 24 in a diamond shape. In FIG. 24, the incident direction is non-orthogonal to the metal layer FCM2 of the first side constituting the mesh. Also, the incident direction is non-orthogonal to the metal layer FCM2 of the second side constituting the mesh and extending in a direction different from the first side. As a result, the reflected light is scattered, making it difficult for the viewer to recognize it. As a result, partial coloring of the second peripheral region FR2 is suppressed.

[0100] (Modification 2 of the second embodiment) 27 is an enlarged plan view illustrating a first portion of the peripheral region of Modification 2 of Embodiment 2. The same components as those described in the above embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0101] In the second modification of the second embodiment, the third wiring CPL extends to have a fifth angle ε with the second direction PY. The extension direction of the third wiring CPL is non-orthogonal to the incident direction. If the third wiring CPL extends obliquely with respect to the second direction PY, the light source light L is reflected at the edge of the third wiring CPL in a direction different from the second direction PY, making it less noticeable.

[0102] The third wiring CPL desirably extends in the same direction as the first side or the second side of the metal layer FCM1, so that the third angle γ and the fifth angle ε are made to coincide with each other, and the third wiring CPL is easily made invisible.

[0103] (Modification 3 of the second embodiment) Fig. 28 is an enlarged plan view illustrating a first portion of the peripheral region of Modification 3 of Embodiment 2. Fig. 29 is an enlarged plan view illustrating a second portion of the peripheral region of Modification 3 of Embodiment 2. The same components as those described in the present embodiment above are given the same reference numerals and redundant description will be omitted.

[0104] In the third modification of the second embodiment, the mesh-like metal layer FCM1 extends to have a third angle δ with the second direction PY. The third angle δ is substantially the same as the first angle α. In this manner, the angle (first angle α) between the first side of the mesh-like metal layer FCM1 and the incident direction of the light source light L is the same as the angle (third angle δ) between the extension direction of the first wiring DPL and the incident direction. This makes the boundary between the first wiring DPL and the mesh-like metal layer FCM1 less noticeable.

[0105] The distance P1 in the first direction PX between adjacent first wirings DPL is approximately the same as the distance P2 in the first direction PX between the metal layer FCM1 and the first wiring DPL. Here, approximately the same distance means, for example, that the difference between the two distances is within a range of the difference not greater than the width of the first wiring DPL in the first direction PX (the same applies hereinafter in this disclosure). This makes the boundary between the first wiring DPL and the mesh-like metal layer FCM1 less noticeable.

[0106] In the mesh-like metal layer FCM1, the maximum distance P4 in the first direction PX exists between two bends. In the metal layer FCM1 adjacent to the first wiring DPL, the distance P3 between the two metal layers FCM1 in the first direction PX is smaller than the distance P4.

[0107] In FIG. 29, the incident direction (second direction PY) and the metal layer FCM2 of the first side constituting the mesh are non-orthogonal. Also, the incident direction and the metal layer FCM2 of the second side constituting the mesh and extending in a direction different from the first side are non-orthogonal. As a result, the reflected light is scattered and becomes difficult for the viewer to recognize. As a result, partial coloring of the second peripheral region FR2 is suppressed. The mesh-like metal layer FCM2 extends to have a fourth angle θ with the second direction PY. The fourth angle θ is approximately the same angle as the second angle β. This makes the boundary between the second wiring GPL and the mesh-like metal layer FCM2 less noticeable.

[0108] In the second peripheral region FR2, a mesh-like metal layer FCM2 is located outside the region occupied by the second wiring GPL. If the distance in the first direction PX between the metal layer FCM2 and the second wiring GPL is greater than the distance P11 in the first direction PX between adjacent second wiring GPL, the space between the metal layer FCM2 and the second wiring GPL may be noticeable and visually recognized. Therefore, as shown in FIG. 29, a fourth wiring DGPL is disposed in the region between the metal layer FCM2 and the second wiring GPL.

[0109] The fourth wiring DGPL is formed in the same layer as the scanning line GL and is formed of the same material. The fourth wiring DGPL is a dummy wiring of the second wiring GPL and is not electrically connected to the gate drive circuit 43 and the scanning line GL. The fourth wiring DGPL is connected to the common potential drive circuit 45 shown in FIG. 2 and has approximately the same potential as the above-mentioned common potential wiring COML. The fourth wiring DGPL is not limited to the common potential, and may have any potential as long as it is a constant potential. Since a dummy wiring extending in the same direction as the extension direction of the second wiring GPL is disposed between the second wiring GPL and the metal layer FCM2, the space between the metal layer FCM2 and the second wiring GPL is made invisible.

[0110] The distance P12 in the first direction PX between adjacent fourth wirings DGPL is approximately the same as the distance P11 described above. The distance in the first direction PX between the fourth wiring DGPL and the second wiring GPL is also approximately the same as the distance P11 described above. The distance P13 in the first direction PX between the metal layer FCM2 and the second wiring GPL is approximately the same as the distance P12. This makes the boundary between the fourth wiring DGPL and the mesh-like metal layer FCM2 less noticeable.

[0111] In the mesh-like metal layer FCM2, the maximum distance P15 in the first direction PX exists between two bends. In the metal layer FCM2 adjacent to the fourth wiring DGPL, the distance P14 between the two metal layers FCM1 in the first direction PX is smaller than the distance P15.

[0112] (Fourth Modification of the Second Embodiment) Fig. 30 is an enlarged plan view illustrating a first portion of the peripheral region of Variation 4 of Embodiment 2. Fig. 31 is an enlarged plan view illustrating a second portion of the peripheral region of Variation 4 of Embodiment 2. The same components as those described in the above-mentioned present embodiment are given the same reference numerals and redundant description will be omitted.

[0113] 30, in the mesh-like metal layer FCM1, there is a maximum distance P4 in the first direction PX between two bends. In the metal layer FCM1 adjacent to the first wiring DPL, the distance P3 between the two metal layers FCM1 in the first direction PX is approximately the same as the distance P4. This makes the boundary between the first wiring DPL and the mesh-like metal layer FCM1 less noticeable.

[0114] In the mesh-like metal layer FCM2, the maximum distance P15 in the first direction PX exists between the two bends. In the metal layer FCM2 adjacent to the fourth wiring DGPL, the distance P14 between the two metal layers FCM1 in the first direction PX is approximately the same as the distance P15. This makes the boundary between the fourth wiring DGPL and the mesh-like metal layer FCM2 less noticeable.

[0115] Although the preferred embodiment has been described above, the present disclosure is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally belong to the technical scope of the present disclosure.

[0116] For example, in the present disclosure, the switching element Tr has been described as being of a bottom gate type, but as described above, the switching element Tr is not limited to a bottom gate structure and may be of a top gate type. If the switching element Tr is of a top gate type, referring to the insulating film stack structure of FIG. 15, the semiconductor layer SC is disposed between the first light-transmitting base material 19 and the first insulating layer, the gate electrode GE is disposed between the first insulating layer 11 and the second insulating layer 12, and the source electrode SE and the contact electrode DEA are formed between the second insulating layer 12 and the third insulating layer 13.

[0117] Furthermore, the common potential may be a DC voltage, i.e., a constant common potential, or may be an AC voltage shared, i.e., a common potential having two limits, an upper limit and a lower limit. Whether the common potential is DC or AC, a common potential is supplied to the storage capacitance electrode IO and the common electrode CE.

[0118] In addition, with respect to the third insulating layer 13, which is a lattice-shaped organic insulating film, a structure is disclosed in which the third insulating layer 13 inside the lattice is completely removed to expose the second insulating layer 12 and the storage capacitor electrode IO underneath, but the present invention is not limited to this. For example, the third insulating layer 13 may be left partially thin inside the lattice region surrounded by the signal lines SL and the scanning lines GL by halftone exposure. As a result, the third insulating layer 13 is thinner inside the lattice region than the lattice region surrounded by the signal lines SL and the scanning lines GL.

[0119] In the third modification of the second embodiment and the fourth modification of the second embodiment, the fourth wiring DGPL may be omitted, and the second wiring GPL may be arranged instead of the fourth wiring DGPL. [Explanation of symbols]

[0120] 1 Display device 2 Display Panel 3 light source 4. Drive circuit 9 Upper control section 10 Array Board 11 First insulating layer 12 Second insulating layer 13 Third insulating layer 13F 1st slope 13R 2nd slope 14 Fourth insulating layer 18 Sealing part 19 First translucent base material 20 Opposing substrate 20C 1st side 20D 2nd side 29 Second translucent base material AA display area CE common electrode DPL 1st wiring DGPL 4th wiring FCM1 Metal Layer FCM2 Metal Layer FR peripheral areas FR1 Week 1 Field FR2 2nd peripheral area GL Tracking Line GPL 2nd wiring L Light source LC Polymer Dispersed Liquid Crystal LS light shielding layer PX 1st direction PY 2nd Direction PZ 3rd direction Pix pixel SL Signal Cable α 1st angle β 2nd angle γ, δ 3rd angle θ 4th angle ε 5th angle

Claims

1. An array substrate; An opposing substrate; a liquid crystal layer between the array substrate and the counter substrate; a light source arranged so that light enters a side surface of the array substrate or a side surface of the counter substrate; The array substrate includes: In the display area, A plurality of signal lines arranged at intervals in a first direction; a plurality of scan lines spaced apart in a second direction; having A mesh-like metal layer is provided in a peripheral area outside the display area, a direction of incidence from a first side surface closest to the light source toward a surface facing the first side surface is non-orthogonal to a first side constituting the mesh of the metal layer; the incident direction is non-orthogonal to a second side that constitutes the mesh and extends in a direction different from the first side, In the peripheral region, the background of the counter substrate is visible from the array substrate, and the background of the array substrate is visible from the counter substrate. Display device.

2. A driving circuit is arranged in the peripheral region, a first peripheral region of the peripheral region includes a plurality of first wirings that are connected to the drive circuit and are supplied with a constant potential; The display device according to claim 1 , wherein the extending direction of the first wirings and the second direction are non-orthogonal to each other.

3. a second peripheral region on the opposite side of the display region from the first peripheral region, the second wirings being connected to the scanning lines; The display device according to claim 2 , wherein a first angle formed between a direction in which the first wirings extend and the second direction is the same as a second angle formed between a direction in which the second wirings extend and the second direction.

4. A driving circuit is arranged in the peripheral region, a first peripheral region of the peripheral region includes a plurality of first wirings that are connected to the drive circuit and are supplied with a constant potential; The display device according to claim 1 , wherein the mesh-like metal layer is present in the first peripheral region outside a region occupied by the first wiring.

5. The display device according to claim 2 , wherein the metal layer is in the same layer as the first wiring.

6. The display device according to claim 2 , further comprising a third wiring that connects the metal layer and the first wiring.

7. 7. The display device according to claim 2, wherein an angle formed between the first side and the incident direction is the same as an angle formed between a direction in which the first wiring extends and the incident direction.

8. a second peripheral region on the opposite side of the display region from the first peripheral region, the second wirings being connected to the scanning lines; 8. A display device as claimed in any one of claims 2 to 7, wherein the mesh-like metal layer is located in the second peripheral region outside the region occupied by the second wiring, and dummy wiring is arranged between the second wiring and the metal layer, extending in the same direction as the extension direction of the second wiring.

9. the opposing substrate includes a light-shielding layer that covers at least a portion of the signal lines and the scanning lines; The display device according to claim 2 , wherein the light-shielding layer does not cover the first wiring.

10. 10. The display device of claim 1, wherein the metal layer is rhomboidal.

11. The display device according to claim 1 , wherein the liquid crystal layer is a polymer dispersed liquid crystal.

Images