Information processing device, memory control program, and information processing method

Abstract

To provide a technique for reducing a load of a processor by reducing the occurrence of a spinlock.SOLUTION: A computer system 1a includes: a primary memory 30 for storing data of a page unit; a secondary memory 20 for storing data of a page being a moving object from the primary memory; and a movement processing part for moving a first management information storage area 31 provided in each of a plurality of arithmetic cores 11 to store a plurality of first links 33 showing a movement order of each page in a page group allocated to each of the plurality of arithmetic cores 11 in a plurality of pages, a second management information storage area 31 provided for an operating system to store a second link 32 for managing a plurality of pages selected according to a movement order from the page group in the plurality of first links as a candidate page group to be moved to the secondary memory from the primary memory to the secondary memory.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an information processing device, a memory control program, Muo and an information processing method. [Background technology]

[0002] Hierarchical memory control is sometimes used to divide the memory space seen by an application into high-speed memory and low-speed memory and create a hierarchy. In hierarchical memory control, a memory expansion technology is known that enables the use of memory with a capacity greater than that of dynamic random access memory (DRAM) by using storage such as solid state drives (SSD) as low-speed memory. In such memory expansion technology, it is common to use a portion of the DRAM as a cache memory for low-speed memory.

[0003] The cache memory is managed in units of pages. The data size of a page is, for example, 4 KB. The process of moving a page from the cache memory to storage is executed by a background thread. The data (pages) to be moved from cache memory to storage are selected using the LRU (Least Recently Used) algorithm.

[0004] An LRU list is used to manage the priority of pages to be moved to storage. The LRU list stores a pointer to a page structure that stores page information (such as addresses), an access flag that indicates when a page has been accessed, and link information for the list.

[0005] Then, by referring to the LRU list thus constructed, the page that has not been accessed for the longest period of time is determined as the page to be moved (cached out) to the storage. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-27444 A [Patent Document 2] JP 2019-95881 A Summary of the Invention [Problem to be solved by the invention]

[0007] In a multi-core CPU equipped with multiple central processing unit (CPU) cores, multiple threads (multi-threads) executed by the multiple CPU cores access the LRU list. A thread that specifies a page to be moved from cache memory to storage also accesses the LRU list to refer to it.

[0008] Therefore, when a thread accesses an LRU list, exclusive control is required to lock the LRU list to prevent other threads from changing it. If a thread tries to reference an LRU list and that LRU list is locked, that thread will use a spinlock to wait until the lock on the LRU list is released.

[0009] In such a conventional hierarchical memory control method, there is a problem that the CPU load increases due to spinlocks for exclusive processing by locking the LRU list, resulting in a decrease in performance. In one aspect, the present invention reduces the burden on the processor by reducing the occurrence of spinlocks. [Means for solving the problem]

[0010] For this reason, the information processing device includes a primary memory in which data in units of pages is stored, a secondary memory in which data of a page to be moved from the primary memory is stored, a processor having a plurality of arithmetic cores, and a memory for storing the data of the page to be moved from the primary memory. , multiple Number The aboveA plurality of first lists indicating the order of movement of each page in a page group allocated to each of the plurality of processing cores among the pages. Strike a first management information storage area for storing the first links; Strike a second link that manages a plurality of pages selected from the page group in the second memory according to the order of the transfer as a page group of candidates to be transferred to the secondary memory; Strike a second management information storage area for storing the second link; Strike and a transfer processing unit that transfers data of a page selected from the page group from the primary memory to the secondary memory. Also, At least one of the multiple computing cores updates the first list provided for that computing core by executing a first thread, and adds to the second list a plurality of pages selected from the group of pages in the first list provided for that computing core according to the order of the movement by executing a second thread. Effect of the Invention

[0011] According to one embodiment, the load on the processor can be reduced by reducing the occurrence of spinlocks. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a computer system as an example of a first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining hierarchical memory control in a computer system as an example of the first embodiment. [Diagram 3] 2 is a diagram for explaining the operational relationship between a per-CPU-core LRU list and an OS LRU list in a computer system as an example of the first embodiment; FIG. [Figure 4] 2 is a diagram for explaining DRAM areas targeted by a CPU core LRU list and an OS LRU list in a computer system as an example of the first embodiment; FIG. [Diagram 5] FIG. 2 is a diagram illustrating an example of a migration information table in the computer system as an example of the first embodiment. [Figure 6] FIG. 2 is a diagram for explaining a page management method in a computer system as an example of the first embodiment. [Figure 7] 11 is a flowchart illustrating a process of updating a per-CPU-core LRU list by a thread in a computer system as an example of the first embodiment. [Figure 8] 11 is a flowchart illustrating a process by a page movement thread in a computer system as an example of the first embodiment. [Figure 9] 11 is a flowchart illustrating a process performed by an OS-associated page migration thread in a computer system as an example of the first embodiment. [Figure 10] 11 is a flowchart illustrating a process by a list deletion thread in a computer system as an example of the first embodiment. [Figure 11] FIG. 11 is a diagram illustrating a schematic configuration of a computer system as an example of a second embodiment. [Figure 12] FIG. 11 is a diagram illustrating an example of a page correspondence table in a computer system as an example of the second embodiment. [Figure 13] FIG. 11 is a diagram for explaining a page management method in a computer system as an example of the second embodiment. [Figure 14] 13 is a flowchart illustrating a process of updating a per-CPU-core LRU list by a thread in a computer system as an example of the second embodiment. [Figure 15] 13 is a flowchart illustrating a process by a page movement thread in a computer system as an example of the second embodiment. [Figure 16] 13 is a flowchart illustrating a process performed by an OS-dependent page migration thread in a computer system as an example of the second embodiment. [Figure 17] FIG. 13 is a diagram illustrating a schematic configuration of a computer system as an example of a third embodiment. [Figure 18] FIG. 13 is a diagram for explaining a page management method in a computer system as an example of a third embodiment. [Figure 19]13 is a flowchart illustrating a process of updating a per-CPU-core LRU list by a thread in a computer system as an example of the third embodiment. [Figure 20] 13 is a flowchart illustrating a process by a page movement thread in a computer system as an example of the third embodiment. [Figure 21] 13 is a flowchart illustrating a process by an OS-assigned page migration thread in a computer system as an example of the third embodiment. [Figure 22] FIG. 13 is a diagram illustrating an example of a functional configuration of a computer system according to a fourth embodiment. [Diagram 23] FIG. 13 is a diagram illustrating a process of a cache redistribution determination unit of a computer system as an example of the fourth embodiment. [Figure 24] 13 is a flowchart illustrating a page movement process in a computer system as an example of the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments of the present information processing device, memory control program, information processing program, and information processing method will be described with reference to the drawings. However, the embodiments shown below are merely examples, and there is no intention to exclude the application of various modified examples and techniques not explicitly stated in the embodiments. In other words, this embodiment can be implemented with various modifications (combinations of the embodiments and each modified example, etc.) without departing from the spirit of the present invention. Furthermore, each figure is not intended to include only the components shown in the figure, but may include other functions, etc.

[0014] [1. Description of the First Embodiment] (A) Configuration FIG. 1 is a diagram illustrating a schematic configuration of a computer system 1a as an example of the first embodiment. The computer system 1a illustrated in FIG.

[0015] Processor 10 is a multi-core processor equipped with multiple CPU cores 11-0, 11-1, 11-2, etc. Hereinafter, when there is no particular need to distinguish between CPU cores 11-0, 11-1, 11-2, etc., they will be referred to as CPU core 11. Furthermore, CPU core 11-0 may be referred to as CPU core #0. Similarly, CPU core 11-1 may be referred to as CPU core #1, and CPU core 11-2 may be referred to as CPU core #2. Each CPU core 11 is an arithmetic core that executes a thread.

[0016] The processor 10 also includes a PCIe root (Peripheral Component Interconnect Express Root) port 12 and a memory controller 13.

[0017] An SSD 20 is connected to the PCIe root port 12, and a DRAM 30 is connected to the memory controller 13. The SSD 20 may be connected in accordance with the NVMe (Non-Volatile Memory Express) standard, and may be implemented in various modified forms. This computer system 1a realizes hierarchical memory control. FIG. 2 is a diagram for explaining hierarchical memory control in a computer system 1a as an example of the first embodiment.

[0018] In the hierarchical memory control, the DRAM 30 is used as a high-speed memory, and the SSD 20 is used as a low-speed memory. Also, a part of the storage area of ​​the DRAM 30 is used as a cache memory (hereinafter, sometimes simply referred to as a cache) 30a.

[0019] The cache 30a is managed in units of pages. The data size of a page is, for example, 4 KB. The process of moving a page from the cache 30a to storage is executed by a page movement thread, which will be described later. The cache 30a corresponds to a primary memory in which data is stored in units of pages.

[0020] In the computer system 1a, data (pages) to be moved from the cache 30a to the SSD 20 are selected by an LRU algorithm, and the selected pages are moved from the cache 30a to the SSD 20.

[0021] The SSD 20 is a storage device that uses semiconductor element memory, and as described above, a part of the storage area is used as memory (low-speed memory).

[0022] In addition, in the storage area of ​​the SSD 20, pages moved from the cache 30a (described later) are stored in areas other than the area used as a low-speed memory. The process of moving pages on the cache 30a to the SSD 20 may be called cache out, or may be called eviction processing or collection processing. The SSD 20 corresponds to a secondary memory that stores data of pages to be moved from the cache 30a.

[0023] Pages evicted from the cache 30a are stored in the SSD 20. Pages evicted from the cache 30a and moved to the SSD 20 may be called moved data. In the example shown in FIG. 1, pages of each CPU core 11 evicted from the cache 30a are stored as moved data 21. The DRAM 30 is a semiconductor memory that allows faster data access than the SSD 20.

[0024] A part of the storage area of ​​the DRAM 30 is used as a high-speed memory by an application executed by the CPU core 11, and another part of the storage area is used as a cache memory (cache) 30a by the application. In the example shown in FIG. 1, the storage area of ​​the DRAM 30 includes a kernel area 31 and a user area .

[0025] The user area 36 is, for example, a storage area used by applications executed by each CPU core 11, and stores data 37 used by each CPU core 11.

[0026] The kernel area 31 is a storage area used by the kernel of an OS (Operating System) executed by the CPU core 11. In this embodiment, an example in which the OS is Linux (registered trademark) is shown.

[0027] In the example shown in FIG. 1, kernel area 31 stores OS LRU list 32, migration information table 34, and per-CPU-core LRU lists 33-0, 33-1, . . . .

[0028] --CPU core LRU list 33-- The per-CPU-core LRU lists 33-0, 33-1, . . . are LRU lists provided for each CPU core 11.

[0029] The per-CPU-core LRU list 33 has, for example, a data structure (list structure) in which link elements called structures are linked in order by pointers. The per-CPU-core LRU list 33 is provided for each CPU core 11, and corresponds to a plurality of first links indicating the order of movement of each page in a page group allocated to each of the plurality of CPU cores 11 among the plurality of pages. The kernel area 31 of the DRAM 30 storing the per-CPU-core LRU list 33 corresponds to a first management information storage area storing the first links.

[0030] 1, the per-CPU-core LRU list 33-0 is provided for the CPU core 11-0, and the per-CPU-core LRU list 33-1 is provided for the CPU core 11-1. The per-CPU-core LRU lists 33 are provided in the same number as the CPU cores 11 provided in the processor 10.

[0031] Hereinafter, per-CPU-core LRU list 33-0 may be referred to as LRU list 33-0 for CPU core #0. Similarly, per-CPU-core LRU list 33-1 may be referred to as LRU list 33-1 for CPU core #1. Hereinafter, when there is no need to distinguish between these per-CPU-core LRU lists 33-0, 33-1, ..., they will be referred to as per-CPU-core LRU list 33.

[0032] In the computer system 1a of the first embodiment, a per-CPU-core LRU list 33 is provided for each CPU core 11. The per-CPU-core LRU list 33 stores information about a page for which data access has occurred when the CPU core 11 executes a thread. For example, the per-CPU-core LRU list 33 stores a pointer to a page structure in which page information (such as an address) is stored, an access flag indicating that the page has been accessed, and list link information.

[0033] The per-CPU-core LRU list 33 manages pages for which data access has been performed by the CPU core 11 according to an LRU algorithm. In the per-CPU-core LRU list 33, pages for which data access has occurred are managed according to the time that they have not been referenced. By referring to the per-CPU-core LRU list 33, it is possible to know the page that was accessed most recently by the CPU core 11, i.e., the page that has not been referenced by the CPU core 11 for the longest time.

[0034] A page transfer thread 101 (described in detail later) executed by each CPU core 11 refers to this CPU core LRU list 33 to identify a page that has not been referenced for the longest time by the CPU core 11 (hereinafter, sometimes referred to as the own CPU core 11) that executes the page transfer thread 101. Then, this identified page is selected as a transfer candidate page to be transferred from the cache 30a to the SSD 20.

[0035] --OS LRU list 32--

[0036] The OS LRU list 32 manages migration candidate pages selected from each CPU core LRU list 33 using an LRU algorithm. That is, the OS LRU list 32 manages migration candidate pages selected by the page migration thread 101 executed by each CPU core 11 from its own CPU core 11's per-CPU core LRU list 33.

[0037] The OS LRU list 32 is an LRU list used by a page movement thread 101 (described in detail later) that is provided in the OS as a standard function. The OS LRU list 32 can be said to be an LRU list provided for the OS. The OS LRU list 32 may also be called the Linux LRU list 32. The OS LRU list 32 corresponds to a second link provided for the operating system, which manages a plurality of pages selected from a group of pages in a plurality of CPU core LRU lists 33 according to the order of movement, as a group of candidate pages to be moved to the SSD 20. The kernel area 31 of the DRAM 30 that stores the OS LRU list 32 corresponds to a second management information storage area that stores the second links.

[0038] The OS LRU list 32 is managed by the OS, and corresponds to a second link that indicates a group of pages that are candidates for being selected from one of a plurality of CPU core LRU lists 33 and moved to the SSD 20 .

[0039] The page migration thread 101 identifies the migration candidate page that has not been referenced for the longest period of time from among the migration candidate pages registered in the OS LRU list 32 according to the LRU algorithm, and selects it as the migration target page. The page migration thread 101 stores this selected migration target page in the SSD 20.

[0040] FIG. 3 is a diagram for explaining the operational relationship between the CPU core LRU list 33 and the OS LRU list 32 in the computer system 1a as an example of the first embodiment.

[0041] The page migration thread 101, which will be described later, selects a page to be migrated from among multiple migration candidate pages managed in the per-CPU-core LRU list 33, and places this migration target page in the OS LRU list 32, which is migrated to the SSD 20 (see symbol P1 in Figure 3).

[0042] An OS-specific page migration thread 102, which will be described later, selects a migration target page from among a plurality of migration candidate pages managed in the per-CPU-core LRU list 33, and migrates the migration target page to the SSD 20 (see symbol P2 in FIG. 3).

[0043] FIG. 4 is a diagram for explaining DRAM areas targeted by the CPU core LRU list 33 and the OS LRU list 32 in the computer system 1a as an example of the first embodiment.

[0044] 4, the per-CPU-core LRU list 33 manages only the cache 30a. That is, only the pages in the cache 30a are managed by the per-CPU-core LRU list 33.

[0045] In contrast, the OS LRU list 32 manages the entire storage area (entire DRAM area) of the DRAM 30. That is, the pages in the storage area of ​​the DRAM 30 are managed by the OS LRU list 32. FIG. 5 is a diagram illustrating an example of the migration information table 34 in the computer system 1a as an example of the first embodiment.

[0046] The migration information table 34 is information for managing whether or not a page has been migrated to the SSD 20, and is configured by associating, with each page, information indicating whether or not the page has been migrated to the SSD 20.

[0047] 5 is configured by associating a movement flag with information for identifying a page. The information for identifying a page may be a page address or identification information set for each page, and may be implemented in various modifications.

[0048] The migration flag is information indicating whether or not a page has been migrated to the SSD 20, and is set to "0" if the page has not been migrated (not migrated) to the SSD 20, and is set to "1" if the page has been migrated (migrated) to the SSD 20. That is, a page whose migration flag is set to "1" in the migration information table 34 is a migrated page.

[0049] The migration information table 34 corresponds to migration management information that manages pages migrated to the SSD 20 by the OS-specific page migration thread 102. The DRAM 30 that stores the migration information table 34 corresponds to a storage unit that stores the migration information table 34. FIG. 6 is a diagram for explaining a page management method in the computer system 1a as an example of the first embodiment. In the computer system 1a of the first embodiment, each CPU core 11 is provided with a per-CPU-core LRU list 33. In the example shown in FIG. 6, the processor 10 is configured as a four-core processor having CPU cores #0 to #3.

[0050] In the computer system 1a of the first embodiment, it is assumed that there is no sharing of data between the CPU cores 11. Furthermore, the per-CPU-core LRU list 33 is controlled independently for each CPU core 11, and the per-CPU-core LRU list 33 is not accessed from the OS-specific page migration thread 102.

[0051] In the computer system 1a of the first embodiment, each of the CPU cores #0 to #3 executes a thread 104, a page migration thread 101, and a list deletion thread 103, respectively. Furthermore, among the CPU cores #0 to #3, for example, any one of the CPU cores 11 that has been set in advance as a primary CPU core executes an OS-assigned page migration thread 102. In addition, a migration information table 34 and an OS LRU list 32 are stored in the kernel area 31 of the DRAM 30 (see FIG. 1).

[0052] As described above, a per-CPU-core LRU list 33 is provided corresponding to each CPU core 11. That is, an LRU list 33-0 for CPU core #0 is provided corresponding to CPU core #0, an LRU list 33-1 for CPU core #1 is provided corresponding to CPU core #1, an LRU list 33-2 for CPU core #2 is provided corresponding to CPU core #2, and an LRU list 33-3 for CPU core #3 is provided corresponding to CPU core #3.

[0053] For example, the LRU list 33-0 for the CPU core #0 is accessed only by the thread 104, the page movement thread 101, and the list deletion thread 103 executed by the CPU core #0. That is, the per-CPU-core LRU list 33-0 is accessed only by the CPU core #0, and is not accessed by the other CPU cores #1 to #3.

[0054] Similarly, the per-CPU-core LRU list 33-1 is accessed only by the thread 104, page movement thread 101, and list deletion thread 103 executed by the CPU core #1. In other words, the per-CPU-core LRU list 33-1 is accessed only by the CPU core #1, and is not accessed by the other CPU cores #0, #2, and #3.

[0055] Furthermore, the per-CPU-core LRU list 33-2 is accessed only by the thread 104, the page movement thread 101, and the list deletion thread 103 executed by the CPU core #2. That is, the per-CPU-core LRU list 33-2 is accessed only by the CPU core #2, and is not accessed by the other CPU cores #0, #1, and #3.

[0056] Furthermore, the per-CPU-core LRU list 33-3 is accessed only by the thread 104, the page movement thread 101, and the list deletion thread 103 executed by the CPU core #3. That is, the per-CPU-core LRU list 33-3 is accessed only by the CPU core #3, and is not accessed by the other CPU cores #0 to #2. Here, a page management method in the computer system 1a of the first embodiment will be described using the processing performed in the CPU core #0 as an example.

[0057] The CPU core #0 realizes arithmetic processing by executing the thread 104. The thread 104 performs processing such as updating the access flag and adding a new page to the LRU list 33-0 for the CPU core #0 (see reference character S1 in FIG. 6). In the following description, when the CPU core 11 executes the thread 104 to realize some processing, this may be expressed as the thread 104 realizing the processing.

[0058] By executing the page migration thread 101, the CPU core #0 refers to the LRU list 33-0 for the CPU core #0 and selects a candidate page for migration from among the pages registered in the LRU list 33 for the CPU core #0 based on the LRU algorithm (see symbol S2 in Figure 6).

[0059] In the following description, when the CPU core 11 executes the page movement thread 101 to realize some processing, this may be expressed as "the page movement thread 101 realizes processing." The page migration thread 101 adds the selected migration candidate page to the OS LRU list 32 (see reference symbol S3 in FIG. 6).

[0060] By executing the OS-specific page migration thread 102, the CPU core 11 refers to the OS LRU list 32 and selects a migration target page based on the LRU algorithm from among the migration candidate pages registered in the OS LRU list 32 (see reference numeral S4 in FIG. 6). Note that hereinafter, the realization of some processing by the CPU core 11 executing the OS-specific page migration thread 102 may be expressed as "the OS-specific page migration thread 102 realizing processing." Then, the OS-dependent page migration thread 102 migrates the selected migration target page to the SSD 20 (see reference symbol S5 in FIG. 6).

[0061] The CPU core 11 that executes the OS-specific page migration thread 102 corresponds to a migration processing unit that migrates data of a page selected from the page group in the OS-specific LRU list 32 from the cache 30 a to the SSD 20 .

[0062] In addition, the OS-associated page migration thread 102 registers the page (migrated page) that has been migrated to the SSD 20 in the migration information table 34 (see reference numeral S6 in FIG. 6). For example, the OS-associated page migration thread 102 sets the migration flag of the page in the migration information table 34 to “1” (sets the flag).

[0063] CPU core #0 executes list deletion thread 103 to delete pages in its own per-CPU-core LRU list 33 that have a migration flag set to "1" in migration information table 34. Note that hereinafter, the execution of some processing by CPU core 11 by executing list deletion thread 103 may be expressed as "list deletion thread 103 achieving processing."

[0064] Specifically, list deletion thread 103 refers to migration information table 34, and compares the migrated pages registered in migration information table 34 with migration candidate pages registered in CPU core #0 LRU list 33-0 that it manages. Then, of the migration candidate pages registered in CPU core #0 LRU list 33-0, it deletes pages that match the migrated pages registered in migration information table 34.

[0065] The list deletion thread 103 refers to the migration information table 34 to find out the migrated table, and deletes the migrated page from the per-CPU-core LRU list 33 (see reference numeral S7 in FIG. 6). Note that the above-mentioned processing by the list deletion thread 103 may be executed by the page migration thread 101. Access to the migration information table 34 is realized by a lightweight exclusive process. This allows atomic access to be achieved.

[0066] The CPU core 11 that executes the list deletion thread 103 is provided for each of the multiple CPU cores 11, and corresponds to a deletion processing unit that refers to the migration information table 34 and deletes the page that has been migrated to the SSD 20 from the per-CPU-core LRU list 33. The other CPU cores 11 also perform similar processing.

[0067] (B) Operation The process of updating the CPU core-specific LRU list 33 by the thread 104 in the computer system 1a as an example of the first embodiment configured as described above will be described with reference to the flowchart (steps A1 to A6) shown in FIG.

[0068] In step A1, the thread 104 checks whether to reserve a page in the memory area. If the result of the check is that a page is to be reserved (see the YES route in step A1), the process proceeds to step A2. In step A2, the thread 104 allocates a page to the thread 104 and updates the per-CPU-core LRU list 33.

[0069] In step A3, the thread 104 checks whether the memory usage exceeds a predetermined threshold (a fixed amount). If the check result shows that the memory usage exceeds the fixed amount (see the YES route in step A3), the thread 104 starts the page transfer thread 101 in step A4.

[0070] Then, the process proceeds to step A5. Also, if the result of the check in step A1 indicates that the thread 104 does not reserve a page in the memory area (see the NO route in step A1), the process proceeds to step A5.

[0071] In step A5, the thread 104 checks whether the memory has been accessed. If the check result shows that the memory has been accessed (see the YES route in step A5), the process proceeds to step A6, where the per-CPU-core LRU list 33 is updated. After that, the process returns to step A1. If the result of the check in step A3 is that the memory usage does not exceed the certain amount (see NO route in step A3), the process proceeds to step A5. Also, if the result of the check in step A5 is that there is no memory access by the thread 104 (see the NO route in step A5), the process returns to step A1.

[0072] Next, a process by the page movement thread 101 in the computer system 1a as an example of the first embodiment will be described with reference to the flowchart (steps A11 to A13) shown in Fig. 8. When the page movement thread 101 is started, a timer (not shown) starts counting time.

[0073] In step A11, the page movement thread 101 checks whether it has been started from a thread 104 executed by the same CPU core 11 (its own CPU core 11) as the CPU core 11 executing the page movement thread 101. If the check shows that the page movement thread 101 has been started from the thread 104 (see the YES route in step A11), the process proceeds to step A13.

[0074] In step A13, the page movement thread 101 selects a migration candidate page based on the LRU algorithm by referring to the CPU core-specific LRU list 33. The page movement thread 101 also adds the selected migration candidate page to the OS LRU list 32. The timer may also be reset at this timing. The page transfer thread 101 starts the OS-specific page transfer thread 102. After that, the process returns to step A11.

[0075] Also, if the result of the check in step A11 is that the program was started rather than started from thread 104, for example, due to sleep release (see NO route in step A11), the process proceeds to step A12.

[0076] In step A12, the page transfer thread 101 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step A12), the process returns to step A11. On the other hand, if the certain period of time has elapsed (see the YES route from step A12), the process proceeds to step A13.

[0077] Next, a process by the OS-associated page transfer thread 102 in the computer system 1a as an example of the first embodiment will be described with reference to the flowchart (steps A21 to A23) shown in Fig. 9. Note that when the OS-associated page transfer thread 102 is started, a timer (not shown) starts counting time.

[0078] In step A21, the OS-specific page transfer thread 102 checks whether it has been started from the page transfer thread 101. If the check result shows that the OS-specific page transfer thread 102 has been started from the page transfer thread 101 (see the YES route in step A21), the process proceeds to step A23.

[0079] In step A23, the OS-associated page migration thread 102 selects a page to be migrated based on the LRU algorithm with reference to the OS LRU list 32. The OS-associated page migration thread 102 also stores the selected page to be migrated in the SSD 20, and further deletes the page that has been migrated to the SSD 20 from the OS LRU list 32.

[0080] Furthermore, the OS-dependent page migration thread 102 sets a value indicating that the page has been migrated to the SSD 20 in the migration flag of the migration information table 34. Also, a timer may be reset at this timing. The page transfer thread 101 starts the OS-specific page transfer thread 102. After that, the process returns to step A21.

[0081] Also, if the result of the check in step A21 shows that the application was started not from the page movement thread 101 but was started, for example, due to sleep release (see NO route in step A21), the process proceeds to step A22.

[0082] In step A22, the OS-specific page migration thread 102 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step A22), the process returns to step A21. On the other hand, if the certain period of time has elapsed (see the YES route from step A22), the process proceeds to step A23.

[0083] Next, a process by the list deletion thread 103 in the computer system 1a as an example of the first embodiment will be described with reference to the flowchart (steps A31 to A33) shown in Fig. 10. When the list deletion thread 103 is started, a timer (not shown) starts counting time.

[0084] In step A31, the list deletion thread 103 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step A31), the process returns to step A31. On the other hand, if the certain period of time has elapsed (see the YES route from step A31), the process proceeds to step A32.

[0085] In step A32, the list deletion thread 103 checks whether any of the pages in the per-CPU-core LRU list 33 of its own CPU core 11 has a migration flag set to "1" in the migration information table 34. If the check shows that any of the pages in the per-CPU-core LRU list 33 of its own CPU core 11 has a migration flag set to "1" in the migration information table 34 (see the NO route in step A32), the process returns to step A31.

[0086] On the other hand, if the result of the check in step A32 shows that among the pages in the per-CPU-core LRU list 33 of the local CPU core 11, there is a page whose migration flag is set to "1" in the migration information table 34 (see the YES route in step A32), proceed to step A33.

[0087] In step A33, the list deletion thread 103 deletes a page (moved page) whose migration flag is set to "1" in the migration information table 34 from the per-CPU-core LRU list 33 of its own CPU core 11. After that, the process returns to step A31. The other CPU cores 11 also perform similar processing.

[0088] (C) Effects In this way, according to the computer system 1a as an example of the first embodiment, the per-CPU-core LRU list 33 is distributed to each CPU core 11, and each per-CPU-core LRU list 33 is controlled independently for each CPU core 11. As a result, the per-CPU-core LRU list 33 is accessed only by the own CPU core 11, and is not accessed by other CPU cores 11. This eliminates the need for exclusive control of the per-CPU-core LRU list 33, making a spinlock unnecessary. This reduces the load on the processor 10 due to page movement processing, and improves the processing performance of applications.

[0089] In each CPU core 11, the list deletion thread 103 can easily find out which pages have been migrated to the SSD 20 by referring to the migration flags in the execution migration information table 34, and can delete the migrated pages from the per-CPU-core LRU list 33.

[0090] [2. Description of the Second Embodiment] (A) Configuration FIG. 11 is a diagram illustrating a schematic configuration of a computer system 1b as an example of the second embodiment.

[0091] 11, the computer system 1b of the second embodiment has a page correspondence table 35 instead of the migration information table 34 of the DRAM 30 of the first embodiment, and other parts are configured similarly to the computer system 1a of the first embodiment. In the following drawings, the same reference numerals as those already described indicate similar parts, and therefore the description thereof will be omitted. FIG. 12 is a diagram illustrating a page correspondence table 35 in a computer system 1b as an example of the second embodiment.

[0092] --Page-compatible table 35-- The page correspondence table 35 is information that associates pages with CPU cores 11, and indicates in which CPU core 11 the migration candidate page selected by the page migration thread 101 is registered in the per-CPU-core LRU list 33.

[0093] The page correspondence table 35 illustrated in FIG. 12 is configured by associating, for each page, the CPU core 11 (CPU core number) that manages the page using the per-CPU-core LRU list 33.

[0094] The OS-specific page migration thread 102 refers to this page correspondence table 35 to identify the CPU core 11 corresponding to the page that has been migrated to the SSD 20, and deletes the migration candidate page from the CPU core-specific LRU list 33 of the CPU core 11.

[0095] For example, the OS-specific page migration thread 102 executed by the primary CPU core 11 can access the per-CPU-core LRU list 33 managed by another CPU core 11 by referring to the page correspondence table 35. Note that access to the page correspondence table 35 can be achieved by lightweight exclusive processing, enabling atomic access.

[0096] In the page correspondence table 35, the CPU core number associated with the page corresponds to the position information of the CPU core-specific LRU list 33 corresponding to the migration candidate page.

[0097] The page correspondence table 35 corresponds to page correspondence information that associates the pages migrated to the SSD 20 with the CPU core 11. The DRAM 30 that stores the page correspondence table 35 corresponds to a storage unit.

[0098] FIG. 13 is a diagram for explaining a page management method in the computer system 1b as an example of the second embodiment. The computer system 1b of the second embodiment also includes a per-CPU-core LRU list 33 for each CPU core 11. In the example shown in FIG. 13, the processor 10 is configured as a four-core processor including CPU cores #0 to #3.

[0099] In the computer system 1b of the second embodiment, it is assumed that no data is shared between the CPU cores 11. In the computer system 1b of the second embodiment, each of the CPU cores #0 to #3 executes a thread 104 and a page migration thread 101, respectively. Furthermore, among the CPU cores #0 to #3, for example, any one of the CPU cores 11 that has been set in advance as a primary CPU core executes an OS-assigned page migration thread 102. In addition, a page correspondence table 35 and an OS LRU list 32 are stored in the kernel area 31 of the DRAM 30 .

[0100] Furthermore, a per-CPU-core LRU list 33 is provided corresponding to each CPU core 11. That is, an LRU list 33-0 for CPU core #0 is provided corresponding to CPU core #0, an LRU list 33-1 for CPU core #1 is provided corresponding to CPU core #1, an LRU list 33-2 for CPU core #2 is provided corresponding to CPU core #2, and an LRU list 33-3 for CPU core #3 is provided corresponding to CPU core #3.

[0101] For example, the LRU list 33-0 for CPU core #0 is accessed by the thread 104 and the page migration thread 101 executed by the CPU core #0. The LRU list 33-0 for CPU core #0 is also accessed by the OS-specific page migration thread 102 to delete migration candidate pages.

[0102] Similarly, the per-CPU-core LRU list 33-1 is accessed by the thread 104 and page migration thread 101 executed by the CPU core #1, and is also accessed by the OS-specific page migration thread 102 to delete migration candidate pages.

[0103] The CPU core-specific LRU list 33-2 is accessed by the thread 104 and page migration thread 101 executed by the CPU core #2, and is also accessed by the OS-specific page migration thread 102 to delete migration candidate pages.

[0104] Furthermore, the per-CPU-core LRU list 33-3 is accessed by the thread 104 and page migration thread 101 executed by the CPU core #3, and is also accessed by the OS-specific page migration thread 102 to delete migration candidate pages. Here, a page management method in the computer system 1b of the second embodiment will be described using the process performed in the CPU core #0 as an example.

[0105] The CPU core #0 realizes arithmetic processing by executing the thread 104. The thread 104 performs processing such as updating the access flag and adding a new page to the LRU list 33-0 for the CPU core #0 (see reference character S11 in FIG. 13).

[0106] By executing the page migration thread 101, the CPU core #0 refers to the LRU list 33-0 for the CPU core #0 and selects a migration candidate page from among the pages registered in the LRU list 33 for the CPU core #0 based on the LRU algorithm (see symbol S12 in Figure 13). The page migration thread 101 adds the selected migration candidate page to the OS LRU list 32 (see reference character S13 in FIG. 13).

[0107] Furthermore, the page migration thread 101 registers the CPU core number (position information in the OS LRU list 32) corresponding to the migration candidate page in the page correspondence table 35 (see reference numeral S14 in FIG. 13).

[0108] The CPU core 11 executes the OS-associated page migration thread 102 to refer to the OS LRU list 32 and select a migration target page based on the LRU algorithm from among the migration candidate pages registered in the OS LRU list 32 (see reference numeral S15 in FIG. 13). Then, the OS-associated page migration thread 102 migrates the selected migration target page to the SSD 20 (see reference numeral S16 in FIG. 13).

[0109] The OS-specific page movement thread 102 references the page correspondence table 35 and acquires the CPU core number (position information in the OS LRU list 32) corresponding to the migrated page (see reference symbol S17 in FIG. 13). Then, the OS-specific page movement thread 102 deletes the migrated page from the CPU core-specific LRU list 33 of the CPU core 11 represented by the CPU core number acquired from the page correspondence table 35 (see reference symbol S18 in FIG. 13).

[0110] In the computer system 1b of the second embodiment, the OS-specific page migration thread 102 corresponds to a deletion processing unit that refers to the page correspondence table 35 and deletes the page that has been migrated to the SSD 20 from the per-CPU-core LRU list 33. The other CPU cores 11 also perform similar processing.

[0111] (B) Operation The process of updating the CPU core-specific LRU list 33 by the thread 104 in the computer system 1b as an example of the second embodiment configured as described above will be described with reference to the flowchart (steps B1 to B6) shown in FIG.

[0112] In step B1, the thread 104 checks whether to reserve a page in the memory area. If the result of the check is that a page is to be reserved (see the YES route in step B1), the process proceeds to step B2. In step B2, the thread 104 allocates a page to the thread 104 and updates the per-CPU-core LRU list 33.

[0113] In step B3, the thread 104 checks whether the memory usage exceeds a predetermined threshold (a fixed amount). If the check result shows that the memory usage exceeds the fixed amount (see the YES route in step B3), the thread 104 starts the page transfer thread 101 in step B4.

[0114] Then, the process proceeds to step B5. Also, if the result of the check in step B1 indicates that the thread 104 does not reserve a page in the memory area (see the NO route in step B1), the process proceeds to step B5.

[0115] In step B5, the thread 104 checks whether the memory has been accessed. If the check result indicates that the memory has been accessed (see the YES route in step B5), the process proceeds to step B6, where the per-CPU-core LRU list 33 is updated. After that, the process returns to step B1. Also, if the result of the check in step B3 shows that the memory usage does not exceed the certain amount (see NO route in step B3), the process proceeds to step B5. Also, if the result of the check in step B5 is that there is no memory access by the thread 104 (see the NO route in step B5), the process returns to step B1.

[0116] Next, a process by the page movement thread 101 in the computer system 1b as an example of the second embodiment will be described with reference to the flowchart (steps B11 to B13) shown in Fig. 15. When the page movement thread 101 is started, a timer (not shown) starts counting time.

[0117] In step B11, the page movement thread 101 checks whether it has been started from a thread 104 executed by the same CPU core 11 (its own CPU core 11) as the CPU core 11 executing the page movement thread 101. If the check shows that the page movement thread 101 has been started from the thread 104 (see the YES route in step B11), the process proceeds to step B13.

[0118] In step B13, the page movement thread 101 selects a migration candidate page based on the LRU algorithm with reference to the CPU core LRU list 33. The page movement thread 101 also registers the CPU core number (position information of the OS LRU list 32) corresponding to the migration candidate page in the page correspondence table 35. Furthermore, the page migration thread 101 adds the selected migration candidate page to the OS LRU list 32. Also, the timer may be reset at this timing. The page transfer thread 101 starts the OS-specific page transfer thread 102. After that, the process returns to step B11.

[0119] Also, if the result of the check in step B11 shows that the program was started rather than started from thread 104, for example, due to sleep release (see NO route in step B11), the process proceeds to step B12.

[0120] In step B12, the page transfer thread 101 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step B12), the process returns to step B11. On the other hand, if the certain time has elapsed (see the YES route from step B12), the process proceeds to step B13.

[0121] Next, a process by the OS-associated page transfer thread 102 in the computer system 1b as an example of the second embodiment will be described with reference to the flowchart (steps B21 to B23) shown in Fig. 16. Note that when the OS-associated page transfer thread 102 is started, a timer (not shown) starts counting time.

[0122] In step B21, the OS-specific page transfer thread 102 checks whether it has been started from the page transfer thread 101. If the check result shows that the OS-specific page transfer thread 102 has been started from the page transfer thread 101 (see the YES route in step B21), the process proceeds to step B23.

[0123] In step B23, the OS-associated page migration thread 102 selects a migration target page based on the LRU algorithm with reference to the OS LRU list 32. The OS-associated page migration thread 102 also stores the selected migration target page in the SSD 20. Furthermore, the OS-associated page migration thread 102 deletes the page that has been migrated to the SSD 20 from the OS LRU list 32.

[0124] Furthermore, the OS-associated page transfer thread 102 refers to the page correspondence table 35 for the page that has been transferred to the SSD 20, and acquires the CPU core number (position information in the OS LRU list 32) corresponding to the transferred page. Then, the OS-associated page transfer thread 102 deletes the transferred page from the CPU core-specific LRU list 33 that is managed by the acquired CPU core number. Also, the timer may be reset at this timing. After that, the process returns to step B21.

[0125] Also, as a result of the check in step B21, if the thread is started not from the page movement thread 101 but started, for example, due to sleep release (see NO route in step B21), the process proceeds to step B22.

[0126] In step B22, the OS-specific page migration thread 102 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step B22), the process returns to step B21. On the other hand, if the certain period of time has elapsed (see the YES route from step B22), the process proceeds to step B23.

[0127] (C) Effects In this way, according to the computer system 1b as an example of the second embodiment, by distributing the per-CPU-core LRU list 33 for each CPU core 11, the number of threads accessing each per-CPU-core LRU list 33 is reduced. For example, in the example shown in Fig. 13, only the thread 104 and page migration thread 101 of the own CPU core 11 and the OS-associated page migration thread 102 access each per-CPU-core LRU list 33. This makes it possible to shorten the lock time for exclusive control in the per-CPU-core LRU list 33, reduce the load on the CPU core 11 due to spinlock, and improve application performance.

[0128] By referring to the page correspondence table 35, the OS-specific page migration thread 102 can easily know the per-CPU-core LRU list 33 from which the migrated page is to be deleted, and can delete the migrated page from the per-CPU-core LRU list 33.

[0129] [3. Description of the Third Embodiment] (A) Configuration FIG. 17 is a diagram illustrating a schematic configuration of a computer system 1c as an example of the third embodiment.

[0130] As shown in FIG. 17, the computer system 1c of the third embodiment deletes the migration information table 34 in the DRAM 30 of the first embodiment, and other parts are configured in the same manner as the computer system 1a of the first embodiment. In the figure, the same reference numerals as those already described indicate similar parts, and therefore their explanation will be omitted. FIG. 18 is a diagram for explaining a page management method in a computer system 1c as an example of the third embodiment. The computer system 1c of the third embodiment also includes a per-CPU-core LRU list 33 for each CPU core 11. In the example shown in FIG. 18, CPU cores #0 to #2 provided in the processor 10 are illustrated. In the computer system 1c of the third embodiment, it is also assumed that no data is shared between the CPU cores 11.

[0131] In the computer system 1c of the third embodiment, each of the CPU cores #0 to #2 executes a thread 104, a page migration thread 101, and an OS-specific page migration thread 102, respectively.

[0132] Each of the CPU cores #0 to #2 has an OS LRU list 32. The OS LRU list 32 for each CPU core 11 is stored in a kernel area 31 of the DRAM 30.

[0133] Furthermore, a per-CPU-core LRU list 33 is provided corresponding to each CPU core 11. That is, an LRU list 33-0 for CPU core #0 is provided corresponding to CPU core #0, an LRU list 33-1 for CPU core #1 is provided corresponding to CPU core #1, and an LRU list 33-2 for CPU core #2 is provided corresponding to CPU core #2.

[0134] For example, the LRU list 33-0 for the CPU core #0 is accessed by the thread 104, the page migration thread 101, and the OS-specific page migration thread 102 executed by the CPU core #0.

[0135] That is, the LRU list 33-0 for the CPU core #0 is accessed only by the CPU core #0, and is not accessed by the other CPU cores #1 to #2.

[0136] Similarly, the per-CPU-core LRU list 33-1 is accessed by the thread 104, page migration thread 101, and OS-specific page migration thread 102 executed by the CPU core #1.

[0137] That is, the LRU list 33-1 for the CPU core #1 is accessed only by the CPU core #1, and is not accessed by the other CPU cores #0 and #2.

[0138] Furthermore, the per-CPU-core LRU list 33-2 is accessed by the thread 104, the page migration thread 101, and the OS-specific page migration thread 102 executed by the CPU core #2.

[0139] That is, the LRU list 33-2 for the CPU core #2 is accessed only by the CPU core #2, and is not accessed by the other CPU cores #0 and #1. Here, a page management method in the computer system 1c of the third embodiment will be described using the processing performed in the CPU core #0 as an example.

[0140] The CPU core #0 realizes arithmetic processing by executing the thread 104. The thread 104 performs processing such as updating the access flag and adding a new page to the LRU list 33-0 for the CPU core #0 (see reference character S21 in FIG. 18).

[0141] By executing the page migration thread 101, the CPU core #0 refers to the LRU list 33-0 for the CPU core #0 and selects a migration candidate page from among the pages registered in the LRU list 33 for the CPU core #0 based on the LRU algorithm (see symbol S22 in Figure 18). The page migration thread 101 adds the selected migration candidate page to the OS LRU list 32 managed by the CPU core #0 (see reference numeral S23 in FIG. 18).

[0142] The CPU core #0 executes the OS-associated page migration thread 102 to refer to the OS LRU list 32 and select a migration target page based on the LRU algorithm from among the migration candidate pages registered in the OS LRU list 32 (see reference numeral S24 in FIG. 18). Then, the OS-associated page migration thread 102 migrates the selected migration target page to the SSD 20 (see reference numeral S25 in FIG. 18).

[0143] The OS-specific page migration thread 102 deletes the migrated page correspondence table 35 from the per-CPU-core LRU list 33 managed by its own CPU core #0 (see reference numeral S26 in FIG. 18). The other CPU cores 11 also perform similar processing.

[0144] In the computer system 1c of the third embodiment, the OS-associated page migration thread 102 corresponds to a deletion processing unit that deletes pages migrated to the SSD 20 from the OS LRU list 32 and the CPU core LRU list 33 for each of the multiple CPU cores 11.

[0145] (B) Operation The process of updating the CPU core-specific LRU list 33 by the thread 104 in the computer system 1c as an example of the third embodiment configured as described above will be described with reference to the flowchart (steps C1 to C6) shown in FIG.

[0146] In step C1, the thread 104 checks whether to reserve a page in the memory area. If the result of the check is that a page is to be reserved (see the YES route in step C1), the process proceeds to step C2. In step C2, the thread 104 allocates a page to the thread 104 and updates the per-CPU-core LRU list 33.

[0147] In step C3, the thread 104 checks whether the memory usage exceeds a predetermined threshold (a fixed amount). If the check result shows that the memory usage exceeds the fixed amount (see the YES route in step C3), the thread 104 starts the page transfer thread 101 in step C4.

[0148] Then, the process proceeds to step C5. Also, if the result of the check in step C1 indicates that the thread 104 does not reserve a page in the memory area (see the NO route in step C1), the process proceeds to step C5.

[0149] In step C5, the thread 104 checks whether the memory has been accessed. If the check result shows that the memory has been accessed (see the YES route in step C5), the process proceeds to step C6, where the per-CPU-core LRU list 33 is updated. After that, the process returns to step C1. Moreover, if the result of the check in step C3 shows that the memory usage does not exceed the certain amount (see NO route in step C3), the process proceeds to step C5. Also, if the result of the check in step C5 is that there is no memory access by the thread 104 (see the NO route in step C5), the process returns to step C1.

[0150] Next, a process by the page movement thread 101 in the computer system 1c as an example of the third embodiment will be described with reference to the flowchart (steps C11 to C13) shown in Fig. 20. When the page movement thread 101 is started, a timer (not shown) starts counting time.

[0151] In step C11, the page movement thread 101 checks whether it has been started from a thread 104 executed by the same CPU core 11 (its own CPU core 11) as the CPU core 11 executing the page movement thread 101. If the check shows that the page movement thread 101 has been started from the thread 104 (see the YES route in step C11), the process proceeds to step C13.

[0152] In step C13, the page move thread 101 refers to the CPU core LRU list 33 and selects a migration candidate page based on the LRU algorithm. The page move thread 101 also adds the selected migration candidate page to the OS LRU list 32. Furthermore, the page move thread 101 starts the OS-associated page move thread 102 of its own CPU core 11. The timer may also be reset at this timing. After that, the process returns to step C11.

[0153] Also, if the result of the check in step C11 is that the program was started rather than started from the thread 104, for example, due to sleep release (see NO route in step C11), the process proceeds to step C12.

[0154] In step C12, the page transfer thread 101 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step C12), the process returns to step C11. On the other hand, if the certain period of time has elapsed (see the YES route from step C12), the process proceeds to step C13.

[0155] Next, a process by the OS-associated page migration thread 102 in the computer system 1c as an example of the third embodiment will be described with reference to the flowchart (steps C21 to C23) shown in Fig. 21. Note that when the OS-associated page migration thread 102 is started, a timer (not shown) starts counting time.

[0156] In step C21, the OS-specific page migration thread 102 checks whether it has been started from the page migration thread 101. If the check result shows that the OS-specific page migration thread 102 has been started from the page migration thread 101 (see the YES route in step C21), the process proceeds to step C23.

[0157] In step C23, the OS-associated page transfer thread 102 refers to the OS LRU list 32 of its own CPU core 11 and selects a page to be transferred based on the LRU algorithm. The OS-associated page transfer thread 102 also stores the selected page to be transferred in the SSD 20. The OS-associated page transfer thread 102 also deletes the page that has been transferred to the SSD 20 from the OS LRU list 32 of its own CPU core 11. The timer may also be reset at this timing. After that, the process returns to step C21.

[0158] Also, as a result of the check in step C21, if it is determined that the thread has been started rather than started from the page movement thread 101, for example, due to sleep release (see NO route in step C21), the process proceeds to step C22.

[0159] In step C22, the OS-specific page migration thread 102 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step C22), the process returns to step C21. On the other hand, if the certain time has elapsed (see the YES route from step C22), the process proceeds to step C23.

[0160] (C) Effects In this way, according to computer system 1c as an example of the third embodiment, per-CPU-core LRU list 33 is provided for each CPU core 11, and each per-CPU-core LRU list 33 is controlled independently for each CPU core 11. As a result, per-CPU-core LRU list 33 is accessed only by its own CPU core 11, and is not accessed by other CPU cores 11. This eliminates the need for exclusive control of per-CPU-core LRU list 33, making spinlock unnecessary. This reduces the load on processor 10 due to page movement processing, and improves application processing performance.

[0161] [4.Other] The disclosed technology is not limited to the above-described embodiment, and can be modified in various ways without departing from the spirit of the present embodiment. Each configuration and each process of the present embodiment can be selected as needed, or can be combined as appropriate.

[0162] For example, in the above-described embodiment, the computer system 1 includes the SSD 20, and the SSD 20 is used as the low-speed memory, but this is not limited to this. A storage device other than the SSD 20 may be used as the low-speed memory, and various modifications can be made.

[0163] In the above embodiment, the page to be moved to the SSD 20 is selected based on the LRU algorithm, but the present invention is not limited to this. The page to be moved to the SSD 20 may be selected based on other algorithms such as FIFO (First In, First Out). The selection may be based on:

[0164] Furthermore, in the above-described embodiment, the OS LRU list 32 and the CPU core LRU list 33 are stored in the kernel area 31 of the DRAM 30. That is, the kernel area 31 of the DRAM 30 functions as the first management information storage area and the second management information storage area, but this is not limited to this. For example, at least one of the OS LRU list 32 and the CPU core LRU list 33 may be stored in another storage area such as the user area 36 of the DRAM 30 or the SSD 20, and various modifications can be made. Furthermore, the above disclosure enables a person skilled in the art to implement and manufacture the present embodiment.

[0165] [4. Description of the Fourth Embodiment] In the computer systems 1a to 1c of the above-described embodiments, a per-CPU-core LRU list 33 is provided for each CPU core 11. Each per-CPU-core LRU list 33 is accessed only by the CPU core 11 in which it is provided, and is not accessed by other CPU cores 11. This makes it impossible to redistribute the cache capacity between the CPU cores 11.

[0166] For example, in a two-CPU core configuration having CPU core #0 and CPU core #2, if the memory access frequency of CPU core #0 is low, when CPU core #1 newly secures cache, if there is no free space in cache 30a, one of the pages will be moved to SSD 20.

[0167] However, even if CPU core #0 has a page that is accessed infrequently, CPU core #1 cannot operate the CPU core per-CPU LRU list 33 of CPU core #0, and therefore cannot move the cache of CPU core #0 to SSD 20, and instead moves the page from the cache of CPU #1 to SSD 20.

[0168] The cache capacity of CPU core #0 and CPU core #1 is zero when the server starts up. After the server starts up, each CPU core #0 and #1 goes to get cache on a first-come, first-served basis, and the amount of cache reserved for each CPU core #0 and #1 when the free cache capacity is finally depleted becomes the initial cache capacity of each CPU core #0 and #1. Note that if the initial state is not the optimal ratio, it is recommended to redistribute the cache. A known conventional method for redistributing cache capacity among CPU cores is to use the frequency of cache misses of each CPU core as an index.

[0169] In other words, by repeatedly releasing one page of cache from a CPU core with a low frequency of cache misses and increasing one page of cache from a CPU core with a high frequency of cache misses, the cache is redistributed to gradually approach the optimal cache capacity. However, in such a conventional method, it takes a long time to reach the optimum cache capacity, and the performance degradation during that time becomes a problem. In the computer system 1d according to the fourth embodiment, the time required for redistributing cache capacity is reduced.

[0170] (A) Configuration FIG. 22 is a diagram illustrating an example of the functional configuration of a computer system 1d as an example of the fourth embodiment.

[0171] The computer system 1d illustrated in Fig. 22 includes a cache redistribution processing unit 40 in addition to the computer system 1a of the first embodiment illustrated in Fig. 6. Note that some of the configuration of the computer system 1a illustrated in Fig. 6 is omitted in Fig. 22. Moreover, the computer system 1d of the fourth embodiment has the same hardware configuration as the computer system 1a of the first embodiment illustrated in FIG. --Cache redistribution processing unit 40-- The cache redistribution processor 40 redistributes the cache capacity using the required memory capacity of each CPU core 11 and information on the frequency of cache misses. The cache redistribution processor 40 has the functions of a required memory capacity tallying unit 41, a cache miss frequency tallying unit 42, and a cache redistribution determining unit 43. The function of the cache redistribution processor 40 is realized by, for example, any one of the CPU cores 11, which is set in advance as a primary, among the CPU cores #0 to #3. --Cache Capacity Table 44--

[0172] The cache capacity table 44 holds the value of the cache capacity (cache capacity value) of each CPU core 11. The cache capacity value is the size of the storage area allocated to each CPU core 11 in the cache 30a, and indicates the memory size available to each CPU core 11 in the cache 30a. The page migration thread 101 of each CPU core 11 manages migration candidate pages using the cache capacity value read from this cache capacity table 44 .

[0173] The page transfer thread 101 reads a cache capacity value corresponding to the CPU core 11 in which it is provided (its own CPU core 11) from the cache capacity table 44, and performs page transfer processing so that the cache capacity of the own CPU core 11 does not exceed this cache capacity value. The information constituting the cache capacity table 44 is stored in the kernel area 31 of the DRAM 30, for example. --Required memory capacity calculation unit 41--

[0174] When the thread 104 of each CPU core 11 makes a memory allocation request or a memory release request (API readout), this information is input to the requested memory capacity aggregation unit 41. API is an abbreviation for Application Programming Interface.

[0175] The requested memory capacity tallying unit 41 accumulates the requested memory capacity for each CPU core 11. The requested memory capacity tallying unit 41 accumulates the requested memory capacity for each CPU core 11 by using information on the memory capacity when an API that secures memory is called from a thread. For example, the memory size included in the argument of the malloc function that allocates dynamic memory may be used as the memory capacity information. Note that the method of obtaining the required memory capacity information is not limited to the method of using the argument of the malloc function, and can be modified as appropriate. When a thread calls an API for releasing memory, the requested memory capacity counting unit 41 subtracts the memory capacity released by the thread from the requested memory capacity. The required memory capacity for each CPU core 11 calculated by the required memory capacity tallying unit 41 is stored in the kernel area 31 of the DRAM 30, for example. --Cache miss frequency counting unit 42--

[0176] The cache miss frequency counting unit 42 counts the number of cache misses for each CPU core 11. For example, when a page fault interrupt occurs during memory access by a thread, the cache miss frequency counting unit 42 determines that a cache miss has occurred (cache miss determination). When the cache miss frequency counting unit 42 determines that a cache miss has occurred, it counts up (increments) the number of cache misses for the CPU core 11 in which the cache miss occurred.

[0177] The cache miss frequency counting unit 42 counts the number of cache misses (cache miss frequency) for each predetermined time period for each CPU core 11. The cache miss frequency is cleared by the cache redistribution determining unit 43 (described later) every time the predetermined time period elapses.

[0178] The number of cache misses (cache miss frequency) for each CPU core 11 counted by the cache miss frequency counting unit 42 is stored in the kernel area 31 of the DRAM 30, for example.

[0179] --Cache redistribution determination unit 43-- The cache redistribution determination unit 43 determines the cache capacity to be redistributed (redistributed cache size) based on the required memory capacity of each CPU core 11 and information on the frequency of cache misses.

[0180] The cache redistribution determination unit 43 checks the ratio of the maximum and minimum cache miss frequencies among multiple CPU cores 11 at regular time intervals, and performs cache redistribution if this ratio is equal to or greater than a certain value (threshold value).

[0181] The cache redistribution determination unit 43 determines the CPU core 11 that will perform the cache redistribution and the memory capacity to be redistributed, and uses the determined memory capacity to update the cache capacity table 44. The value of the cache miss frequency counted by the cache miss frequency counting unit 42 is cleared at regular time intervals. FIG. 23 is a diagram for explaining the process of the cache redistribution determination unit 43 of the computer system 1d as an example of the fourth embodiment. FIG. 23 illustrates the cache capacity, required memory capacity, and cache miss frequency for each of the CPU cores #0 to #2. The cache redistribution determination unit 43 executes cache redistribution when the ratio between the maximum and minimum values ​​of the cache miss frequency is equal to or greater than a certain value (eg, 3 or greater).

[0182] 23, the cache miss frequency of CPU core #0 is the maximum value of "400," and the cache miss frequency of CPU core #1 is the minimum value of "100." Since the ratio of these cache miss frequencies, 4 (=400÷100), is equal to or greater than the threshold value of "3," cache redistribution determination unit 43 determines to perform cache redistribution.

[0183] In addition, in cache redistribution, the cache redistribution determination unit 43 determines the CPU core 11 (CPU_L) with the lowest cache miss frequency as the cache capacity transfer source, and determines the CPU core 11 (CPU_H) with the highest cache miss frequency as the cache capacity transfer destination.

[0184] In the example shown in FIG. 23, the cache redistribution determination unit 43 determines the CPU core #1 with the lowest cache miss frequency as the cache capacity transfer source, and determines the CPU core #0 with the highest cache miss frequency as the cache capacity transfer destination. In cache redistribution, the cache redistribution determination unit 43 moves cache capacity from the CPU core 11 (CPU_L) with the lowest cache miss frequency to the CPU core 11 (CPU_H) with the highest cache miss frequency.

[0185] Furthermore, the cache redistribution determination unit 43 determines the cache capacity (redistribution cache size) to be moved from the source CPU core 11 to the destination CPU core 11 by redistribution.

[0186] The cache redistribution determination unit 43 determines the number of pages of data to be moved by redistribution (number of pages to be moved) based on the ratio (required memory capacity ratio) between the required memory capacity of the source CPU core 11 and the required memory capacity of the destination CPU core 11. For example, the cache redistribution determination unit 43 calculates the number of pages to be moved based on the following formula (1). Number of pages to be moved = Required memory capacity of destination / Required memory capacity of source (1)

[0187] In the example shown in Figure 23, the required memory capacity of the destination CPU core 11 is "20G" and the required memory capacity of the destination CPU core 11 is "2G", so the cache redistribution determination unit 43 calculates the number of pages to be moved based on equation (1) as shown below. Number of pages moved = 20 / 2 = 10 (pages)

[0188] Then, the cache redistribution determination unit 43 multiplies the calculated number of pages to be moved (for example, 10 pages) by the data size of a page (for example, 4 KB) to determine the redistribution cache size (for example, 40 KB).

[0189] The cache redistribution determination unit 43 uses the calculated redistribution cache size to update the cache capacity table 44. Specifically, the cache redistribution determination unit 43 subtracts the calculated redistribution cache size from the cache capacity value of the source CPU core 11 in the cache capacity table 44, and adds the redistribution cache size to the cache capacity value of the destination CPU core 11.

[0190] That is, the cache redistribution determination unit 43 determines the redistribution cache size according to the ratio of the required memory capacity of the source CPU core 11 to the destination CPU core 11. The page transfer thread 101 selects transfer target pages for the number of transfer pages, and stores the transfer target pages for the number of transfer pages in the SSD 20 at once. This allows the redistribution to be completed in a shorter time than moving the cache capacity one page at a time.

[0191] (B) Operation The page transfer process in the computer system 1d as an example of the fourth embodiment configured as described above will be described with reference to the flowchart (steps D1 to D9) shown in Fig. 24. When the page transfer thread 101 is started, a timer (not shown) starts counting time.

[0192] In step D1, the requested memory capacity tallying unit 41 checks whether the thread 104 has requested memory (requested memory allocation). If the thread 104 has not requested memory allocation (see NO route in step D1), the process proceeds to step D3. Also, if the thread 104 requests memory (see the YES route from step D1), the process proceeds to step D2.

[0193] In step D2, the requested memory capacity tallying unit 41 adds the memory capacity requested by the thread 104 to the requested memory capacity of the CPU core 11 that executes the thread 104. Then, the process proceeds to step D3.

[0194] In step D3, the requested memory capacity compilation unit 41 checks whether the thread 104 has released the memory. If the thread 104 has not released the memory (see the NO route in step D3), the process proceeds to step D5. If the thread 104 releases the memory (see the YES route of step D3), the process proceeds to step D4.

[0195] In step D4, the required memory capacity tallying unit 41 subtracts the memory capacity released by the thread 104 from the memory capacity required by the CPU core 11 that executes the thread 104. Then, the process proceeds to step D5.

[0196] In step D5, the cache miss frequency counting unit 42 checks whether a page fault has occurred in the memory access of the thread 104. If a page fault has not occurred (see the NO route in step D5), the process proceeds to step D7. If a page fault has occurred (see the YES route from step D5), the process proceeds to step D6.

[0197] In step D6, the cache miss frequency counting unit 42 increments the number of cache misses (cache miss frequency) of the CPU core 11 that executes the thread 104. Then, the process proceeds to step D7.

[0198] In step D7, the cache redistribution determination unit 43 checks whether a certain period of time has elapsed by referring to the time measured by the timer. If the certain period of time has not elapsed (see NO route in step D7), the process returns to step D1. On the other hand, if the certain period of time has elapsed (see the YES route from step D7), the process proceeds to step D8.

[0199] In step D8, the cache redistribution determination unit 43 checks whether the ratio of the maximum value to the minimum value of the cache miss frequency is equal to or greater than a certain value among the multiple CPU cores 11 included in the computer system 1d. If the check shows that the ratio of the maximum value to the minimum value of the cache miss frequency is not equal to or greater than a certain value (see the NO route in step D8), the process returns to step D1. On the other hand, if the ratio between the maximum and minimum values ​​of the cache miss frequency is equal to or greater than a certain value (see the YES route from step D8), the process proceeds to step D9.

[0200] In step D9, the cache redistribution determination unit 43 determines the redistribution cache size according to the ratio of the required memory capacities of the CPU core 11 of the transfer source and the CPU core 11 of the transfer destination.

[0201] In addition, the cache redistribution determination unit 43 uses the calculated redistribution cache size to update the cache capacity table 44. Furthermore, the cache redistribution determination unit 43 clears the cache miss frequency counted by the cache miss frequency counting unit 42. After that, the process returns to step D1.

[0202] (C) Effects According to computer system 1d as an example of the fourth embodiment, the same effects as those of computer system 1a of the first embodiment described above can be obtained, and in addition, by having a cache redistribution processing unit 40 redistribute cache capacity between CPU cores 11, it is possible to redistribute cache capacity between CPU cores 11 even in a configuration in which the cache LRU list (per-CPU-core LRU list 33) is separated for each CPU core 11.

[0203] In the cache redistribution processing unit 40, the cache redistribution determination unit 43 executes cache redistribution when the ratio between the maximum and minimum values ​​of the cache miss frequency is equal to or greater than a certain value. In other words, when a bias in the cache miss frequency occurs among a plurality of CPU cores 11, the cache redistribution processing unit 40 performs cache redistribution processing to eliminate the bias in the cache miss frequency and improve the average performance.

[0204] In addition, the cache redistribution determination unit 43 determines the CPU core #1 with the lowest cache miss frequency as the source of cache capacity transfer, and determines the CPU core #0 with the highest cache miss frequency as the destination of cache capacity transfer. This makes it possible to efficiently eliminate bias in cache miss frequency and improve average performance.

[0205] Furthermore, the cache redistribution determination unit 43 determines the redistribution cache size according to the ratio of the required memory capacity between the source CPU core 11 and the destination CPU core 11. This makes it possible to shorten the time required for redistributing the cache capacity, compared to a conventional method in which the cache of a CPU core with a low cache miss frequency is released by one page and the cache of a CPU core with a high cache miss frequency is increased by one page. Furthermore, by shortening the time required for redistributing the cache capacity, the time for performance degradation due to cache capacity imbalance can be shortened, and average performance can be improved.

[0206] The computer system 1d of the fourth embodiment described above is configured by providing the cache redistribution processing unit 40 to the computer system 1a of the first embodiment shown in Fig. 6, but is not limited to this. For example, the computer system 1b of the second embodiment or the computer system 1c of the third embodiment described above may be configured by providing the cache redistribution processing unit 40, and various modifications can be made.

[0207] [5. Notes] Regarding the above embodiment, the following supplementary notes are further disclosed. (Appendix 1) A primary memory in which data is stored in units of pages; a secondary memory for storing data of a page to be moved from the primary memory; A processor having a plurality of computing cores; a first management information storage area provided for each of the plurality of processor cores, storing a plurality of first links indicating a movement order of each page in a page group assigned to each of the plurality of processor cores among the plurality of pages; a second management information storage area provided for the operating system, for storing a second link for managing a plurality of pages selected from a page group in the plurality of first links according to the order of movement as a page group of candidates to be moved to the secondary memory; a transfer processing unit that transfers data of a page selected from the page group of the second link from the primary memory to the secondary memory; An information processing device comprising:

[0208] (Appendix 2) a storage unit that stores migration management information that manages pages migrated to the secondary memory by the migration processing unit; a deletion processing unit provided for each of the plurality of processing cores, the deletion processing unit referencing the migration management information and deleting the page that has been migrated to the secondary memory from the first link; 2. An information processing device according to claim 1, comprising:

[0209] (Appendix 3) a storage unit that stores page correspondence information that associates the page moved to the secondary memory with the processor core; a deletion processing unit that refers to the page correspondence information and deletes the page that has been moved to the secondary memory from the first link; 2. An information processing device according to claim 1, comprising:

[0210] (Appendix 4) a deletion processing unit that deletes the second link and the page that has been moved to the secondary memory from the first link for each of the plurality of processing cores; 2. An information processing device according to claim 1, comprising:

[0211] (Appendix 5) A primary memory in which data is stored in units of pages; a secondary memory for storing data of a page to be moved from the primary memory; A processor having a plurality of computing cores; In an information processing device comprising: Among the plurality of arithmetic cores, an arithmetic core that uses the primary memory is execute a process of registering a page to which the processing core has performed data access in a plurality of first links indicating the order of movement of each page in a page group assigned to the processing core; One of the plurality of computing cores A process is executed in which a second link is provided for the operating system, the second link being used to register a plurality of pages selected from a page group in the plurality of first links according to the order of movement as a page group of candidates to be moved to the secondary memory, and data of a page selected from the page group of the second link is moved from the primary memory to the secondary memory. A memory control program comprising:

[0212] (Appendix 6) causing any one of the plurality of processor cores to execute a process of storing in a storage unit migration management information for managing the pages migrated to the secondary memory; causing each of the plurality of computing cores to refer to the migration management information and execute a process of deleting the page that has been migrated to the secondary memory from the first link; 6. The memory control program according to claim 5,

[0213] (Appendix 7) storing page correspondence information that associates the page moved to the secondary memory with the processing core in a storage unit; The page that has been moved to the secondary memory is deleted from the first link by referring to the page correspondence information. 6. The memory control program according to claim 5, further comprising: causing any one of the plurality of processor cores to execute a process.

[0214] (Appendix 8) causing each of the plurality of computing cores to execute a process of deleting the second link and the page that has been moved to the secondary memory from the first link; 6. The memory control program according to claim 5,

[0215] (Appendix 9) In an information processing device having a processor including a plurality of arithmetic cores, a memory capacity tallying unit that totals memory capacity requirements for each of the plurality of processor cores; a cache miss frequency counting unit that counts the number of cache misses for each of the plurality of processor cores; a cache redistribution determination unit that determines a cache capacity to be redistributed based on a required memory capacity of each processor core; An information processing device comprising:

[0216] (Appendix 10) The cache redistribution determination unit determines the cache capacity to be redistributed according to a ratio between a required memory capacity of a processor core at a source of the redistribution and a required memory capacity of a processor core at a destination of the redistribution. 10. The information processing device according to claim 9.

[0217] (Appendix 11) The cache redistribution determination unit redistributes the cache capacity when a ratio between a maximum value and a minimum value of cache miss frequencies in the plurality of processing cores is equal to or greater than a threshold value. 11. The information processing device according to claim 9 or 10.

[0218] (Appendix 12) The cache redistribution determination unit determines the processor core with the lowest cache miss frequency as the source of cache capacity transfer, and determines the processor core with the highest cache miss frequency as the destination of cache capacity transfer. 12. The information processing device according to claim 11.

[0219] (Appendix 13) In an information processing device having a processor including a plurality of arithmetic cores, One of the plurality of computing cores accumulating the required memory capacity for each of the plurality of processing cores; Counting the number of cache misses for each of the plurality of processor cores; Determine the cache capacity to be redistributed based on the memory capacity required by each processor core. An information processing program that causes a process to be executed.

[0220] (Appendix 14) A process of determining the cache capacity to be redistributed according to a ratio between the required memory capacity of the processor core at the source of the redistribution and the required memory capacity of the processor core at the destination of the redistribution. The information processing program according to claim 13, characterized in that the program causes any one of the plurality of processing cores to execute the above.

[0221] (Appendix 15) a process of redistributing the cache capacity when a ratio between a maximum value and a minimum value of a cache miss frequency in the plurality of processing cores is equal to or greater than a threshold value; 15. The information processing program according to claim 13 or 14, characterized in that the program causes any one of the plurality of processing cores to execute the above.

[0222] (Appendix 16) A process of determining the processor core with the lowest cache miss frequency as the source of cache capacity transfer and the processor core with the highest cache miss frequency as the destination of cache capacity transfer. 16. The information processing program according to claim 15, further comprising causing any one of the plurality of processing cores to execute the above.

[0223] (Appendix 17) In an information processing device having a processor including a plurality of arithmetic cores, A process of accumulating a required memory capacity for each of the plurality of processing cores; counting the number of cache misses for each of the plurality of processor cores; A process of determining the cache capacity to be redistributed based on the memory capacity required by each computing core; 13. An information processing method comprising:

[0224] (Appendix 18) A process of determining the cache capacity to be redistributed according to a ratio between the required memory capacity of the processor core at the source of the redistribution and the required memory capacity of the processor core at the destination of the redistribution. 18. The information processing method according to claim 17, comprising:

[0225] (Appendix 19) a process of redistributing the cache capacity when a ratio between a maximum value and a minimum value of a cache miss frequency in the plurality of processing cores is equal to or greater than a threshold value; 19. The information processing method according to claim 17 or 18, comprising:

[0226] (Appendix 20) A process of determining the processor core with the lowest cache miss frequency as the source of cache capacity transfer and the processor core with the highest cache miss frequency as the destination of cache capacity transfer. 20. The information processing method according to claim 19, comprising: [Explanation of symbols]

[0227] 1a, 1b, 1c Computer Systems 10 Processors 11-0, 11-1, 11-2, 11 CPU cores 12 PCIe root ports 13 Memory Controller 20 SSD 21 Movement Data 30 DRAM 30a Cache 31 Kernel Area 32 LRU list for OS (LRU list for Linux) 33-0, 33-1, . . . , 33 LRU list for each CPU core 34 Movement Information Table 35 page table 40 Cache redistribution processing unit 41 Memory requirement counting unit 42 Cache Miss Frequency Counting Unit 43 Cache redistribution decision unit 44 Cache Capacity Table 101 Page Movement Thread 102 OS-specific page transfer thread 103 List Deletion Thread 104 threads

Claims

1. a primary memory in which data is stored in units of pages; a secondary memory for storing data of a page to be moved from the primary memory; A processor having a plurality of computing cores; a first management information storage area provided for each of the plurality of processor cores, the first management information storage area storing a plurality of first lists indicating a migration order of each of the plurality of pages in a page group assigned to each of the plurality of processor cores among the plurality of pages; a second management information storage area provided for the operating system, for storing a second list for managing a plurality of pages selected from the page group in the plurality of first lists according to the order of movement as a page group of candidates to be moved to the secondary memory; a transfer processing unit that transfers data of a page selected from the page group in the second list from the primary memory to the secondary memory; Equipped with At least one of the plurality of arithmetic cores, By executing a first thread, the first list provided for the processing core is updated; By executing a second thread, a plurality of pages selected according to the order of movement from among the pages in the first list provided for the own computing core are added to the second list. An information processing device comprising:

2. a storage unit that stores migration management information for managing pages migrated to the secondary memory by the migration processing unit; a deletion processing unit provided for each of the plurality of processing cores, the deletion processing unit referencing the migration management information and deleting the page that has been migrated to the secondary memory from the first list; The information processing device according to claim 1 , further comprising:

3. a storage unit that stores page correspondence information that associates the page moved to the secondary memory with the processor core; a deletion processing unit that refers to the page correspondence information and deletes the page that has been moved to the secondary memory from the first list; The information processing device according to claim 1 , further comprising:

4. the second management information storage area is provided in each of the processor cores, a deletion processing unit that deletes the second list and the page that has been moved to the secondary memory from the first list for each of the plurality of processing cores; The information processing device according to claim 1 , further comprising:

5. a primary memory in which data is stored in units of pages; a secondary memory for storing data of a page to be moved from the primary memory; A processor having a plurality of computing cores; a first management information storage area provided for each of the plurality of processor cores, the first management information storage area storing a plurality of first lists indicating a migration order of each of the plurality of pages in a page group assigned to each of the plurality of processor cores among the plurality of pages; a second management information storage area provided for the operating system, for storing a second list for managing a plurality of pages selected from the page group in the plurality of first lists according to the order of movement as a page group of candidates to be moved to the secondary memory; In an information processing device comprising: At least one of the plurality of arithmetic cores By executing a first thread, the first list provided for the processing core is updated; By executing a second thread, a plurality of pages selected according to the order of movement from among the pages in the first list provided for the own computing core are added to the second list. Execute the process, A preset one of the plurality of arithmetic cores See the second list above, Data of a page selected from the page group of the second list is moved from the primary memory to the secondary memory. A memory control program for causing a process to be executed.

6. a memory capacity tallying unit that totals memory capacity requirements for each of the plurality of processor cores; a cache miss frequency counting unit that counts the number of cache misses for each of the plurality of processor cores; a cache redistribution determination unit that determines a cache capacity to be redistributed based on a required memory capacity of each processor core; The information processing device according to any one of claims 1 to 4, comprising:

7. The cache redistribution determination unit determines the cache capacity to be redistributed according to a ratio between a required memory capacity of a processor core at a source of the redistribution and a required memory capacity of a processor core at a destination of the redistribution.

7. The information processing device according to claim 6.

8. The cache redistribution determination unit redistributes the cache capacity when a ratio between a maximum value and a minimum value of cache miss frequencies in the plurality of processing cores is equal to or greater than a threshold value.

8. The information processing device according to claim 6 or 7.

9. The cache redistribution determination unit determines the processor core with the lowest cache miss frequency as the source of cache capacity transfer, and determines the processor core with the highest cache miss frequency as the destination of cache capacity transfer.

9. The information processing device according to claim 8.

10. At least one of the plurality of arithmetic cores accumulating the required memory capacity for each of the plurality of processing cores; Counting the number of cache misses for each of the plurality of processor cores; Determine the cache capacity to be redistributed based on the memory capacity required by each processor core.

6. The memory control program according to claim 5, further comprising: a program for executing a process.

11. a primary memory in which data is stored in units of pages; a secondary memory for storing data of a page to be moved from the primary memory; A processor having a plurality of computing cores; a first management information storage area provided for each of the plurality of processor cores, the first management information storage area storing a plurality of first lists indicating a migration order of each of the plurality of pages in a page group assigned to each of the plurality of processor cores among the plurality of pages; a second management information storage area provided for the operating system, for storing a second list for managing a plurality of pages selected from the page group in the plurality of first lists according to the order of movement as a page group of candidates to be moved to the secondary memory; In an information processing device comprising: At least one of the plurality of arithmetic cores, By executing a first thread, the first list provided for the processing core is updated; Adding a plurality of pages selected from the pages in the first list provided for the processing core of the processing core in accordance with the order of the movement to the second list by executing a second thread; and accumulating the required memory capacity for each of the plurality of processing cores; Counting the number of cache misses for each of the plurality of processor cores; Determine the cache capacity to be redistributed based on the memory capacity required by each processor core. Execute the process, A preset one of the plurality of arithmetic cores, See the second list above, Data of a page selected from the page group of the second list is moved from the primary memory to the secondary memory.

2. An information processing method comprising: executing a process.

Images