Detection device and drive control device

Abstract

To provide a drive control device including a drive control circuit that controls the drive of a device to be driven such as a motor, or an abnormality detection portion that detects an abnormality in a drive control signal output from the drive control circuit.SOLUTION: In a drive system 10, a drive control device 30 includes a filter unit 140 that smoothes a PWM signal output from a drive control circuit 40 that controls the driving of a drive target device 20, and an abnormality detection unit 130 that detects an abnormality in the drive control circuit on the basis of the level of a smoothed PWM signal smoothed by the filter unit. The abnormality detection unit detects an abnormality in the drive control circuit when the level of the smoothed PWM signal is out of a reference range.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a detection device and a drive control device. [Background technology]

[0002] Patent Document 1 describes a vehicle control device equipped with a clock generating circuit that generates periodic clock pulses and processes various data based on the clock pulses generated by the clock generating circuit, characterized in that the vehicle control device is provided with a time constant circuit in which a resistor and a capacitor are connected in series, a pulse voltage output means that outputs a pulse voltage at a predetermined time interval based on the clock pulses to the time constant circuit, a potential detection means that detects the potential of the capacitor that constitutes the time constant circuit, and a clock abnormality determination means that determines that a clock abnormality has occurred when the potential detected by the detection means deviates from a predetermined range (Claim 1).

[0003] Patent document 2 describes a brushless motor control device that drives and controls a brushless motor to rotate in accordance with an external command, comprising: a drive control unit that generates a drive signal for driving the brushless motor; a current detection circuit that detects the current value of each phase of the brushless motor; a plurality of AD conversion circuits connected to the current detection circuits of each phase; a clock generation circuit that outputs a clock pulse that serves as a reference for an operating cycle; a pulse output circuit that outputs a pulse signal based on the clock pulse; and an RC filter to which the pulse signal is input, the RC filter comprising a resistor and a capacitor connected in series, a pull-up resistor connected to a predetermined power supply connected to an intermediate connection point thereof, and the intermediate connection point being further connected to the plurality of AD conversion circuits (Claim 1). [Prior art document] [Patent documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 8-230651 [Patent Document 2] International Publication No. 2015 / 159474 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, it is possible to detect an abnormality in a clock generation circuit or an AD conversion circuit for detecting the current flowing through the coil of a brushless motor, but it is not possible to detect an abnormality in a drive control circuit for controlling the drive of a driven device such as a motor, or in a drive control signal output by the drive control circuit. [Means for solving the problem]

[0005] In a first aspect of the present invention, there is provided a detection device. The detection device may include a filter unit that smoothes a PWM signal output by a drive control circuit that controls driving of a driven device. The detection device may include an abnormality detection unit that detects an abnormality in the drive control circuit based on the level of the smoothed PWM signal smoothed by the filter unit.

[0006] The abnormality detection section may detect an abnormality in the drive control circuit in response to the level of the smoothed PWM signal being outside the reference range.

[0007] The detection device may further include a reference range setting section that sets the reference range in accordance with the duty ratio of the PWM signal to be output by the drive control circuit.

[0008] The abnormality detection section may detect an abnormality in the drive control circuit in response to the ripple of the smoothed PWM signal falling outside a reference range.

[0009] The abnormality detection section may detect an abnormality in the drive control circuit when a ripple in the smoothed PWM signal at a timing corresponding to a change point of the PWM signal output by the drive control circuit falls outside a reference range.

[0010] The abnormality detection unit may output a detection signal indicating the normality of the drive control circuit at time intervals shorter than a predetermined timeout time while not detecting an abnormality in the drive control circuit. The detection device may further include a watchdog timer that detects an abnormality in the drive control circuit in response to not receiving a detection signal indicating the normality of the drive control circuit within the timeout time.

[0011] The watchdog timer may detect an abnormality in the drive control circuit in response to receiving a detection signal indicating that the drive control circuit is normal at a time interval less than a predetermined lower limit time.

[0012] The drive control circuit and the abnormality detection unit may be realized by a microcontroller, and the filter unit and the watchdog timer may be provided outside the microcontroller.

[0013] The drive control circuit may output a PWM signal corresponding to each of the multiple channels. The filter unit may be provided corresponding to each of the multiple channels. The detection device may further include a switching unit that switches which of the multiple channels the smoothed PWM signal from the filter unit corresponding to should be supplied to the anomaly detection unit.

[0014] The detection device may further include a drive stopping unit that stops control of the driven device by the drive control circuit in response to detection of an abnormality in the drive control circuit.

[0015] According to a second aspect of the present invention, there is provided a drive control device. The drive control device may include a drive control circuit that controls driving of a drive target device. The drive control device may include a detection device that detects an abnormality in the drive control circuit.

[0016] According to a third aspect of the present invention, there is provided a detection method. The detection method may include performing a filter process to smooth a PWM signal output by a drive control circuit that controls driving of a driven device. The detection method may include detecting an abnormality in the drive control circuit based on a level of the smoothed PWM signal smoothed by the filter process.

[0017] According to a fourth aspect of the present invention, there is provided a detection program executed by a computer, which may cause the computer to function as an abnormality detection unit that detects an abnormality in a drive control circuit based on a level of a smoothed PWM signal that is smoothed by a filter that smoothes a PWM signal output by the drive control circuit that controls driving of a driven device.

[0018] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0019] [Figure 1] 1 shows the configuration of a drive system 10 according to the present embodiment. [Diagram 2] 4 shows an operation flow of the drive system 10 according to the present embodiment. [Diagram 3] 1 shows the number of interface terminals used for selecting and inputting a smoothed PWM signal in the drive system 10 according to this embodiment. [Figure 4] 4 shows ripples that occur in a smoothed PWM signal in accordance with changes in clock frequency in the drive system 10 according to the present embodiment. [Diagram 5] 22 illustrates an example computer 2200 in which aspects of the present invention may be embodied, in whole or in part. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] 1 shows the configuration of a drive system 10 according to this embodiment. The drive system 10 includes a drive target device 20 and a drive control device 30.

[0022] The drive target device 20 is a device that is to be driven by the drive control device 30. As an example, the drive target device 20 is a motor. The drive target device 20 may be, for example, a motor that drives a vehicle such as an electric vehicle (EV). In this embodiment, the drive target device 20 is a three-phase motor having a U-phase terminal connected to a U-phase coil, a V-phase terminal connected to a V-phase coil, and a W-phase terminal connected to a W-phase coil. Note that the drive target device 20 is not limited to a device that performs mechanical operations. For example, the drive target device 20 may be an electric device or power facility that operates by receiving a voltage or current output by the drive control device 30.

[0023] The drive control device 30 is connected to the drive target device 20 and drives the drive target device 20. The drive control device 30 supplies a voltage or current for driving the drive target device 20 to one or more input terminals of the drive target device 20. In this embodiment, the drive control device 30 supplies a current to be input to each of a U-phase terminal, a V-phase terminal, and a W-phase terminal of the drive target device 20, which is a three-phase motor.

[0024] The drive control device 30 includes a drive unit 180, a drive control circuit 40, and a detection device 50. The drive unit 180 is connected to the drive control circuit 40 via a drive stop unit 170 of the detection device 50. The drive unit 180 drives the drive target device 20 in response to one or more drive control signals input from the drive control circuit 40.

[0025] In this embodiment, the driving unit 180 is a three-phase inverter as an example. In general, a three-phase inverter has the following functions and configurations. The driving unit 180 as a three-phase inverter has an upper arm semiconductor switch and a lower arm semiconductor switch connected in series between a positive power supply line and a negative power supply line for each phase. The U-phase terminal of the drive target device 20 is connected to a midpoint between the upper arm semiconductor switch and the lower arm semiconductor switch of the U-phase, the V-phase terminal of the drive target device 20 is connected to a midpoint between the upper arm semiconductor switch and the lower arm semiconductor switch of the V-phase, and the W-phase terminal of the drive target device 20 is connected to a midpoint between the upper arm semiconductor switch and the lower arm semiconductor switch of the W-phase.

[0026] The driving unit 180 inputs a driving control signal for the upper arm semiconductor switch and a driving control signal for the lower arm semiconductor switch for each of the three phases. That is, the driving unit 180 inputs driving control signals for six channels (three phases x two upper and lower switches). Each semiconductor switch is turned on when the corresponding driving control signal becomes a first level (logic H, for example), and turned off when the corresponding driving control signal becomes a second level (logic L, for example). The driving unit 180 boosts the input terminal of the drive target device 20 to a positive reference potential in response to the upper arm semiconductor switch being turned on and the lower arm semiconductor switch being turned off, and lowers the input terminal of the drive target device 20 to a negative reference potential in response to the upper arm semiconductor switch being turned off and the lower arm semiconductor switch being turned on.

[0027] The drive control circuit 40 controls the drive of the drive target device 20 by the drive unit 180. In this embodiment, the drive control circuit 40 is realized by a microcontroller 100. The microcontroller 100 may be a computer including one or more processor cores, memories such as ROM and / or RAM, a timer, and an input / output device. Alternatively, the microcontroller 100 may be a computer such as a PC (personal computer), a workstation, a server computer, or a general-purpose computer. The microcontroller 100 operates as each component included in the drive control circuit 40 in this figure by executing a drive control program for controlling the drive of the drive target device 20. Alternatively, each component included in the drive control circuit 40 in this figure may be realized by a dedicated circuit.

[0028] The drive control circuit 40 has a clock source 105 and a drive control unit 110. The clock source 105 generates a clock CLK1 used by the drive control unit 110. Here, the "clock" is a pulse signal that rises to logic H and then falls to logic L at predetermined regular intervals.

[0029] The drive control unit 110 is connected to the clock source 105, and outputs a drive control signal using the clock CLK1 to control the drive of the drive target device 20. The drive control unit 110 may output a PWM (Pulse Width Modulation) signal corresponding to each of the multiple channels. In this embodiment, the drive control unit 110 outputs PWM signals for six channels for controlling the on / off of each of the upper arm side semiconductor switches and the lower arm side semiconductor switches that the drive unit 180 has for each phase.

[0030] Here, the drive control section 110 performs drive control of the drive target device 20 by PWM control. For this reason, each drive control signal output by the drive control section 110 is a PWM signal. For example, the microcontroller 100 executes a drive control program to generate a period for outputting a PWM signal and a pulse width (period for which the PWM signal should be logic H) that the PWM signal should have by using a counter using a timer circuit included in the microcontroller 100, and outputs a PWM signal that is logic H during a period of a desired pulse width for each period of the PWM signal and logic L during the other periods by using a digital output circuit. The drive control section 110 may receive a drive command that indicates the drive amount of the drive target device 20 from a device or the like external to the drive control device 30, and output a PWM signal having a duty ratio according to the drive amount for each channel so as to drive the drive target device 20 with a drive amount according to the drive command.

[0031] The detection device 50 is connected to the drive control circuit 40 and detects an abnormality in the drive control circuit 40. The detection device 50 has one or more filter units 140a to f, a switching unit 150, a reference range setting unit 115, a clock source 120, an AD converter 125, an abnormality detection unit 130, a clock source 160, a watchdog timer 165, and a drive stopping unit 170. In this embodiment, the reference range setting unit 115, the clock source 120, the AD converter 125, and the abnormality detection unit 130 are realized by a microcontroller 100. The microcontroller 100 operates as each of the components of the reference range setting unit 115, the clock source 120, the AD converter 125, and the abnormality detection unit 130 by executing a detection program for detecting an abnormality in the drive control circuit 40.

[0032] Alternatively, the reference range setting unit 115, the clock source 120, the AD converter 125, and the anomaly detection unit 130 may be realized by dedicated circuits. In this embodiment, one or more filter units 140a-f, the switching unit 150, the clock source 160, the watchdog timer 165, and the drive stopping unit 170 are provided outside the microcontroller 100. These components are realized by dedicated circuits. Alternatively, at least one of these components may be realized by executing a detection program in the microcontroller 100.

[0033] One or more filter units 140a-f (also referred to as "filter unit 140") are provided corresponding to one or more channels, respectively. In this embodiment, each filter unit 140 is provided corresponding to each of the six channels. Each filter unit 140 is connected to the drive control unit 110, smoothes the PWM signal output by the drive control unit 110, and outputs the smoothed PWM signal.

[0034] For example, the filter unit 140 is an RC filter. The filter unit 140 removes high-frequency components of the PWM signal and extracts only low-frequency components to smooth the PWM signal to a voltage level (analog amount) according to the duty ratio. The filter unit 140 may output an average or weighted average of the PWM signal in a predetermined period as a smoothed PWM signal. In this case, the weighted average may be such that a larger weight is used for the PWM signal closer to the current time. The smoothed PWM signal output by the filter unit 140 may be an analog signal having a voltage level (or current level) according to the duty ratio of the digital PWM signal output by the drive control unit 110.

[0035] The switching unit 150 is connected to one or more filter units 140. The switching unit 150 switches which of the one or more channels the smoothed PWM signal from the filter unit 140 corresponding to should be supplied to the anomaly detection unit 130, in response to a selection signal supplied from the anomaly detection unit 130. Note that two or more switching units 150 may be provided, and smoothed PWM signals from two or more filter units 140 corresponding to two or more of the multiple channels may be supplied to the anomaly detection unit 130 via the AD converter 125.

[0036] The reference range setting section 115 is connected to the drive control section 110. The reference range setting section 115 sets, for each of one or more channels, a reference range within which a smoothed PWM signal obtained by smoothing a PWM signal output by the drive control section 110 should be determined to be normal. Here, the reference range setting section 115 may set the reference range according to the duty ratio of the PWM signal to be output by the drive control section 110.

[0037] The clock source 120 generates a clock CLK2 used by the AD converter 125. The AD converter 125 receives a smoothed PWM signal selected from the smoothed PWM signals of one or more channels from the switching unit 150 and converts it into a digital value. In a configuration in which the switching unit 150 simultaneously selects and outputs two or more smoothed PWM signals, two or more AD converters 125 that receive an analog signal from one input terminal and convert it into a digital signal may be provided, and each of the two or more smoothed PWM signals may be analog-to-digital converted.

[0038] The abnormality detection unit 130 is connected to the reference range setting unit 115 and the AD converter 125. The abnormality detection unit 130 outputs a selection signal to the switching unit 150 for selecting a smoothed PWM signal to be inspected from among the smoothed PWM signals of a plurality of channels. The abnormality detection unit 130 receives the smoothed PWM signal selected in response to the selection signal via the AD converter 125. Then, the abnormality detection unit 130 detects an abnormality in the drive control circuit 40 based on the level of the smoothed PWM signal.

[0039] In this embodiment, the abnormality detection unit 130 detects an abnormality in the drive control circuit 40 when the level of the smoothed PWM signal falls outside the reference range, using the reference range set by the reference range setting unit 115. The abnormality detection unit 130 may receive the analog smoothed PWM signal from the switching unit 150 without going through the AD converter 125. In this case, the abnormality detection unit 130 may detect an abnormality in the drive control circuit 40 when the analog smoothed PWM signal falls outside the analog reference range set by the reference range setting unit 115.

[0040] While not detecting an abnormality in the drive control circuit 40, the abnormality detection unit 130 outputs a detection signal indicating the normality of the drive control circuit 40 (for example, a detection signal of logic H, indicated as a "normal signal") to the watchdog timer 165 at time intervals shorter than a predetermined timeout time. Furthermore, in response to detecting an abnormality in the drive control circuit 40, the abnormality detection unit 130 stops outputting the normal signal and outputs a drive stop signal (for example, a drive stop signal of logic H) to the drive stop unit 170 to instruct the drive target device 20 to be stopped.

[0041] The clock source 160 generates a clock CLK3 used by a watchdog timer 165 (also referred to as "WDT"). The watchdog timer 165 is connected to the abnormality detection unit 130 and the clock source 160. The watchdog timer 165 receives a normal signal that is output by the abnormality detection unit 130, for example, periodically. The watchdog timer 165 detects an abnormality in the drive control circuit 40 in response to not receiving the normal signal within a timeout period.

[0042] For example, the watchdog timer 165 sets the timer value to an initial value every time it receives a normal signal, and decrements the timer value in response to the clock CLK3. The watchdog timer 165 may determine that the timeout time has elapsed if it does not receive a normal signal before the timer value becomes 0. In response to detecting an abnormality in the drive control circuit 40, the watchdog timer 165 outputs a drive stop signal to the drive stop unit 170 to instruct the drive target device 20 to stop driving.

[0043] The drive stopping unit 170 is connected to the drive control unit 110, the abnormality detection unit 130, and the watchdog timer 165. The drive stopping unit 170 stops the control of the drive target device 20 by the drive control circuit 40 in response to the detection of an abnormality in the drive control circuit 40. When an abnormality in the drive control circuit 40 is not detected and a drive stop signal instructing to stop driving the drive target device 20 is not received from either the abnormality detection unit 130 or the watchdog timer 165, the drive stopping unit 170 supplies one or more drive control signals output by the drive control unit 110 to the drive unit 180 without changing them. When an abnormality in the drive control circuit 40 is detected and a drive stop signal instructing to stop driving the drive target device 20 is received from at least one of the abnormality detection unit 130 or the watchdog timer 165, the drive stopping unit 170 changes one or more drive control signals output by the drive control unit 110 to a signal value for stopping the drive of the drive target device 20 and supplies the changed signal value to the drive unit 180. For example, the drive stopping unit 170 may supply a plurality of drive control signals to the drive unit 180 for short-circuiting all phases of either the upper arm or the lower arm, thereby suppressing or stopping the rotation of the driven target device 20, which is a motor.

[0044] In the drive control device 30 described above, the drive control section 110 outputs drive control signals for six channels required by the drive section 180 to drive the drive target device 20, which is a three-phase motor. Alternatively, the drive section 180 may request any number (one or more) of drive control signals required to drive the drive target device 20 depending on the type of the drive target device 20, and the drive control section 110 may supply any number of drive control signals required by the drive section 180.

[0045] Furthermore, the drive control device 30 may have a separate AD converter 125 for each channel of the drive control signal, instead of having the switching unit 150. In this case, each AD converter 125 receives the smoothed PWM signal output by the corresponding filter unit 140, performs analog-to-digital conversion, and supplies the signal to the anomaly detection unit 130.

[0046] Furthermore, the drive control device 30 may not have the drive stop unit 170. In this case, the abnormality detection unit 130 may notify, for example, a higher-level control device that an abnormality has been detected in the drive control circuit 40. Then, the drive control device 30 may carry out abnormality processing in accordance with the higher-level control device in response to a drive command from the higher-level control device that has received this notification.

[0047] Furthermore, the drive control device 30 does not need to have the watchdog timer 165. In this case, the abnormality detection unit 130 does not need to have the function of outputting a detection signal indicating that the drive control circuit 40 is normal.

[0048] 2 shows an operation flow of the drive system 10 according to this embodiment. For the sake of convenience, this operation flow shows each step in sequence, but the processing of each step may be performed in a different order or in parallel as long as there is no dependency between the steps.

[0049] In S200 (step 200), the drive control section 110 outputs one or more drive control signals for driving the drive target device 20 with a drive amount corresponding to a drive command input from a device external to the drive control device 30. Each drive control signal is a PWM signal having a change timing and a duty ratio determined by the drive control section 110 according to the drive amount specified by the drive command and the rotation angle of the drive target device 20, which is a motor, etc.

[0050] In S205, the reference range setting unit 115 calculates and sets a reference range of the smoothed drive control signal for determining that the drive control circuit 40 is normal, according to the duty ratio of each drive control signal to be output by the drive control unit 110. The reference range setting unit 115 may set a range obtained by adding positive and negative margins to a target value of the smoothed PWM signal (theoretical value of the digital value to be received via the AD converter 125) according to the duty ratio that the drive control signal should have, as the reference range.

[0051] For example, when the drive control signal is a PWM signal with a duty ratio of 60% in which logic H is 5V and logic L is 0V, the target value of the smoothed PWM signal is 3V (5V×60%). If the AD converter 125 is a 12-bit AD converter with a minimum analog input of 0V and a maximum analog input of 5V, the AD converter 125 converts 0V to a digital value of 0 and 5V to a digital value of 4095. Therefore, the AD converter 125 converts the 3V smoothed PWM signal to a digital value of 2457 (=4095×60%). Therefore, the reference range setting unit 115 adds, for example, +50 as a positive margin and, for example, −50 as a negative margin to 2457, which is the target value (or theoretical value) of the smoothed PWM signal corresponding to the drive control signal with a duty ratio of 60%, to set the range from 2407 to 2507 as the reference range.

[0052] Since the drive control unit 110 controls each of the drive control signals of the multiple channels individually, the drive control signals of the multiple channels may have different duty ratios. Therefore, the reference range setting unit 115 may set a different reference range for each channel. When detecting an abnormality in the drive control circuit 40 using a smoothed PWM signal smoothed over one or more periods in a case where the drive target device 20 is rotated at a constant speed at all times, the abnormality detection unit 130 may use a fixed reference range, and the drive control device 30 may have a configuration without the reference range setting unit 115.

[0053] In S210, each filter unit 140 smoothes the PWM signal output by the drive control unit 110 as a drive control signal and outputs it as a smoothed PWM signal. Each filter unit 140 smooths the PWM signal to output an average value or a value close to the average value of the PWM signal in a certain period of time in the recent past. By such smoothing or averaging, each filter unit 140 can remove high-frequency components of the PWM signal and extract only low-frequency components to obtain a voltage level (analog quantity) according to the duty ratio of the PWM signal. For example, when an RC filter is used as the filter unit 140, the smoothed PWM signal is a weighted average value obtained by weighting the PWM signal more heavily and averaging the instantaneous value closer to the current time. Here, for example, if the cutoff frequency of the RC filter is made sufficiently low compared to the frequency of the PWM signal (for example, 1 / 1000 frequency), the filter unit 140 can obtain a smoothed PWM signal that shows the duty ratio of the PWM signal by reducing or removing the influence of the fluctuation (switching between logic H and logic L) of each cycle of the PWM signal.

[0054] In S215, the abnormality detection unit 130 outputs a selection signal for selecting a smoothed PWM signal to be inspected from among the smoothed PWM signals of the multiple channels to the switching unit 150. The switching unit 150 selects the smoothed PWM signal specified by the selection signal from among the smoothed PWM signals of the multiple channels, and outputs it to the AD converter 125.

[0055] Here, the abnormality detection unit 130 may output a selection signal to sequentially switch among the smoothed PWM signals at a predetermined cycle, and may sequentially inspect the smoothed PWM signals. The abnormality detection unit 130 may also repeat the process of sequentially inspecting all of the smoothed PWM signals at each predetermined cycle.

[0056] In S220, the AD converter 125 receives the smoothed PWM signal to be inspected from the switching unit 150 and converts it into a digital smoothed PWM signal. In S225, the abnormality detection unit 130 receives the digital smoothed PWM signal from the AD converter 125 and detects an abnormality in the drive control circuit 40 based on the level of the smoothed PWM signal. The abnormality detection unit 130 may detect an abnormality in the drive control circuit 40 in response to the level of the smoothed PWM signal falling outside the reference range set by the reference range setting unit 115.

[0057] In S230, in response to detecting an abnormality in the drive control circuit 40, the abnormality detection unit 130 outputs a drive stop signal to the drive stop unit 170 to instruct the drive of the drive target device 20 to be stopped. In S235, in response to receiving this drive stop signal, the drive stop unit 170 changes each drive control signal output by the drive control unit 110 to a signal value for stopping the drive of the drive target device 20, and supplies the changed signal value to the drive unit 180. As a result, the drive stop unit 170 stops the drive control of the drive target device 20 by the drive control unit 110.

[0058] In S240, the abnormality detection unit 130 outputs a normal signal to the watchdog timer 165 in response to not detecting an abnormality in the drive control circuit 40. In S245, the watchdog timer 165 determines whether or not an abnormality in the drive control circuit 40 has been detected due to a timeout of the normal signal. While the normal signal is received within the timeout period, in S250, the watchdog timer 165 does not detect an abnormality in the drive control circuit 40 and clears the timer value of the watchdog timer 165 to its initial value. The drive system 10 advances the process to S200 and continues driving the drive target device 20.

[0059] The watchdog timer 165 detects an abnormality in the drive control circuit 40 in response to not receiving a normal signal within the timeout period. For example, in S240, if the abnormality detection unit 130 is unable to output a normal signal due to an abnormality in the abnormality detection unit 130 itself, the watchdog timer 165 can detect an abnormality (monitoring failure) in the drive control circuit 40 due to a timeout. In response to detecting an abnormality in the drive control circuit 40, the watchdog timer 165 outputs a drive stop signal to the drive stop unit 170 to instruct the drive of the drive target device 20 to be stopped, and the process proceeds to S235.

[0060] According to the detection device 50 described above, the anomaly detection section 130 can detect an anomaly in the PWM signal output by the drive control section 110. The anomaly detection section 130 according to this embodiment does not need to detect an anomaly by timer measuring the PWM signal using the clock CLK1 used by the drive control section 110 as a reference clock, and can detect an anomaly using a smoothed PWM signal sampled by the AD converter 125 using a clock CLK2 different from the clock CLK1. Therefore, it is possible to prevent the clock CLK1 from causing a common cause failure (CCF) of the drive control circuit 40 and the detection device 50 when the detection device 50 samples the PWM signal.

[0061] Even when the AD converter 125 samples the smoothed PWM signal using the clock CLK1 as the source instead of the clock CLK2, the detection device 50 samples the smoothed PWM signal, which is obtained by smoothing the PWM signal, at a relatively low speed using the AD converter 125 and detects an abnormality based on the level of the smoothed PWM signal. Therefore, the range of common cause failures (CCFs) can be sufficiently narrowed by using a different frequency division mechanism, for example.

[0062] Furthermore, the detection device 50 described above can detect an abnormality in the drive control circuit 40 in the following example failure cases.

[0063] (1) Duty ratio abnormality Even if the cycle of the PWM signal generated by the drive control unit 110 is normal, an error may occur in the period during which the PWM signal is set to logic H due to a malfunction of the drive control circuit 40. In this case, the PWM signal output by the drive control unit 110 will have a duty ratio different from the PWM signal that should be output by the drive control unit 110.

[0064] In this case, the reference range setting unit 115 sets a reference range according to the duty ratio of the PWM signal that should be output by the drive control unit 110. Meanwhile, the filter unit 140 smoothes the PWM signal having an erroneous duty ratio that is actually output by the drive control unit 110, and outputs a smoothed PWM signal according to the erroneous duty ratio. As a result, in S225, the abnormality detection unit 130 detects that the level of the smoothed PWM signal falls outside the reference range set by the reference range setting unit 115, thereby being able to detect an abnormality in the drive control circuit 40.

[0065] (2) PWM signal period abnormality Even if the pulse width (e.g., the length of the period of logical H) of the PWM signal generated by drive control section 110 is normal, an error may occur in the period of the PWM signal due to a malfunction of drive control circuit 40 or the like. In this case, the PWM signal output by drive control section 110 will have a different duty ratio (=pulse width / period) from the PWM signal that should originally be output by drive control section 110. In this case as well, detection device 50 can detect an abnormality in drive control circuit 40 in the same manner as in (1) above.

[0066] (3) Cycle abnormality of clock source 105 When drive control unit 110 defines both the pulse width and period of the PWM signal by the number of cycles of clock CLK1 generated by clock source 105, both the pulse width and period of the PWM signal change in proportion to the period of clock CLK1. In this case, even if an error occurs in the period of clock CLK1, the duty ratio of the PWM signal will be the same as the duty ratio of the PWM signal that should be output by drive control unit 110.

[0067] Here, when the drive control unit 110 and the abnormality detection unit 130 are realized by the microcontroller 100, both the drive control unit 110 and the abnormality detection unit 130 are realized by a processor core of the microcontroller 100 that operates using the clock CLK1 as a base clock. Therefore, the abnormality detection unit 130 outputs a normal signal at a time interval proportional to the period of the clock CLK1. Therefore, when the period of the clock CLK1 becomes larger than a certain level, the period at which the abnormality detection unit 130 outputs the normal signal also becomes larger, and the period of the detection signal exceeds the timeout time. This allows the watchdog timer 165 to detect an abnormality in which the clock period of the clock source 105 becomes larger.

[0068] The watchdog timer 165 may use a timeout time that is a certain margin added to the period of the normal signal that should be output by the abnormality detection unit 130. For example, the watchdog timer 165 may use a timeout time that is a period of the original normal signal plus a margin of +10% (i.e., a timeout time of the period of the normal signal × 1.1).

[0069] Furthermore, the watchdog timer 165 may detect an abnormality in the drive control circuit 40 in response to receiving a normal signal at a time interval less than a predetermined lower limit time. When the abnormality detection unit 130 operates using the clock CLK1 as a base clock, if the period of the clock CLK1 becomes shorter than a certain level, the period at which the abnormality detection unit 130 outputs a normal signal also becomes shorter. The watchdog timer 165 detects an abnormality in the drive control circuit 40 when it receives a normal signal at a time interval less than the lower limit time, and can therefore also detect an abnormality in which the clock period of the clock source 105 becomes shorter.

[0070] The watchdog timer 165 may use a lower limit time obtained by subtracting a certain margin from the period of the normal signal. For example, the watchdog timer 165 may use a lower limit time obtained by subtracting a 10% margin from the period of the normal signal (i.e., a lower limit time of 0.9 times the period of the normal signal).

[0071] (4) Other abnormalities in the microcontroller 100 When the microcontroller 100 fails, the watchdog timer 165 cannot receive a normal signal within the timeout period. Therefore, the watchdog timer 165 can detect an abnormality in the drive control circuit 40 even when the microcontroller 100 fails and the components in the microcontroller 100 in the detection device 50 do not operate normally. In order to improve reliability, the processor cores in the microcontroller 100 may be made redundant or multiplexed. In this case, the multiple cores in the microcontroller 100 may perform lock-step operation. That is, for example, the microcontroller 100 synchronously executes the processes of the drive control unit 110, the reference range setting unit 115, and the abnormality detection unit 130 in each processor core, and compares the processing results by each processor core. Then, if the processing results by each processor core match, the operation is continued and drive control is performed according to the processing results. If the processing result of any processor core differs from the processing result of the other processors, the microcontroller 100 determines that one of the processor cores has failed, detects an abnormality in the drive control circuit 40, and stops the drive control.

[0072] 3 shows the number of interface terminals used for selecting and inputting a smoothed PWM signal in the drive system 10 according to this embodiment. In this figure, the "Drive Target" column shows the number of drive target devices 20, which are three-phase motors as an example of drive targets of the drive control device 30. When there is one three-phase motor to be driven, a six-channel PWM signal is used. When there are two three-phase motors to be driven, a 12-channel PWM signal is used.

[0073] The "Switching" column indicates how many channels of smoothed PWM signals the switching unit 150 can select from to supply the smoothed PWM signal to the microcontroller 100 (i.e., how many channels of smoothed PWM signals are multiplexed and supplied to the microcontroller 100). For example, "1:1" indicates that the smoothed PWM signals of each channel are supplied directly to the microcontroller 100. "2:1" indicates that the switching unit 150 selects one smoothed PWM signal from the smoothed PWM signals of two channels and supplies it to the microcontroller 100.

[0074] The "number of selection signal bits" indicates the number of bits of the selection signal to be supplied from the abnormality detection unit 130 to the switching unit 150. For example, in the case of "1:1", the switching unit 150 is not required, and therefore the selection signal is also not required (i.e., the number of bits of the selection signal is 0). In the case of "2:1", a one-bit selection signal can be used to select which of the two-channel smoothed PWM signals is to be supplied to the microcontroller 100. In the case of "4:1", a two-bit selection signal can be used to select which of the four-channel smoothed PWM signals is to be supplied to the microcontroller 100 (i.e., a signal that can specify four values, 00, 01, 10, and 11, in binary).

[0075] The "number of AD converter inputs" indicates how many smoothed PWM signals are to be AD converted by the AD converter 125 when the smoothed PWM signals used for driving control of the number of three-phase motors shown in the "drive target" column are multiplexed using the switching unit 150 shown in the "switching" column and supplied to the AD converter 125. For example, when the "drive target" is 1 and the "switching" is "4:1", 6-channel PWM signals are multiplexed at 4:1, so if the microcontroller 100 can input two smoothed PWM signals and perform AD conversion, all smoothed PWM signals can be inspected. Also, when the "drive target" is 2 and the "switching" is "4:1", 12-channel PWM signals are multiplexed at 4:1, so if the microcontroller 100 can input three smoothed PWM signals and perform AD conversion, all smoothed PWM signals can be inspected.

[0076] "Number of interface terminals" indicates the number of interface terminals of the microcontroller 100 required for selecting and inputting the smoothed PWM signal. This "number of interface terminals" is the sum of the number of bits of the selection signal indicated in "number of selection signal bits" and the number of inputs of the smoothed PWM signal indicated in "number of AD converter inputs."

[0077] As shown in this figure, the drive control device 30 can reduce the number of terminals of the microcontroller 100 required to receive smoothed PWM signals of multiple channels by switching between multiple smoothed PWM signals output by multiple filter sections 140 using a switching section 150 and supplying them to the AD converter 125.

[0078] 4 shows ripples that occur in the smoothed PWM signal in accordance with changes in the clock frequency of the clock CLK1 in the drive system 10 according to this embodiment. More specifically, from the top of the figure, the ripple waveform of the smoothed PWM signal, the waveform of a PWM signal with a frequency of 825 Hz, the waveform of a PWM signal with a frequency of 1.65 kHz, the waveform of a PWM signal with a frequency of 3.3 kHz, and the waveform of a PWM signal with a frequency of 6.6 kHz are shown.

[0079] As shown in the waveforms of each PWM signal, the PWM signal becomes logic H and then logic L with a pulse width corresponding to the duty ratio within each period of the length corresponding to the frequency of the PWM signal. If the normal PWM signal frequency is 825 kHz and the frequency of the clock CLK1 becomes double, quadruple, and eight times due to an abnormality, the drive control unit 110 outputs PWM signals with double (1.65 kHz), quadruple (3.3 kHz), and eight times (6.6 kHz) frequencies accordingly. When the drive control unit 110 determines the pulse width and period of the PWM signal based on the period of the clock CLK1, it outputs a PWM signal with the same duty ratio even if the frequency of the clock CLK1 changes to double, quadruple, and eight times as shown in this figure.

[0080] In contrast, as shown in the waveform of the smoothed PWM signal, the magnitude of the ripple that occurs in the smoothed PWM signal changes depending on the frequency of the PWM signal that is the target of smoothing. In this figure, the waveforms of the smoothed PWM signals when the PWM signal frequencies are 825 Hz, 1.65 kHz, 3.3 kHz, and 6.6 kHz are each shown with the same line type as the waveforms of the respective PWM signals.

[0081] As shown in the figure, the smoothed PWM signal obtained by smoothing the PWM signal has a periodic fluctuation (ripple) that is smaller than the amplitude between logic H and logic L of the PWM signal. When the same filter unit 140 is used, as shown at time points S1 and S2 in the figure, the magnitude of the ripple generated in the smoothed PWM signal becomes larger as the frequency of the PWM signal to be smoothed becomes lower, and becomes smaller as the frequency of the PWM signal to be smoothed becomes higher. This is because the filter unit 140 is a low-pass filter such as an RC filter, and at frequencies higher than the cutoff frequency, the higher the frequency, the more the vibration of the input signal is attenuated and output.

[0082] If the smoothed PWM signal is an average or weighted average of the PWM signal in a predetermined period, filter unit 140 sets the average or weighted average to a larger value the longer the period of the most recent PWM signal at logic H, and sets the average or weighted average to a smaller value the longer the period of the most recent PWM signal at logic L. Even in this case, when the same filter unit 140 is used, the magnitude of the ripple generated in the smoothed PWM signal becomes larger the lower the frequency of the PWM signal to be smoothed, and becomes smaller the higher the frequency of the PWM signal to be smoothed.

[0083] Therefore, the abnormality detection unit 130 may detect an abnormality in the drive control circuit 40 when the ripple of the smoothed PWM signal falls outside the reference range. Specifically, in S205 of Fig. 2, the reference range setting unit 115 may set the reference range to a range obtained by adding positive and negative margins to the theoretical value of the smoothed PWM signal including the ripple, instead of setting the reference range to a range obtained by adding positive and negative margins to the theoretical value of the smoothed PWM signal not taking ripple into consideration as described in relation to Fig. 2.

[0084] For example, in the example shown in the figure, the theoretical value of the smoothed PWM signal without considering the ripple is 2.5V (5V x duty ratio 50%), while the theoretical value of a normal 825Hz PWM signal including the ripple is about 2.57V. Therefore, the reference range setting unit 115 may set the reference range to a range from 2.54V to 2.60V, which is obtained by adding a margin of, for example, ±0.03V to the theoretical value of the smoothed PWM signal including the ripple. Depending on the size of the margin, the reference range setting unit 115 may set a reference range that does not include the theoretical value of the smoothed PWM signal without considering the ripple.

[0085] The theoretical value of the smoothed PWM signal including the ripple may vary depending on the duty ratio of the PWM signal. Therefore, the reference range setting unit 115 may generate a reference range including the theoretical value of the smoothed PWM signal including the ripple depending on the duty ratio of the PWM signal to be output by the drive control circuit 40. In this case, the reference range setting unit 115 may store in advance a table in which the theoretical values ​​or reference ranges of the smoothed PWM signal correspond to various duty ratios of the PWM signal, and generate a reference range according to the duty ratio of the PWM signal using this table. Also, for example, the reference range setting unit 115 may store in advance a numerical model of the filter unit 140, and input the PWM signal to be output by the drive control circuit 40 to this numerical model to calculate the theoretical value of the smoothed PWM signal.

[0086] As a result, even if an abnormality occurs in the frequency of the clock CLK1 and the ripple of the smoothed PWM signal falls outside the reference range, the abnormality detection unit 130 can detect an abnormality in the drive control circuit 40. Here, the detection device 50 may detect an abnormality by the abnormality detection unit 130 when the frequency of the clock CLK1 becomes higher than the normal frequency, and may detect an abnormality by using a timeout of the watchdog timer 165 when the frequency of the clock CLK1 becomes lower than the normal frequency.

[0087] In order to be able to determine the ripple of the smoothed PWM signal, the AD converter 125 may sample the smoothed PWM signal at a timing corresponding to a change point of the PWM signal output by the drive control unit 110. In the example shown in the figure, the AD converter 125 samples the smoothed PWM signal at time points S1 and S2, which are timings corresponding to the change points where the PWM signal changes from logic H to logic L. Alternatively, the AD converter 125 may sample the smoothed PWM signal at a timing corresponding to the change point where the PWM signal changes from logic L to logic H.

[0088] To achieve this, for example, the microcontroller 100 may generate a timer interrupt at the timing when the pulse of the PWM signal should fall or rise, and perform drive control to fall or rise the PWM signal in response to the timer interrupt, while sampling by the AD converter 125. Note that the AD converter 125 does not necessarily have to sample the smoothed PWM signal at the same timing as the change point of the PWM signal, and may sample the smoothed PWM signal at a timing slightly delayed from the change point of the PWM signal. In this way, the abnormality detection unit 130 can detect an abnormality in the drive control circuit 40 in response to the ripple of the smoothed PWM signal falling outside the reference range at the timing corresponding to the change point of the PWM signal output by the drive control circuit 40.

[0089] Alternatively, the AD converter 125 may sample at least one of the maximum and minimum values ​​of the smoothed PWM signal, at which the ripple is maximum in a predetermined period, such as the period of the PWM signal or a multiple of the period. This allows the abnormality detection unit 130 to detect an abnormality in the drive control circuit 40 when the ripple of the smoothed PWM signal falls outside the reference range.

[0090] Various embodiments of the present invention may be described with reference to flow charts and block diagrams, where the blocks may represent (1) stages of a process in which operations are performed or (2) sections of an apparatus responsible for performing the operations. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer readable instructions stored on a computer readable medium, and / or a processor provided with computer readable instructions stored on a computer readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry including logical AND, logical OR, logical XOR, logical NAND, logical NOR, and other logical operations, memory elements such as flip-flops, registers, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

[0091] A computer-readable medium may include any tangible device capable of storing instructions that are executed by a suitable device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture that includes instructions that can be executed to create means for performing the operations specified in the flowcharts or block diagrams. Examples of computer-readable media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), Blu-ray (RTM) disks, memory sticks, integrated circuit cards, and the like.

[0092] The computer readable instructions may include either assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0093] Computer readable instructions may be provided to a processor or programmable circuitry of a general purpose computer, special purpose computer, or other programmable data processing apparatus, either locally or over a local area network (LAN), a wide area network (WAN), such as the Internet, etc., to execute the computer readable instructions to create means for performing the operations specified in the flowcharts or block diagrams. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

[0094] 5 illustrates an example of a computer 2200 in which aspects of the present invention may be embodied in whole or in part. Programs installed on the computer 2200 may cause the computer 2200 to function as or perform operations associated with an apparatus or one or more sections of the apparatus according to an embodiment of the present invention, and / or to perform a process or steps of the process according to an embodiment of the present invention. Such programs may be executed by the CPU 2212 to cause the computer 2200 to perform specific operations associated with some or all of the blocks of the flowcharts and block diagrams described herein.

[0095] The computer 2200 according to this embodiment includes a CPU 2212, a RAM 2214, a graphic controller 2216, and a display device 2218, which are connected to each other by a host controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a DVD-ROM drive 2226, and an IC card drive, which are connected to the host controller 2210 via an input / output controller 2220. The computer also includes legacy input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0096] The CPU 2212 operates according to a program stored in the ROM 2230 and the RAM 2214, thereby controlling each unit. The graphic controller 2216 retrieves image data generated by the CPU 2212 into a frame buffer or the like provided in the RAM 2214 or into the graphic controller 2216 itself, and causes the image data to be displayed on the display device 2218.

[0097] The communication interface 2222 communicates with other electronic devices via a network. The hard disk drive 2224 stores programs and data used by the CPU 2212 in the computer 2200. The DVD-ROM drive 2226 reads programs or data from the DVD-ROM 2201 and provides the programs or data to the hard disk drive 2224 via the RAM 2214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0098] The ROM 2230 stores therein a boot program or the like executed by the computer 2200 upon activation, and / or a program that depends on the hardware of the computer 2200. The input / output chip 2240 may also connect various input / output units to the input / output controller 2220 via a parallel port, a serial port, a keyboard port, a mouse port, and the like.

[0099] The programs are provided by a computer-readable medium such as a DVD-ROM 2201 or an IC card. The programs are read from the computer-readable medium, installed in the hard disk drive 2224, the RAM 2214, or the ROM 2230, which are also examples of computer-readable media, and executed by the CPU 2212. Information processing described in these programs is read by the computer 2200, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be constructed by realizing information manipulation or processing according to the use of the computer 2200.

[0100] For example, when communication is performed between the computer 2200 and an external device, the CPU 2212 may execute a communication program loaded in the RAM 2214 and instruct the communication interface 2222 to perform communication processing based on the processing described in the communication program. Under the control of the CPU 2212, the communication interface 2222 reads transmission data stored in a transmission buffer processing area provided in the RAM 2214, the hard disk drive 2224, the DVD-ROM 2201, or a recording medium such as an IC card, and transmits the read transmission data to the network, or writes reception data received from the network to a reception buffer processing area or the like provided on the recording medium.

[0101] Furthermore, the CPU 2212 may cause all or a necessary portion of a file or database stored in an external recording medium such as the hard disk drive 2224, the DVD-ROM drive 2226 (DVD-ROM 2201), an IC card, etc. to be read into the RAM 2214, and perform various types of processing on the data on the RAM 2214. The CPU 2212 then writes back the processed data to the external recording medium.

[0102] Various types of information, such as various types of programs, data, tables, and databases, may be stored in the recording medium and undergo information processing. The CPU 2212 may perform various types of processing on the data read from the RAM 2214, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequence of the program, and write back the results to the RAM 2214. The CPU 2212 may also search for information in a file, database, etc. in the recording medium. For example, when a plurality of entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored in the recording medium, the CPU 2212 may search for an entry that matches a condition, in which an attribute value of the first attribute is specified, from among the plurality of entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0103] The above-described programs or software modules may be stored in a computer-readable medium on the computer 2200 or in the vicinity of the computer 2200. Also, a recording medium such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet can be used as a computer-readable medium, thereby providing the programs to the computer 2200 via the network.

[0104] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0105] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0106] 10 Drive System 20 Driven device 30 Drive control device 40 Drive control circuit 50 Detection Device 100 Microcontrollers 105 Clock Source 110 Drive control unit 115 Reference range setting section 120 Clock Source 125 A / D converter 130 Abnormality detection unit 140a~f Filter section 150 Switching section 160 Clock Source 165 Watchdog Timer 170 Drive stop part 180 Drive unit 2200 Computer 2201 DVD-ROM 2210 Host Controller 2212 CPU 2214 RAM 2216 Graphics Controller 2218 Display Device 2220 Input / Output Controller 2222 Communication Interface 2224 Hard Disk Drive 2226 DVD-ROM drive 2230 ROM 2240 Input / Output Chip 2242 Keyboard

Claims

1. A filter unit that smoothes a PWM signal output from a drive control circuit that controls the drive of a driven device; an abnormality detection unit that detects an abnormality in the drive control circuit based on a level of the smoothed PWM signal smoothed by the filter unit; Equipped with The abnormality detection unit detects an abnormality in the drive control circuit when a ripple in the smoothed PWM signal at a timing corresponding to a change point of the PWM signal output by the drive control circuit falls outside a reference range. Detection device.

2. A filter unit that smoothes a PWM signal output by a drive control circuit that controls the drive of a driven device; an abnormality detection unit that detects an abnormality in the drive control circuit based on a level of the smoothed PWM signal smoothed by the filter unit; Equipped with the drive control circuit outputs the PWM signal corresponding to each of a plurality of channels; the filter unit is provided corresponding to each of a plurality of channels, a switching unit that switches which of the plurality of channels the smoothed PWM signal from the filter unit corresponding to is to be supplied to the abnormality detection unit; Detection device.

3. 3. The detection device according to claim 2, wherein the abnormality detection unit detects an abnormality in the drive control circuit when a level of the smoothed PWM signal falls outside a reference range.

4. The detection device according to claim 3 , wherein the abnormality detection unit detects an abnormality in the drive control circuit when a ripple in the smoothed PWM signal falls outside the reference range.

5. The detection device according to claim 4, wherein the abnormality detection unit detects an abnormality in the drive control circuit when a ripple in the smoothed PWM signal at a timing corresponding to a change point of the PWM signal output by the drive control circuit falls outside the reference range.

6. 6. The detection device according to claim 1, further comprising a reference range setting unit that sets the reference range in accordance with a duty ratio of a PWM signal to be output by the drive control circuit.

7. the abnormality detection unit outputs a detection signal indicating a normal state of the drive control circuit at a time interval shorter than a predetermined timeout time while not detecting an abnormality in the drive control circuit; The detection device further includes a watchdog timer that detects an abnormality in the drive control circuit when a detection signal indicating a normal state of the drive control circuit is not received within the timeout period.

7. A detection device according to any one of claims 1 to 6.

8. 8. The detection device according to claim 7, wherein the watchdog timer detects an abnormality in the drive control circuit in response to receiving the detection signal indicating that the drive control circuit is normal at a time interval less than a predetermined lower limit time.

9. The detection device according to claim 1 , further comprising a drive stopping unit that stops control of the driven device by the drive control circuit in response to detection of an abnormality in the drive control circuit.

10. A drive control circuit for controlling the drive of a driven device; The detection device according to claim 1 , which detects an abnormality in the drive control circuit. A drive control device comprising:

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