Light-emitting component, light-emitting element array chip, and optical measurement device

Abstract

To synchronize and operate lighting and extinguishing of a plurality of arrayed light emitting elements.SOLUTION: A light-emitting component includes a substrate 80, a plurality of light emitting elements Hs provided on the substrate 80 and emitting light in a direction intersecting the surface of the substrate 80, a plurality of holes 55 respectively arranged around the plurality of light emitting elements Hs, and a p-type ohmic electrode 331 that is electrically connected to each of the plurality of light emitting elements Hs and controls both lighting and extinguishing of the plurality of light emitting elements Hs.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a light emitting component, a light emitting element array chip, and an optical measurement device. [Background technology]

[0002] Patent document 1 describes a light-emitting element array in which a large number of light-emitting elements whose threshold voltage or threshold current can be controlled externally are arranged one-dimensionally, two-dimensionally, or three-dimensionally, electrodes that control the threshold voltage or threshold current of each light-emitting element are connected to each other by electrical means, and a clock line that applies a voltage or current from the outside is connected to each light-emitting element.

[0003] Patent Document 2 describes a self-scanning light source head that includes a substrate, surface-emitting semiconductor lasers arranged in an array on the substrate, and thyristors arranged on the substrate as switching elements that selectively turn on and off the emission of the surface-emitting semiconductor lasers. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 1-238962 [Patent Document 2] JP 2009-286048 A Summary of the Invention [Problem to be solved by the invention]

[0005] In 3D sensing and the like, a light-emitting unit using a light-emitting element head in which a large number of light-emitting elements are arranged is adopted. It is conceivable to configure each of these light-emitting elements as multiple light-emitting elements rather than as a single light-emitting element, and to synchronize the turning on and off of these multiple light-emitting elements to form an array. In this case, the electrode structure that turns on and off the multiple light-emitting elements in the array may also be a structure for synchronous operation. An object of the present invention is to operate a plurality of arrayed light-emitting elements in a synchronized manner so that they are turned on and off. [Means for solving the problem]

[0006] The invention described in claim 1 provides a light emitting device comprising: a substrate; a plurality of light emitting elements provided on the substrate and emitting light in a direction intersecting a surface of the substrate; a plurality of holes arranged around each of the plurality of light emitting elements; and a gate electrode electrically connected to each of the plurality of light emitting elements and controlling the plurality of light emitting elements to be turned on and off. The light-emitting element has a layer structure including a thyristor and a light-emitting layer that is provided between layers constituting the thyristor and emits light, and a gate layer of the thyristor is connected as a common layer between the plurality of light-emitting elements through the plurality of holes and is electrically connected to the gate electrode. It is a light-emitting component. Claim 2 The invention described in claim 1 is characterized in that the uppermost layer of the thyristor is connected as a common layer between the plurality of light emitting elements through the plurality of holes. 1 The light emitting component according to claim 1, Claim 3 The invention described in claim 2 further includes a current confinement layer that is oxidized through the hole and constricts a current flowing through the light emitting layer. 1 The light emitting component according to claim 1, Claim 4 The invention described in claim 1 is the light emitting component according to claim 1, wherein the hole has a depth that reaches at least the position of the lower surface of the gate electrode at the location of the hole. Claim 5 The invention described in claim 1 is characterized in that the hole has a depth reaching the position of the lowest layer among the layers of the light emitting element having a thyristor structure. 4 The light emitting component according to claim 1, Claim 6 The invention described in claim 1 is characterized in that the plurality of holes are arranged at predetermined intervals in a circular shape around an emission port through which the light emitting element emits light in order to form a circular current confinement layer that is oxidized through the holes and constricts a current flowing through the light emitting layer. 5 The light emitting component according to claim 1, Claim 7 The invention described in a substrate; a plurality of light-emitting elements provided on the substrate and emitting light in a direction intersecting a surface of the substrate; a plurality of first holes arranged around each of the light-emitting elements; and a gate electrode electrically connected to each of the light-emitting elements and controlling the light-emitting elements to be turned on and off; A thyristor is further provided on the light emitting element. The thyristor has second holes at the same positions as the first holes, and a gate layer of the thyristor is connected as a common layer between the light emitting elements through the second holes and is electrically connected to the gate electrode. It is a light-emitting component. Claim8 The invention described in claim 1 is characterized in that the thyristor is laminated on the light emitting element via a tunnel junction layer or a III-V compound layer having metallic conductivity. 7 The light emitting component according to claim 1, Claim 9 The invention described in claims 1 to 8 The light-emitting element array chip according to any one of claims 1 to 5 includes a row of light-emitting elements arranged in a row in the main scanning direction, and a driving means for inputting and outputting signals for driving the light-emitting elements. Claim 10 The invention described in claims 1 to 8 a light-emitting component according to any one of claims 1 to 5, a light-receiving unit that receives reflected light from an object irradiated with light from the light-emitting component, and a processing unit that processes information related to the light received by the light-receiving unit to measure a distance from the light-emitting component to the object or a shape of the object. is . Effect of the Invention

[0007] According to the invention as recited in claim 1, it is possible to operate a plurality of arrayed light emitting elements by synchronously turning them on and off. Claim 2 According to the invention described in the above, the efficiency of switching is improved. Claim 3 According to the invention described in the above, a current can be applied to the light exit port from which light is emitted. Claim 4 According to the invention described in the above, it becomes easier to separate the light emitting points of each of the plurality of light emitting elements. Claim 5 According to the invention described in the above, it becomes easier to separate the light emitting points of each of the plurality of light emitting elements. Claim 6 According to the invention described in the above, the shape of the light exit port can be made closer to a circle. Claim 7 According to the invention described in the above, the light emitting layer and the transfer thyristor can be separated from each other. Claim 8 According to the invention described in the above, the voltage required for driving the light emitting element can be reduced. Claim 9 According to the invention described in the above, it is possible to provide a light-emitting element array chip capable of synchronizing the turning on and off of a plurality of arrayed light-emitting elements. Claim 10 According to the invention described in the above, an optical measurement device in which light emitting elements are lit in parallel can be obtained. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is an equivalent circuit diagram illustrating a circuit configuration of a light emitting component. [Diagram 2] 1A and 1B are an example of a planar layout view and a cross-sectional view of a light emitting component to which the present embodiment is applied, where (a) is the planar layout view of the light emitting component, and (b) is the cross-sectional view taken along line IIB-IIB in (a). [Diagram 3] 1 is an enlarged view of a surface-emitting laser element in a light-emitting component to which the present embodiment is applied. [Figure 4] 2 is an enlarged view of a light emitting element in a light emitting component to which the present embodiment is applied. [Diagram 5] 4 is a timing chart illustrating the operation of the light emitting component. [Figure 6] 11A and 11B are diagrams showing modified examples of light emitting elements in a light emitting component to which the present embodiment is applied. [Figure 7] FIG. 13 is a diagram for explaining points that must be taken into consideration when a surface emitting laser element and a setting thyristor are configured in a stacked structure. [Figure 8] 1 is a top view of a light emitting device in which a light emitting chip using a light emitting component is arranged. [Figure 9] 1 is a diagram showing an example of a configuration of a light-emitting chip, a configuration of a signal generating circuit of a light-emitting device, and a configuration of wiring (lines) on a circuit board. [Figure 10] FIG. 1 is a diagram illustrating an optical measurement device using a light emitting device. [Figure 11] FIG. 1 is a diagram illustrating an image forming apparatus using a light emitting device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following, elements will be represented using element symbols, such as Al for aluminum.

[0010] First, a description will be given of the light emitting component 10. The light emitting component 10 of this embodiment includes a plurality of surface emitting laser elements VCSEL arranged in a row on the surface of a substrate 80 having a rectangular surface shape.

[0011] (Circuit configuration of light emitting component 10) 1 is an equivalent circuit diagram for explaining the circuit configuration of a light emitting component 10. Each element described below is arranged based on the layout (see FIG. 2 described later) on the light emitting component 10, except for the terminals (φ1 terminal, φ2 terminal, Vgk terminal, and φI terminal). A Vsub terminal provided on the back surface of a substrate 80 is shown pulled out to the outside of the substrate 80.

[0012] The light emitting component 10 includes a light emitting section 102 that is configured with surface emitting laser elements VCSEL1 to VCSEL128.

[0013] Furthermore, the light emitting component 10 includes transfer thyristors T1 to T128 (which will be referred to as transfer thyristor T when no distinction is made) arranged in a row similarly to the surface emitting laser elements VCSEL1 to VCSEL128.

[0014] Note that, although the transfer thyristor T is used here as an example of a transfer element, other circuit elements may be used as long as they are elements that are turned on in sequence. For example, a shift register or a circuit element that combines multiple transistors may be used. The light emitting component 10 also includes coupling diodes D1 to D127 (when no distinction is required, these will be referred to as coupling diodes D) between each pair of the transfer thyristors T1 to T128 arranged in numerical order. Furthermore, the light emitting component 10 includes power line resistors Rg1 to Rg128 (when no distinction is made, they are referred to as power line resistors Rg).

[0015] The light emitting component 10 also includes one start diode SD and current limiting resistors R1 and R2 that are provided to prevent excessive current from flowing through a first transfer signal line 72 through which a first transfer signal φ1 is transmitted and a second transfer signal line 73 through which a second transfer signal φ2 is transmitted, which will be described later. Here, the drive unit 101 is configured by the transfer thyristors T1 to T128, the power line resistors Rg1 to Rg128, the coupling diodes D1 to D127, the start diode SD, and the current limiting resistors R1 and R2. As shown in FIG. 2(b) to be described later, the surface-emitting laser elements VCSEL1 to VCSEL128, the transfer thyristors T1 to T128, the power line resistors Rg1 to Rg128, the coupling diodes D1 to D127, the start diode SD, and the current limiting resistors R1 and R2 are arranged in a row on the substrate 80.

[0016] The surface-emitting laser elements VCSEL1-VCSEL128 of the light-emitting unit 102, the driver 101, and the transfer thyristors T1-T128 are arranged in numerical order from the left side in Fig. 1. Furthermore, the coupling diodes D1-D127 and the power line resistors Rg1-Rg128 are also arranged in numerical order from the left side in the figure.

[0017] In this embodiment, the number of each of the surface-emitting laser elements VCSEL, the transfer thyristors T, and the power line resistances Rg in the light-emitting unit 102 is 128. The number of the coupling diodes D is 127, which is one less than the number of the transfer thyristors T. The number of the surface-emitting laser elements VCSELs etc. is not limited to the above and may be a predetermined number. The number of the transfer thyristors T may be greater than the number of the surface-emitting laser elements VCSELs.

[0018] The above-mentioned coupling diode D and start diode SD are two-terminal semiconductor elements with a diode structure having an anode terminal (anode) and a cathode terminal (cathode), while the surface-emitting laser element VCSEL and transfer thyristor T are semiconductor elements with a thyristor structure having three terminals, an anode terminal (anode), a gate terminal (gate), and a cathode terminal (cathode). Note that the surface-emitting laser element VCSEL, the coupling diode D, the start diode SD, and the transfer thyristor T may not necessarily have an anode terminal, a gate terminal, and a cathode terminal configured as electrodes. Therefore, in the following, the terminals may be abbreviated.

[0019] Next, the electrical connections of each element in the light emitting component 10 will be described. The anodes of the surface-emitting laser element VCSEL and the transfer thyristor T are connected to the substrate 80 of the light-emitting component 10 (anode common). These anodes are connected to a power supply line 200a via a back electrode 89 (see FIG. 2(b) described later) which is a Vsub terminal provided on the back surface of the substrate 80. A reference potential Vsub is supplied to this power supply line 200a from a reference potential supply unit 160. Note that this connection is the configuration when a p-type substrate 80 is used; when an n-type substrate is used, the polarity is reversed; when an intrinsic (i) type substrate with no added impurities is used, a terminal that is connected to a power supply line 200a that supplies a reference potential Vsub is provided on the side of the substrate where the driving unit 101 and the light-emitting unit 102 are provided.

[0020] Along the arrangement of the transfer thyristors T, the cathodes of the odd-numbered transfer thyristors T1, T3, ... are connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal via a current limiting resistor R1. A first transfer signal line 201 is connected to this φ1 terminal, and the first transfer signal φ1 is transmitted from the transfer signal generating unit 120. On the other hand, along the arrangement of the transfer thyristors T, the cathodes of the even-numbered transfer thyristors T2, T4, ... are connected to a second transfer signal line 73. The second transfer signal line 73 is connected to a φ2 terminal via a current limiting resistor R2. A second transfer signal line 202 is connected to this φ2 terminal, and the second transfer signal φ2 is transmitted from the transfer signal generating unit 120.

[0021] The cathodes of the surface-emitting laser elements VCSEL1-VCSEL128 are connected to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal. In the light-emitting component 10, the φI terminal is connected to a light-up signal line 204 via a current-limiting resistor RI provided outside the light-emitting component 10, and a light-up signal φI1 is transmitted from the light-up signal generating unit 140. The light-up signal φI1 supplies a current for lighting to the surface-emitting laser elements VCSEL1-VCSEL128.

[0022] The gates Gt1 to Gt128 (referred to as gate Gt when no distinction is made) of the transfer thyristors T1 to T128 are connected in a one-to-one relationship to the gates Gs1 to Gs128 (referred to as gate Gs when no distinction is made) of the surface-emitting laser elements VCSEL1 to VCSEL128 having the same numbers. Therefore, the gates Gt1 to Gt128 and the gates Gs1 to Gs128 having the same numbers are electrically at the same potential. Therefore, for example, a gate is represented as gate Gt1 (gate Gs1) to indicate that the potential is the same.

[0023] The coupling diodes D1 to D127 are connected between the gates Gt of the gates Gt1 to Gt128 of the transfer thyristors T1 to T128, which are arranged in pairs in numerical order. That is, the coupling diodes D1 to D127 are connected in series so that each is sandwiched between the gates Gt1 to Gt128. The coupling diode D1 is connected in a direction such that a current flows from the gate Gt1 to the gate Gt2. The same applies to the other coupling diodes D2 to D127.

[0024] The gate Gt (gate Gs) of the transfer thyristor T is connected to a power supply line 71 via a power supply line resistance Rg provided corresponding to each of the transfer thyristors T. The power supply line 71 is connected to a Vgk terminal. A power supply line 200b is connected to the Vgk terminal, and a power supply potential Vgk is supplied from the power supply potential supply unit 170.

[0025] The gate Gt1 of the transfer thyristor T1 is connected to the cathode terminal of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

[0026] (Specific Configuration of Light Emitting Component 10) Fig. 2 is an example of a planar layout diagram and a cross-sectional diagram of a light emitting component 10 to which the present embodiment is applied. Fig. 3 is an enlarged view of a surface emitting laser element VCSEL in the light emitting component 10 to which the present embodiment is applied. In the following description, for ease of explanation, the upper side in the figure may be referred to as the upper side and the lower side in the figure as the lower side, but these are not necessarily the upper and lower sides in terms of the actual installation orientation. Of these, Fig. 2(a) is a planar layout diagram of the light emitting component 10, and Fig. 2(b) is a cross-sectional diagram along line IIB-IIB in Fig. 2(a). In Fig. 2(a), the rightward direction on the paper surface is the x-direction, the upward direction on the paper surface is the y-direction, and the surface direction on the paper surface is the z-direction. The plane is a surface seen from the surface side of the paper surface (z-direction). Therefore, in Fig. 2(b), the leftward direction on the paper surface is the z-direction, and the upward direction on the paper surface is the y-direction.

[0027] 2(a) shows a portion mainly including the surface-emitting laser elements VCSEL1 to VCSEL4 and the transfer thyristors T1 to T4. Note that the Vsub terminal (rear electrode 89) provided on the rear surface of the substrate 80 is shown extended out of the substrate 80.

[0028] In Fig. 2(b), which is a cross-sectional view taken along line IIB-IIB in Fig. 2(a), the surface-emitting laser element VCSEL1, the transfer thyristor T1, the coupling diode D1, and the power line resistor Rg1 are shown from the bottom. In Fig. 2(a) and (b), the main elements and terminals are indicated by name. Note that on the surface of the substrate 80, the surface-emitting laser elements VCSEL (the surface-emitting laser elements VCSEL1 to VCSEL4) are arranged in the x direction.

[0029] 2 and 3, in this embodiment, the surface-emitting laser element VCSEL is composed of a plurality of light-emitting elements Hs. Each of the plurality of light-emitting elements Hs has a function as a surface-emitting laser element VCSEL, and emits light from a plurality of emission ports 50. Here, for ease of explanation, five light-emitting elements Hs1 to Hs5 are illustrated as the plurality of light-emitting elements Hs, but in reality, for example, 40 light-emitting elements Hs are provided to constitute the surface-emitting laser element VCSEL.

[0030] First, the cross-sectional structure of the light emitting component 10 will be described with reference to FIG. On a p-type substrate 80 (substrate 80), a p-type DBR structure anode (DBR) layer 81 (pDBR layer 81) constituting a surface-emitting laser element VCSEL, a transfer thyristor T, a coupling diode D1, and a power supply line resistance Rg1, an n-type gate layer 82 (n-gate layer 82), a light-emitting layer 83, a p-type gate layer 84 (p-gate layer 84), and an n-type DBR structure cathode (DBR) layer 85 (nDBR layer 85) are provided in this order. In the following, the notation in ( ) is used. The same applies to other cases. Here, a semiconductor layer in which the pDBR layer 81, the n-gate layer 82, the light-emitting layer 83, the p-gate layer 84, and the nDBR layer 85 are stacked is referred to as a semiconductor stack.

[0031] As shown in Fig. 2(b), the light emitting component 10 is provided with a protective layer 90 made of a light-transmitting insulating material that is provided so as to cover the front and side surfaces of the laminated structure. In Fig. 2(b), the arrow indicates the direction in which light from the surface emitting laser element VCSEL is emitted (light emission direction). Here, this is the direction intersecting with the surface of the substrate 80 (z direction). Here, the "surface" refers to the front or back surface of the light emitting component 10.

[0032] These laminated structures are connected to wiring such as a power supply line 71, a first transfer signal line 72, a second transfer signal line 73, and a light-up signal line 75 via through holes (indicated by circles in FIG. 2(a)) provided in the protective layer 90. In the following explanation, the explanation of the protective layer 90 and the through holes will be omitted.

[0033] As shown in FIG. 2(b), a back surface electrode 89 serving as a Vsub terminal is provided on the back surface of the substrate 80.

[0034] The pDBR layer 81, n-gate layer 82, light-emitting layer 83, p-gate layer 84, and nDBR layer 85 are each a semiconductor layer, and are monolithically laminated by epitaxial growth. The semiconductor laminate between the laminate structures is removed by etching (mesa etching) to form a plurality of laminate structures (islands) (laminated structures 301, 302, 303, ... described below) that are electrically isolated from one another. Note that the plurality of laminate structures may be electrically isolated from one another by ion implantation or the like instead of etching.

[0035] Here, the notation of the pDBR layer 81 and the nDBR layer 85 corresponds to the functions (functions) when forming the surface-emitting laser element VCSEL. That is, the pDBR layer 81 functions as the anode of the surface-emitting laser element VCSEL and also functions as a DBR layer. Also, the nDBR layer 85 functions as the cathode of the surface-emitting laser element VCSEL and also functions as a DBR layer. That is, the surface-emitting laser element VCSEL has a thyristor structure equipped with an anode and a cathode. It can also be said that the surface-emitting laser element VCSEL has a layer structure equipped with a thyristor and a light-emitting layer 83 that is provided between layers that constitute the thyristor and emits light.

[0036] When the coupling diode D and the power supply line resistance Rg are configured, they have different functions as described later.

[0037] As described below, the multiple stacked structures include those that do not include some of the multiple layers, namely, pDBR layer 81, n gate layer 82, light emitting layer 83, p gate layer 84, and nDBR layer 85. For example, stacked structure 301 has a portion that does not include some of pDBR layer 81, n gate layer 82, light emitting layer 83, p gate layer 84, and nDBR layer 85.

[0038] Next, the planar layout of the light emitting component 10 will be described with reference to FIG. The laminated structure 301 is provided with a surface-emitting laser element VCSEL1. The laminated structure 302 is provided with a transfer thyristor T1 and a coupling diode D1. The laminated structure 303 is provided with a power line resistor Rg1. The laminated structure 304 is provided with a start diode SD. The laminated structure 305 is provided with a current limiting resistor R1, and the laminated structure 306 is provided with a current limiting resistor R2. In the light emitting component 10, a plurality of laminated structures similar to the laminated structures 301, 302, and 303 are formed in parallel. In these laminated structures, surface emitting laser elements VCSEL2, VCSEL3, VCSEL4, ..., transfer thyristors T2, T3, T4, ..., coupling diodes D2, D3, D4, ..., etc. are provided in the same manner as the laminated structures 301, 302, and 303.

[0039] Here, the laminated structure 301 to the laminated structure 306 will be described in detail with reference to FIGS. 2(a) and 2(b). As shown in FIG. 2( b ), the surface emitting laser element VCSEL 1 provided in the stacked structure 301 is composed of a pDBR layer 81 , an n-gate layer 82 , a light emitting layer 83 , a p-gate layer 84 , and an nDBR layer 85 .

[0040] As shown in black in FIG. 2(b), the pDBR layer 81 of the surface-emitting laser element VCSEL includes a current confinement layer (current confinement layer 81b in FIG. 4 described later) that confines the current flowing through the light-emitting layer 83. The current confinement layer is a layer provided to restrict the current flowing through the surface-emitting laser element VCSEL to the center of the surface-emitting laser element VCSEL. That is, the peripheral portion of the surface-emitting laser element VCSEL has many defects due to mesa etching. For this reason, non-radiative recombination is likely to occur. Therefore, the current confinement layer is provided so that the central portion of the surface-emitting laser element VCSEL becomes a current passing portion (region) α where the current easily flows, and the peripheral portion becomes a current blocking portion (region) β where the current does not easily flow. The current blocking portion β may be referred to as a current confinement region.

[0041] The provision of the current blocking portion β reduces the power consumed by non-radiative recombination, thereby reducing power consumption and improving the light extraction efficiency, which is the amount of light that can be extracted per unit of power. The current confinement layer will be described later.

[0042] In order to suppress loss due to the passage of light emitted from the surface-emitting laser element VCSEL, the surface-emitting laser element VCSEL is provided with an emission aperture 50 through which light is emitted from the light-emitting elements Hs1 to Hs5 of the surface-emitting laser element VCSEL. The emission aperture 50 can also be referred to as a portion on the emission surface of the surface-emitting laser element VCSEL where the amount of emitted light is strongest.

[0043] A plurality of holes 55 are provided around each of the light emitting elements Hs1 to Hs5 provided in the surface emitting laser element VCSEL. Here, eight holes 55 are provided for each of the light emitting elements Hs1 to Hs5. The eight holes 55 are provided around the emission port 50 so as to surround the emission port 50. The holes 55 are provided by removing the pDBR layer 81, the n-gate layer 82, the emission layer 83, the p-gate layer 84, and the nDBR layer 85, as well as between the stacked structures. As will be described later, the current confinement layer 81b is oxidized through the edge portion of the stacked structure 301 and the holes 55 to form a current blocking portion β. The edge portion of the stacked structure 301 refers to the end portion of the stacked structure 301 formed by removing the semiconductor stacked body. In other words, the edge portion of the stacked structure 301 refers to the side surface of the stacked structure 301 where the semiconductor stacked body of the stacked structure 301 is exposed.

[0044] An n-type ohmic electrode 321 (n ohmic electrode 321) provided on the nDBR layer 85 (region 311) serves as a cathode electrode. The n ohmic electrode 321 is provided between the emission aperture 50 and the hole 55 so as to surround the emission aperture 50. A p-type ohmic electrode 331 (p ohmic electrode 331) provided on the p-gate layer 84 exposed by removing the nDBR layer 85 serves as a gate Gs1. The p-type ohmic electrode 331 is an example of a gate electrode that is electrically connected to each of a plurality of light-emitting elements, which will be described in detail later, and controls the lighting and extinguishing of the plurality of light-emitting elements Hs. Note that the p-gate layers 84 of multiple light-emitting elements Hs included in the same VCSEL are connected to each other. However, holes 56 are formed between the light-emitting element Hs included in one VCSEL and the light-emitting element Hs included in another VCSEL so that the p-gate layers 84 are not connected to each other. For example, holes 56 are formed between the light-emitting element Hs included in VCSEL1 and the light-emitting element Hs included in the adjacent VCSEL2 so that the p-gate layers 84 are not connected to each other.

[0045] The transfer thyristor T1 is composed of a laminated pDBR layer 81, an n gate layer 82, a light emitting layer 83, a p gate layer 84, and an nDBR layer 85. An n ohmic electrode 323 provided on the nDBR layer 85 (region 313) serves as a cathode terminal. Furthermore, a p ohmic electrode 332 provided on the p gate layer 84 exposed by removing the nDBR layer 85 serves as a terminal of the gate Gt1 (sometimes referred to as gate terminal Gt1).

[0046] Similarly, the coupling diode D1 provided in the stacked structure 302 is composed of a p-gate layer 84 and an n-DBR layer 85. The n-ohmic electrode 324 provided on the n-DBR layer 85 (region 314) serves as a cathode terminal. Furthermore, the p-ohmic electrode 332 provided on the p-gate layer 84 exposed by removing the n-DBR layer 85 serves as an anode terminal. Here, the anode terminal of the coupling diode D1 is the same as the gate Gt1 (gate terminal Gt1).

[0047] The power supply line resistance Rg1 provided in the stacked structure 303 is composed of the p-gate layer 84. That is, the power supply line resistance Rg1 is provided using the p-gate layer 84 between the p-ohmic electrode 333 and the p-ohmic electrode 334 provided on the p-gate layer 84 exposed by removing the nDBR layer 85 as a resistor.

[0048] The start diode SD provided in the stacked structure 304 is composed of a p-gate layer 84 and an n-DBR layer 85. That is, the start diode SD has an n-ohmic electrode 325 provided on the n-DBR layer 85 (region 315) as a cathode terminal. Furthermore, the start diode SD has a p-ohmic electrode 335 provided on the p-gate layer 84 exposed by removing the n-DBR layer 85 as an anode terminal. The current limiting resistor R1 provided in the laminated structure 305 and the current limiting resistor R2 provided in the laminated structure 306 are provided in the same manner as the power line resistor Rg1 provided in the laminated structure 303, and each uses the p-gate layer 84 between two p-ohmic electrodes (not numbered) as a resistor.

[0049] The connections between the elements will be described with reference to FIG. The light-up signal line 75 includes a trunk 75a and multiple branches 75b. The trunk 75a is provided so as to extend in the column direction of the surface-emitting laser elements VCSEL. The branches 75b branch out from the trunk 75a and are connected to an n-ohmic electrode 321, which is the cathode terminal of the surface-emitting laser element VCSEL1 provided in the stacked structure 301. The cathode terminals of the other surface-emitting laser elements VCSEL are similarly connected. The light-on signal line 75 is connected to a φI terminal provided on the side of the surface-emitting laser element VCSEL1.

[0050] The first transfer signal line 72 is connected to an n ohmic electrode 323 which is the cathode terminal of the transfer thyristor T1 provided in the multilayer structure 302. The first transfer signal line 72 is connected to the cathode terminals of other odd-numbered transfer thyristors T provided in a multilayer structure similar to the multilayer structure 302. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided in the multilayer structure 305. On the other hand, the second transfer signal line 73 is connected to an n ohmic electrode (without reference numeral) which is the cathode terminal of the even-numbered transfer thyristor T provided in a stacked structure not provided with a reference numeral. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided in the stacked structure 306.

[0051] The power supply line 71 is connected to a p-ohmic electrode 334 which is one terminal of a power supply line resistor Rg1 provided in the laminated structure 303. One terminal of the other power supply line resistor Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vgk terminal.

[0052] The p-ohmic electrode 331 (gate terminal Gs1) provided on the multilayer structure 301 is connected to the p-ohmic electrode 332 (gate terminal Gt1) of the multilayer structure 302 by a connection wire .

[0053] The p-ohmic electrode 332 (gate terminal Gt1) is connected to the p-ohmic electrode 333 (the other terminal of the power supply line resistance Rg1) of the laminated structure 303 by a connection wire 77. An n-ohmic electrode 324 (cathode terminal of the coupling diode D1) provided on the stacked structure 302 is connected by a connection wire 79 to a p-type ohmic electrode (without symbol) which is the gate terminal Gt2 of the adjacent transfer thyristor T2. Although the description is omitted here, the same applies to other surface emitting laser elements VCSEL, transfer thyristors T, coupling diodes D, etc.

[0054] The p-ohmic electrode 332 (gate terminal Gt1) of the multilayer structure 302 is connected to an n-ohmic electrode 325 (cathode terminal of the start diode SD) provided on the multilayer structure 304 by a connection wiring 78. The p-ohmic electrode 335 (anode terminal of the start diode SD) is connected to a second transfer signal line 73. The above connections and configurations are for when a p-type substrate 80 is used, and the polarity is reversed when an n-type substrate is used. When an i-type substrate is used, a terminal connected to a power supply line 200a that supplies a reference potential Vsub is provided on the side of the substrate where the driving unit 101 and the light emitting unit 102 are provided. The connections and configurations are the same as when a p-type substrate is used or when an n-type substrate is used.

[0055] Now, with reference to FIG. 2(b), a method for manufacturing the light emitting component 10 will be described. First, a semiconductor laminate is formed by epitaxially growing a pDBR layer 81, an n-gate layer 82, a light-emitting layer 83, a p-gate layer 84, and an nDBR layer 85 in this order on a p-type substrate 80. Here, the substrate 80 is described as being p-type GaAs, but it may be n-type GaAs or intrinsic (i) type GaAs with no impurities added.

[0056] The DBR layer is, for example, Al 0.9 Ga 0.1 A low refractive index layer with high Al composition of As and, for example, Al 0.2 Ga 0.8 It is composed of a combination of a high refractive index layer with a low Al composition of As. The film thickness (optical path length) of each of the low refractive index layer and the high refractive index layer is set to, for example, 0.25 (1 / 4) of the central wavelength. The Al composition ratio of the low refractive index layer and the high refractive index layer may be changed in the range of 0 to 1.

[0057] The pDBR layer 81 is formed by stacking a lower pDBR layer 81a, a current confinement layer 81b, and an upper pDBR layer 81c in this order (see FIG. 4B, which will be described later). The lower pDBR layer 81a and the upper pDBR layer 81c have an impurity concentration of, for example, 1×10 18 / cm 3 The current confinement layer 81b is, for example, AlAs or p-type AlGaAs having a high concentration of Al impurities. Any material may be used as long as Al is oxidized to form Al2O3, thereby increasing the electrical resistance and constricting the current path. The nDBR layer 85 has an impurity concentration of, for example, 1×10 18 / cm 3 It is.

[0058] The n-gate layer 82 has an impurity concentration of, for example, 1×10 17 / cm 3 n-type Al 0.9 The Al composition may be changed within the range of 0 to 1.

[0059] The light emitting layer 83 has a quantum well structure in which well layers and barrier layers are alternately stacked. The well layers are, for example, GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, GaInP, etc., and the barrier layers are, for example, AlGaAs, GaAs, GaInP, GaInAsP, etc. The light emitting layer 83 may be a quantum wire or a quantum dot.

[0060] The p-gate layer 84 has an impurity concentration of, for example, 1×10 17 / cm 3 p-type Al 0.9 The Al composition may be changed within the range of 0 to 1.

[0061] These semiconductor layers are stacked by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like to form a semiconductor stack.

[0062] Next, n ohmic electrodes 321, 323, 324, etc. are formed on the n DBR layer 85. The n ohmic electrodes (n ohmic electrodes 321, 323, 324, etc.) are made of, for example, Au containing Ge (AuGe) which easily makes ohmic contact with n-type semiconductor layers such as the n DBR layer 85. The n ohmic electrodes (n ohmic electrodes 321, 323, 324, etc.) are formed by, for example, a lift-off method.

[0063] Next, the nDBR layer 85, p-gate layer 84, light-emitting layer 83, n-gate layer 82, and pDBR layer 81 are sequentially etched to separate the laminated structures such as laminated structures 301 and 302. At the same time, a hole 55 is formed in the laminated structure 301. This etching may be wet etching using a sulfuric acid-based etching solution (sulfuric acid:hydrogen peroxide:water=1:10:300 in weight ratio) or may be anisotropic dry etching (RIE) using boron chloride or the like. This etching for separating the laminated structures is sometimes called mesa etching or post etching.

[0064] Next, the current confinement layer 81b with its exposed side surface is oxidized from the side surface at the edge portion and the hole 55 of the laminated structure to form a current blocking portion β. The current confinement layer 81b is oxidized, for example, by steam oxidation at 300 to 400°C to oxidize Al of the current confinement layer 81b, which is AlAs, AlGaAs, or the like. At this time, oxidation progresses from the exposed side surface, and a current blocking portion β made of Al2O3, which is an oxide of Al, is formed. The portion of the current confinement layer 81b that has not been oxidized becomes a current passing portion α.

[0065] Next, the nDBR layer 85 is etched to expose the p gate layer 84. This etching may be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid:hydrogen peroxide:water=1:10:300 in weight ratio), or may be performed by anisotropic dry etching using, for example, boron chloride. Then, p ohmic electrodes (p ohmic electrodes 331, 332, etc.) are formed on the p gate layer 84. The p ohmic electrodes are made of, for example, Au containing Zn (AuZn) which is easy to make ohmic contact with p-type semiconductor layers such as the p gate layer 84. Then, the p ohmic electrodes (p ohmic electrodes 331, 332, etc.) are formed by, for example, a lift-off method.

[0066] Next, a protective layer 90 is formed of an insulating material such as SiO2, SiON, or SiN so as to cover the surfaces of the laminated structures 301, 302, etc. Then, through holes (openings) are provided in the protective layer 90 on the n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) and p-ohmic electrodes (p-ohmic electrodes 331, 332, etc.). Furthermore, wiring (power supply line 71, first transfer signal line 72, second transfer signal line 73, light-up signal line 75, etc.) and a back electrode 89 are formed through the through holes provided in the protective layer 90 to connect the n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) and the p-ohmic electrodes (p-ohmic electrodes 331, 332, etc.). The wiring and the back electrode 89 are made of Al, Au, or the like.

[0067] In this manner, the light emitting component 10 is manufactured. The substrate 80 may be a semiconductor substrate made of InP, GaN, InAs, other III-V group, II-VI material, sapphire, Si, Ge, etc. When the substrate is changed, the material of the semiconductor laminate monolithically laminated on the substrate is a material that approximately matches the lattice constant of the substrate (including strained structure, strain relaxation layer, metamorphic growth). As an example, InAs, InAsSb, GaInAsSb, etc. are used on the InAs substrate, InP, InGaAsP, etc. are used on the InP substrate, GaN, AlGaN, InGaN are used on the GaN substrate or sapphire substrate, and Si, SiGe, GaP, etc. are used on the Si substrate. However, when the substrate is attached to another support substrate after the crystal growth, the semiconductor material does not need to be approximately lattice matched to the support substrate.

[0068] (Layer structure of the light emitting element Hs of the surface emitting laser element VCSEL) Fig. 4 is an enlarged view of a light-emitting element Hs in a light-emitting component 10 to which the present embodiment is applied. Fig. 4(a) is a plan view of the light-emitting element Hs, Fig. 4(b) is a cross-sectional view taken along line IVB-IVB in Fig. 4(a), and Fig. 4(c) is a cross-sectional view taken along line IVC-IVC in Fig. 4(a).

[0069] As shown in FIG. 4(a), eight holes 55 are provided around the light emitting element Hs. These holes 55 are also called trenches, and therefore the surface emitting laser element VCSEL having this configuration is also called a trench type. As shown in FIG. 4(b), the holes 55 are provided so as to reach the substrate 80 by removing the nDBR layer 85, the p-gate layer 84, the light emitting layer 83, the n-gate layer 82, and the pDBR layer 81 by etching. The current confinement layer 81b provided in the pDBR layer 81 is oxidized through the holes 55. Then, oxidation proceeds from the holes 55 to the surroundings with the holes 55 as the center. In other words, the central portion surrounded by the eight holes 55 becomes the portion (current passing portion α) that is not oxidized.

[0070] As shown in FIGS. 4(b) and 4(c), except for the current passing portion α at the emission port 50, the current confinement layer 81b is oxidized from between the adjacent holes 55 and from the outer side surface of the laminated structure 301.

[0071] The holes 55 are arranged in a circle surrounding the emission port 50, so that the planar shape of the non-oxidized portion (current passing portion α) becomes closer to a circle. In the surface-emitting laser element VCSEL, the smaller the emission port 50 is in a circle and the easier it is to oscillate in a single mode and the intensity distribution becomes single-peaked. Therefore, it is preferable that the holes 55 are arranged in a circle and the current passing portion α becomes closer to a circle. That is, in this case, the current confinement layer 81b is also formed in a circle around the holes 55. In order to form the current confinement layer 81b in a circle, the holes 55 are arranged at predetermined intervals in a circle around the emission port 50 from which the light-emitting element Hs emits light.

[0072] The nDBR layer 85, the p-gate layer 84, the light-emitting layer 83, the n-gate layer 82, and the pDBR layer 81 other than the hole 55 of the light-emitting element Hs function as a setting thyristor that sets (controls) the on / off of the surface-emitting laser element VCSEL. The nDBR layer 85, the p-gate layer 84, the light-emitting layer 83, the n-gate layer 82, and the upper pDBR layer 81c located above the current confinement layer 81b function as a current path. Therefore, the larger the area of ​​the light-emitting element Hs other than the hole 55, the smaller the resistance to the current flowing through the surface-emitting laser element VCSEL. Therefore, the number of the holes 55 may be set according to the shape of the non-oxidized portion (current passing portion α) and the resistance of the path of the current flowing through the surface-emitting laser element VCSEL. The number of the holes 55 may be at least four. The planar shape of the hole 55 is square in FIG. 4(a), but it may be other shapes such as a circle or a rectangle.

[0073] Moreover, it is preferable that the hole 55 has a depth that reaches at least the position of the lower surface of the p-type ohmic electrode 331, which is the gate electrode, at the location of the hole 55. That is, it is preferable that the hole 55 penetrates at least the nDBR layer 85 and reaches the position of the upper surface of the p-gate layer 84. This makes it easier to separate the light-emitting points of each of the multiple light-emitting elements. It is more preferable that the hole 55 has a depth that reaches the position of the bottom layer among the layers of the light emitting element Hs having a thyristor structure. That is, it is more preferable that the hole 55 has a depth that reaches the position of the pDBR layer 81. Note that FIG. 4(b) shows a case where the hole 55 not only reaches the pDBR layer 81 but also penetrates the pDBR layer 81 and reaches the substrate 80. The hole 55 may stop at the portion where it reaches the position of the pDBR layer 81 without penetrating the pDBR layer 81. Such a configuration shortens the etching time, while penetrating the pDBR layer 81 makes it easier to separate the light emitting points of the multiple light emitting elements Hs.

[0074] As shown in FIG. 4(c), the p-gate layer 84 in the light-emitting element Hs having the thyristor structure is connected as a common layer between the plurality of light-emitting elements Hs through the plurality of holes 55. It is further electrically connected to the p-type ohmic electrode 331, which is the gate electrode. That is, as shown in FIG. 4(b), the p-gate layer 84 is divided at some places by the holes 55, but as shown in FIG. 4(c), it is connected and electrically connected to each other at places where the holes 55 are not present. As a result, the p-gate layer 84, which is the upper gate layer of the thyristor, is connected as a common layer between the plurality of light-emitting elements Hs and functions as a common gate layer between the plurality of light-emitting elements Hs. The upper gate layer means the gate layer located at the upper side of the two gate layers of the thyristor, and the lower gate layer means the gate layer located at the lower side of the two gate layers of the thyristor.

[0075] Furthermore, the nDBR layer 85, which is the top layer of the thyristor structure, is connected as a common layer between the multiple light-emitting elements Hs via the multiple holes 55. That is, as shown in Fig. 4(b), the nDBR layer 85 has some portions that are divided by the holes 55, but as shown in Fig. 4(c), in portions where the holes 55 are not present, the layers are connected to each other and electrically connected. With this configuration, the efficiency of switching by the p-type ohmic electrode 331 is improved. As a result, even if there are multiple light-emitting elements Hs, they can be turned on and off at approximately the same time. This can also be said to be the ability to synchronize the timing of turning on and off the multiple light-emitting elements Hs.

[0076] <Thyristor> Next, the basic operation of the thyristor (surface-emitting laser element VCSEL, transfer thyristor T) will be described. As described above, the thyristor is a semiconductor element having three terminals, an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate), and is configured by stacking a p-type semiconductor layer (pDBR layer 81, p-gate layer 84) and an n-type semiconductor layer (n-gate layer 82, nDBR layer 85) made of GaAs, GaAlAs, AlAs, etc. on a substrate 80. That is, the thyristor has a pnpn structure. Here, the forward potential (diffusion potential) Vd of the pn junction configured by the p-type semiconductor layer and the n-type semiconductor layer will be described as 1.5V as an example.

[0077] In the following, as an example, the reference potential Vsub supplied to the rear electrode 89 (see FIG. 2) which is the Vsub terminal will be described as a high level potential (hereinafter referred to as "H") of 0V, and the power supply potential Vgk supplied to the Vgk terminal will be described as a low level potential (hereinafter referred to as "L") of -5V. Therefore, they may be described as "H" (0V) and "L" (-5V).

[0078] First, we will explain the operation of a single thyristor. Here, we assume that the anode of the thyristor is 0V. A thyristor in the off state, where no current flows between the anode and cathode, transitions to the on state (turns on) when a potential lower than the threshold voltage (a negative potential with a large absolute value) is applied to the cathode. Here, the threshold voltage of a thyristor is the gate potential minus the forward potential Vd (1.5V) of the pn junction. When the thyristor is turned on, the gate of the thyristor becomes at a potential close to the potential of the anode terminal. In this case, the anode is 0V, so the gate becomes 0V. Also, the cathode of a thyristor in the on state becomes at a potential close to the potential obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the anode. In this case, the anode is 0V, so the cathode of a thyristor in the on state becomes at a potential close to -1.5V (a negative potential with an absolute value greater than 1.5V). The potential of the cathode is set in relation to the power supply that supplies current to the thyristor in the on state.

[0079] A thyristor in the on state transitions to the off state (turns off) when the cathode reaches a potential higher than the potential required to maintain the on state (a potential close to -1.5V as mentioned above) (a negative potential with a small absolute value, 0V, or a positive potential). On the other hand, if a potential lower than the potential required to maintain the on state (a negative potential with a large absolute value) is continuously applied to the cathode of a thyristor in the on state and a current capable of maintaining the on state (maintenance current) is supplied, the thyristor will maintain the on state.

[0080] The voltages shown above are merely examples, and should be changed depending on the emission wavelength and light amount of the surface-emitting laser element VCSEL. In that case, the potential ("L") of the light-up signal φI should be adjusted.

[0081] Since the thyristor is made of a semiconductor such as GaAs, it may emit light between the n-gate layer 82 and the p-gate layer 84 when in the on state. The amount of light emitted by the thyristor is determined by the area of ​​the cathode and the current flowing between the cathode and the anode. Therefore, when the light emitted from the thyristor is not utilized, unnecessary light may be suppressed, for example, by reducing the area of ​​the cathode or by blocking the light with materials constituting the electrodes and wiring.

[0082] (Operation of the light emitting component 10) Next, the operation of the light emitting component 10 will be described. <Timing chart> FIG. 5 is a timing chart illustrating the operation of the light emitting component 10. As shown in FIG. Fig. 5 shows a timing chart of a portion for controlling (referred to as lighting control) lighting (oscillation) or non-lighting of five light-emitting laser elements VCSEL, which are surface-emitting laser elements VCSEL1 to VCSEL5 of the light-emitting component 10. Note that in Fig. 5, the surface-emitting laser elements VCSEL1, VCSEL2, VCSEL3, and VCSEL5 of the light-emitting component 10 are turned on, and the surface-emitting laser element VCSEL4 is turned off (non-lighting).

[0083] 5, time passes in alphabetical order from time a to time k. The surface-emitting laser element VCSEL1 is controlled to be turned on or off (lighting control) in period T(1), the surface-emitting laser element VCSEL2 in period T(2), the surface-emitting laser element VCSEL3 in period T(3), and the surface-emitting laser element VCSEL4 in period T(4). Similarly, the surface-emitting laser elements VCSEL numbered 5 or more are controlled to be turned on or off. Here, the periods T(1), T(2), T(3), ... are assumed to be periods of the same length, and when there is no need to distinguish between them, they will be referred to as period T.

[0084] The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 1 and 2) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 1 and 2) are signals having two potentials, "H" (0 V) and "L" (-5 V). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, periods T(1) and T(2)). In the following, "H" (0V) and "L" (-5V) may be abbreviated to "H" and "L".

[0085] The first transfer signal φ1 transitions from “H” (0 V) to “L” (−5 V) at time b when the period T(1) starts, and transitions from “L” to “H” at time f. Then, transitions from “H” to “L” at time i when the period T(2) ends. The second transfer signal φ2 is “H” (0 V) at start time b of the period T(1), transitions from “H” (0 V) to “L” (−5 V) at time e, and transitions from “L” to “H” between end time i and time j of the period T(2). Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted backward by a period T on the time axis. Meanwhile, the second transfer signal φ2 has a waveform indicated by a dashed line in period T(1) and a waveform in period T(2) that are repeated from period T(3) onwards. The waveform of the second transfer signal φ2 in period T(1) is different from that in period T(3) and after because period T(1) is the period during which the light emitting component 10 starts operating.

[0086] As described below, a pair of transfer signals, a first transfer signal φ1 and a second transfer signal φ2, propagates the on state of the transfer thyristors T in numerical order, thereby designating the surface-emitting laser element VCSEL having the same number as the on-state transfer thyristor T as the target for control of lighting (oscillation) or non-lighting (lighting control).

[0087] Next, there will be described the lighting signal φI1 transmitted to the φI terminal of the light emitting component 10. The lighting signal φI1 is a signal having two potentials, "H" (0V) and "L" (-5V). Here, the lighting signal φI1 will be described during a period T(1) of lighting control for the surface-emitting laser element VCSEL1 of the light-emitting component 10. The lighting signal φI1 is “H” (0 V) at start time b of the period T(1), and transitions from “H” (0 V) to “L” (−5 V) at time c. It then transitions from “L” to “H” at time d, and maintains “H” at time e.

[0088] The operation of the light emitting component 10 will be described according to the timing chart shown in Fig. 5 while referring to Fig. 1. In the following, the periods T(1) and T(2) during which the lighting of the surface emitting laser elements VCSEL1 and VCSEL2 is controlled will be described.

[0089] (1) Time a At time a, the reference potential supplying unit 160 of the signal generating circuit 110 of the light emitting component 10 sets the reference potential Vsub to "H" (0V). The power supply potential supplying unit 170 sets the power supply potential Vgk to "L" (-5V). Then, the power supply line 200a of the light emitting component 10 becomes the reference potential Vsub of "H" (0V), and the Vsub terminal of the light emitting component 10 becomes "H". Similarly, the power supply line 200b becomes the power supply potential Vgk of "L" (-5V), and the Vgk terminal of the light emitting component 10 becomes "L" (see FIG. 1). As a result, the power supply line 71 of the light emitting component 10 becomes "L" (see FIG. 1).

[0090] Then, the transfer signal generating unit 120 of the signal generating circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to "H" (0V). Then, the first transfer signal line 201 and the second transfer signal line 202 become "H" (see FIG. 1). As a result, the φ1 terminal and the φ2 terminal of the light emitting component 10 become "H". The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes "H", and the second transfer signal line 73 connected to the φ1 terminal via the current limiting resistor R2 also becomes "H" (see FIG. 1).

[0091] Furthermore, the light-up signal generating unit 140 of the signal generating circuit 110 sets the light-up signal φI1 to "H" (0V). Then, the light-up signal line 204 becomes "H" (see FIG. 1). As a result, the φI terminal of the light-emitting component 10 becomes "H" via the current limiting resistor RI, and the light-up signal line 75 connected to the φI terminal also becomes "H" (0V) (see FIG. 1).

[0092] The anode (pDBR layer 81) of the surface-emitting laser element VCSEL is connected to the Vsub terminal set to "H". The anode (pDBR layer 81) of the transfer thyristor T is connected to the Vsub terminal set to "H".

[0093] The cathodes of the odd-numbered transfer thyristors T1, T3, T5, ... are connected to the first transfer signal line 72 and are set to "H" (0V). The cathodes of the even-numbered transfer thyristors T2, T4, T6, ... are connected to the second transfer signal line 73 and are set to "H". Therefore, the anode and cathode of each of the transfer thyristors T are both "H" and the transfer thyristors T are in the off state.

[0094] The cathode terminal of the surface-emitting laser element VCSEL is connected to the light-up signal line 75 of "H" (0V). Therefore, the anode and cathode of the surface-emitting laser element VCSEL are both "H" and the surface-emitting laser element VCSEL is in an off state.

[0095] As described above, the gate Gt1 is connected to the cathode of the start diode SD. The gate Gt1 is connected to the power supply line 71 at the power supply potential Vgk ("L" (-5V)) via the power supply line resistance Rg1. The anode terminal of the start diode SD is connected to the second transfer signal line 73, and is connected to the φ2 terminal at "H" (0V) via the current limiting resistance R2. Therefore, the start diode SD is forward biased, and the cathode (gate Gt1) of the start diode SD becomes a value (-1.5V) obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential ("H" (0V)) of the anode of the start diode SD. In addition, when the gate Gt1 becomes -1.5V, the coupling diode D1 becomes forward biased because the anode (gate Gt1) is -1.5V and the cathode is connected to the power supply line 71 ("L" (-5V)) via the power supply line resistance Rg2. Therefore, the potential of the gate Gt2 becomes -3V obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the gate Gt1 (-1.5V). Furthermore, the coupling diode D2 is forward biased because its anode (gate Gt1) is -3V and its cathode is connected to the power line 71 ("L" (-5V)) via the power line resistance Rg2. Therefore, the potential of the gate Gt3 becomes -4.5V obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the gate Gt2 (-3V). However, the gates Gt numbered 4 and above are not affected by the anode of the start diode SD being "H" (0V), and the potential of these gates Gt becomes "L" (-5V), which is the potential of the power line 71.

[0096] Since the gate Gt is the gate Gs, the potential of the gate Gs is the same as the potential of the gate Gt. Therefore, the threshold voltages of the surface-emitting laser element VCSEL and the transfer thyristor T are values ​​obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potentials of the gates Gt and Gs. That is, the threshold voltage of the transfer thyristor T1 is −3 V, the threshold voltage of the surface-emitting laser element VCSEL2 and the transfer thyristor T2 is −4.5 V, the threshold voltage of the surface-emitting laser element VCSEL3 and the transfer thyristor T3 is −6 V, and the threshold voltage of the surface-emitting laser elements VCSEL and the transfer thyristors T whose numbers are 4 or more is −6.5 V.

[0097] (2) Time b 5, the first transfer signal φ1 transitions from “H” (0 V) to “L” (−5 V), causing the light emitting component 10 to start operating. When the first transfer signal φ1 transitions from "H" to "L", the potential of the first transfer signal line 72 transitions from "H" (0 V) to "L" (-5 V) via the φ1 terminal and the current limiting resistor R1. Then, the voltage applied to the transfer thyristor T1 is -3.3 V, and therefore the transfer thyristor T1, whose threshold voltage is -3 V, is turned on. As a result of the transfer thyristor T1 being turned on, the potential of the first transfer signal line 72 becomes a potential close to -3.2 V (a negative potential with an absolute value greater than 3.2 V) obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode of the transfer thyristor T1. The transfer thyristor T3 has a threshold voltage of −6 V, and the transfer thyristors T with odd numbers equal to or greater than 5 have a threshold voltage of −6.5 V. The voltage applied to the transfer thyristor T3 and the transfer thyristors T with odd numbers equal to or greater than 5 is −1.5 V obtained by adding the voltage of 1.7 V applied to the surface-emitting laser element VCSEL to −3.2 V, and therefore the transfer thyristor T3 and the transfer thyristors T with odd numbers equal to or greater than 5 are not turned on. On the other hand, the even-numbered transfer thyristors T cannot be turned on because the second transfer signal φ2 is “H” (0 V) and the second transfer signal line 73 is “H” (0 V).

[0098] When the transfer thyristor T1 is turned on, the potential of the gates Gt1 / Gs1 becomes "H" (0V), which is the potential of the anode of the transfer thyristor T1. Then, the potential of the gate Gt2 (gate Gs2) becomes -1.5V, the potential of the gate Gt3 (gate Gs3) becomes -3V, the potential of the gate Gt4 (gate Gs4) becomes -4.5V, and the potential of the gates Gt (gate Gl) whose numbers are 5 or more becomes "L". As a result, the threshold voltage of the surface-emitting laser element VCSEL1 is −1.5V, the threshold voltage of the transfer thyristor T2 and the surface-emitting laser element VCSEL2 is −3V, the threshold voltage of the transfer thyristor T3 and the surface-emitting laser element VCSEL3 is −4.5V, the threshold voltage of the transfer thyristor T4 and the surface-emitting laser element VCSEL4 is −6V, and the threshold voltage of the transfer thyristors T and the surface-emitting laser elements VCSEL numbered 5 or more is −6.5V. However, since the first transfer signal line 72 is set to −1.5 V by the transfer thyristor T1 in the on state, the odd-numbered transfer thyristors T in the off state are not turned on. Since the second transfer signal line 73 is “H” (0 V), the even-numbered transfer thyristors T are not turned on. Since the light-up signal line 75 is “H” (0 V), none of the surface-emitting laser elements VCSEL are lighted up.

[0099] Immediately after time b (here, this refers to the time when a steady state is reached after a change in the thyristors etc. occurs due to a change in the signal potential at time b. The same applies to other cases), the transfer thyristor T1 is in the on state, and the other transfer thyristors T and the surface-emitting laser element VCSEL are in the off state.

[0100] (3) Time c At time c, the light-up signal φI1 transitions from “H” (0 V) to “L” (−5 V). When the light-up signal φI1 transitions from "H" to "L", the light-up signal line 75 transitions from "H" (0V) to "L" (-5V) via the current limiting resistor RI and the φI terminal. Then, -3.3V obtained by adding the voltage of 1.7V applied to the surface-emitting laser element VCSEL is applied to the surface-emitting laser element VCSEL1, and the surface-emitting laser element VCSEL1 having a threshold voltage of -1.5V is turned on, and the surface-emitting laser element VCSEL1 is turned on (emits light). As a result, the potential of the light-up signal line 75 becomes a potential close to -3.2V. Note that although the threshold voltage of the surface-emitting laser element VCSEL2 is -3V, the voltage applied to the surface-emitting laser element VCSEL2 is -1.5V obtained by adding the voltage of 1.7V applied to the surface-emitting laser element VCSEL to -3.2V, so that the surface-emitting laser element VCSEL2 is not turned on. Immediately after the time c, the transfer thyristor T1 and the surface-emitting laser element VCSEL1 are in the on state, and the surface-emitting laser element VCSEL1 is turned on (emitting light).

[0101] (4) Time d At time d, the light-up signal φI1 transitions from “L” (−5 V) to “H” (0 V). When the light-up signal φI1 transitions from "L" to "H", the potential of the light-up signal line 75 transitions from -3.2 V to "H" via the current limiting resistor RI and the φI terminal. Then, the anode of the surface-emitting laser element VCSEL1 becomes "H", so the surface-emitting laser element VCSEL1 is turned off (not lit). The light-up period of the surface-emitting laser element VCSEL1 is the period during which the light-up signal φI1 is "L", from time c when the light-up signal φI1 transitions from "H" to "L" to time d when the light-up signal φI1 transitions from "L" to "H". Immediately after the time d, the transfer thyristor T1 is in the ON state.

[0102] (5) Time e At time e, the second transfer signal φ2 transitions from “H” (0 V) to “L” (−5 V). At this point, the period T(1) during which the surface-emitting laser element VCSEL1 is controlled to be turned on ends, and a period T(2) during which the surface-emitting laser element VCSEL2 is controlled to be turned on begins. When the second transfer signal φ2 transitions from “H” to “L”, the potential of the second transfer signal line 73 transitions from “H” to “L” via the φ2 terminal. As described above, the transfer thyristor T2 turns on because its threshold voltage is −3 V. As a result, the potential of the gate terminal Gt2 (gate terminal Gs2) becomes “H” (0 V), the potential of the gate Gt3 (gate Gs3) becomes −1.5 V, the potential of the gate Gt4 (gate Gs4) becomes −3 V, and the potential of the gate Gt5 (gate Gs5) becomes −4.5 V. And the potential of the gates Gt (gate Gs) whose numbers are 6 or more becomes −5 V. Immediately after the time point e, the transfer thyristors T1 and T2 are in the ON state.

[0103] (6) Time f At time f, the first transfer signal φ1 transitions from “L” (−5 V) to “H” (0 V). When the first transfer signal φ1 transitions from "L" to "H", the potential of the first transfer signal line 72 transitions from "L" to "H" via the φ1 terminal. Then, the anode and cathode of the transfer thyristor T1 in the on state both become "H", and the transfer thyristor T1 is turned off. Then, the potential of the gate Gt1 (gate Gs1) changes toward the power supply potential Vgk ("L" (-5V)) of the power supply line 71 via the power supply line resistance Rg1. As a result, the coupling diode D1 is in a state in which a potential is applied in a direction in which no current flows (reverse bias). Therefore, the influence of the gate Gt2 (gate Gs2) being "H" (0V) does not extend to the gate Gt1 (gate Gs1). In other words, the transfer thyristor T having the gate Gt connected by the reverse-biased coupling diode D has a threshold voltage of -6.5V and does not turn on even if the first transfer signal φ1 or the second transfer signal φ2 becomes "L" (-5V). Immediately after the time f, the transfer thyristor T2 is in the on state.

[0104] (7)Other At time g, when the light-up signal φI1 transitions from “H” (0 V) to “L” (−5 V), the surface-emitting laser element VCSEL2 is turned on, and the surface-emitting laser element VCSEL2 lights up (emits light), similar to the surface-emitting laser element VCSEL1 at time c. Then, at time h, when the light-up signal φI1 transitions from “L” (−5 V) to “H” (0 V), the surface-emitting laser element VCSEL2 is turned off, similar to the surface-emitting laser element VCSEL1 at time d, and the surface-emitting laser element VCSEL2 is extinguished. Furthermore, at time i, when the first transfer signal φ1 transitions from “H” (0 V) to “L” (−5 V), the transfer thyristor T3, whose threshold voltage is −3 V, is turned on, similar to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. At time i, the period T(2) for controlling the lighting of the surface-emitting laser element VCSEL2 ends, and a period T(3) for controlling the lighting of the surface-emitting laser element VCSEL3 starts. From here on, we will repeat what has been explained so far.

[0105] When the surface-emitting laser element VCSEL is not turned on (emitted light) and is to be kept turned off (not lit), the light-up signal φI may be kept at “H” (0 V) like the light-up signal φI1 shown from time j to time k in the period T(4) during which the surface-emitting laser element VCSEL4 is controlled to be turned on in Fig. 5. By doing so, even if the threshold voltage of the surface-emitting laser element VCSEL4 is -1.5 V, the surface-emitting laser element VCSEL4 is not turned on, and the surface-emitting laser element VCSEL4 remains turned off (not lit).

[0106] As described above, the gate terminals Gt of the transfer thyristors T are connected to each other via the coupling diode D. Therefore, when the potential of the gate Gt changes, the potential of the gate Gt connected to the gate Gt whose potential has changed via the forward-biased coupling diode D also changes. Then, the threshold voltage of the transfer thyristor T having the gate whose potential has changed changes. When the threshold voltage is higher than −3.3 V (a negative value with a small absolute value), the transfer thyristor T turns on at the timing when the first transfer signal φ1 or the second transfer signal φ2 transitions from “H” (0 V) to “L” (−5 V). The surface-emitting laser element VCSEL, whose gate Gs is connected to the gate Gt of the transfer thyristor T in the on state, has a threshold voltage of -1.5 V, so when the lighting signal φI transitions from "H" (0 V) to "L" (-5 V), it turns on and the surface-emitting laser element VCSEL lights up (emits light).

[0107] That is, when the transfer thyristor T is turned on, it designates the surface-emitting laser element VCSEL that is the target of the lighting control, and the lighting signal φI of “L” (−5 V) turns on the surface-emitting laser element VCSEL that is the target of the lighting control and lights up (emits light). The light-up signal φI at “H” (0 V) maintains the surface-emitting laser element VCSEL in an off state and maintains the surface-emitting laser element VCSEL in a non-lighted state. That is, the light-up signal φI sets the surface-emitting laser element VCSEL to be on (emitting light) or off (not emitting light). In this manner, the lighting signal φI is set in accordance with image data to control the lighting or non-lighting of each of the surface-emitting laser elements VCSEL.

[0108] As described above, the light emitting component 10 is configured as a self-scanning light emitting device array (SLED).

[0109] (Variation 1) In the above embodiment, a surface-emitting laser element VCSEL in which the light-emitting layer 83 is present inside the thyristor structure has been shown, but the thyristor structure and the light-emitting layer 83 may be configured separately. Here, a surface-emitting laser element VCSEL in which the thyristor structure and the light-emitting layer 92 described below are separated and the upper and lower parts of the light-emitting layer 92 are configured as an upper DBR layer and a lower DBR layer will be described.

[0110] Fig. 6 is a diagram showing a modified example of the light emitting element Hs in the light emitting component 10 to which the present embodiment is applied. Fig. 6(a) is a plan view of the light emitting element Hs, Fig. 6(b) is a cross-sectional view taken along line VIB-VIB in Fig. 6(a), and Fig. 6(c) is a cross-sectional view taken along line VIC-VIC in Fig. 6(a).

[0111] In the light emitting element Hs in the first modification, a p-type DBR structure anode layer 91 (p anode (DBR) layer 91), a light emitting layer 92, and an n-type DBR structure cathode layer 93 (n cathode (DBR) layer 93) are provided on a p-type substrate 80 (substrate 80), which constitute a surface emitting laser element VCSEL. A tunnel junction (tunnel diode) layer 94 (tunnel junction layer 94) is provided on the n-type DBR structure anode layer 93 (n anode (DBR) layer 93). Furthermore, a p-type anode layer 95 (p anode layer 95), an n-type gate layer 96 (n gate layer 96), a p-type gate layer 97 (p gate layer 97), and an n-type cathode layer 98 (n cathode layer 98) are provided in this order on the tunnel junction layer 94, which constitute a setting thyristor S that sets (controls) the on / off of the surface emitting laser element VCSEL. In the following, the notation in parentheses is used. The same applies to other cases. Here, the semiconductor layer in which the p anode (DBR) layer 91, the light emitting layer 92, the n cathode (DBR) layer 93, the tunnel junction layer 94, the p anode layer 95, the n gate layer 96, the p gate layer 97, and the n cathode layer 98 are stacked is referred to as a semiconductor stack.

[0112] Here, the notation of the p-anode (DBR) layer 91 and the n-cathode (DBR) layer 93 corresponds to the function (operation) when configuring the surface-emitting laser element VCSEL. That is, the p-anode (DBR) layer 91 functions as the anode of the surface-emitting laser element VCSEL, and the n-cathode (DBR) layer 93 functions as the cathode of the surface-emitting laser element VCSEL. In other words, the surface-emitting laser element VCSEL has a diode structure equipped with an anode and a cathode. The designations of p anode layer 95, n gate layer 96, p gate layer 97, and n cathode layer 98 correspond to their functions when configuring the setting thyristor S. That is, the p anode layer 95 functions as an anode, the n gate layer 96 and the p gate layer 97 function as a gate, and the n cathode layer 98 functions as a cathode.

[0113] An n-type ohmic electrode 321 (n ohmic electrode 321) provided on the n cathode layer 98 serves as a cathode electrode. The n ohmic electrode 321 is provided between the emission aperture 50 and the hole 55 so as to surround the emission aperture 50. A p-type ohmic electrode 331 (p ohmic electrode 331) provided on the p gate layer 97 exposed by removing the n cathode layer 98 serves as a gate Gs1.

[0114] The p-anode (DBR) layer 91 of the surface-emitting laser element VCSEL includes a current confinement layer 91b that confines the current, as shown by the black dots in FIG. 6(b). Specifically, the p-anode (DBR) layer 91 is configured by laminating a lower p-anode (DBR) layer 91a, a current confinement layer 91b, and an upper p-anode (DBR) layer 91c in this order.

[0115] The thickness (optical path length) of the current confinement layer 91b in the p-anode (DBR) layer 91 is determined by the structure to be adopted. When emphasis is placed on extraction efficiency and process reproducibility, it is preferable to set it to an integer multiple of the thickness (optical path length) of the low refractive index layer and the high refractive index layer constituting the DBR layer, for example, 0.75 (3 / 4) of the central wavelength. In addition, in the case of an odd multiple, it is preferable that the current confinement layer 91b is sandwiched between a high refractive index layer and a high refractive index layer. In addition, in the case of an even multiple, it is preferable that the current confinement layer 91b is sandwiched between a high refractive index layer and a low refractive index layer. In other words, it is preferable that the current confinement layer 91b is provided so as to suppress the disturbance of the refractive index period caused by the DBR layer. Conversely, when it is desired to reduce the influence (refractive index and distortion) of the oxidized portion, the thickness of the current confinement layer 91b is preferably several tens of meters, and it is preferable that it is inserted in the part of the node of the standing wave standing in the DBR layer.

[0116] Moreover, eight holes 55 are provided around the light-emitting element Hs. As shown in FIG. 6(b), the holes 55 are provided by removing the n-cathode layer 98, the p-gate layer 97, the n-gate layer 96, the p-anode layer 95, the tunnel junction layer 94, the n-cathode (DBR) layer 93, the light-emitting layer 92, and the p-anode (DBR) layer 91 by etching, so as to reach the substrate 80. The current confinement layer 91b provided in the p-anode (DBR) layer 91 is oxidized through the holes 55. As a result, the central portion surrounded by the eight holes 55 becomes a portion that is not oxidized (current passing portion α). Moreover, the surrounding area becomes a current blocking portion β. As shown in FIGS. 6(b) and 6(c), except for the current passing portion α at the emission port 50, the current confinement layer 91b is oxidized from between the adjacent holes 55 and from the outer side surface of the laminated structure 301.

[0117] Fig. 7 is a diagram for explaining points that must be considered when configuring a laminated structure of a surface-emitting laser element VCSEL and a setting thyristor S. Fig. 7(a) is a schematic energy band diagram of the laminated structure of a surface-emitting laser element VCSEL and a setting thyristor S, Fig. 7(b) is an energy band diagram in a reverse bias state of the tunnel junction layer 94, and Fig. 7(c) shows the current-voltage characteristics of the tunnel junction layer 94. As shown in the energy band diagram of FIG. 7(a), when a voltage is applied between the n-ohmic electrode 321 and the rear electrode 89 in FIG. 6 so that the surface-emitting laser element VCSEL and the setting thyristor S are forward biased, the n ++ Layers 94a and p ++ A reverse bias is applied between layer 94b.

[0118] The tunnel junction layer 94 is a n-type semiconductor layer having a high concentration of n-type impurities. ++ A layer 94a and a p ++ The junction with layer 94b. Therefore, the width of the depletion region is narrow, and when forward biased, ++ From the conduction band on the layer 94a side to p ++ Electrons tunnel into the valence band on the layer 94b side, and at this time, negative resistance characteristics appear. On the other hand, as shown in FIG. 7(b), when the tunnel junction layer 94 (tunnel junction) is reverse biased (−V), ++ The potential Ev of the valence band on the layer 94b side is n + The potential Ec of the conduction band on the layer 94a side is higher than that of the layer 94b. + From the valence band of layer 94b, n ++ Electrons tunnel into the conduction band on the layer 94a side. As the reverse bias voltage (-V) increases, electrons tunnel more easily. That is, as shown in FIG. 7(c), a current easily flows through the tunnel junction layer 94 (tunnel junction) under a reverse bias.

[0119] 7(a), when the setting thyristor S is turned on, even if the tunnel junction layer 94 is reverse biased, a current flows between the surface-emitting laser element VCSEL and the setting thyristor S. This causes the surface-emitting laser element VCSEL to emit light (light up). When the connected transfer thyristor T is turned on and enters the on state, the setting thyristor S is in a state in which it can transition to the on state. Then, when the lighting signal φI becomes “L”, the setting thyristor S is turned on and enters the on state, and lights up the surface-emitting laser element VCSEL (sets lighting).

[0120] Instead of the tunnel junction layer 94, a III-V compound layer having metallic conductivity and epitaxially grown on a III-V compound semiconductor layer may be used. InNAs, which will be described as an example of a material for the metallic conductive III-V compound layer, has a negative band gap energy when the composition ratio x of InN is in the range of about 0.1 to about 0.8. InNSb has a negative band gap energy when the composition ratio x of InN is in the range of about 0.2 to about 0.75. The negative band gap energy means that there is no band gap. Therefore, it exhibits conductive properties (conductive properties) similar to those of a metal. In other words, metallic conductive properties (conductive properties) mean that a current flows if there is a gradient in the potential, similar to that of a metal.

[0121] The lattice constant of III-V group compounds (semiconductors) such as GaAs and InP is in the range of 5.6 Å to 5.9 Å. This lattice constant is close to the lattice constant of Si, which is about 5.43 Å, and the lattice constant of Ge, which is about 5.66 Å. In contrast, the lattice constant of InN, which is also a III-V compound, is about 5.0 Å in the zinc blende structure, and the lattice constant of InAs is about 6.06 Å. Therefore, the lattice constant of InNAs, a compound of InN and InAs, can be close to the 5.6 Å to 5.9 Å of GaAs and other compounds. The lattice constant of InSb, a III-V compound, is about 6.48 Å. Since the lattice constant of InN is about 5.0 Å, the lattice constant of InNSb, a compound of InSb and InN, can be close to the lattice constant of GaAs, which is 5.6 Å to 5.9 Å.

[0122] That is, InNAs and InNSb can be monolithically epitaxially grown on a layer of a III-V compound (semiconductor) such as GaAs. Also, a layer of a III-V compound (semiconductor) such as GaAs can be monolithically laminated by epitaxial growth on a layer of InNAs or InNSb.

[0123] Therefore, by stacking the setting thyristor S and the surface-emitting laser element VCSEL so as to be connected in series via a metallic conductive III-V compound layer instead of the tunnel junction layer 94, it is possible to prevent the n-cathode (DBR) layer 93 of the surface-emitting laser element VCSEL and the p-anode layer 95 of the setting thyristor S from being reverse biased.

[0124] According to the embodiment described above in detail, it is possible to operate the arrayed light emitting elements Hs by synchronously turning them on and off.

[0125] In the above example, the light emitting element Hs is a VCSEL, but the light emitting element Hs is not limited to this. For example, a light emitting thyristor may be used as the light emitting element Hs. In the above example, the current confinement layer is provided in the pDBR layers 81 and 91, but it may be provided in any layer other than the light-emitting layers 83 and 92. However, it is preferable to provide the current confinement layer in a p-type layer rather than an n-type layer. It is also preferable to provide the current confinement layer in a layer closer to the light-emitting layers 83 and 92.

[0126] (Variation 2) In the second modification, the light emitting component 10 is used to form a light emitting chip C. That is, the configuration of the light emitting component 10 is mounted and formed into a chip shape. Then, a case will be described in which the light emitting chips C are further arranged in a row to form a light emitting device 65.

[0127] FIG. 8 is a top view of a light emitting device 65 in which a light emitting chip C using the light emitting component 10 is disposed. 8, a light emitting device 65 is configured as a light source unit, in which 40 light emitting chips C1 to C40 (when no distinction is made, they are referred to as light emitting chips C) as an example of light emitting element array chips are arranged in a staggered pattern in two rows in the X direction on a circuit board. The light emitting chips C1 to C40 may have the same configuration. In this specification, "~" indicates a plurality of components distinguished from each other by numbers, and includes those written before and after "~" and those with numbers therebetween. For example, the light-emitting chips C1 to C40 include the light-emitting chip C1 to the light-emitting chip C40 in numerical order.

[0128] In the present embodiment, the number of the light-emitting chips C is 40 in total, but is not limited to this. The light emitting device 65 is equipped with a signal generating circuit 110 that drives the light emitting chip C. The signal generating circuit 110 is an example of a driving means for inputting and outputting a signal that drives the light emitting chip C. The signal generating circuit 110 is configured with, for example, an integrated circuit (IC). The light emitting device 65 does not need to be equipped with the signal generating circuit 110. In this case, the signal generating circuit 110 is provided outside the light emitting device 65, and supplies a control signal for controlling the light emitting chip C via a cable or the like. Here, the light emitting device 65 will be described as including the signal generating circuit 110.

[0129] Fig. 9 is a diagram showing an example of the configuration of the light-emitting chip C, the configuration of the signal generating circuit 110 of the light-emitting device 65, and the configuration of wiring (lines) on a circuit board. Fig. 9(a) shows the configuration of the light-emitting chip C, and Fig. 9(b) shows the configuration of the signal generating circuit 110 of the light-emitting device 65, and the configuration of wiring (lines) on a circuit board. Note that Fig. 9(b) shows the light-emitting chips C1 to C9 out of the light-emitting chips C1 to C40.

[0130] First, the configuration of the light-emitting chip C shown in FIG. 9(a) will be described. The light-emitting chip C includes a light-emitting unit 102 including a plurality of surface-emitting laser elements VCSEL (surface-emitting laser elements VCSEL1 to VCSEL128) arranged in a row along a long side on a side close to one of the long sides of the surface of the substrate 80 having a rectangular surface shape. The plurality of surface-emitting laser elements VCSEL are an example of a row of light-emitting components arranged in a row in the main scanning direction. Furthermore, the light-emitting chip C includes terminals (φ1 terminal, φ2 terminal, Vgk terminal, φI terminal) which are a plurality of bonding pads for receiving various control signals and the like, at both ends of the long side direction of the surface of the substrate 80. Note that these terminals are provided in the order of the φI terminal and the φ1 terminal from one end of the substrate 80, and the order of the Vgk terminal and the φ2 terminal from the other end of the substrate 80. The light-emitting unit 102 is provided between the φ1 terminal and the φ2 terminal. Furthermore, a back electrode 89 (see FIG. 2) is provided on the back side of the substrate 80 as a Vsub terminal. Here, on the surface of the substrate 80, the direction in which the surface-emitting laser elements VCSEL1 to VCSEL128 are arranged is the x direction, and the direction perpendicular to the x direction is the y direction.

[0131] Note that the term "in a row" does not necessarily mean that the multiple surface-emitting laser elements VCSEL are arranged in a straight line as shown in Fig. 9(a), but may also mean that the multiple surface-emitting laser elements VCSEL are arranged with different amounts of deviation from each other in a direction perpendicular to the row direction. For example, the surface-emitting laser elements VCSEL may be arranged with an amount of deviation in a direction perpendicular to the row direction. In addition, the surface-emitting laser elements VCSEL may be arranged alternately between adjacent surface-emitting laser elements VCSEL, or in a zigzag pattern for each of the multiple surface-emitting laser elements VCSEL.

[0132] Next, the configuration of the signal generating circuit 110 of the light emitting device 65 and the configuration of the wiring (lines) on the circuit board will be described with reference to FIG. 9(b). As described above, the signal generating circuit 110 and the light emitting chips C1 to C40 are mounted on the circuit board of the light emitting device 65, and wiring (lines) that connect the signal generating circuit 110 and the light emitting chips C1 to C40 are provided.

[0133] First, the configuration of the signal generating circuit 110 will be described. Various data and control signals are input to the signal generating circuit 110. The signal generating circuit 110 rearranges the data, corrects the amount of light, and so on, based on the various data and control signals. The signal generating circuit 110 includes a transfer signal generating unit 120 that transmits a first transfer signal φ1 and a second transfer signal φ2 to the light emitting chips C1 to C40 based on various control signals. The signal generating circuit 110 also includes a light-up signal generating unit 140 that transmits light-up signals φI1 to φI40 (referred to as light-up signal φI when no distinction is made) to the light-emitting chips C1 to C40, respectively, based on various control signals. Furthermore, the signal generating circuit 110 includes a reference potential supplying unit 160 that supplies a reference potential Vsub serving as a potential reference to the light emitting chips C1 to C40, and a power supply potential supplying unit 170 that supplies a power supply potential Vgk for driving the light emitting chips C1 to C40.

[0134] Next, the arrangement of the light emitting chips C1 to C40 will be described. The odd-numbered light-emitting chips C1, C3, C5, ... are arranged in a row at intervals in the long side direction of the respective substrates 80. The even-numbered light-emitting chips C2, C4, C6, ... are also arranged in a row at intervals in the long side direction of the respective substrates 80. The odd-numbered light-emitting chips C1, C3, C5, ... and the even-numbered light-emitting chips C2, C4, C6, ... are arranged in a staggered manner rotated by 180 degrees so that the long sides of the light-emitting units 102 provided in the light-emitting chips C face each other. The positions of the surface-emitting laser elements VCSEL between the light-emitting chips C are set so that they are arranged at predetermined intervals in the main scanning direction (X direction). Note that the light-emitting chips C1 to C40 in FIG. 9(b) are indicated by arrows in the direction of the arrangement of the surface-emitting laser elements VCSEL of the light-emitting unit 102 shown in FIG. 9(a) (in the numerical order of the surface-emitting laser elements VCSEL1 to VCSEL128).

[0135] The wiring (lines) connecting the signal generating circuit 110 and the light emitting chips C1 to C40 will be described. The circuit board is provided with a power supply line 200a that is connected to a back surface electrode 89 (see FIG. 2) that is a Vsub terminal provided on the back surface of the substrate 80 of the light-emitting chip C and supplies a reference potential Vsub. The circuit board is provided with a power supply line 200b that is connected to a Vgk terminal provided on the light-emitting chip C and supplies a power supply potential Vgk for driving.

[0136] The circuit board is provided with a first transfer signal line 201 for transmitting a first transfer signal φ1 from the transfer signal generating unit 120 of the signal generating circuit 110 to the φ1 terminals of the light emitting chips C1 to C40, and a second transfer signal line 202 for transmitting a second transfer signal φ2 to the φ2 terminals of the light emitting chips C1 to C40. The first transfer signal φ1 and the second transfer signal φ2 are transmitted commonly (in parallel) to the light emitting chips C1 to C40.

[0137] The circuit board is also provided with light-up signal lines 204-1 to 204-40 (when no distinction is required, these lines are referred to as light-up signal lines 204) that transmit light-up signals φI1 to φI40 from the light-up signal generating unit 140 of the signal generating circuit 110 to the φI terminals of the light-emitting chips C1 to C40 via current-limiting resistors RI, respectively.

[0138] As described above, the reference potential Vsub and the power supply potential Vgk are commonly supplied to all the light-emitting chips C1 to C40 on the circuit board. The first transfer signal φ1 and the second transfer signal φ2 are also commonly (in parallel) transmitted to the light-emitting chips C1 to C40. On the other hand, the light-up signals φI1 to φI40 are individually transmitted to the light-emitting chips C1 to C40.

[0139] [Optical measurement device 1] The light emitting device 65 described above can be used for optical measurement. FIG. 10 is a diagram for explaining an optical measurement device 1 using a light emitting device 65. As shown in FIG. The optical measurement device 1 includes the above-mentioned light emitting device 65, a light receiving unit 11 that receives light, and a processing unit 12 that processes data. A measurement target (object) 13 is placed facing the optical measurement device 1. In Fig. 10, the measurement target 13 is a person as an example. Fig. 10 is a view seen from above.

[0140] As described above, the light emitting device 65 turns on the surface emitting laser element VCSEL, and emits light linearly in the left-right direction in the drawing while moving the light irradiation direction in the up-down direction around the light emitting device 65 as shown by the solid line. That is, the light is scanned and irradiated onto the measurement object 13.

[0141] The light receiving unit 11 is a device that receives light reflected by the measurement object 13. The light receiving unit 11 receives light directed toward the light receiving unit 11 as indicated by the dashed line. The light receiving unit 11 is preferably an imaging device that receives light from two-dimensional directions.

[0142] The processing unit 12 is configured as a computer equipped with an input / output unit for inputting and outputting data. The processing unit 12 processes information related to the light to calculate the distance to the measurement object 13 and the three-dimensional shape of the measurement object 13. The processing unit 12 of the optical measurement device 1 controls the light emitting device 65 to emit light. Then, the processing unit 12 calculates the optical path length from being emitted from the light emitting device 65, being reflected by the measurement object 13, to reaching the light receiving unit 11 from the time difference between the timing (time) when the light emitting device 65 emits light and the timing (time) when the light receiving unit 11 receives the reflected light from the measurement object 13. The positions of the light emitting device 65 and the light receiving unit 11 and the interval between them are predetermined. Therefore, the processing unit 12 measures (calculates) the distance from the light emitting device 65 and the light receiving unit 11 or the distance from a point (reference point) used as a reference to the measurement object 13. The reference point is a point (point) provided at a predetermined position from the light emitting device 65 and the light receiving unit 11.

[0143] This method is based on the arrival time of light and is called the time-of-flight (TOF) method. If this method is performed for a plurality of points on the measurement object 13, the three-dimensional shape of the measurement object 13 is measured. As described above, the light emitted from the light emitting device 65 is irradiated onto the measurement object 13. Then, the reflected light from the portion of the measurement object 13 that is close to the light emitting device 65 is incident on the light receiving unit 11 first. When the imaging device for acquiring the above-mentioned two-dimensional image is used, a bright spot is recorded in the frame image at the portion where the reflected light reaches. From the bright spots recorded in a series of a plurality of frame images, the optical path length is calculated for each bright spot. Then, the distance from the light emitting device 65 and the light receiving unit 11 or the distance from a reference point (reference point) is calculated. That is, the three-dimensional shape of the measurement object 13 is calculated.

[0144] The optical measurement device 1 as described above can be applied to calculating the distance to an article. It can also be applied to identifying an article by calculating the shape of the article. It can also be applied to identifying a person's face (face recognition) by calculating the shape of the face. Furthermore, by loading it into a vehicle, it can be applied to detecting obstacles in front, behind, or to the sides. In this way, the optical measurement device 1 can be widely used to calculate distance, shape, and the like.

[0145] [Image forming device 2] The light emitting device 65 described above can be used for image formation. FIG. 11 is a diagram illustrating an image forming apparatus 2 using a light emitting device 65. As shown in FIG. The image forming apparatus 2 includes the above-mentioned light emitting device 65, a drive control unit 21, and a screen 22 that receives light.

[0146] The operation of the image forming apparatus 2 will now be described. As described above, the light emitting device 65 sets the surface emitting laser element VCSEL to light / non-light. Then, as shown by the solid line, the light emitting device 65 is centered and the light emitting direction is moved in the vertical direction while emitting light linearly in the horizontal direction in the figure. That is, the light is scanned and irradiated onto the screen 22. As a result, a two-dimensional still image (two-dimensional image) is obtained. Then, an image signal is input, and the drive control unit 21 drives the light emitting device 65 based on the image signal so that a two-dimensional image is formed, and the light sustaining period is sequentially rewritten as a frame, thereby obtaining a two-dimensional moving image. These two-dimensional still images and moving images are projected onto the screen 22.

[0147] Although the present embodiment has been described above, the technical scope of the present invention is not limited to the scope described in the above embodiment. It is clear from the claims that various modifications and improvements to the above embodiment are also included in the technical scope of the present invention. [Explanation of symbols]

[0148] 1...optical measurement device, 2...image forming device, 50...emission port, 55...hole, 65...light emitting device, 80...substrate, 81, 91...p anode (DBR) layer, 81b, 91b...current confinement layer, 82, 96...n gate layer, 83, 92...light emitting layer, 84, 97...p gate layer, 85, 93...n cathode (DBR) layer, 94...tunnel junction layer, 95...p anode layer, 98...n cathode layer, 101...driver, 102...light emitting section, 110...signal generating circuit, 120...transfer signal generating section, 140...lighting signal generating section, 160...substrate Semi-potential supplying section, 170...power supply potential supplying section, 301 to 306...laminated structure, φ1...first transfer signal, φ2...second transfer signal, φI (φI1 to φI40)...lighting signal, α...current passing section (area), β...current blocking section (area), C (C1 to C40)...light emitting chip, D (D1 to D127)...coupling diode, SD...start diode, T (T1 to T128)...transfer thyristor, VCSEL (VCSEL1 to VCSEL128)...vertical cavity surface emitting laser, Vgk...power supply potential, Vsub...reference potential

Claims

1. A substrate; A plurality of light emitting elements are provided on the substrate, and each of the light emitting elements emits light in a direction intersecting with a surface of the substrate; A plurality of holes arranged around each of the plurality of light emitting elements; a gate electrode electrically connected to each of the plurality of light-emitting elements and configured to control the plurality of light-emitting elements to be turned on and off at the same time; Equipped with the light-emitting element has a layered structure including a thyristor and a light-emitting layer that is provided between layers constituting the thyristor and emits light; The gate layer of the thyristor is connected as a common layer between the plurality of light emitting elements through the plurality of holes, and is electrically connected to the gate electrode.

2. 2. The light emitting component according to claim 1, wherein the uppermost layer of the thyristor is connected as a common layer between a plurality of light emitting elements via a plurality of the holes.

3. 2. The light emitting component according to claim 1, wherein the thyristor comprises a current confinement layer that is oxidized through the hole and that constricts a current flowing through the light emitting layer.

4. 2. The light emitting component according to claim 1, wherein the hole has a depth that reaches at least the position of a lower surface of the gate electrode at the hole location.

5. 5. The light emitting component according to claim 4, wherein the hole has a depth reaching a position of a lowermost layer among the layers of the light emitting element having a thyristor structure.

6. The light-emitting component of claim 5, wherein the plurality of holes are arranged in a circular shape at predetermined intervals around the emission port through which the light-emitting element emits light, so that a circular current confinement layer is formed that is oxidized through the holes and constricts the current flowing through the light-emitting layer.

7. A substrate, A plurality of light emitting elements are provided on the substrate, and each of the light emitting elements emits light in a direction intersecting with a surface of the substrate; a plurality of first holes arranged around each of the plurality of light emitting elements; a gate electrode electrically connected to each of the plurality of light-emitting elements and configured to control the plurality of light-emitting elements to be turned on and off at the same time; Equipped with A thyristor is further provided on the light emitting element, the thyristor has second holes at the same positions as the first holes, The gate layer of the thyristor is connected as a common layer between the plurality of light emitting elements via the plurality of second holes, and is electrically connected to the gate electrode.

8. 8. The light emitting component according to claim 7, wherein the thyristor is laminated on the light emitting element via a tunnel junction layer or a III-V compound layer having metallic conductivity.

9. a light emitting component row in which the light emitting components according to any one of claims 1 to 8 are arranged in a row in a main scanning direction; A driving means for inputting and outputting a signal for driving the light emitting component; A light-emitting element array chip comprising:

10. A light emitting component according to any one of claims 1 to 8; a light receiving unit that receives reflected light from an object onto which light is irradiated from the light emitting component; a processing unit that processes information about the light received by the light receiving unit to measure a distance from the light emitting component to an object or a shape of the object; An optical measurement device comprising:

Images