Semiconductor memory and method of operating the semiconductor memory

Abstract

To provide a semiconductor memory and a method of operating the semiconductor memory that generate an appropriate word line voltage, and suppressing a decrease in a read operation margin of the semiconductor memory even if characteristics of a memory cell fluctuate.SOLUTION: A semiconductor memory comprises: a memory cell; a monitor cell with the same size as a memory cell; a reference cell with a size larger than the memory cell; and a word voltage control circuit. In the monitor cell, a first transistor with a gate connected to a word line, and a second transistor are connected in series between a first voltage line and a ground line. In the reference cell, a third transistor and a fourth transistor are connected in series between the first voltage line and the ground line. In a read operation, the word voltage control circuit adjusts a high-level voltage of the word line so as that a voltage difference between a first connection node for connecting the first transistor in an on-state and the second transistor in the on-state and a second connection node for connecting the third transistor in the on-state and the fourth transistor in the on-state becomes small.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory and a method of operating a semiconductor memory. [Background technology]

[0002] The miniaturization of semiconductor manufacturing processes has tended to increase the variability in the electrical characteristics of elements such as transistors. This has resulted in a decrease in the operating margin of semiconductor memories such as SRAM (Static Random Access Memory). SRAM stores data in memory cells with a flip-flop structure. Therefore, if the operating margin decreases, there is a risk that the logic of the data stored in the memory cell may be inverted during a read operation.

[0003] To prevent the reduction of the operating margin during the read operation of SRAM, a method has been proposed to lower the high-level voltage of the word line during the read operation. For example, the high-level voltage of the word line is set to a voltage lower than the power supply voltage by the threshold voltage of a transistor with the same device structure as a specific transistor included in a memory cell. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-66493 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-53981 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-9674 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-260186 [Patent Document 5] Japanese Patent Application Laid-Open No. 2008-65968 [Patent Document 6] International Publication No. 2010 / 146640 [Patent Document 7] Japanese Patent Application Laid-Open No. 2009-20957 [Patent Document 8] Japanese Patent Application Laid-Open No. 2010-231853 [Patent Document 9] Japanese Patent Application Laid-Open No. 2008-210443 [Patent Document 10] Japanese Patent Application Laid-Open No. 2010-282704 [Patent Document 11] Japanese Patent Application Laid-Open No. 2010-61703 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the semiconductor manufacturing process varies, the characteristics of the memory cell may vary not only in accordance with the variation in the threshold voltage of the predetermined transistor, but also in accordance with, for example, the variation in the composite characteristics of a plurality of transistors, or in accordance with the variation in the characteristics of parasitic components such as diffusion layer resistance, etc. Therefore, it is difficult to generate an appropriate word line voltage that corresponds to the variation in the semiconductor manufacturing process by simply adjusting the high-level voltage of the word line voltage in accordance with the threshold voltage of the predetermined transistor.

[0006] The present invention has been made in consideration of the above points, and aims to generate an appropriate word line voltage and suppress a decrease in the read operation margin of a semiconductor memory even when the semiconductor manufacturing process fluctuates and the characteristics of the memory cell fluctuate. [Means for solving the problem]

[0007] According to one aspect, a semiconductor memory includes: a memory cell including a pair of driver transistors and a pair of transfer transistors, each having its gate connected to a word line; a monitor cell including a first transistor having the same size as the transfer transistor and having its gate connected to the word line, and a second transistor having the same size as the driver transistor, the first transistor and the second transistor being connected in series between a first voltage line and a ground line; a reference cell including a third transistor larger in size than the transfer transistor and a fourth transistor larger in size than the driver transistor, the third transistor and the fourth transistor being connected in series between a first voltage line and a ground line; and a word voltage control circuit that adjusts a high-level voltage of the word line so that, during a read operation of reading data from the memory cell, a difference between a first voltage at a first connection node connecting the first transistor in an on state and the second transistor in an on state and a second voltage at a second connection node connecting the third transistor in an on state and the fourth transistor in an on state is small. [Effects of the Invention]

[0008] Even if the semiconductor manufacturing process fluctuates and the characteristics of the memory cells fluctuate, an appropriate word line voltage can be generated, and a decrease in the read operation margin of the semiconductor memory can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of a semiconductor memory according to a first embodiment. [Figure 2] FIG. 10 is a block diagram showing an example of a semiconductor memory according to a second embodiment. [Figure 3] 3 is a circuit diagram showing an example of the memory cell array of FIG. 2. FIG. [Figure 4] 3 is a circuit diagram showing an example of a main part of the semiconductor memory of FIG. 2. [Figure 5] FIG. 10 is a block diagram showing an example of a semiconductor memory according to a third embodiment. [Figure 6]FIG. 6 is a circuit diagram illustrating an example of the voltage averaging circuit of FIG. 5. [Figure 7] FIG. 10 is a circuit diagram showing an example of a main part of a semiconductor memory according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiments will be described below with reference to the drawings. In the following, the same symbols as the signal or voltage names are used for signal or voltage lines that transmit signals or voltages, and the same symbols as the power supply voltages are used for power supply lines. Signal lines shown as single lines in the drawings, such as address signals, may be multi-bit. The symbol " / " at the beginning of a signal name indicates a negative logic signal. A transistor with a circle on the gate indicates a p-channel MOS (Metal Oxide Semiconductor) transistor, and a transistor without a circle on the gate indicates an n-channel MOS transistor.

[0011] FIG. 1 illustrates an example of a semiconductor memory according to a first embodiment. For example, the semiconductor memory 100 illustrated in FIG. 1 is an SRAM, and may take the form of a memory macro, a memory chip, or a package containing a memory chip. The semiconductor memory 100 includes a monitor cell 10, a reference cell 20, a voltage comparator circuit 30, a word line driver circuit 40, and a memory cell 50. For example, the memory cell 50 is a six-transistor type, and includes load transistors L1 and L2, driver transistors D1 and D2, and transfer transistors T1 and T2.

[0012] The load transistors L1 and L2 have the same shape and electrical characteristics. The driver transistors D1 and D2 have the same shape and electrical characteristics. The transfer transistors T1 and T2 have the same shape and electrical characteristics. Hereinafter, the load transistors L1 and L2, the driver transistors D1 and D2, and the transfer transistors T1 and T2 may be simply referred to as transistors L1 and L2, transistors D1 and D2, and transistors T1 and T2, respectively.

[0013] In the memory cell 50, the load transistor L1 and the driver transistor D1 are connected in series between the power supply line VDD and the ground line VSS and function as an inverter IV1. The gates of the load transistor L1 and the driver transistor D1 are connected to the bit line BL via the transfer transistor T1. The load transistor L2 and the driver transistor D2 are connected in series between the power supply line VDD and the ground line VSS and function as an inverter IV2. The gates of the load transistor L2 and the driver transistor D2 are connected to the bit line / BL via the transfer transistor T2. The gates of the transfer transistors T1 and T2 are connected to the word line WL.

[0014] In memory cell 50, the drains of load transistor L1 and driver transistor D1 are connected to the gates of load transistor L2 and driver transistor D2. The drains of load transistor L2 and driver transistor D2 are connected to the gates of load transistor L1 and driver transistor D1. That is, the output of inverter IV1 is connected to the input of inverter IV2, and the output of inverter IV2 is connected to the input of inverter IV1.

[0015] The memory cell 50 retains data using a latch formed by a pair of inverters IV1 and IV2. For ease of understanding, Fig. 1 shows one memory cell 50, one word line WL, and one pair of bit lines BL and / BL. However, the semiconductor memory 100 may have multiple memory cells 50, multiple word lines WL, and multiple pairs of bit lines BL and / BL.

[0016] Hereinafter, the memory state of the memory cell 50 in which the inverter IV1 outputs a low level and the inverter IV2 outputs a high level will be referred to as a "1" memory state. The memory state in which the inverter IV1 outputs a high level and the inverter IV2 outputs a low level will be referred to as a "0" memory state of the memory cell 50. The output nodes of the inverters IV1 and IV2 are storage nodes that hold data. In a read operation to read data from the memory cell 50, when the word line WL is set to a high level, the outputs of the inverters IV2 and IV1 are connected to the bit lines BL and / BL, which are precharged to a high level, via the transfer transistors T1 and T2, respectively.

[0017] In a read operation of the memory cell 50 in the "1" storage state, the transfer transistors T1 and T2 are turned on, so that the high level of the output node of the inverter IV2 is read onto the bit line BL, and the low level of the output node of the inverter IV1 is read onto the bit line / BL. At this time, the voltage of the output node of the inverter IV1 rises due to the current flowing from the bit line / BL via the transfer transistor T2. In order to prevent the memory cell 50 from being inverted from the "1" storage state to the "0" storage state, it is necessary to maintain the voltage of the output node of the inverter IV1 (the voltage of the input node of the inverter IV2) below the logical threshold voltage of the inverter IV2.

[0018] In a read operation of the memory cell 50 in the "0" storage state, the transfer transistors T1 and T2 are turned on, so that the low level of the output node of the inverter IV2 is read onto the bit line BL, and the high level of the output node of the inverter IV1 is read onto the bit line / BL. At this time, the voltage of the output node of the inverter IV2 rises due to the current flowing from the bit line BL via the transfer transistor T1. In order to prevent the memory cell 50 from being inverted from the "0" storage state to the "1" storage state, it is necessary to maintain the voltage of the output node of the inverter IV2 (the voltage of the input node of the inverter IV1) below the logical threshold voltage of the inverter IV1.

[0019] The voltage at the output node of inverter IV1 in a read operation of the "1" memory state is determined by the voltage division between the on-resistance of transfer transistor T2 and the on-resistance of driver transistor D1. Similarly, the voltage at the output node of inverter IV2 in a read operation of the "0" memory state is determined by the voltage division between the on-resistance of transfer transistor T1 and the on-resistance of driver transistor D2.

[0020] For this reason, the on-resistance of the transfer transistors T1 and T2 during a read operation must be set to a resistance value that does not invert the memory state of the memory cell 50 even when current flows from the bit lines BL and / BL into the memory cell 50. In this embodiment, the high-level voltage of the word line WL is adjusted according to the divided voltage resulting from the on-resistance of the transfer transistor T1 (or T2) and the on-resistance of the driver transistor D2 (or D1). This prevents the memory state of the memory cell 50 from being inverted during a read operation.

[0021] For example, in a read operation of the memory cell 50 storing "1", a high level of the bit line / BL is applied to the gate of the load transistor L2 via the transfer transistor T2. This increases the source-drain resistance of the load transistor L2, reducing the amount of current supplied from the load transistor L2 to the output node of the inverter IV2. However, the precharge voltage of the bit line BL, supplied via the transfer transistor T1, is supplied to the output node of the inverter IV2, preventing the output node of the inverter IV2 from inverting from high to low. Furthermore, since the load transistor L1 receives a high level at its gate and maintains a high resistance state, the current flowing through the load transistor L1 during a read operation of the memory cell 50 storing "1" is so small that its impact can be ignored.

[0022] The monitor cell 10 has a transfer transistor MT2 corresponding to the transfer transistor T2 of the memory cell 50 and a driver transistor MD1 corresponding to the driver transistor D1 of the memory cell 50. The monitor cell 10 also has a load transistor ML1 corresponding to the load transistor L1 of the memory cell 50. For example, the transfer transistor MT2 has the same size as the transfer transistors T1 and T2, the driver transistor MD1 has the same size as the driver transistors D1 and D2, and the load transistor ML1 has the same size as the load transistors L1 and L2.

[0023] Here, "same size" of transistors means that the gate widths of the transistors are the same, the channel lengths of the transistors are the same, and the thicknesses of the gate insulating films of the transistors are the same. Furthermore, "same size" of transistors means that the sizes of the source regions are the same, and the sizes of the drain regions are the same. This allows the electrical characteristics of the transistors to be made equivalent. For example, transistors of the same size can be manufactured using the same layout data.

[0024] The gate of the transfer transistor MT2 is connected to the word line WL. The transistors MT2 and MD1 are connected in series between the high-level voltage line HV and the ground line VSS via the connection node ND1. For example, the high-level voltage HV is set to the same value as the power supply voltage VDD. The transistors ML1 and MD1 are connected in series between the power supply line VDD and the ground line VSS via the connection node ND1. The gates of the transistors ML1 and MD1 are connected to the power supply line VDD, so that the load transistor ML1 is always off and the driver transistor MD1 is always on.

[0025] During a read operation of the memory cell 50, the word line WL is set to a high level, turning on the transfer transistor MT2. The monitor cell 10 generates a voltage V1 at the connection node ND1 that corresponds to the resistive voltage division of the on-state transistors MT2 and MD1. Since the connection node ND1 corresponds to the storage node that stores data in the memory cell 50, the voltage V1 represents the voltage at the output node of the inverter IV1 or IV2 that outputs a low level in the memory cell 50. In other words, the monitor cell 10 can monitor the voltage of the storage node of the memory cell 50. Note that, to make the electrical characteristics of the monitor cell 10 equivalent to those of the memory cell 50, it is preferable to place the monitor cell 10 close to the memory cell 50.

[0026] The reference cell 20 has a transfer transistor RT2 corresponding to the transfer transistor T2 of the memory cell 50 and a driver transistor RD1 corresponding to the driver transistor D1 of the memory cell 50. The reference cell 20 also has a load transistor RL1 corresponding to the load transistor L1 of the memory cell 50. The transfer transistor RT2 is larger in size than the transfer transistors T1 and T2, and the driver transistor RD1 is larger in size than the driver transistors D1 and D2. The load transistor RL1 is larger in size than the load transistors L1 and L2.

[0027] For example, the transfer transistor RT2 is the same as (e.g., twice as large as) the transfer transistors T1 and T2. The driver transistor RD1 is the same as (e.g., twice as large as) the driver transistors D1 and D2. The load transistor RL1 is the same as (e.g., twice as large as) the load transistors L1 and L2. This allows the ratios W / L of the gate width W to the gate length L of the transfer transistors RT2, T1, and T2 to be the same, and the threshold voltages of the transfer transistors RT2, T1, and T2 to be equal to each other. Therefore, the on-resistances of the transfer transistors RT2, T1, and T2 when the same voltage is applied to the gates can be equal to each other.

[0028] Furthermore, since the ratios W / L of the driver transistors RD1, D1, and D2 can be made the same, the threshold voltages of the driver transistors RD1, D1, and D2 can be made the same. This allows the on-resistances of the driver transistors RD1, D1, and D2 to be made the same when the same voltage is applied to their gates. Furthermore, since the ratios W / L of the load transistors RL1, L1, and L2 can be made the same, the threshold voltages of the load transistors RL1, L1, and L2 can be made the same. This allows the off-resistances of the load transistors RL1, L1, and L2 to be made the same when the same voltage is applied to their gates.

[0029] Here, larger-sized transistors are less susceptible to variations in electrical characteristics due to variations in the semiconductor manufacturing process than smaller-sized transistors. Therefore, when the variations in the manufacturing process of the semiconductor memory 100 are within the standard range (within specifications), the threshold voltage of the transfer transistor RT2 of the reference cell 20 can be set to be equivalent to the threshold voltages of the transfer transistors T1 and T2 of the memory cell 50 in the standard state.

[0030] Similarly, regardless of variations in the semiconductor manufacturing process, the threshold voltage of driver transistor RD1 can be set to a value equivalent to the threshold voltages of driver transistors D1 and D2 of memory cell 50 in the standard state. Regardless of variations in the semiconductor manufacturing process, the threshold voltage of load transistor RL1 can be set to a value equivalent to the threshold voltages of load transistors L1 and L2 of memory cell 50 in the standard state. Here, the standard state is, for example, a state that indicates the median (typical) value of electrical characteristics when the semiconductor manufacturing process varies within a predetermined range.

[0031] In the reference cell 20, the transistors RT2 and RD1 are connected in series between the high-level voltage line HV and the ground line VSS via a connection node ND2. The transistors RL1 and RD2 are connected in series between the power supply line VDD and the ground line VSS via a connection node ND2. The gates of the transistors RL1 and RD2 are connected to the power supply line VDD, so that the load transistor RL1 is always off and the driver transistor RD2 is always on.

[0032] The reference cell 20 generates, at the connection node ND2, a voltage V2 corresponding to the resistive voltage division of the transistors RT2 and RD1 in the on state. The connection node ND2 corresponds to the storage node that stores data in the memory cell 50, so the voltage V2 represents the voltage of the output node of the inverter IV1 or IV2 that outputs a low level in the memory cell 50 in the standard state. In other words, the reference cell 20 can generate, at the connection node ND2, the voltage of the storage node of the memory cell 50 in the standard state when the semiconductor manufacturing process variations are within the standard range.

[0033] Here, the memory cell 50 is designed so that, when the fluctuations in the semiconductor manufacturing process are within a standard range, the logic of the data held in the storage nodes of the memory cell 50 is not inverted during a read operation. Therefore, the voltage V2 generated at the connection node ND2 is a voltage that does not invert the logic of the data held in the storage nodes of the memory cell 50 when the transfer transistors T1 and T2 are turned on during a read operation of the memory cell 50.

[0034] Therefore, by adjusting the high-level voltage of the word line WL so that the voltage V1 of the monitor cell 10 is equal to the voltage V2 (reference voltage), it is possible to prevent the logic of the data held in the storage node of the memory cell 50 from being inverted during a read operation. In other words, even if the electrical characteristics of the memory cell 50 change due to fluctuations in the semiconductor manufacturing process, it is possible to prevent a decrease in the read margin of the memory cell 50 by adjusting the high-level voltage of the word line WL so that the voltage V1 is equal to the voltage V2.

[0035] During a read operation, the voltage comparison circuit 30 compares voltages V1 and V2 and outputs a word line control signal WLCNT indicating the comparison result. For example, during a read operation, when voltage V1 is higher than voltage V2, the voltage comparison circuit 30 generates a word line control signal WLCNT that lowers the high-level voltage of the word line WL. During a read operation, when voltage V1 is lower than voltage V2, the voltage comparison circuit 30 generates a word line control signal WLCNT that raises the high-level voltage of the word line WL.

[0036] During a read operation, the word line drive circuit 40 adjusts the high-level voltage of the word line WL in response to the word line control signal WLCNT, and supplies the adjusted high-level voltage to the memory cell 50 and the monitor cell 10. The voltage comparison circuit 30 and the word line drive circuit 40 function as a word voltage control circuit that controls the voltage of the word line WL during a read operation.

[0037] For example, if the high-level voltage of the word line WL decreases based on the detection of voltage V1 > voltage V2, the on-resistance of the transfer transistor MT2 of the monitor cell 10 increases. This reduces the current flowing through the transfer transistor MT2, causing the voltage V1 to decrease. If the high-level voltage of the word line WL increases based on the detection of voltage V1 < voltage V2, the on-resistance of the transfer transistor MT2 of the monitor cell 10 decreases. This increases the current flowing through the transfer transistor MT2, causing the voltage V1 to increase.

[0038] In this way, the voltage comparator circuit 30 and the word line driver circuit 40 compare the voltages V1 and V2 and adjust the high-level voltage of the word line WL so that the difference between the voltages V1 and V2 becomes small, thereby generating a high-level voltage of the word line WL such that the voltage V1 is equal to the voltage V2.

[0039] The solid and dashed arrows in the equivalent circuits of the monitor cell 10 and the reference cell 20 indicate the current flowing between the source and drain of each transistor MT2, RT2, ML1, RL1, MD1, and RD1. The longer the solid arrow, the larger the current, and the dashed arrow indicates almost no current. In this embodiment, by adjusting the high-level voltage of the word line WL, the current flowing through the transfer transistor MT2 (RT2) can be made smaller than the current flowing through the driver transistor MD1 (RD1), regardless of variations in the semiconductor manufacturing process.

[0040] The gate of the transfer transistor RT2 of the reference cell 20 may be connected not to the high-level voltage line HV but to a voltage line that is set to a high level during a read operation and set to a low level during other operations. For example, a read operation refers to a period during which the word line WL is set to a high level. This allows the reference cell 20 to have the same transistor structure (same size) as the memory cell 50, similar to the reference cell 20A shown in FIG. 4 (described later). As a result, it becomes easier to match the electrical characteristics of the reference cell 20 to those of the memory cell 50.

[0041] As described above, in this embodiment, the semiconductor memory 100 can set the high-level voltage of the word line WL during a read operation to an appropriate voltage that does not invert the logic of the data held in the storage node of the memory cell 50, regardless of variations in the semiconductor manufacturing process. As a result, it is possible to suppress a decrease in the read operation margin of the semiconductor memory 100 due to variations in the semiconductor manufacturing process.

[0042] Furthermore, in the reference cell 20, the size of the transfer transistor RT2 is set to be equal to that of the transfer transistors T1 and T2, and the size of the driver transistor RD1 is set to be equal to that of the driver transistors D1 and D2. This allows the electrical characteristics of the transfer transistor RT2 to be the electrical characteristics of the transfer transistors T1 and T2 in the standard state, regardless of variations in the semiconductor manufacturing process. Furthermore, the electrical characteristics of the driver transistor RD1 can be the electrical characteristics of the driver transistors D1 and D2 in the standard state, regardless of variations in the semiconductor manufacturing process. As a result, the reference cell 20 can generate a voltage V2 equal to the low-level voltage of the storage node during a read operation of the memory cell 50 in the standard state, regardless of variations in the semiconductor manufacturing process.

[0043] In the monitor cell 10, the transfer transistor MT2 is set to the same size as the transfer transistors T1 and T2 of the memory cell 50, and the driver transistor MD1 is set to the same size as the driver transistors D1 and D2 of the memory cell 50. This allows the voltage V1 of the connection node ND1 of the monitor cell 10 to be monitored as the voltage of the storage node of the memory cell 50, and the monitored voltage V1 can be supplied to the voltage comparison circuit 30.

[0044] FIG. 2 shows an example of a semiconductor memory according to a second embodiment. The same elements as those in FIG. 1 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. For example, the semiconductor memory 100A shown in FIG. 2 is an SRAM, and has the form of a memory macro, a memory chip, or a package in which memory chips are mounted. The semiconductor memory 100A includes a monitor cell 10A, a reference cell 20A, a voltage comparator circuit 30, a word line driver circuit 40, a memory cell array 52, a command decoder circuit 60, a row selector circuit 70, a column selector circuit 80, a sense amplifier 82, an array power supply circuit 90, and an inverter IV. Examples of the monitor cell 10A, the reference cell 20A, the voltage comparator circuit 30, the inverter IV, and the word line driver circuit 40 are shown in FIG. 4.

[0045] The memory cell array 52 has a plurality of memory cells 50 arranged in a matrix. The memory cells 50 arranged vertically in FIG. 2 are connected to m+1 pairs of bit lines BL, / BL (BL0, / BL0, BL1, / BL1, ..., BLm, / BLm), respectively. The memory cells 50 arranged horizontally in FIG. 2 are connected to n+1 word lines WL (WL0, WL1, ..., WLn).

[0046] The command decoder circuit 60 decodes a command signal CMD received via an external terminal, and outputs a control signal according to the decoding result to the row selection circuit 70, the column selection circuit 80, the sense amplifier 82, etc. The row selection circuit 70 decodes an address signal AD received via an address terminal based on the control signal from the command decoder circuit 60, and outputs a word line enable signal / WLEN that selects one of the word lines WL according to the decoding result.

[0047] The column selection circuit 80 decodes the address signal AD based on a control signal from the command decoder circuit 60 and selects one of the bit line pairs BL and / BL according to the decoding result. In a write operation, a data signal DQ received via a data terminal is transmitted as complementary data to the selected bit line pair BL and / BL. The logic of the data signal DQ is then written to the memory cell 50 connected to the selected word line and the selected bit line pair BL and / BL. In a read operation, complementary data is read from the memory cell 50 connected to the selected word line and the selected bit line pair BL and / BL to the selected bit line pair BL and / BL. The complementary data read to the bit line pair BL and / BL is amplified by a sense amplifier 82 and output to the data terminal DQ as read data.

[0048] The array power supply circuit 90 supplies a power supply voltage VDD to the memory cells 50, the monitor cells 10A, the reference cells 20A, the voltage comparison circuit 30, the word line drive circuit 40, etc. The power supply voltage VDD is a voltage supplied to the memory cell array 52, etc., in order to cause the semiconductor memory 100A to perform read and write operations.

[0049] The monitor cell 10A is provided in common to a plurality of memory cells 50 in the memory cell array 52. ​​In the example shown in FIG. 2, the monitor cell 10A is connected to the word line WLn, but it may be connected to another word line WL. The monitor cell 10A may also be formed using one of the columns of dummy memory cells (not shown) arranged around the memory cell array 52. ​​In this case, the column of dummy memory cells is connected to a pair of dummy bit lines. The dummy memory cells have the same element configuration as the memory cells 50, but data is not read or written from or to the dummy memory cells.

[0050] Furthermore, the monitor cell 10A may be a dummy memory cell (not shown) arranged in the memory cell array 52. ​​By using a dummy memory cell arranged in the memory cell array 52, the electrical characteristics of the monitor cell 10A can be made equivalent to those of the memory cells 50. Furthermore, the amount of variation in the electrical characteristics of the monitor cell 10A due to variations in the semiconductor manufacturing process can be made equivalent to the amount of variation in the electrical characteristics of the memory cells 50.

[0051] A word line drive circuit 40 is provided corresponding to each word line WL (WL0, WL1, ..., WLn). Note that a word line drive circuit 40 may be used for read operations, and a separate word line drive circuit may be provided for write operations. The voltage comparator circuit 30 outputs a word line control signal WLCNT common to all word line drive circuits 40.

[0052] 3 is a circuit diagram showing an example of the memory cell array 52 of FIG. 2. The circuit configuration of the memory cell 50 is the same as that of the memory cell 50 of FIG. 1. As explained in FIG. 2, the memory cells 50 arranged vertically in FIG. 3 are connected to a bit line pair BL0, / BL0 or a bit line pair BL1, / BL1, etc. The memory cells 50 arranged horizontally in FIG. 3 are connected to a word line WL0 or a word line WL1, etc.

[0053] 4 is a circuit diagram showing an example of a main part of the semiconductor memory 100 of FIG. 2. The monitor cell 10A has transfer transistors MT1 and MT2, driver transistors MD1 and MD2, and load transistors ML1 and ML2. The transfer transistors MT1 and MT2 correspond to the transfer transistors T1 and T2 of the memory cell 50. The driver transistors MD1 and MD2 correspond to the driver transistors D1 and D2 of the memory cell 50. The load transistors ML1 and ML2 correspond to the load transistors L1 and L2 of the memory cell 50.

[0054] The element configuration of the monitor cell 10A is the same as that of the memory cell 50, and the element layout of the monitor cell 10A is the same as that of the memory cell 50. That is, the element size of each transistor of the monitor cell 10A is the same as that of the corresponding transistor of the memory cell 50. Therefore, like the monitor cell 10 of FIG. 1, the electrical characteristics of the monitor cell 10A can be made equivalent to those of the memory cell 50.

[0055] On the other hand, some of the wiring of the monitor cell 10A differs from that of the memory cell 50. For example, the gate and one of the source and drain of the transfer transistor MT1 are connected to the power supply line VDD. The gate of the transfer transistor MT2 is connected to the word line WLn. One of the source and drain of the transfer transistor MT2 is connected to the power supply line VDD. In the monitor cell 10A, the output node of the inverter IVM1 and the input node of the inverter IVM2 are connected to the voltage comparator circuit 30 via a connection node ND1.

[0056] The transfer transistor MT2 of the monitor cell 10A is turned off while the word line WL is low. Therefore, the monitor cell 10A can be set to a "1" storage state by the power supply voltage VDD supplied via the transfer transistor MT1 while the word line WL is low. In other words, the monitor cell 10A can be set to a "1" storage state when the word line WL transitions to a high level and access to the memory cell 50 begins.

[0057] Here, the term "same element layout" includes, for example, the same layout of the active regions (source and drain regions) and the same layout of the gates. Furthermore, the term "same element layout" may also include the same contact pattern connected to the transistor, or the same layout of at least a portion of the wiring connected to the transistor. Thus, the term "same element layout" does not necessarily mean that the layout of the monitor cell 10A is completely identical to the layout of the memory cell 50.

[0058] By making the element layouts the same or similar, the electrical characteristics and operational characteristics, including parasitic components, of the memory cell 50 and the monitor cell 10A can be made similar to each other. Here, "similar electrical characteristics and operational characteristics" includes the case where the resistive voltage division ratios of the memory cell 50 and the monitor cell 10A when the transfer transistor and the driver transistor are both on are the same, substantially the same, or have a strong correlation between them.

[0059] The reference cell 20A has transfer transistors RT1 and RT2, driver transistors RD1 and RD2, and load transistors RL1 and RL2. The transfer transistors RT1 and RT2 correspond to the transfer transistors T1 and T2 of the memory cell 50. The driver transistors RD1 and RD2 correspond to the driver transistors D1 and D2 of the memory cell 50. The load transistors RL1 and RL2 correspond to the load transistors L1 and L2 of the memory cell 50.

[0060] The element configuration of the reference cell 20A is the same as that of the memory cell 50, and the element layout of the reference cell 20A is the same as that of the memory cell 50. That is, the element size of each transistor of the reference cell 20A is the same as (e.g., twice) the element size of the corresponding transistor of the memory cell 50. Therefore, similar to the reference cell 20 of FIG. 1, the electrical characteristics of the reference cell 20A can be made equivalent to the electrical characteristics of the memory cell 50 in a standard state, regardless of variations in the semiconductor manufacturing process.

[0061] On the other hand, some of the wiring of the reference cell 20A differs from that of the memory cell 50. For example, the gate and one of the source and drain of the transfer transistor RT1 are connected to the power supply line VDD. The gate of the transfer transistor RT2 is connected to the output of the inverter IV, and one of the source and drain of the transfer transistor RT2 is connected to the power supply line VDD. In the reference cell 20A, the output node of the inverter IVR1 and the input node of the inverter IVR2 are connected to the voltage comparison circuit 30 via a connection node ND2.

[0062] The inverter IV receives the word line enable signal / WLEN and outputs a signal obtained by inverting the logic of the word line enable signal / WLEN to the gate of the transfer transistor RT2. The signal obtained by inverting the logic of the word line enable signal / WLEN has the same logic as the word line signal WL. In FIG. 4, the word line enable signal / WLEN supplied to the word line drive circuit 40 is supplied to the input of the inverter IV2. However, as shown in FIG. 2, a separate word line enable signal / WLEN that is not supplied to the word line drive circuit 40 may be supplied to the input of the inverter IV2.

[0063] By supplying a signal with the inverted logic of the word line enable signal / WLEN to the gate of the transfer transistor RT2, the transfer transistor RT2 can be turned off while the word line enable signal / WLEN is high. This allows the reference cell 20A to be set to a "1" memory state by the power supply voltage VDD supplied via the transfer transistor RT1. In other words, the reference cell 20A can be set to a "1" memory state when the word line WL transitions to a high level and access to the memory cell 50 begins.

[0064] Note that, instead of the inverter IV, another word line driving circuit (for example, a replica with the same element size) having the same circuit configuration as the word line driving circuit 40 may be arranged. Like the word line driving circuit 40, the other word line driving circuit receives a word line enable signal / WLEN and outputs a word line signal WL. Note that, in the transistor N1 of the other word line driving circuit corresponding to the transistor N1 of the word line driving circuit 40, for example, one of the source and drain is connected to the word line WL, and the other of the source and drain is connected to a high-level voltage line such as the power supply line VDD.

[0065] If another word line drive circuit is provided instead of the inverter IV, the gate of the transfer transistor RT2 of the reference cell 20A receives the word line signal WL output from the other word line drive circuit. A load equivalent to the load applied to the word line WL connected to each word line drive circuit 40 may be connected to the word line WL transmitting the word line signal WL output from the other word line drive circuit. This allows the timing of the word line signal WL received at the gate of the transfer transistor MT2 of the monitor cell 10A to be approximately the same as the timing of the word line signal WL received at the gate of the transfer transistor RT2 of the reference cell 20A from the other word line drive circuit.

[0066] The voltage comparison circuit 30 includes an amplifier 31, a feedback capacitor 32, and resistors 33 and 34. The negative input of the amplifier 31 receives the voltage V1 at the connection node ND1 via the resistor 33. The positive input of the amplifier 31 receives the voltage V2 at the connection node ND2 via the resistor 34. The feedback capacitor 32 is connected between the output and negative input of the amplifier 31. The resistor 33 and the feedback capacitor 32 function as a time constant for stable operation of the amplifier 31. The resistor 34 is arranged to eliminate an offset of the input voltage difference caused by the resistor 33. The amplifier 31 outputs a word line control signal WLCNT in accordance with the voltages V1 and V2.

[0067] 1, the voltage comparison circuit 30 generates a word line control signal WLCNT that lowers the high-level voltage of the word line WL when the voltage V1 is higher than the voltage V2 during a read operation. The voltage comparison circuit 30 generates a word line control signal WLCNT that raises the high-level voltage of the word line WL when the voltage V1 is lower than the voltage V2 during a read operation. Note that the circuit configuration of the voltage comparison circuit 30 in FIG. 1 may be different from the circuit configuration of the voltage comparison circuit 30 shown in FIG. 4.

[0068] The word line drive circuit 40 includes an inverter IVD that receives a word line enable signal / WLEN and outputs word line signals WL (WL0-WLn), and a transistor N1 that is diode-connected between a word line control signal line WLCNT and a word line WL. One of the source and drain of the transistor N1 and its gate are connected to the word line WL, and the other of the source and drain is connected to the output of the amplifier 31.

[0069] During a read operation, the word line drive circuit 40 receives a low-level word line enable signal / WLEN and outputs a high-level word line signal WL to the word line WL from the inverter IVD. At this time, the transistor N1 causes the high level of the word line WL to increase as the voltage value of the word line control signal WLCNT increases, and decreases as the voltage of the word line control signal WLCNT decreases. In other words, the word line drive circuit 40 can adjust the high-level voltage of the word line WL according to the voltage of the word line control signal WLCNT and supply the adjusted high-level voltage to the memory cell 50 and the monitor cell 10A.

[0070] The operation of the voltage comparator circuit 30 and the word line driver circuit 40 is the same as that described in Fig. 1. That is, the voltage comparator circuit 30 and the word line driver circuit 40 can compare the voltages V1 and V2 and adjust the high-level voltage of the word line WL so that the difference between the voltages V1 and V2 becomes small.

[0071] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, the semiconductor memory 100A can set the high-level voltage of the word line WL during a read operation to an appropriate voltage that does not invert the logic of the data held in the storage node of the memory cell 50, regardless of variations in the semiconductor manufacturing process. As a result, it is possible to suppress a decrease in the read operation margin of the semiconductor memory 100A due to variations in the semiconductor manufacturing process.

[0072] Furthermore, in this embodiment, the device configuration and layout of the monitor cell 10A are the same as those of the memory cell 50, and the device size of each transistor of the monitor cell 10A is the same as that of the corresponding transistor of the memory cell 50. This allows the electrical characteristics of the monitor cell 10A to be made equivalent to those of the memory cell 50 with high accuracy.

[0073] The element configuration of the reference cell 20A is the same as that of the memory cell 50. The element layout of the reference cell 20A is the same as that of the memory cell 50, and the element size of the reference cell 20A is the same as that of the memory cell 50. This allows the electrical characteristics of the reference cell 20A to be made equivalent to those of the memory cell 50 in a standard state with high precision, regardless of variations in the semiconductor manufacturing process. can.

[0074] Furthermore, by supplying a signal with the inverted logic of the word line enable signal / WLEN to the gate of the transfer transistor RT2 of the reference cell 20A, the transfer transistor RT2 can be turned off while the word line enable signal / WLEN is at a high level. This allows the reference cell 20A, which has electrical characteristics equivalent to those of the memory cell 50, to be set to a "1" storage state when the word line WL transitions to a high level and access to the memory cell 50 begins.

[0075] FIG. 5 is a block diagram showing an example of a semiconductor memory according to a third embodiment. The same elements as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor memory 100B shown in FIG. 5 is an SRAM, and has the form of a memory macro, a memory chip, or a package in which a memory chip is mounted. The semiconductor memory 100B has the same circuit configuration as the semiconductor memory 100A shown in FIG. 2, except that it includes a plurality of monitor cells 10A and a voltage averaging circuit 25.

[0076] For example, multiple monitor cells 10A are arranged on both sides of the memory cell array 52 and connected to word lines WL (WL0, WLn), respectively. Each monitor cell 10A has the same circuit configuration as the monitor cell 10A shown in Fig. 4, with the gate of the transfer transistor MT2 connected to a predetermined word line WL and generating a voltage V1 (V11, V12, V13, V14) at a connection node ND1.

[0077] For example, the plurality of monitor cells 10A may be formed using columns of dummy memory cells (not shown) arranged on both sides of the memory cell array 52. ​​Furthermore, the plurality of monitor cells 10A may be formed using dummy memory cells (not shown) arranged in the memory cell array 52. ​​Note that the positions and number of word lines WL to which the monitor cells 10A are connected are not limited to the example shown in FIG.

[0078] The voltage averaging circuit 25 receives the voltages V11, V12, V13, and V14 generated by the multiple monitor cells 10A. The voltage averaging circuit 25 obtains the average voltage of the voltages V11, V12, V13, and V14 and outputs the obtained average voltage as voltage AV1 to the voltage comparison circuit 30. The voltage comparison circuit 30 operates in the same manner as the voltage comparison circuit 30 in FIG. 4 except that it receives voltage AV1 instead of voltage V1.

[0079] In this embodiment, by arranging a plurality of monitor cells 10A around or inside the memory cell array 52, the average voltage of the storage nodes of a plurality of memory cells 50 in the memory cell array 52 can be monitored.

[0080] FIG. 6 is a circuit diagram showing an example of the voltage averaging circuit 25 shown in FIG. 5. The voltage averaging circuit 25 includes an amplifier 27 and resistors R11, R12, R13, and R14 connected between the positive input of the amplifier 27 and voltage lines V11, V12, V13, and V14, respectively. For example, the resistors R11, R12, R13, and R14 have the same resistance. The amplifier 27 feeds the output voltage back to its negative input, but no feedback resistor is inserted. Therefore, the gain of the amplifier 27 is 1, and the amplifier 27 can output a voltage AV1 that is an average of the voltages V11, V12, V13, and V14. To increase the number of monitor cells 10A, simply connect resistors corresponding to the number of monitor cells 10A in parallel with the voltage averaging circuit 25.

[0081] As described above, this embodiment can also achieve the same effects as the above-described embodiments. Furthermore, in this embodiment, by arranging multiple monitor cells 10A around or inside the memory cell array 52, it is possible to monitor the average voltage of the storage nodes of the multiple memory cells 50. As a result, the semiconductor memory 100B can set the high-level voltage of the word line WL during a read operation to an appropriate voltage that does not invert the logic of the data held in the storage nodes of the memory cells 50, based on the average voltage of the storage nodes of the multiple memory cells 50. As a result, it is possible to suppress, on average, a reduction in the read operation margin of the semiconductor memory 100B due to variations in the semiconductor manufacturing process across the multiple memory cells 50.

[0082] FIG. 7 shows an example of a main part of a semiconductor memory according to a fourth embodiment. The same elements as those in FIGS. 4 and 5 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The semiconductor memory 100C shown in FIG. 7 is an SRAM, and has the form of a memory macro, a memory chip, or a package on which a memory chip is mounted. The semiconductor memory 100C has the same circuit configuration as the semiconductor memory 100B shown in FIG. 5, except that it has a word line drive circuit 40C instead of the word line drive circuit 40. The monitor cell 10A, the reference cell 20A, and the voltage comparator circuit 30 have the same circuit configuration as those in FIG. 4.

[0083] 5, the voltage averaging circuit 25 outputs the average voltage of the voltages V (V11-V14) from the multiple monitor cells 10A arranged around the memory cell array 52 to the voltage comparison circuit 30 as the voltage AV1.

[0084] The word line drive circuit 40C includes a switch SW disposed between the output of an inverter IVD and the word lines WL (WL0-WLn), and an inverter IV that controls the switch SW. For example, the switch SW is a CMOS (Complementary Metal Oxide Semiconductor) transmission gate. The switch SW is turned on during a low-level period of a read enable signal / RDEN, which changes to a low level during a read operation, and connects the output of the inverter IVD to the word line WL. The switch SW is turned off during a high-level period of the read enable signal / RDEN, and disconnects the output of the inverter IVD from the word line WL.

[0085] For example, in a read operation, the read enable signal / RDEN changes to low level after a predetermined time has passed since the word line enable signal / WLEN changed to low level. In a read operation, there is a time delay between when the voltage of the word line WL starts to rise due to the word line enable signal / WLEN changing to low level and when the voltage of the word line control signal WLCNT stabilizes.

[0086] When the voltages V11-V14 from the multiple monitor cells 10A are averaged by the voltage averaging circuit 25, the voltage AV1 output by the voltage averaging circuit 25 may not stabilize until all of the voltages V11-V14 reach the voltage averaging circuit 25. If the voltage AV1 is unstable, the voltage of the word line control signal WLCNT output by the voltage comparison circuit 30 may also be unstable, which may cause the high level of the word line WL supplied to the memory cell 50 to be unstable.

[0087] Therefore, in this embodiment, the read enable signal / RDEN and the switch SW transmit a high level to the word line WL after the voltage of the word line control signal WLCNT has stabilized. This allows a stable high level of the word line WL to be supplied to the memory cell 50. This makes it possible to prevent a decrease in the read operation margin of the semiconductor memory 100C due to fluctuations in the voltage of the word line control signal WLCNT.

[0088] Note that a delay from when the word line WL is driven high until the voltage of the word line control signal WLCNT stabilizes occurs even when the single monitor cell 10A shown in Figure 4 is used. For this reason, in the semiconductor memory 100A shown in Figure 4, a word line drive circuit 40C may be provided instead of the word line drive circuit 40. In this case as well, it is possible to prevent the read operation margin of the semiconductor memory 100A from decreasing due to fluctuations in the voltage of the word line control signal WLCNT.

[0089] As described above, this embodiment can also achieve the same effects as the above-described embodiments. Furthermore, in this embodiment, the switch SW delays the supply of a high level to the word line WL to the memory cell 50 until the voltage of the word line control signal WLCNT stabilizes. This prevents the high level voltage of the word line WL from fluctuating in response to voltage fluctuations in the word line control signal WLCNT during a read operation, and prevents a decrease in the read operation margin of the semiconductor memory 100C.

[0090] The invention is not limited to the specifically disclosed embodiments, but various modifications and variations are possible without departing from the scope of the appended claims. [Explanation of symbols]

[0091] 10, 10A monitor cell 20, 20A reference cell 25 Voltage averaging circuit 27 Amplifier 30 Voltage comparison circuit 31 Amplifier 32 Feedback capacitance 33, 34 Resistance 40, 40C Word line driver circuit 50 memory cells 52 Memory Cell Array 60 Command decoder circuit 70 Row selection circuit 80 Column selection circuit 82 Sense amplifier 90 Array power supply circuit 100, 100A, 100B, 100C semiconductor memory AD Address signal AV1 Voltage BL bit line CMD Command signal D1, D2 driver transistors DQ Data terminal HV High level voltage line IV, IV1, IV2 inverters IVD inverter IVM1, IVM2 inverters IVR1, IVR2 inverter L1, L2 load transistors MD1, MD2 driver transistors ML1, ML2 load transistors MT1, MT2 transfer transistors N1 transistor ND1, ND2 connection node RD1, RD2 driver transistors / RDEN Read enable signal RL1, RL2 load transistors RT1, RT2 transfer transistors SW switch T1, T2 transfer transistors V1, V11-V14, V2 voltage VDD power line VSS ground wire WL, WL0-WLn word lines WLCNT Word line control signal / WLEN Word line enable signal

Claims

1. a memory cell including a pair of driver transistors and a pair of transfer transistors having gates connected to a word line; a monitor cell including a first transistor having the same size as the transfer transistor and a gate connected to the word line, and a second transistor having the same size as the driver transistor, the first transistor and the second transistor being connected in series between a first voltage line and a ground line; a reference cell including a third transistor having a size larger than that of the transfer transistor and a fourth transistor having a size larger than that of the driver transistor, the third transistor and the fourth transistor being connected in series between a first voltage line and a ground line; a word voltage control circuit that adjusts a high level voltage of the word line so that a difference between a first voltage of a first connection node that connects the first transistor in an on state and the second transistor in an on state and a second voltage of a second connection node that connects the third transistor in an on state and the fourth transistor in an on state becomes small during a read operation of reading data from the memory cell; A semiconductor memory having

2. The gate of the third transistor is connected to a control voltage line that changes in the same manner as the voltage change of the word line.

2. The semiconductor memory of claim 1.

3. the size of the third transistor is equal to the size of the transfer transistor; The size of the fourth transistor is equal to the size of the driver transistor.

3. The semiconductor memory according to claim 1.

4. The element configuration of the monitor cell is the same as the element configuration of the memory cell, The element size of the monitor cell is the same as the element size of the memory cell; The element configuration of the reference cell is the same as the element configuration of the memory cell, The element size of the reference cell is equal to the element size of the memory cell.

4. The semiconductor memory according to claim 1.

5. the layout of the elements of the monitor cell is the same as the layout of the elements of the memory cell; The layout of the elements of the reference cells is the same as the layout of the elements of the memory cells.

5. The semiconductor memory according to claim 4.

6. The word voltage control circuit includes: a voltage comparison circuit that generates a word line control signal for lowering a high level voltage of the word line when the first voltage is higher than the second voltage during the read operation, and generates the word line control signal for raising a high level voltage of the word line when the first voltage is lower than the second voltage; a word line drive circuit that adjusts a voltage of the word line in response to the word line control signal during the read operation; 6. The semiconductor memory according to claim 1, further comprising:

7. The word line driving circuit includes: a word line driver for driving the word line; a transistor having a gate and a drain connected to an output of the word line driver and a source receiving the word line control signal; 7. The semiconductor memory of claim 6, comprising:

8. The word line driving circuit has a switch that connects the output of the word line driver to the word line after the operation of the voltage comparison circuit becomes stable during the read operation.

8. The semiconductor memory according to claim 7.

9. a plurality of the memory cells connected to a plurality of the word lines, respectively; a plurality of monitor cells each having a gate of the first transistor connected to a predetermined number (two or more) of the word lines; a voltage averaging circuit that obtains an average of the first voltages generated from the first connection nodes of the plurality of monitor cells; The word line voltage control circuit receives the average voltage acquired by the voltage averaging circuit instead of the voltage of the first connection node, and adjusts the high level voltage of the word line so that the difference between the average voltage and the second voltage becomes small.

8. The semiconductor memory according to claim 1.

10. the word voltage control circuit has a switch for connecting an output node of the high level voltage adjusted according to the difference between the first voltage and the second voltage to the word line; The switch is turned on after the voltage averaging circuit acquires the average voltage in the read operation.

10. The semiconductor memory of claim 9.

11. 1. A method for operating a semiconductor memory having: a memory cell including a pair of driver transistors and a pair of transfer transistors having gates connected to a word line; a monitor cell including a first transistor having the same size as the transfer transistors and having a gate connected to the word line, and a second transistor having the same size as the driver transistors, the first transistor and the second transistor being connected in series between a first voltage line and a ground line; and a reference cell including a third transistor larger in size than the transfer transistors and a fourth transistor larger in size than the driver transistors, the third transistor and the fourth transistor being connected in series between a first voltage line and a ground line, During a read operation for reading data from the memory cell, the high level voltage of the word line is adjusted so that a difference between a first voltage of a first connection node connecting the first transistor in an on state and the second transistor in an on state and a second voltage of a second connection node connecting the third transistor in an on state and the fourth transistor in an on state becomes small. How semiconductor memories operate.

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