Semiconductor integrated circuit device and electronic device

Abstract

To provide a semiconductor integrated circuit device capable of simplifying a circuit configuration and suppressing power consumption.SOLUTION: A semiconductor integrated circuit device includes: a reference cell having the same layer structures as a plurality of memory cells; a data reading circuit for reading stored data by generating a determination current based on a current flowing to the reference cell to which driving potential is applied, and comparing a current flowing to a memory cell to be read with the determination current; a driving current generation circuit that generates a driving potential higher than a power potential at a high potential side supplied to the data reading circuit in a verify mode; a current generation circuit for level detection for generating a current for level detection corresponding to a reading current of the memory cell to be read based on the driving potential; and a boost stop control circuit that controls stopping of a boost operation of the drive potential generation circuit based on the current for level detection; wherein the driving potential generation circuit is a bootstrap circuit.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor integrated circuit device and an electronic device. [Background technology]

[0002] Conventionally, electrically writable non-volatile memory (EEPROM) Known examples of such non-volatile memory include the Erasable Programmable Read Only Memory (EPROM). In the non-volatile memory described in Patent Document 1, when a word line voltage is generated by a constant voltage circuit, the reference voltage is made to have a temperature dependency that is the opposite to the temperature dependency of the memory cell current, thereby adjusting the word line drive capability according to temperature and suppressing a decrease in the read margin. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-217287 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the nonvolatile memory described in Patent Document 1 has an internal regulator and timing generation circuit for adjusting the driving capability of the word lines, which makes the circuit configuration complicated and may result in high power consumption. [Means for solving the problem]

[0005] One aspect of the semiconductor integrated circuit device according to the present invention is A plurality of non-volatile memory cells in which data can be electrically written and erased; a reference cell having the same layer structure as each of the transistors of the plurality of memory cells; a data read circuit that generates a determination current based on a current flowing through the reference cell to which a driving potential is applied, and compares a current flowing through a memory cell to be read out among the plurality of memory cells to which the driving potential is applied with the determination current, thereby reading out data stored in the memory cell to be read out; a drive potential generating circuit that generates the drive potential higher than a high potential side power supply potential supplied to the data read circuit in a verify mode of the memory cells; a level detection current generating circuit for generating a level detection current corresponding to a read current of the memory cell to be read based on the drive potential; a boost stop control circuit that performs stop control of the boost operation of the drive potential generating circuit based on the level detection current, the level detection current generating circuit and the drive potential generating circuit operate based on the drive potential; The drive potential generating circuit is a bootstrap circuit.

[0006] One aspect of the electronic device according to the present invention is The present invention includes one aspect of the semiconductor integrated circuit device. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile memory. [Diagram 2] 2 is a circuit diagram showing a configuration example of a memory cell array, a word line driver circuit, and a source line driver circuit in FIG. [Diagram 3] FIG. 1 is a diagram showing a schematic structure of a memory cell. [Figure 4] 2 is a diagram showing an example of the configuration of a word line boosting circuit, a data read circuit, and a reference current generating circuit in FIG. 1; [Diagram 5] FIG. 13 is a diagram showing a cell current and a reference current. [Figure 6] 4 is a diagram showing a configuration example of a word line boosting circuit, a data read circuit, and a reference current generating circuit of a comparative example. [Figure 7]FIG. 13 is a diagram showing a cell current and a reference current in a comparative example. [Figure 8] FIG. 13 is a diagram showing an example of the configuration of a word line boosting circuit, a data read circuit, and a reference current generating circuit according to a second embodiment. [Figure 9] FIG. 13 is a diagram showing an example of the configuration of a word line boosting circuit, a data read circuit, and a reference current generating circuit according to a third embodiment. [Figure 10] FIG. 1 is a diagram showing a schematic configuration of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. First embodiment 1-1.Non-volatile memory As shown in Fig. 10 described later, the semiconductor integrated circuit device 1 of this embodiment includes a nonvolatile memory 2. The semiconductor integrated circuit device 1 may incorporate only an electrically rewritable nonvolatile memory 2 such as a flash memory or an EEPROM, or may incorporate a circuit block having a predetermined function or a functional circuit such as a CPU in addition to the nonvolatile memory 2. EEPROM is an abbreviation for Electrically Erasable Programmable Read Only Memory, and CPU is an abbreviation for Central Processing Unit. In the following, a flash memory will be described as an example of the nonvolatile memory 2.

[0010] Fig. 1 is a block diagram showing a schematic configuration of a nonvolatile memory 2. As shown in Fig. 1, the nonvolatile memory 2 includes a memory cell array 10, a power supply circuit 20, a word line boost circuit 30, a word line drive circuit 40, a source line drive circuit 50, a switch circuit 60, and a memory control circuit 70. The memory control circuit 70 controls the power supply circuit 20, the word line boost circuit 30, the word line drive circuit 40, the source line drive circuit 50, and the switch circuit 60 so as to cause a plurality of memory cells MC included in the memory cell array 10 to perform an erase operation, a write operation, or a read operation.

[0011] The memory cells MC of the memory cell array 10 are arranged in a matrix of m rows and n columns, where m and n are each an integer equal to or greater than 2. For example, the memory cell array 10 includes 2048×1024 memory cells arranged in a matrix of 2048 rows and 1024 columns, and 128 pieces of 8-bit data are stored by the 1024 memory cells MC arranged in one row.

[0012] The memory cell array 10 also includes a number of word lines WL0, WL1,...WLm, a number of source lines SL0, SL1,...SLm, and a number of bit lines BL0, BL1,...BLn. Each of the word lines is connected to a number of memory cells MC arranged in a respective row. Each of the source lines is connected to a number of memory cells MC arranged in a respective row. Each of the bit lines is connected to a number of memory cells MC arranged in a respective column.

[0013] The power supply circuit 20 includes, for example, a reference power supply potential VSS and a data erase / write potential VSS. The high power supply potential VPP for the logic circuit and the logic power supply potential VDD for the logic circuit are supplied from the outside. Alternatively, the power supply circuit 20 may generate another power supply potential by boosting or lowering one of a plurality of power supply potentials supplied from the outside.

[0014] The reference power supply potential VSS is a reference potential that serves as a reference relative to other potentials, and the following description will be given of the case where the reference power supply potential VSS is the ground potential. The high power supply potential VPP is a predetermined potential higher than the reference power supply potential VSS, for example, about 5V to 10V. The logic power supply potential VDD is a potential higher than the reference power supply potential VSS and lower than the high power supply potential VPP, for example, about 1.2V to 1.8V.

[0015] The power supply circuit 20 supplies a logic power supply potential VDD to the memory control circuit 70, and is controlled by the memory control circuit 70 to supply, as necessary, a high power supply potential VPP and a logic power supply potential VDD to each section of the nonvolatile memory 2. In Fig. 1, the power supply potential supplied from the power supply circuit 20 to the word line boosting circuit 30 is shown as a word line power supply potential VWL, and the power supply potential supplied from the power supply circuit 20 to the source line driving circuit 50 is shown as a source line power supply potential VSL.

[0016] For example, in an erase mode in which a memory cell is put into an erased state, the power supply circuit 20 supplies a high power supply potential VPP as a word line power supply potential VWL and a source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 supplies the high power supply potential VPP to the word line drive circuit 40 as a word line power supply potential INT_VWL.

[0017] In a write mode in which data is written to a memory cell, the power supply circuit 20 supplies a high power supply potential VPP as a word line power supply potential VWL and a source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 supplies the high power supply potential VPP to the word line drive circuit 40 as a word line power supply potential INT_VWL.

[0018] In a read mode in which data is read from a memory cell, the power supply circuit 20 supplies a logic power supply potential VDD as a word line power supply potential VWL and a source line power supply potential VSL to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 generates a drive potential V1 that is higher than the logic power supply potential VDD, which is a high-potential power supply potential supplied to the data read circuit 71, and supplies the drive potential V1 to the word line drive circuit 40 as the word line power supply potential INT_VWL.

[0019] In a verify mode of the memory cell, the power supply circuit 20 supplies a logic power supply potential VDD to the word line boost circuit 30 and the source line drive circuit 50. The word line boost circuit 30 generates a drive potential V1 that is higher than the logic power supply potential VDD, which is a high-potential power supply potential supplied to the data read circuit 71, and supplies the drive potential V1 to the word line drive circuit 40 as the word line power supply potential INT_VWL.

[0020] The word line driving circuit 40 drives a plurality of word lines WL0, WL1, ..., WLm connected to a memory cell selected by the memory control circuit 70. The source line driving circuit 50 drives a plurality of source lines SL1, SL2, ..., SLm connected to a memory cell selected by the memory control circuit 70.

[0021] The switch circuit 60 includes, for example, a plurality of transistors respectively connected to the paths of the plurality of bit lines BL0, BL1, . . . , BLn, and these transistors are turned on or off under the control of the memory control circuit 70. The memory control circuit 70 is connectable via the switch circuit 60 to memory cells connected to the plurality of bit lines BL0, BL1, . . . , BLn.

[0022] The memory control circuit 70 is composed of, for example, logic circuits including combinational circuits and sequential circuits, analog circuits, etc., and includes a reference cell RC1, a data read circuit 71, a reference current generation circuit 72, and a verify circuit 73. The memory control circuit 70 is supplied with a chip select signal CS, a mode select signal MS, an operation clock signal CK, and an address signal ADR.

[0023] When the nonvolatile memory 2 is selected by the chip select signal CS, the memory control circuit 70 sets the nonvolatile memory 2 to an erase mode, a write mode, a read mode, or a memory cell verify mode in accordance with the mode select signal MS.

[0024] In the write mode, read mode, and memory cell verify mode, the memory control circuit 70 controls each part of the nonvolatile memory 2 to access a memory cell designated by the address signal ADR in synchronization with the operating clock signal CK.

[0025] In the write mode, the memory control circuit 70 inputs write data and controls each unit of the nonvolatile memory 2 to write the data to a memory cell specified by the address signal ADR. In the read mode and memory cell verify mode, the memory control circuit 70 controls each unit of the nonvolatile memory 2 to read data from a memory cell specified by the address signal ADR, and outputs the read data.

[0026] For example, in a read mode and a memory cell verify mode, the memory control circuit 70 turns on a transistor of the switch circuit 60 connected to a memory cell specified by an address signal ADR, and reads data based on a read current I1 flowing through that memory cell.

[0027] At this time, the data read circuit 71 generates a decision current I0 based on the current flowing through the reference cell RC1. The data read circuit 71 also compares the current flowing through a memory cell designated by the address signal ADR with the decision current I0 to determine whether the data stored in the designated memory cell is "0" or "1."

[0028] 1-2.Memory cell array Fig. 2 is a circuit diagram showing a configuration example of the memory cell array 10, the word line driving circuit 40, and the source line driving circuit 50 of Fig. 1. Fig. 3 is a diagram showing a schematic structure of one memory cell of the memory cell array 10. The schematic configuration of the memory cell array 10 will be described with reference to Figs. 2 and 3.

[0029] As shown in Fig. 2, the memory cell array 10 includes a plurality of memory cells MC. Also, as shown in Fig. 3, the memory cell MC includes an N-channel MOS transistor having a control gate 412a, a floating gate 412c, oxide insulating films 412b and 412d, a source 411, and a drain 413. The transistor of the memory cell MC stores one bit of data according to the charge stored in the floating gate 412c.

[0030] 3, the memory cell MC includes electrodes 401, 402, and 403 electrically connected to a source 411, a gate 412, and a drain 413. Potentials such as a reference power supply potential VSS, a drive potential V1, a logic power supply potential VDD, and a high power supply potential VPP are supplied to the electrodes 401, 402, and 403, and the transistors of the memory cell MC execute various modes such as a write mode and an erase mode. Data can be electrically written and erased into the memory cells MC.

[0031] The gate of the reference cell RC1 may include a control gate 412a, a floating gate 412c, and oxide insulating films 412b and 412d. In other words, the reference cell RC1 may have the same layer structure as each of the transistors included in the multiple memory cells MC of the memory cell array 10.

[0032] 2, each of the word lines WL0, WL1, ... is connected to the control gate 412a of the transistors of the memory cells MC arranged in each row. Each of the source lines SL0, SL1, ... is connected to the sources 411 of the transistors of the memory cells MC arranged in each row. Also, each of the bit lines BL0, BL1, ... is connected to the drains 413 of the transistors of the memory cells MC arranged in each column.

[0033] The word line drive circuit 40 includes a plurality of word line drivers 41 that drive the control gates 412a of the transistors of the memory cells MC connected to the word lines WL0, WL1, . . ., a plurality of transistors 42, and an inverter 43 that supplies a high potential power supply to the word line drivers 41. Each word line driver 41 is composed of, for example, a level shifter, a buffer circuit, an inverter, or the like. A word line power supply potential INT_VWL is supplied to each word line driver 41 from the inverter 43.

[0034] High active row selection signals SW0, SW1, ... that are activated to a high level when selecting one or more rows of memory cells MC from among the memory cells MC that constitute the memory cell array 10 are input from the memory control circuit 70 to the input terminals of the multiple word line drivers 41. When the row selection signal is active, the word line driver 41 outputs the word line power supply potential INT_VWL to the word lines, and when the row selection signal is non-active, the word line driver 41 outputs the reference power supply potential VSS to the word lines.

[0035] The source line driving circuit 50 includes a source line driver 51, a plurality of transmission gates TG, and a plurality of inverters 52 to drive the sources 411 of the transistors of the memory cells MC connected to the source lines SL0, SL1, . The source line driver 51 is composed of, for example, a level shifter, a buffer circuit, an inverter, or the like. The plurality of transmission gates TG are connected between the output terminal of the source line driver 51 and the source lines SL0, SL1, .

[0036] A source line power supply potential VSL is supplied to the source line driver 51 from the power supply circuit 20. A high active source line drive signal SSL that is activated to a high level when a high power supply potential is applied to the source line is input to an input terminal of the source line driver 51 from the memory control circuit 70. The source line driver 51 outputs the source line power supply potential VSL when the source line drive signal SSL is active, and outputs the reference power supply potential VSS when the source line drive signal SSL is non-active.

[0037] Each transmission gate TG is composed of an N-channel MOS transistor and a P-channel MOS transistor, and functions as a switch circuit that opens and closes the connection between the output terminal of the source line driver 51 and the source line. In the transmission gate TG, the gate of the N-channel MOS transistor is connected to the output terminal of the word line driver 41, and the gate of the P-channel MOS transistor is connected to the output terminal of the inverter 52.

[0038] The inverter 52 receives the word line power supply potential INT_VWL from the word line boost circuit 30. The row selection signals SW0 to SWm are input to the input terminals of the inverter 52. The inverter 52 inverts the row selection signals SW0 to SWm, and applies the inverted signals to the gates of the P-channel MOS transistors of the transmission gates TG.

[0039] The switch circuit 60 includes N-channel MOS transistors Q0, Q1... connected between the drains 413 of the transistors of the memory cells MC connected to the bit lines BL0, BL1... and the memory control circuit 70. High-active column selection signals SB0, SB1... that are activated to a high level when selecting one or more columns of memory cells from among the multiple memory cells that make up the memory cell array 10 are applied to the gates of the N-channel MOS transistors Q0, Q1... from the memory control circuit 70.

[0040] In the write mode, the memory control circuit 70 activates the corresponding row selection signal and column selection signal to select the word line and bit line connected to the memory cell MC designated by the address signal ADR, deactivates the other row selection signals and column selection signals, and activates the source line drive signal SSL. In the following, as an example, a case where the word line WL0 and bit line BL0 are selected will be described.

[0041] The inverter 43 and the inverter 52 are supplied with the high power supply potential VPP as the word line power supply potential INT_VWL, and the source line driver 51 is supplied with the high power supply potential VPP as the source line power supply potential VSL. The high power supply potential VPP is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which a non-active erase mode signal ER is input. The word line driver 41 to which an active row selection signal SW0 is input outputs the high power supply potential VPP to the word line WL0. Moreover, the source line driver 51 to which an active source line drive signal SSL is input outputs the high power supply potential VPP.

[0042] The inverter 52, to which the active row selection signal SW0 is input, inverts the high power supply potential VPP and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG, thereby turning on the transmission gate TG and applying the high power supply potential VPP output from the source line driver 51 to the source line SL0.

[0043] Furthermore, the N-channel MOS transistor Q0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the reference power supply potential VSS to the bit line BL0. In this manner, the memory control circuit 70 controls the word line drive circuit 40 and the source line drive circuit 50 to apply the high power supply potential VPP to the control gate 412a and source 411 of the transistor of the memory cell MC designated by the address signal ADR, and applies the reference power supply potential VSS to the drain.

[0044] As a result, a current flows from the source 411 to the drain 413 of the transistor of the memory cell MC designated by the address signal ADR. Hot carriers generated by the current are injected into the floating gate 412c, and negative charges are accumulated in the floating gate 412c, increasing the threshold voltage of the transistor of the memory cell MC. In this embodiment, the hot carriers are electrons.

[0045] On the other hand, the word line driver 41 to which the non-active row selection signals SW1 to SWm are input outputs the reference power supply potential VSS to the word lines WL1 to WLm. The inverter 52 to which the non-active row selection signals SW1 to SWm are input inverts the reference power supply potential VSS and outputs the high power supply potential VPP to the P-channel MOS transistors of the transmission gates TG. Therefore, the transmission gates TG connected to the word lines WL1 to WLm are turned off. Also, the N-channel MOS transistors Q1 to Qn of the switch circuit 60 to which the non-active column selection signals SB1 to SBn are input are turned off. As a result, no current flows between the source and drain of the transistor of the memory cell MC not specified by the address signal ADR, so the threshold voltage of the transistor does not change.

[0046] In the erase mode, in order to select a word line connected to a memory cell MC designated by an address signal ADR, the memory control circuit 70 activates the corresponding row selection signal, deactivates the other row selection signals, deactivates the column selection signals SB0 to SBn, and activates the source line drive signal SSL. In the following, a case where the word line WL0 is selected will be described as an example.

[0047] The inverter 43 and the inverter 52 are supplied with the high power supply potential VPP as the word line power supply potential INT_VWL, and the source line driver 51 is supplied with the high power supply potential VPP as the source line power supply potential VSL. The inverter 43 to which an active erase mode signal ER is input applies the reference power supply potential VSS to the high potential side power supply terminal of the word line driver 41. The word line driver 41 to which an active row selection signal SW0 is input is not activated, but the transistor 42 to which the active erase mode signal ER is applied at its gate applies the reference power supply potential VSS to the word line WL0. The source line driver 51 to which an active source line drive signal SSL is input outputs the high power supply potential VPP.

[0048] The inverter 52, to which the active row selection signal SW0 is input, inverts the high power supply potential VPP and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG, thereby turning on the P-channel MOS transistor of the transmission gate TG, and the high power supply potential VPP output from the source line driver 51 is applied to the source line SL0.

[0049] Also, the N-channel MOS transistors Q0 to Qn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. In this manner, the memory control circuit 70 turns off the N-channel MOS transistors Q0 to Qn of the switch circuit 60 to open the drain 413 of the transistor of the memory cell MC, controls the word line drive circuit 40 to apply the reference power supply potential VSS to the control gate 412a, and controls the source line drive circuit 50 to apply the high power supply potential VPP to the source. As a result, when negative charges are accumulated in the floating gate 412c of the transistor of the memory cell MC, the negative charges accumulated in the floating gate 412c are released to the source 411, and the threshold voltage of the transistor is reduced.

[0050] On the other hand, the inverter 52 to which the inactive row selection signals SW1 to SWm are input inverts the reference power supply potential VSS and applies the high power supply potential VPP to the gates of the P-channel MOS transistors of the transmission gates TG. Therefore, the transmission gates TG connected to the word lines WL1 to WLm are turned off. As a result, the negative charges stored in the floating gates 412c of the transistors of the memory cells MC not specified by the address signal ADR are not discharged, and the threshold voltages of the transistors do not change.

[0051] In the read mode and memory cell verify mode, the memory control circuit 70 activates the corresponding row selection signal and column selection signal to select the word line and bit line connected to the memory cell MC designated by the address signal ADR, and deactivates the other row selection signals and column selection signals, while keeping the source line drive signal SS L is made inactive. In the following, as an example, a case where the word line WL0 and the bit line BL0 are selected will be described.

[0052] A drive potential V1 is supplied to the inverter 43 and the inverter 52 as the word line power supply potential INT_VWL, and a logic power supply potential VDD is supplied to the source line driver 51 as the source line power supply potential VSL. The drive potential V1 is supplied to the high potential power supply terminal of the word line driver 41 by the inverter 43 to which a non-active erase mode signal ER is input. The word line driver 41 to which an active row selection signal SW0 is input outputs the drive potential V1 to the word line WL0. Moreover, the source line driver 51 to which a non-active source line drive signal SSL is input outputs the reference power supply potential VSS.

[0053] The drive potential V1 output from the word line driver 41 is also applied to the gate of the N-channel MOS transistor of the transmission gate TG connected to the word line WL0, thereby turning on the N-channel MOS transistor of the transmission gate TG, and the reference power supply potential VSS output from the source line driver 51 is applied to the source line SL0.

[0054] Furthermore, the N-channel MOS transistor Q0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the logic power supply potential VDD to the bit line BL0. In this manner, the memory control circuit 70 controls the word line drive circuit 40 to apply the drive potential V1 to the control gate 412a of the transistor of the memory cell MC designated by the address signal ADR, and controls the source line drive circuit 50 to apply the reference power supply potential VSS to the source, thereby turning on the N-channel MOS transistor Q0 of the switch circuit 60 and applying the logic power supply potential VDD to the drain.

[0055] As a result, in the memory cell MC designated by the address signal ADR, a drain current flows from the drain 413 to the source 411 of the transistor of the memory cell MC. Since the magnitude of the drain current varies depending on the amount of negative charge stored in the floating gate 412c, the memory control circuit 70 can read data from the memory cell MC based on the magnitude of the drain current.

[0056] 1-3. Reading data Fig. 4 is a diagram showing an example of the configuration of the word line boost circuit 30, the data read circuit 71, and the reference current generating circuit 72 shown in Fig. 1. As shown in Fig. 4, in this embodiment, the word line boost circuit 30 includes a drive potential generating circuit 31, a boost stop control circuit 32, and a level detection current generating circuit 33.

[0057] The data read circuit 71 generates a decision current I0 based on the current flowing through a reference cell RC1 to which a driving potential V1 has been applied, and reads out the data stored in the memory cell MC1 to be read by comparing the read current I1 flowing through the memory cell MC1 to which the driving potential V1 has been applied, among the multiple memory cells MC, with the decision current I0.

[0058] In a verify mode for a plurality of memory cells MC, the drive potential generating circuit 31 generates the drive potential V1 higher than the logic power supply potential VDD, which is a high-potential power supply potential supplied to the data read circuit 71. The drive potential generating circuit 31 is a so-called bootstrap circuit.

[0059] In the verify mode, the read signal RD goes from low to high. Since the transistor QP30 of the dynamic potential generating circuit 31 is turned off, the driving potential V1 supplied from the driving potential generating circuit 31 to the level detection current generating circuit 33, the data read circuit 71 and the reference current generating circuit 72 is the word line power supply potential INT_VWL.

[0060] The reference current generating circuit 72 is supplied with the driving potential V1 from the driving potential generating circuit 31, and the reference cell RC1 and the transistor QN2 are turned on.

[0061] The inverter 101 of the reference current generating circuit 72 inverts the read signal RD and outputs a low level. As a result, the transistor QP1 turns on. Also, because the read signal RD is at a high level, the transistors QN1 and QN5 turn on. Because the transistors QN1 and QN2 and the reference cell RC1 are on, a low level signal is input to the gates of the transistors QP2, QP7 to QP10, turning them on.

[0062] The reference current I2 is generated when at least one of the mirror ratio adjustment signals XSA0 to XSA3 input to the gates of the transistors QP3 to QP6 of the reference current generating circuit 72 is at a low level. That is, the reference current I2 is generated by turning on at least one of the transistors QP3 to QP6. For example, when the transistor QP4 is on, the reference current I2 flows from the logic power supply potential VDD through the transistors QP4, QP8, QN3, and QN5.

[0063] Furthermore, the reference current I2 is adjustable. By setting the mirror ratio adjustment signals XSA0 to XSA3 to a high level or a low level, respectively, it is possible to adjust the number of transistors QP3 to QP6 that are turned on. Therefore, the reference current I2 flowing through the transistor QN5 of the reference current generation circuit 72 is adjustable.

[0064] For example, when the current capabilities of the transistors QP3 to QP6 of the reference current generating circuit 72 are equal, the mirror ratio can be adjusted to four different values ​​in proportion to the number of transistors that are turned on. When the current capabilities of the transistors QP3 to QP6 of the reference current generating circuit 72 are different from each other, the mirror ratio can be adjusted to 15 different values, so that the reference current generating circuit 72 can generate 15 types of reference current I2.

[0065] In the data read circuit 71, since the read signal RD is at a high level, the transistors QN6, QP11, and QP12 are turned on. When the reference current I2 is generated, the transistor QN4 is turned on together with the transistor QN3 of the reference current generating circuit 72. Since the transistors QN4 and QN6 are turned on, a low-level signal is input to the gates of the transistors QP13 and QP14, turning them on.

[0066] Since the memory cell MC1 to be read is the target to be read, a high-level signal is input as the address signal ADR supplied to the data read circuit 71, and the transistor QN7 is turned on. In addition, the data read circuit 71 is supplied with a drive potential V1 from the drive potential generating circuit 31, and the memory cell MC1 to be read and the transistor QN8 are turned on, so that a read current I1 flows through the memory cell MC1 to be read.

[0067] The reference current I2 flowing through the transistor QN5 of the reference current generation circuit 72 is mirrored to the transistor QN6 of the data read circuit 71 to generate a decision current I0. The data read circuit 71 is a so-called sense amplifier, which amplifies the difference between the decision current I0 and the read current I1 and outputs a read signal OUT via an inverter 102.

[0068] As described above, the reference current I2 can be adjusted according to the mirror ratio adjustment signals XSA0 to XSA3, and therefore the decision current I0 generated by mirroring the reference current I2 can also be adjusted. By adjusting the decision current I0 according to the read current I1 flowing through the memory cell MC1 to be read, the data stored in the memory cell MC1 to be read can be read with high accuracy.

[0069] 1-4.Boost stop control The level detection current generating circuit 33 generates a level detection current I3 corresponding to the read current I1 of the memory cell MC1 to be read, based on the drive potential V1.

[0070] The boost stop control circuit 32 controls the stop of the boost operation of the drive potential generating circuit 31 based on the level detection current I3.

[0071] The transistors QP31 and QN31 of the drive potential generation circuit 31 form a CMOS inverter, and are supplied with a logic power supply potential VDD, which is the high-side power supply potential supplied to the data read circuit 71. This CMOS inverter functions as a coupling capacitance drive circuit that drives the coupling capacitance C0 in the subsequent stage. When the read signal RD is at a low level, the transistor QP31 of the drive potential generation circuit 31 is turned off and the transistor QN31 is turned on. The coupling capacitance C0 is supplied with the reference power supply potential VSS and charged.

[0072] Also, when the read signal RD is at a low level, the transistor QP30 is turned on, so that the drive potential V1 that the drive potential generation circuit 31 supplies to the level detection current generation circuit 33, the data read circuit 71, and the reference current generation circuit 72 becomes the word line power supply potential VWL.

[0073] When the read signal RD switches from low to high, the transistor QP30 turns off, and the drive potential V1 supplied to the memory cell MC1 to be read becomes the word line power supply potential INT_VWL. The transistor QP31 turns on and the transistor QN31 turns off, so that the logic power supply potential VDD is supplied to the coupling capacitance C0. The word line power supply potential INT_VWL starts to rise due to the charge stored in the coupling capacitance C0. In other words, the drive potential generating circuit 31 starts a boost operation.

[0074] The voltage supplied to the CMOS inverter composed of transistors QP31 and QN31 included in the coupling capacitance drive circuit that drives the coupling capacitance C0 is the logic power supply potential VDD. This logic power supply potential VDD is lower than the word line power supply potential INT_VWL, which is the word line voltage of the memory cell MC1 to be read. In addition, the transistors QP31 and QN31 that constitute the CMOS inverter are transistors with a lower breakdown voltage than the transistor QP30 to which the word line power supply potential VWL is supplied.

[0075] In the read mode performed in the low voltage region, the driving time of the transistors QP31 and QN31 constituting the CMOS inverter is shortened, and the driving potential generating circuit 31 can sufficiently boost the driving potential V1 in a short time. Moreover, by using low-voltage transistors for the transistors QP31 and QN31, the power consumption of the CMOS inverter can be reduced. Moreover, by using low-voltage transistors for the transistors QP31 and QN31, the CMOS inverter can be made smaller, and the driving potential generating circuit 31 can be made smaller.

[0076] In the level detection current generating circuit 33, when the word line power supply potential INT_VWL starts to rise and exceeds a predetermined voltage, the transistors QP21 and QP22 are activated. The two-stage CMOS inverter is activated. Because a high-level read signal RD is input to it, the output signal is high. This high-level output signal is input to the gate and drain of the voltage detection transistor A in the subsequent stage. The gate and drain of the voltage detection transistor A are electrically connected.

[0077] A high-level signal is input to the gate and drain of the voltage detection transistor A of the level detection current generating circuit 33, turning it on. As a result, a high-level signal is input to the gate of the voltage detection transistor B, turning the voltage detection transistor B on.

[0078] On the other hand, inverter 203 of boost stop control circuit 32 inverts the high-level read signal RD, so a low-level signal is input to inverter 204 and the gate of transistor QN23 of level detection current generation circuit 33. As a result, transistor QN23 is turned off and the output signal of inverter 204 becomes high level. The output signal of inverter 204 is input to the gates of transistor QP24 of boost stop control circuit 32 and transistor QN24 of level detection current generation circuit 33, so transistor QP24 is turned off and transistor QN24 is turned on.

[0079] A level detection current I3 flows through the voltage detection transistor B and the transistor QN24, and the potential of the node DET changes from high to low.

[0080] That is, when the read signal RD switches from high to low and the drive potential V1 rises to a predetermined potential, the level detection current generating circuit 33 generates the level detection current I3. As a result, the potential of the node DET becomes low.

[0081] Furthermore, the low-level output signal of the inverter 203 of the boost stop control circuit 32 is input to the NOR 205. Since the potential of the node DET is low, both of the two input signals of the NOR 205 are low. Therefore, the output signal of the NOR 205 is high. Therefore, the transistor QN25 of the boost stop control circuit 32 is turned on, and the output signal of the inverter 206 is low. This low-level output signal is input to the NAND 301 of the drive potential generation circuit 31.

[0082] The high-level read signal RD is inverted twice by the inverters 201 and 202 of the boost stop control circuit 32, and a high-level signal is output. As a result, a high-level signal is input to the NAND 301 and the inverter 302 of the drive potential generation circuit 31.

[0083] Since the high-level output signal of the inverter 202 and the low-level output signal of the inverter 206 are input to the NAND 301 of the driving potential generating circuit 31, the output signal of the NAND 301 becomes high level. Therefore, the transistor QP31 is turned off. Therefore, the supply of the logic power supply potential VDD to the coupling capacitance C0 is stopped, and the boosting operation of the driving potential generating circuit 31 is stopped.

[0084] Moreover, the inverter 302 in the drive potential generating circuit 31 receives the high-level output signal of the inverter 202, and therefore the output signal of the inverter 302 becomes low level. As a result, the transistor QN31 is turned off.

[0085] When the read signal RD switches from low to high, the drive potential generating circuit 31 starts boosting the drive potential V1. When the drive potential V1 is boosted to a predetermined boost stop level, the transistors QP21 and QP22 of the level detection current generating circuit 33 are activated. This turns on the voltage detection transistors A and B, and the level detection current generating circuit 33 generates a level detection current I3. Based on this level detection current I3, The potential of the node DET switches from high to low, and the boost stop control circuit 32 controls the drive potential generating circuit 31 to stop the boost operation.

[0086] In this embodiment, it is possible to adjust the boost stop level of the drive potential V1 by adjusting the thresholds of the voltage detection transistors A and B. In addition, by adjusting the boost level and not boosting the drive potential V1 to a desired potential or higher, it is possible to reduce the power consumption of the drive potential generation circuit 31.

[0087] In addition, since the voltage detection transistors A and B operate near the threshold voltage, they can be provided with temperature characteristics in which the driving ability increases at high temperatures and decreases at low temperatures. This makes it possible to suppress a decrease in the read margin due to temperature changes. In addition, since the boosting operation of the word line boosting circuit 30 is a temporary boosting operation by the bootstrap circuit, no external power supply or external device such as a regulator is required, and the configuration can be simplified.

[0088] 1-5. Cell current and reference current 5 is a diagram showing the cell current and the reference current during programming and erasing in this embodiment. Programming indicates the write mode, erasing indicates the erase mode, and the cell current indicates the read current I1 flowing through the memory cell MC1 to be read in the write mode and erase mode. The reference current indicates the determination current I0 in this embodiment.

[0089] In this embodiment, the current capabilities of the transistors QP3 to QP6 are different from each other. In this case, as described above, the reference current generating circuit 72 can generate 15 types of reference currents I2, and therefore the data reading circuit 71 can generate 15 types of decision currents I0. In Fig. 5, two types of decision currents I0 out of the 15 types of decision currents I0 are illustrated by dashed lines.

[0090] During programming, the temperature characteristics of the cell current and the reference current are negative from approximately -40° C. to approximately 130° C. In addition, the reference current maintains a value approximately 3 μA lower than the cell current, and the marginal fluctuation of the cell current and the reference current due to temperature changes is small.

[0091] Similarly, during erasing, the temperature characteristics of the cell current and the reference current are negative from approximately -40° C. to approximately 130° C. The reference current maintains a value approximately 3 μA higher than the cell current, and the marginal fluctuation of the cell current and the reference current due to temperature change is small.

[0092] As described above, by adjusting the mirror ratio adjustment signals XSA0 to XSA3, the reference current generation circuit 72 can generate, for example, 15 types of reference currents I2. Therefore, the data read circuit 71 can generate 15 types of determination currents I0. This allows the reference current to be finely adjusted in accordance with the cell current, making it possible to perform verify with high accuracy. Furthermore, in this embodiment, in both the program and erase cases, the fluctuation in margin between the cell current and the reference current due to temperature changes can be reduced.

[0093] 1-6.Comparative Example FIG. 6 is a diagram showing an example of the configuration of the word line boost circuit 30, data read circuit 71, and reference current generation circuit 72 of the comparative example, and FIG. 7 is a diagram showing the cell current and reference current during programming and erasing of the comparative example. As shown in FIG. 6, the comparative example illustrates a case in which, compared to this embodiment, transistors QP5, QP6 and QP9, QP10 are omitted, and the current capabilities of transistors QP3 and QP4 are equal. Furthermore, transistors QP3 and QP4 are controlled by mirror ratio adjustment signals XSA0 and XSA1. In this case, the reference current generation circuit 72 is capable of generating two types of reference current I2, Therefore, the data read circuit 71 can generate two types of decision current I0. In Fig. 7, the two types of decision current I0 are illustrated by dashed lines.

[0094] During erasing, the temperature characteristics of the cell current and the reference current are negative from approximately -40°C to approximately 130°C. Also, the margin between the cell current and the reference current is approximately 10μA at approximately -40°C and approximately 5μA at approximately 130°C. The margin becomes smaller as the temperature rises.

[0095] In the case of the erase in the comparative example, the margin between the cell current and the reference current is larger than that in the present embodiment, so there is a possibility that the accuracy of the verify may be reduced. Also, even if the margin between the cell current and the reference current is set to about 3 μA at about −40° C. as in the present embodiment, at about 130° C., the reference current may become larger than the cell current, and verify may not be performed correctly.

[0096] On the other hand, during programming, the temperature characteristics of the cell current and the reference current are negative from about -40°C to about 130°C. Also, the margin between the cell current and the reference current is about 4μA at about -40°C and about 2μA at about 130°C. The margin becomes smaller as the temperature increases.

[0097] In the case of the comparative example program, unlike the present embodiment, the cell current is larger than the reference current, so there is a possibility that the program verification cannot be performed correctly. If the verification is performed using the reference current of the comparative example program, the erase cell current and the program cell current are both larger than the program reference current, so that it is not possible to distinguish between the erase cell current and the program cell current, and there is a possibility that the verification cannot be performed correctly.

[0098] In the comparative example, the data read circuit 71 can generate two types of decision currents I0. In this case, the two types of decision currents I0 generated are, for example, the erase reference current and the program reference current shown in FIG. 7. In the comparative example, since the decision current I0 that can be generated is two types, in order to adjust the erase reference current and the program reference current to the erase current and the program current, it is necessary to adjust the current capabilities of the transistors QP3 and QP4. For example, when changing the current capabilities of the transistors QP3 and QP4, design changes and process changes that take into account manufacturing variations are required, and it is not realistic to adjust the current capabilities of the transistors QP3 and QP4 to the cell current. In other words, since it is not realistic to adjust the reference current to the cell current, the reference current increased by the word line boost cannot be adjusted to an optimal current value for verify.

[0099] 2. Second embodiment A configuration example of the word line boost circuit 30, the data read circuit 71, and the reference current generating circuit 72 in the second embodiment will be described. In describing the second embodiment, the same components as those in the first embodiment are given the same reference numerals, and the description thereof will be omitted or simplified. Fig. 8 is a diagram showing a schematic configuration example of the word line boost circuit 30, the data read circuit 71, and the reference current generating circuit 72 in the second embodiment.

[0100] The level detection current generating circuit 33 includes a p-type voltage detection transistor C and an n-type voltage detection transistor B. The source of the voltage detection transistor C is electrically connected to the output of the CMOS inverter formed by the preceding transistors QP22 and QN22, and is supplied with a drive potential V1.

[0101] The gate of the voltage detection transistor B is connected to the gate and drain of the voltage detection transistor C. The drain of the voltage detection transistor B is supplied with a logic power supply potential VDD, which is the high-potential power supply potential, and the source of the voltage detection transistor B is supplied with a reference power supply potential VSS, which is the ground potential, so that a current flows between the source and drain of the voltage detection transistor B.

[0102] When the read signal RD switches from low to high, the drive potential generating circuit 31 starts boosting the drive potential V1. When the drive potential V1 is boosted to a predetermined boost stop level, the transistors QP21 and QP22 of the level detection current generating circuit 33 are activated. This activates the voltage detection transistors C and B, and the level detection current generating circuit 33 generates a level detection current I3. Based on this level detection current I3, the potential of the node DET switches from high to low, and the boost stop control circuit 32 controls the drive potential generating circuit 31 to stop boosting.

[0103] In the second embodiment, it is possible to adjust the boost stop level of the drive potential V1 by adjusting the thresholds of the voltage detection transistors C and B. In addition, by adjusting the boost level and not boosting the drive potential V1 to a desired potential or higher, it is possible to reduce the power consumption of the drive potential generation circuit 31.

[0104] In the second embodiment, the polarity of the voltage detection transistor C is different from that of the voltage detection transistor B, so that they complement each other to reduce the effect of process variations on the threshold. That is, the boost stop control circuit 32 can control the stop of the boost operation of the drive potential generation circuit 31 with high accuracy by adjusting the thresholds of the voltage detection transistors B and C.

[0105] 3. Third embodiment A configuration example of the word line boost circuit 30, the data read circuit 71, and the reference current generating circuit 72 in the third embodiment will be described. In describing the third embodiment, the same components as those in the first embodiment are given the same reference numerals, and the description thereof will be omitted or simplified. Fig. 9 is a diagram showing a schematic configuration example of the word line boost circuit 30, the data read circuit 71, and the reference current generating circuit 72 in the third embodiment.

[0106] The level detection current generating circuit 33 of the third embodiment omits the voltage detection transistors A and B of the first embodiment and instead includes one or more voltage detection transistors D1...Dn. The one or more voltage detection transistors D1...Dn have a control gate 412a, a floating gate 412c, and oxide insulating films 412b, 412d. In other words, the one or more voltage detection transistors D1...Dn have the same layer structure as the multiple memory cells MC of the memory cell array 10. Here, n is an integer of 2 or more.

[0107] The read signal RD switches from low level to high level, and the drive potential generating circuit 31 starts boosting the drive potential V1. When the drive potential V1 is boosted to a predetermined boost stop level, the transistors QP21 and QP22 of the level detection current generating circuit 33 are activated. As a result, one or more voltage detection transistors D1...Dn to which the drive potential V1 is supplied to the control gate 412a are turned on, and the level detection current generating circuit 33 generates a level detection current I3. Based on this level detection current I3, the potential of the node DET switches from high level to low level, and the boost stop control circuit 32 controls the drive potential generating circuit 31 to stop boosting.

[0108] The level detection current I3 generated by the level detection current generating circuit 33 is generated based on a drive potential V1 being supplied to the gate of one or more voltage detection transistors D1...Dn, and a current flowing between the source and drain based on the drive potential V1.

[0109] The one or more voltage detection transistors D1...Dn have the same layer structure as the multiple memory cells MC of the memory cell array 10, and therefore operate in the same manner as the memory cell MC1 to be read. Specifically, the one or more voltage detection transistors D1...Dn have a control gate 412a and a floating gate 412c, similar to the memory cell MC1 to be read, and a drive potential V1 is applied to the control gate 412a.

[0110] The one or more voltage detection transistors D1...Dn have the same layer structure as the memory cell MC1 to be read and the same drive potential V1 is applied to the control gate 412a, so that the one or more voltage detection transistors D1...Dn behave in the same manner as the memory cell MC1 to be read.

[0111] In the third embodiment, a transistor having the same layer structure as the memory cell MC1 to be read is used as the voltage detection transistor, so that the boost stop level can be adjusted with high accuracy. Also, by providing a plurality of voltage detection transistors D1...Dn, the influence of manufacturing variations in each voltage detection transistor Di can be suppressed, and the level detection current generation circuit 33 can control the stop of the boost operation of the drive potential generation circuit 31 with high accuracy. Here, i is an integer between 2 and n.

[0112] 4.Electronic equipment An electronic device 500 according to this embodiment will be described with reference to Fig. 10. Fig. 10 is a functional block diagram showing a schematic configuration of the electronic device 500 according to this embodiment.

[0113] The electronic device 500 may include a semiconductor integrated circuit device 1, a CPU 510, an operation unit 520, a ROM (Read Only Memory) 530, a RAM (Random Access Memory) 540, a communication unit 550, a display unit 560, and an audio output unit 570. Note that the electronic device 500 may be configured such that some of these elements are omitted or changed, or other elements are added.

[0114] The semiconductor integrated circuit device 1 includes a non-volatile memory 2, and performs various processes in response to commands from the CPU 510. For example, the semiconductor integrated circuit device 1 corrects input data and converts the format of data based on parameters stored in the non-volatile memory 2.

[0115] The CPU 510 performs various calculation processes and control processes using data supplied from the semiconductor integrated circuit device 1 in accordance with programs stored in the ROM 530, etc. For example, the CPU 510 performs various data processes in response to operation signals supplied from the operation unit 520, controls the communication unit 550 to perform data communication with the outside, generates image signals for displaying various images on the display unit 560, and generates audio signals for outputting various sounds from the audio output unit 570.

[0116] Operation unit 520 is an input device including, for example, operation keys and button switches, and outputs an operation signal according to an operation by a user to CPU 510. ROM 530 stores programs, data, and the like for CPU 510 to perform various arithmetic processing and control processing. RAM 540 is used as a working area for CPU 510, and temporarily stores programs and data read from ROM 530, data input using operation unit 520, or results of arithmetic operations executed by CPU 510 according to programs, and the like.

[0117] The communication unit 550 is configured, for example, by an analog circuit and a digital circuit, and performs data communication between the CPU 510 and an external device. The display unit 560 is, for example, an LCD (Liquid Crystal Display). It displays various information based on a display signal supplied from the CPU 510. Audio output unit 570 includes, for example, a speaker, and outputs audio based on an audio signal supplied from CPU 510.

[0118] Examples of electronic devices 500 include smart cards, calculators, electronic dictionaries, electronic game devices, mobile terminals such as mobile phones, digital still cameras, digital movie devices, televisions, videophones, security television monitors, head mounted displays, personal computers, printers, network devices, car navigation devices, measuring devices, and medical devices (e.g., electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, and electronic endoscopes).

[0119] According to this embodiment, it is possible to provide an electronic device 500 that can accurately read out data stored in a plurality of memory cells MC in a nonvolatile memory 2 built into a semiconductor integrated circuit device 1. It is also possible to provide an electronic device 500 that can reduce power consumption. For example, it is possible to omit the ROM 530 by storing a program in the nonvolatile memory 2 of the semiconductor integrated circuit device 1, and to omit the RAM 540 by storing data in the nonvolatile memory 2 of the semiconductor integrated circuit device 1.

[0120] 5. Effects Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments, and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be appropriately combined.

[0121] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0122] The following can be derived from the above-described embodiment and modified examples.

[0123] One aspect of the semiconductor integrated circuit device is A plurality of non-volatile memory cells in which data can be electrically written and erased; a reference cell having the same layer structure as each of the transistors of the plurality of memory cells; a data read circuit that generates a determination current based on a current flowing through the reference cell to which a driving potential is applied, and compares a current flowing through a memory cell to be read out among the plurality of memory cells to which the driving potential is applied with the determination current, thereby reading out data stored in the memory cell to be read out; a drive potential generating circuit that generates the drive potential higher than a high potential side power supply potential supplied to the data read circuit in a verify mode of the memory cells; a level detection current generating circuit for generating a level detection current corresponding to a read current of the memory cell to be read based on the drive potential; a boost stop control circuit that performs stop control of the boost operation of the drive potential generating circuit based on the level detection current, the level detection current generating circuit and the drive potential generating circuit operate based on the drive potential; The drive potential generating circuit is a bootstrap circuit.

[0124] According to this semiconductor integrated circuit device, the drive potential is boosted by the bootstrap circuit, and a dedicated regulator is not required, so that the configuration of the semiconductor integrated circuit device can be simplified. Since the boost stop control circuit controls the stop of the boost operation of the drive potential generation circuit based on the drive potential, the drive potential generation circuit does not boost the drive potential beyond the potential of the boost stop level, so that the power consumption of the semiconductor integrated circuit device can be reduced. Furthermore, the boost operation by the drive potential generation circuit and the stop control of the boost operation by the drive potential generation circuit by the boost stop control circuit are shorter than the stabilization time of the regulator output, so that the response time of the control of the semiconductor integrated circuit device can be shortened, and current consumption can be reduced.

[0125] One aspect of the semiconductor integrated circuit device is The voltage supplied to the CMOS inverter of the coupling capacitance driving circuit of the bootstrap circuit may be lower than the word line voltage of the memory cell to be read.

[0126] According to this semiconductor integrated circuit device, the voltage supplied to the CMOS inverter of the coupling capacitance drive circuit can be lowered, so that a low-voltage transistor can be used for the CMOS inverter. This makes it possible to shorten the drive time of the CMOS inverter. In addition, in a read operation performed in a low-voltage region, the drive potential can be sufficiently boosted because the drive time of the CMOS inverter can be shortened.

[0127] One aspect of the semiconductor integrated circuit device is The MOS transistors constituting the CMOS inverter may be transistors with a lower withstand voltage than the transistors of the bootstrap circuit.

[0128] According to this semiconductor integrated circuit device, the driving capability of the CMOS inverter can be increased, so that a sufficient driving potential can be obtained.

[0129] One aspect of the semiconductor integrated circuit device is The supply voltage to the CMOS inverter may be the high-potential power supply potential.

[0130] According to this semiconductor integrated circuit device, by supplying the CMOS inverter with the same power supply potential as the high-potential power supply potential supplied to the data read circuit, it is possible to share the power supply and simplify the circuit configuration of the CMOS inverter.

[0131] One aspect of the semiconductor integrated circuit device is The level detection current generating circuit includes: A p-type transistor, An n-type transistor, Equipped with The source of the p-type transistor is supplied with the driving potential, the gate of the n-type transistor is electrically connected to the gate and drain of the p-type transistor; The high potential side power supply potential is supplied to the drain of the n-type transistor, and a ground potential is supplied to the source of the n-type transistor; A current may flow between the source of the n-type transistor and the drain of the n-type transistor.

[0132] According to this semiconductor integrated circuit device, by performing level detection using a combination of transistors of different polarities, it is possible to compensate for the effects of manufacturing variations in each transistor, and to set the voltage detection level with high accuracy.

[0133] One aspect of the semiconductor integrated circuit device is The level detection current generating circuit includes: The memory cell may include one or more transistors having the same layer structure as the memory cells, the driving potential being supplied to a gate thereof, and a current flowing between a source and a drain based on the driving potential.

[0134] According to this semiconductor integrated circuit device, the level detection current is generated based on transistors having the same layer structure as the multiple memory cells, making it possible to generate a highly accurate level detection current. Moreover, by generating the level detection current based on multiple transistors, it becomes possible to generate a more accurate level detection current.

[0135] One aspect of the electronic device is The present invention provides an aspect of the semiconductor circuit device.

[0136] According to this electronic device, the drive potential is boosted by the bootstrap circuit, and a dedicated regulator is not required, so that the configuration of the semiconductor integrated circuit device can be simplified. Since the boost stop control circuit controls the stop of the boost operation of the drive potential generation circuit based on the drive potential, the drive potential generation circuit does not boost the drive potential beyond the potential of the boost stop level, so that the power consumption of the semiconductor integrated circuit device can be reduced. Furthermore, the boost operation by the drive potential generation circuit and the stop control of the boost operation by the drive potential generation circuit by the boost stop control circuit are shorter than the stabilization time of the regulator output, so that the response time of the control of the semiconductor integrated circuit device can be shortened, and current consumption can be reduced. [Explanation of symbols]

[0137] 1...semiconductor integrated circuit device, 2...non-volatile memory, 10...memory cell array, 20...power supply circuit, 30...word line boost circuit, 31...drive potential generation circuit, 32...boost stop control circuit, 33...level detection current generation circuit, 40...word line drive circuit, 41...word line driver, 42...transistor, 43...inverter, 50...source line drive circuit, 51...source line driver, 52...inverter, 60...switch circuit, 70...memory control circuit, 71...data read circuit, 72...reference current generation circuit, 7 3...verification circuit, 412a...control gate, 412c...floating gate, 500...electronic device, 510...CPU, 520...operation unit, 530...ROM, 540...RAM, 550...communication unit, 560...display unit, 570...audio output unit, C0...coupling capacitance, I0...judgment current, I1...read current, I2...reference current, I3...level detection current, MC...memory cell, MC1...memory cell to be read, RD...read signal, V1...driving potential, VDD...logic power supply potential, VSS...reference power supply potential

Claims

1. A plurality of non-volatile memory cells in which data can be electrically written and erased; a reference cell having the same layer structure as each of the transistors of the plurality of memory cells; a data read circuit that generates a determination current based on a current flowing through the reference cell to which a driving potential is applied, and compares a current flowing through a memory cell to be read out among the plurality of memory cells to which the driving potential is applied with the determination current, thereby reading out data stored in the memory cell to be read out; a drive potential generating circuit that generates the drive potential higher than a high potential side power supply potential supplied to the data read circuit in a verify mode of the memory cells; a level detection current generating circuit for generating a level detection current corresponding to a read current of the memory cell to be read based on the drive potential; a boost stop control circuit that performs stop control of the boost operation of the drive potential generating circuit based on the level detection current, the level detection current generating circuit and the drive potential generating circuit operate based on the drive potential; The semiconductor integrated circuit device, wherein the drive potential generating circuit is a bootstrap circuit.

2. 2. The semiconductor integrated circuit device according to claim 1, A semiconductor integrated circuit device, wherein a voltage supplied to a CMOS inverter of a coupling capacitance driving circuit of the bootstrap circuit is lower than a word line power supply potential of the memory cell to be read.

3. 3. The semiconductor integrated circuit device according to claim 2, a MOS transistor constituting the CMOS inverter has a lower breakdown voltage than a transistor of the bootstrap circuit,

4. 4. The semiconductor integrated circuit device according to claim 2, A semiconductor integrated circuit device, wherein a supply voltage to the CMOS inverter is a power supply potential on the high potential side.

5. 5. The semiconductor integrated circuit device according to claim 1, The level detection current generating circuit includes: A p-type transistor; An n-type transistor; Equipped with The source of the p-type transistor is supplied with the driving potential; the gate of the n-type transistor is electrically connected to the gate and drain of the p-type transistor; the high-potential power supply potential is supplied to the drain of the n-type transistor, and a ground potential is supplied to the source of the n-type transistor; A semiconductor integrated circuit device, wherein a current flows between the source of the n-type transistor and the drain of the n-type transistor.

6. 5. The semiconductor integrated circuit device according to claim 1, The level detection current generating circuit includes: A semiconductor integrated circuit device including one or more transistors having the same layer structure as the plurality of memory cells, the drive potential being supplied to a gate thereof, and a current flowing between a source and a drain thereof based on the drive potential.

7. 7. An electronic device comprising the semiconductor integrated circuit device according to claim 1.

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