Optical modulator and method for manufacturing optical modulator

Abstract

To provide an optical modulator and a method for manufacturing the optical modulator with which it is possible to lower the concentration of a p-type dopant in a core layer.SOLUTION: An optical modulator comprises a first mesa waveguide extending in a first direction and a second mesa waveguide. The first mesa waveguide includes a p-type first semiconductor layer provided on a substrate, a core layer provided on the first semiconductor layer, a p-type second semiconductor layer provided on the core layer, and an n-type third semiconductor layer provided on the core layer. The second semiconductor layer and third semiconductor layer are arranged adjacent to each other in the first direction. An electrode is provided on the third semiconductor layer. A junction surface between the second semiconductor layer and third semiconductor layer is inclined with respect to a surface that is orthogonal to the first direction.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to an optical modulator and a method for manufacturing an optical modulator. [Background technology]

[0002] Patent Document 1 discloses a Mach-Zehnder type optical modulator having two mesa waveguides. Each mesa waveguide has a lower clad layer provided on a substrate, a core layer provided on the lower clad layer, and an upper clad layer provided on the core layer. On each mesa waveguide, a plurality of modulation electrodes are provided, which are arranged in the extending direction of the mesa waveguide. Between the plurality of modulation electrodes, the upper clad layer has a separation portion made of an i-type semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-102160 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the lower cladding layer is made of a p-type semiconductor, the p-type dopant (e.g., zinc) contained in the lower cladding layer and the dopant (e.g., iron) contained in the separator may interdiffuse. As a result, the p-type dopant diffuses into the core layer. The p-type dopant in the core may become a non-radiative recombination center.

[0005] The present disclosure provides an optical modulator and a method for manufacturing the optical modulator that can reduce the p-type dopant concentration in the core layer. [Means for solving the problem]

[0006] An optical modulator according to one aspect of the present disclosure comprises a first mesa waveguide extending in a first direction, and a second mesa waveguide, the first mesa waveguide comprising a p-type first semiconductor layer provided on a substrate, a core layer provided on the first semiconductor layer, a p-type second semiconductor layer provided on the core layer, and an n-type third semiconductor layer provided on the core layer, the second semiconductor layer and the third semiconductor layer being arranged adjacent to each other in the first direction, an electrode being provided on the third semiconductor layer, and a junction surface between the second semiconductor layer and the third semiconductor layer being inclined with respect to a plane perpendicular to the first direction.

[0007] A manufacturing method of an optical modulator according to one aspect of the present disclosure is a manufacturing method of an optical modulator including a first mesa waveguide and a second mesa waveguide extending in a first direction, the manufacturing method including the steps of: forming a semiconductor laminate on a substrate, the semiconductor laminate including a first semiconductor layer of p-type provided on the substrate, a core layer provided on the first semiconductor layer, and a second semiconductor layer of a first conductivity type provided on the core layer; forming a recess in the second semiconductor layer by wet etching the second semiconductor layer, the length of the recess in the first direction decreasing from an upper end to a lower end of the recess; forming a third semiconductor layer of a second conductivity type in the recess; forming the first mesa waveguide and the second mesa waveguide by etching the second semiconductor layer, the third semiconductor layer, the core layer, and the first semiconductor layer; and forming an electrode on the first mesa waveguide, the electrode being formed on an n-type layer of the second semiconductor layer and the third semiconductor layer. Effect of the Invention

[0008] According to the present disclosure, an optical modulator capable of reducing the p-type dopant concentration in a core layer and a method for manufacturing the optical modulator are provided. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view illustrating a schematic configuration of an optical modulator according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a graph showing the relationship between depth and dopant concentration in the first experiment. [Figure 6] FIG. 6 is a graph showing the relationship between depth and dopant concentration in the second experiment. [Figure 7] FIG. 7 is a graph showing an example of the relationship between the position in the waveguiding direction and the electric field intensity. [Figure 8] FIG. 8 is a graph showing an example of the relationship between the acceptor concentration and the electric field leakage length. [Figure 9] FIG. 9 is a plan view illustrating a schematic process of the method for manufacturing the optical modulator according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a plan view illustrating a schematic process of the method for manufacturing the optical modulator according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a plan view illustrating a schematic process of the method for manufacturing the optical modulator according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a cross-sectional view illustrating a schematic process of the method for manufacturing the optical modulator according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view illustrating a schematic view of a part of the optical modulator according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] An optical modulator according to one embodiment includes a first mesa waveguide and a second mesa waveguide extending in a first direction, the first mesa waveguide including a p-type first semiconductor layer provided on a substrate, a core layer provided on the first semiconductor layer, a p-type second semiconductor layer provided on the core layer, and an n-type third semiconductor layer provided on the core layer, the second semiconductor layer and the third semiconductor layer being disposed adjacent to each other in the first direction, an electrode being provided on the third semiconductor layer, and a junction surface between the second semiconductor layer and the third semiconductor layer being inclined with respect to a plane perpendicular to the first direction.

[0011] According to the optical modulator of this embodiment, the p-type dopant in the first semiconductor layer and the p-type dopant in the second semiconductor layer are unlikely to interdiffuse. Therefore, the p-type dopant in the first semiconductor layer and the second semiconductor layer can be prevented from diffusing toward the core layer. Therefore, the p-type dopant concentration in the core layer can be reduced.

[0012] The junction surface may be inclined such that the length of the third semiconductor layer in the first direction becomes shorter from the electrode toward the core layer. In this case, even if an electric field leak occurs extending from the junction surface into the p-type second semiconductor layer in the first direction, the region in which the electric field spreads in the first direction can be made small.

[0013] The p-type dopant of the second semiconductor layer is 1×10 16 cm -3 In this case, the electric field leakage length extending from the junction surface into the p-type second semiconductor layer in the first direction can be reduced.

[0014] The p-type dopant of the second semiconductor layer is 1×10 17 cm -3 The second semiconductor layer may have the following concentration: In this case, optical loss due to free carrier absorption can be reduced in the second semiconductor layer.

[0015] A manufacturing method of an optical modulator according to one embodiment is a manufacturing method of an optical modulator including a first mesa waveguide and a second mesa waveguide extending in a first direction, the method including the steps of: forming a semiconductor laminate on a substrate, the semiconductor laminate including a first semiconductor layer of p-type provided on the substrate, a core layer provided on the first semiconductor layer, and a second semiconductor layer of a first conductivity type provided on the core layer; forming a recess in the second semiconductor layer by wet etching the second semiconductor layer, the length of the recess in the first direction decreasing from an upper end to a lower end of the recess; forming a third semiconductor layer of a second conductivity type in the recess; forming the first mesa waveguide and the second mesa waveguide by etching the second semiconductor layer, the third semiconductor layer, the core layer, and the first semiconductor layer; and forming an electrode on the first mesa waveguide, the electrode being formed on an n-type layer of the second semiconductor layer and the third semiconductor layer.

[0016] According to the method for manufacturing the optical modulator of this embodiment, the p-type dopant in the first semiconductor layer and the p-type dopant in the p-type layers of the second and third semiconductor layers are unlikely to interdiffuse. Therefore, the p-type dopant in the first and second or third semiconductor layers can be prevented from diffusing toward the core layer. Therefore, the p-type dopant concentration in the core layer can be reduced.

[0017] The third semiconductor layer may be an n-type layer, in which case the p-type dopant in the p-type second semiconductor layer is less likely to diffuse toward the core layer.

[0018] In the step of forming the third semiconductor layer, a length of an upper surface of the third semiconductor layer in the first direction may be longer than a length of an upper surface of the second semiconductor layer in the first direction. In this case, flatness of the upper surface of the third semiconductor layer can be improved.

[0019] [Details of the embodiment of the present disclosure] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same or equivalent elements are designated by the same reference numerals, and duplicated descriptions are omitted. In the drawings, X-axis, Y-axis, and Z-axis directions that intersect with each other are shown as necessary. The X-axis, Y-axis, and Z-axis directions are, for example, perpendicular to each other. The X-axis direction is, for example, the [0-11] direction. The Y-axis direction is, for example, the

[0011] direction. The Z-axis direction is, for example, the

[0100] direction.

[0020] (First embodiment) Fig. 1 is a plan view showing a schematic diagram of an optical modulator according to a first embodiment. The optical modulator 10 shown in Fig. 1 is, for example, a Mach-Zehnder modulator. The optical modulator 10 can modulate the intensity or phase of light in, for example, optical communication to generate a modulated signal. The optical modulator 10 can attenuate light by, for example, adjusting the intensity of the light.

[0021] The optical modulator 10 includes a first arm waveguide AM1 and a second arm waveguide AM2 of a Mach-Zehnder modulator. The first arm waveguide AM1 includes a first mesa waveguide M1. The first arm waveguide AM1 may include a pair of bent waveguides M1b optically coupled to both ends of the first mesa waveguide M1. The second arm waveguide AM2 includes a second mesa waveguide M2. The second arm waveguide AM2 may include a pair of bent waveguides M2b optically coupled to both ends of the second mesa waveguide M2.

[0022] The first mesa waveguide M1 is provided on the substrate 12, extends along the Y-axis direction (first direction), and has a height in the Z-axis direction. The second mesa waveguide M2 ​​extends along the first mesa waveguide M1. The second mesa waveguide M2 ​​may extend along the Y-axis direction and have a height in the Z-axis direction. The extension direction of the second mesa waveguide M2 ​​may be different from the extension direction of the first mesa waveguide M1. Specifically, the angle between the extension direction of the first mesa waveguide M1 and the extension direction of the second mesa waveguide M2 ​​may be, for example, greater than 0° and equal to or less than 20°. The first mesa waveguide M1 and the second mesa waveguide M2 ​​are spaced apart from each other in the X-axis direction.

[0023] The input end of the first mesa waveguide M1 and the input end of the second mesa waveguide M2 ​​are optically coupled to the optical splitter C1 via the bent waveguide M1b and the bent waveguide M2b, respectively. The optical splitter C1 is a multi-mode interference (MMI) coupler such as a 1×2 multi-mode interference coupler. The optical splitter C1 is optically coupled to the output end of the input waveguide W1. The input end of the input waveguide W1 is the input port P1. The input port P1 is located at the edge of the substrate 12. Light is input to the input port P1.

[0024] The output end of the first mesa waveguide M1 and the output end of the second mesa waveguide M2 ​​are optically coupled to the optical multiplexer C2 via the bent waveguide M1b and the bent waveguide M2b, respectively. The optical multiplexer C2 is an MMI coupler, such as a 2×1 multimode interference coupler. The optical multiplexer C2 is optically coupled to the input end of the output waveguide W2. The output end of the output waveguide W2 is the output port P2. The output port P2 is located at the edge of the substrate 12 opposite to the edge where the input port P1 is located. Light is output from the output port P2.

[0025] The first mesa waveguide M1 includes a plurality of modulation sections M1m spaced apart from one another along the Y-axis direction. A separation section M1s is located between the plurality of modulation sections M1m. A wiring E1a extending in the Y-axis direction is connected to each modulation section M1m. The wiring E1a is located on the modulation section M1m. Each wiring E1a is connected to an electrode pad EP1 by a wiring E1b. The electrode pad EP1 is located away from the wiring E1a in the X-axis direction. The electrode pad EP1 extends in the Y-axis direction across the plurality of modulation sections M1m. The wiring E1a, the wiring E1b, and the electrode pad EP1 are located on the substrate 12. The wiring E1a, the wiring E1b, and the electrode pad EP1 include a metal such as gold.

[0026] The second mesa waveguide M2 ​​has a similar configuration to the first mesa waveguide M1. The second mesa waveguide M2 ​​has a plurality of modulation sections M2m arranged at a distance from each other along the Y-axis direction. A separation section M2s is located between the plurality of modulation sections M2m. A wiring E2a extending in the Y-axis direction is connected to each modulation section M2m. The wiring E2a is located on the modulation section M2m. Each wiring E2a is connected to an electrode pad EP2 by a wiring E2b. The electrode pad EP2 is located away from the wiring E2a in the X-axis direction. The electrode pad EP2 extends in the Y-axis direction across the plurality of modulation sections M2m. The wiring E2a, the wiring E2b, and the electrode pad EP2 are located on the substrate 12. The wiring E2a, the wiring E2b, and the electrode pad EP2 include a metal such as gold.

[0027] A driving circuit DR is connected by wiring to one end of the electrode pad EP1 and one end of the electrode pad EP2. The driving circuit DR includes an AC power source PW, a resistor R1, and a resistor R2. The AC power source PW is connected by wiring to one end of the electrode pad EP1 via the resistor R1. The AC power source PW is connected by wiring to one end of the electrode pad EP2 via the resistor R2.

[0028] The other end of the electrode pad EP1 is connected to the ground potential GND via a terminating resistor RT1 by wiring, and the other end of the electrode pad EP2 is connected to the ground potential GND via a terminating resistor RT2 by wiring.

[0029] FIG 2 is a cross-sectional view taken along line II-II in FIG 1. FIG 2 shows cross sections of the modulation section M1m and the modulation section M2m. FIG 3 is a cross-sectional view taken along line III-III in FIG 1. FIG 3 shows cross sections of the separation section M1s and the separation section M2s. FIG 4 is a cross-sectional view taken along line IV-IV in FIG 1. FIG 4 shows cross sections of the modulation section M1m and the separation section M1s.

[0030] 2 to 4, the first mesa waveguide M1 includes a p-type first semiconductor layer 16 provided on a substrate 12, a core layer 18 provided on the first semiconductor layer 16, a p-type second semiconductor layer 26 provided on the core layer 18, and an n-type third semiconductor layer 20 provided on the core layer 18. A semiconductor layer 14 may be provided between the substrate 12 and the first semiconductor layer 16. A p-type semiconductor layer 28 may be provided on the second semiconductor layer 26. An n-type semiconductor layer 22 may be provided on the third semiconductor layer 20.

[0031] The second semiconductor layer 26 and the third semiconductor layer 20 are disposed adjacent to each other in the Y-axis direction. A plurality of second semiconductor layers 26 and a plurality of third semiconductor layers 20 may be arranged in the Y-axis direction. The second semiconductor layers 26 and the third semiconductor layers 20 may be arranged alternately in the Y-axis direction. The number of the third semiconductor layers 20 may match the number of the electrodes E1. The junction plane JN between the second semiconductor layer 26 and the third semiconductor layer 20 is inclined with respect to a plane (XZ plane) perpendicular to the Y-axis direction. That is, the junction plane JN is inclined with respect to the Z-axis direction in the YZ cross section of the first mesa waveguide M1. The junction plane JN is a PN junction plane. In this embodiment, the junction plane JN is inclined such that the length L20 of the third semiconductor layer 20 in the Y-axis direction becomes shorter from the electrode E1 toward the core layer 18. That is, the junction plane JN is inclined such that the length L26 of the second semiconductor layer 26 in the Y-axis direction becomes longer from the electrode E1 toward the core layer 18. The junction plane JN is inclined at an angle (90°-θ) with respect to the XZ plane. That is, the junction plane JN is inclined at an angle θ with respect to the primary surface 12a of the substrate 12. The angle θ can be 50° or more and 60° or less. The angle θ can be controlled by the crystal orientation of the III-V compound semiconductor contained in the second semiconductor layer 26. For example, when the primary surface 12a of the substrate 12 is a (100) plane and the second semiconductor layer 26 is epitaxially grown on the primary surface 12a, the angle θ can be 55°.

[0032] The junction surface JN may be inclined such that the length L20 of the third semiconductor layer 20 in the Y-axis direction increases from the electrode E1 toward the core layer 18. In other words, the junction surface JN may be inclined such that the length L26 of the second semiconductor layer 26 in the Y-axis direction decreases from the electrode E1 toward the core layer 18.

[0033] In the first mesa waveguide M1, an electrode E1 is provided on the third semiconductor layer 20. A semiconductor layer 22 may be disposed between the third semiconductor layer 20 and the electrode E1. A wiring E1a is provided on the electrode E1. In the first mesa waveguide M1, the electrode E1 and the wiring E1a are not provided on the second semiconductor layer 26.

[0034] Similarly, in the second mesa waveguide M2, an electrode E2 is provided on the third semiconductor layer 20. A semiconductor layer 22 may be disposed between the third semiconductor layer 20 and the electrode E2. A wiring E2a is provided on the electrode E2. In the second mesa waveguide M2, the electrode E2 and the wiring E2a are not provided on the second semiconductor layer 26.

[0035] As shown in FIG. 2, in the modulation section M1m and the modulation section M2m, the semiconductor layer 14, the first semiconductor layer 16, the core layer 18, the third semiconductor layer 20, and the semiconductor layer 22 may be provided in this order on the major surface 12a of the substrate 12. The first semiconductor layer 16 constitutes a lower cladding layer. The third semiconductor layer 20 constitutes an upper cladding layer. The core layer 18 of the first mesa waveguide M1 and the core layer 18 of the second mesa waveguide M2 ​​are disposed apart from each other in the X-axis direction. In a cross section of the first mesa waveguide M1 perpendicular to the Y-axis direction, a light spot S1 is formed across the first semiconductor layer 16, the core layer 18, and the third semiconductor layer 20. In a cross section of the second mesa waveguide M2 ​​perpendicular to the Y-axis direction, a light spot S2 is formed across the first semiconductor layer 16, the core layer 18, and the third semiconductor layer 20.

[0036] 3, in the separation portions M1s and M2s, the semiconductor layer 14, the first semiconductor layer 16, the core layer 18, the second semiconductor layer 26, and the semiconductor layer 28 may be provided in this order on the major surface 12a of the substrate 12. The second semiconductor layer 26 constitutes an upper cladding layer.

[0037] The substrate 12 is, for example, a semi-insulating semiconductor substrate. The substrate 12 includes a III-V group compound semiconductor doped with an insulating dopant. The substrate 12 includes, for example, InP doped with iron (Fe). The dopant concentration of the substrate 12 is 1×10 17 cm -3 More than 1×10 18 cm -3 It can be the following:

[0038] As shown in FIG. 2 and FIG. 3, the semiconductor layer 14 includes a first portion 14a located between the core layer 18 and the substrate 12, and a pair of second portions 14b located on both sides of the first portion 14a. The first portion 14a and the pair of second portions 14b extend in the Y-axis direction. Therefore, the width of the semiconductor layer 14 (length in the X-axis direction) is larger than the width of the core layer 18. The semiconductor layer 14 of the first mesa waveguide M1 and the semiconductor layer 14 of the second mesa waveguide M2 ​​are connected to each other. In this embodiment, the semiconductor layer 14 of the first mesa waveguide M1 and the semiconductor layer 14 of the second mesa waveguide M2 ​​are connected to each other to form a single semiconductor layer. The semiconductor layer 14 does not need to include a pair of second portions 14b. In this case, the semiconductor layer 14 of the first mesa waveguide M1 and the semiconductor layer 14 of the second mesa waveguide M2 ​​can be electrically connected to each other by a semiconductor layer or a conductive layer provided between the substrate 12 and the semiconductor layer 14.

[0039] The semiconductor layer 14 includes a III-V compound semiconductor doped with a p-type dopant. The semiconductor layer 14 includes, for example, InGaAs or InP doped with zinc (Zn). The semiconductor layer 14 has a dopant concentration that is greater than the dopant concentration of the first semiconductor layer 16. The dopant concentration of the semiconductor layer 14 can be 10 times or more greater than the dopant concentration of the first semiconductor layer 16. The dopant concentration of the semiconductor layer 14 is 5×10 18 cm-3 or more or 1×10 19 cm -3 The thickness T1 of the semiconductor layer 14 is, for example, not less than 0.5 μm and not more than 2.0 μm.

[0040] The first semiconductor layer 16 includes a first portion 16a located between the core layer 18 and the semiconductor layer 14, and a pair of second portions 16b located on both sides of the first portion 16a. The thickness of the first portion 16a is greater than the thickness of the second portion 16b. The first portion 16a and the pair of second portions 16b extend in the Y-axis direction. Therefore, the width of the first semiconductor layer 16 is greater than the width of the core layer 18. The first semiconductor layer 16 of the first mesa waveguide M1 and the first semiconductor layer 16 of the second mesa waveguide M2 ​​are connected to each other. In this embodiment, the first semiconductor layer 16 of the first mesa waveguide M1 and the first semiconductor layer 16 of the second mesa waveguide M2 ​​are connected to each other to form a single semiconductor layer. The first semiconductor layer 16 does not need to include a pair of second portions 16b.

[0041] The first semiconductor layer 16 includes a III-V compound semiconductor doped with a p-type dopant. The first semiconductor layer 16 may include a semiconductor material different from the semiconductor material of the semiconductor layer 14. The first semiconductor layer 16 includes, for example, InP doped with Zn. The dopant concentration of the first semiconductor layer 16 is about 1×10 17 cm -3 More than 2×10 18 cm -3 The thickness T2 of the first semiconductor layer 16 (the thickness of the first portion 16a) may be larger than the thickness T1 of the semiconductor layer 14, and is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0042] The core layer 18 is an i-type semiconductor layer, i.e., an undoped semiconductor layer. The core layer 18 may have a multiple quantum well structure. The core layer 18 includes, for example, an AlGaInAs-based III-V group compound semiconductor. The width of the core layer 18 is, for example, 1.5 μm or less. The p-type dopant concentration in the core layer 18 is, for example, 1×10 16 cm -3 The following is the result.

[0043] The third semiconductor layer 20 includes a III-V compound semiconductor doped with an n-type dopant. The third semiconductor layer 20 includes, for example, InP doped with Si. The dopant concentration of the third semiconductor layer 20 is 1×10 17 cm -3 More than 2×10 18 cm -3 The thickness of the third semiconductor layer 20 is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0044] The semiconductor layer 22 includes a III-V compound semiconductor doped with an n-type dopant. The semiconductor layer 22 may include a semiconductor material different from the semiconductor material of the third semiconductor layer 20. The semiconductor layer 22 includes, for example, InGaAs or InP doped with Si. The semiconductor layer 22 has a dopant concentration greater than the dopant concentration of the third semiconductor layer 20. The dopant concentration of the semiconductor layer 22 is 1×10 18 cm -3 or more or 1×10 19 cm -3 The thickness of the semiconductor layer 22 is, for example, not less than 0.1 μm and not more than 0.5 μm.

[0045] The second semiconductor layer 26 includes a III-V compound semiconductor doped with a p-type dopant. The second semiconductor layer 26 may include the same semiconductor material as the first semiconductor layer 16. The second semiconductor layer 26 includes, for example, InP doped with Zn. The second semiconductor layer 26 has a dopant concentration that is less than the dopant concentration of the first semiconductor layer 16. The dopant concentration of the second semiconductor layer 26 is less than 5×10 16 cm -3 5×10 or more 17 cm -3 or less, or 5 x 10 16 cm -3 More than 1×10 17 cm -3 The thickness of the second semiconductor layer 26 may be smaller than the thickness T2 of the first semiconductor layer 16, and is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0046] The semiconductor layer 28 includes a III-V compound semiconductor doped with a p-type dopant. The semiconductor layer 28 may include a semiconductor material different from the semiconductor material of the second semiconductor layer 26. The semiconductor layer 28 includes, for example, InGaAs or InP doped with Zn. The semiconductor layer 28 has a dopant concentration that is less than the dopant concentration of the first semiconductor layer 16. The dopant concentration of the semiconductor layer 28 is less than 5×10 16 cm -3 5×10 or more 17 cm -3 or less, or 5 x 10 16 cm -3 More than 1×10 17 cm -3 The thickness of the semiconductor layer 28 is, for example, not less than 10 nm and not more than 100 nm.

[0047] The electrode E1 is connected to the semiconductor layer 22 of the first mesa waveguide M1. The electrode E1 is in ohmic contact with the semiconductor layer 22 of the first mesa waveguide M1. The electrode E1 is connected to the wiring E1a. Similarly, the electrode E2 is connected to the semiconductor layer 22 of the second mesa waveguide M2. The electrode E2 is in ohmic contact with the semiconductor layer 22 of the second mesa waveguide M2. The electrode E2 is connected to the wiring E2a. Each of the electrodes E1 and E2 includes, for example, a Ni layer, a Ge layer, and a Au layer. Further electrodes may be connected to the semiconductor layer 14.

[0048] An insulating film 30 containing, for example, an inorganic material may be provided on the main surface 12a of the substrate 12, the side surface of the first mesa waveguide M1, and the side surface of the second mesa waveguide M2. A buried region 32 may be provided on the insulating film 30 so as to bury the first mesa waveguide M1 and the second mesa waveguide M2. The buried region 32 contains, for example, a resin. The insulating film 30 may be provided on the buried region 32.

[0049] In the optical modulator 10 of this embodiment, an AC voltage is applied to the electrodes E1 and E2 by the drive circuit DR. For example, by applying a voltage to the first mesa waveguide M1, the intensity or phase of the light propagating through the core layer 18 of the first mesa waveguide M1 is adjusted. Similarly, by applying a voltage to the second mesa waveguide M2, the intensity or phase of the light propagating through the core layer 18 of the second mesa waveguide M2 ​​is adjusted.

[0050] According to the optical modulator 10 of the present embodiment, the p-type dopant in the second semiconductor layer 26 and the p-type dopant in the first semiconductor layer 16 are unlikely to interdiffuse. This makes it possible to suppress the p-type dopant in the first semiconductor layer 16 and the second semiconductor layer 26 from diffusing toward the core layer 18. This makes it possible to reduce the p-type dopant concentration in the core layer 18.

[0051] 4, the junction plane JN may be inclined so that the length L20 of the third semiconductor layer 20 in the Y-axis direction becomes shorter from the electrode E1 toward the core layer 18. In this case, even if an electric field leak occurs extending from the junction plane JN into the p-type second semiconductor layer 26 in the Y-axis direction, the region in which the electric field spreads in the Y-axis direction can be made smaller. Therefore, the length in the Y-axis direction of the region to which a voltage is applied in the core layer 18 can be made smaller.

[0052] The p-type dopant of the second semiconductor layer 26 is 1×10 16 cm -3 When the p-type dopant of the second semiconductor layer 26 has a concentration of 1×10 17 cm -3 When the second semiconductor layer 26 has the following concentrations, the optical loss due to free carrier absorption can be reduced.

[0053] Below, we will explain various experiments that were performed to evaluate the optical modulator 10. The experiments explained below do not limit the present disclosure.

[0054] (First experiment) The optical modulator of the first experiment has the structure shown in Figures 1 to 4. Specifically, the optical modulator of the first experiment has the following structure. Substrate 12: Fe-doped InP substrate (Fe concentration 1×10 17 cm -3 More than 1×10 18 cm -3 below), Semiconductor layer 14: p-InGaAs contact layer. Zn-doped InGaAs layer (thickness 1.1 μm, Zn concentration 2×10 19 cm -3 ), First semiconductor layer 16: p-InP lower cladding layer. Zn-doped InP layer (first portion 16a: 1.5 μm thick, second portion 16b: 1 μm thick, Zn concentration: 5×10 17 cm -3 More than 2×10 18 cm -3 below), Core layer 18: i-core layer. AlGaInAs / AlInAs multiple quantum well (thickness 0.5 μm, width 1.5 μm, distance between core layer 18 of first mesa waveguide M1 and core layer 18 of second mesa waveguide M2 ​​15 μm), Third semiconductor layer 20: Si-doped InP layer (Si concentration 5×10 17 cm -3 More than 2×10 18 cm -3 below), Semiconductor layer 22: Si-doped InGaAs layer (Si concentration 1×10 19 cm -3 (The above) Second semiconductor layer 26: p-InP upper cladding layer. Zn-doped InP layer (thickness 1.2 μm, Zn concentration 1×10 17 cm -3 5×10 or more 17 cm -3 below), Semiconductor layer 28: p-InGaAs layer. Zn-doped InGaAs layer (thickness 50 nm, Zn concentration 1×10 17 cm -3 5×10 or more 17 cm -3 below).

[0055] The optical modulator of the first experiment was measured by SIMS (Secondary Ion Mass Spectrometry), and the results are shown in Figure 5.

[0056] FIG. 5 is a graph showing the relationship between depth and dopant concentration in the first experiment. In the graph, the vertical axis indicates the dopant concentration. The dopant concentration is Zn concentration. The horizontal axis indicates the depth in the direction perpendicular to the main surface of the InP substrate. The position where the depth is 0 is the top surface of the p-InGaAs layer. The graph shows the Zn concentration profile P1ZN. In the i-core layer, the Zn concentration is 1×10 16 cm -3 From the graph in Figure 5, it can be seen that Zn in the p-InP lower cladding layer and Zn in the p-InP upper cladding layer do not diffuse into the i-core layer.

[0057] (Second experiment) The optical modulator of the second experiment has the same structure as the optical modulator of the first experiment, except that it has an SI (Semi-Insulating)-InP upper cladding layer and an SI-InGaAsP layer instead of the p-InP upper cladding layer and the p-InGaAs layer, respectively. Each of the SI-InP upper cladding layer and the SI-InGaAsP layer contains Fe as a dopant.

[0058] The optical modulator in the second experiment was subjected to SIMS measurement, and the results are shown in Figure 6.

[0059] FIG. 6 is a graph showing the relationship between depth and dopant concentration in the second experiment. In the graph, the vertical axis indicates dopant concentration. The dopant concentration is Zn concentration or Fe concentration. The horizontal axis indicates depth in a direction perpendicular to the main surface of the InP substrate. The position where the depth is 0 is the top surface of the SI-InGaAsP layer. The graph shows a Zn concentration profile P2ZN and an Fe concentration profile P2FE. In the core layer, the Zn concentration was 1×10 16 cm -3From the graph in Figure 6, it can be seen that Zn in the p-InP lower cladding layer diffuses into the i-core layer, and Fe in the SI-InP upper cladding layer diffuses into the p-InP lower cladding layer.

[0060] (Third experiment) In a third experiment, the electric field intensity distribution was calculated by simulation for a model structure corresponding to a region including the second semiconductor layer 26 and a pair of third semiconductor layers 20 located on both sides of the second semiconductor layer 26 in Fig. 4. The result is shown in Fig. 7.

[0061] FIG. 7 is a graph showing an example of the relationship between the position in the waveguiding direction and the electric field intensity. In the graph, the vertical axis indicates the electric field intensity, and the horizontal axis indicates the position in the waveguiding direction (Y-axis direction). The model structure has a pair of n-InP layers, each having a length of 1 μm in the waveguiding direction, and a p-InP layer having a length of 5 μm in the waveguiding direction. The Si concentration of each n-InP layer is 2×10 18 cm -3 The acceptor concentration (Zn concentration) of the p-InP layer is 1×10 14 cm -3 , 1×10 15 cm -3 Or 1×10 16 cm -3 The junction between each n-InP layer and p-InP layer is perpendicular to the waveguide direction.

[0062] In the graph, profile C14 is the acceptor concentration of 1×10 14 cm -3 The electric field distribution in the p-InP layer when the acceptor concentration is 1×10 15 cm -3 The profile C16 shows the electric field distribution in the p-InP layer when the acceptor concentration is 1×10 16 cm -3 The electric field leakage length L15 is the electric field strength distribution in the p-InP layer when the acceptor concentration is 1×10 15 cm -3The electric field leakage length L16 is the length in the waveguiding direction of the region having an electric field strength of 1% or more relative to the peak electric field strength when the acceptor concentration is 1×10 16 cm -3 7 shows the length in the waveguide direction of a region having an electric field strength of 1% or more with respect to the peak electric field strength when the acceptor concentration is increased. It can be seen from the graph in FIG. 7 that the electric field leakage length decreases as the acceptor concentration increases.

[0063] FIG. 8 is a graph showing an example of the relationship between the acceptor concentration and the electric field leakage length. In the graph, the vertical axis indicates the electric field leakage length, and the horizontal axis indicates the acceptor concentration. The electric field leakage length L15 is about 3 μm. The electric field leakage length L16 is about 1 μm. It can be seen from the graph in FIG. 8 that the electric field leakage length decreases linearly as the acceptor concentration increases. When the acceptor concentration is 1×10 16 cm -3 If this is the case or more, the electric field leakage length becomes small, at 1 μm or less.

[0064] A method for manufacturing the optical modulator according to the first embodiment will be described below with reference to Figures 9 to 15. The optical modulator 10 can be manufactured as follows.

[0065] (Forming a semiconductor laminate) First, as shown in Fig. 9 and Fig. 10, a semiconductor laminate SL is formed on a substrate 12. The semiconductor laminate SL includes a p-type first semiconductor layer 16 provided on the substrate 12, a core layer 18 provided on the first semiconductor layer 16, and a p-type (first conductivity type) second semiconductor layer 26 provided on the core layer 18. The semiconductor laminate SL may include a semiconductor layer 14 disposed between the substrate 12 and the first semiconductor layer 16. The semiconductor laminate SL may include a p-type semiconductor layer 28 provided on the second semiconductor layer 26. Each layer is formed by, for example, organometallic vapor phase epitaxy (OMVPE).

[0066] Next, a mask MK1 is formed on the semiconductor laminate SL. In this embodiment, a plurality of masks MK1 extend in the X-axis direction and are spaced apart from each other in the Y-axis direction. The masks MK1 can be formed by, for example, photolithography and etching.

[0067] (Wet etching of the second semiconductor layer) Next, as shown in FIGS. 11 and 12, the second semiconductor layer 26 is wet-etched to form a recess RS in the second semiconductor layer 26. The semiconductor layer 28 may also be wet-etched. The wet etching is performed using a mask MK1. Examples of the etchant include an aqueous solution containing hydrochloric acid and hydrogen peroxide. The length LRS of the recess RS in the Y-axis direction decreases from the upper end RS1 to the lower end RS2 of the recess RS. That is, the sidewall of the recess RS has a forward tapered shape.

[0068] (Forming the third semiconductor layer) 11 and 12, a third semiconductor layer 20 of n-type (a second conductivity type opposite to the first conductivity type) is formed in the recess RS. Thereafter, a semiconductor layer 22 may be formed on the third semiconductor layer 20. Each layer is formed by, for example, metal organic chemical vapor deposition using a mask MK1. Each layer does not have to be formed on the mask MK1 by selective growth.

[0069] The length L20U of the upper surface of the third semiconductor layer 20 in the Y-axis direction may be longer than the length L26U of the upper surface of the second semiconductor layer 26 in the Y-axis direction. In this case, the flatness of the upper surface of the third semiconductor layer 20 can be increased.

[0070] (Forming the first mesa waveguide and the second mesa waveguide) Next, as shown in FIG. 13 to FIG. 15, the second semiconductor layer 26, the third semiconductor layer 20, the core layer 18, and the first semiconductor layer 16 are etched to form the first mesa waveguide M1 and the second mesa waveguide M2. The semiconductor layer 22 and the semiconductor layer 28 may also be etched. The first mesa waveguide M1 and the second mesa waveguide M2 ​​may be formed by photolithography and dry etching. First, as shown in FIG. 13 and FIG. 14, the second semiconductor layer 26, the semiconductor layer 28, the third semiconductor layer 20, the semiconductor layer 22, the core layer 18, and the first semiconductor layer 16 are etched using a mask MK2. The first semiconductor layer 16 is partially etched. In this embodiment, a pair of masks MK2 extend in the Y-axis direction and are spaced apart from each other in the X-axis direction. Next, as shown in FIG. 15, the first semiconductor layer 16 and the semiconductor layer 14 are etched using a mask MK3 extending in the Y-axis direction. The width of the mask MK3 in the X-axis direction is greater than the width of the mask MK2 in the X-axis direction. As a result, the first mesa waveguide M1 and the second mesa waveguide M2 ​​are formed.

[0071] 2 and 3, an insulating film 30 is formed so as to cover the first mesa waveguide M1 and the second mesa waveguide M2. Then, a resin is applied onto the insulating film 30 to form a buried region 32. Then, the insulating film 30 is formed on the buried region 32.

[0072] (Forming electrodes) Next, as shown in Figures 2 and 4, an electrode E1 is formed on the first mesa waveguide M1. The electrode E1 is formed on the n-type third semiconductor layer 20 and is not formed on the p-type second semiconductor layer 26. The electrode E1 may be formed on the semiconductor layer 22. Similarly, as shown in Figure 2, an electrode E2 is formed on the second mesa waveguide M2. The electrode E2 is formed on the n-type third semiconductor layer 20 and is not formed on the p-type second semiconductor layer 26. The electrode E2 may be formed on the semiconductor layer 22.

[0073] Next, the wiring E1a and the wiring E2a are formed on the electrodes E1 and E2, respectively. At the same time, the wiring E1b, the wiring E2b, the electrode pad EP1, and the electrode pad EP2 are also formed. The wiring and the electrode pads can be formed by, for example, photolithography, dry etching, deposition, and lift-off.

[0074] In the above manufacturing method, the order of forming the second semiconductor layer 26 and the third semiconductor layer 20 may be reversed. In this case, in the step of forming the semiconductor laminate, the semiconductor laminate SL includes an n-type (first conductive type) third semiconductor layer 20 (second semiconductor layer) provided on the core layer 18. In the step of wet-etching the second semiconductor layer, a recess is formed in the third semiconductor layer 20 by wet-etching the third semiconductor layer 20. In the step of forming the third semiconductor layer, a p-type (second conductive type) second semiconductor layer 26 is formed in the recess. In this case, the junction plane JN shown in FIG. 4 is inclined so that the length L20 of the third semiconductor layer 20 in the Y-axis direction becomes longer from the electrode E1 toward the core layer 18.

[0075] Second embodiment Fig. 16 is a cross-sectional view showing a schematic diagram of a part of the optical modulator according to the second embodiment. The optical modulator shown in Fig. 16 has the same configuration as the optical modulator 10 of the first embodiment, except that it further includes an etching stop layer 50.

[0076] The etch stop layer 50 can function as an etch stop layer when wet etching the second semiconductor layer 26. The etch stop layer 50 includes a III-V compound semiconductor such as InGaAsP.

[0077] In this embodiment, the same effects as those in the first embodiment can be obtained. The etching stop layer 50 can prevent the core layer 18 from being etched when the second semiconductor layer 26 or the third semiconductor layer 20 is wet etched.

[0078] Although the preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments. The components of the respective embodiments may be combined in any desired manner.

[0079] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present invention is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0080] 10...Optical modulator 12...Substrate 12a…main surface 14...Semiconductor layer 14a…Part 1 14b…Second part 16...First semiconductor layer 16a…first part 16b…Second part 18…Core layer 20...Third semiconductor layer 22...Semiconductor layer 26...Second semiconductor layer 28...Semiconductor layer 30...Insulating film 32…Buried area 50...Etching stop layer AM1: First arm waveguide AM2: Second arm waveguide C1…Optical demultiplexer C2…Optical multiplexer C14…Profile C15…Profile C16…Profile DR: Drive circuit E1…electrode E1a…Wiring E1b…Wiring E2…electrode E2a…Wiring E2b…Wiring EP1...electrode pad EP2: Electrode pad GND…Ground potential JN...joint surface M1: First mesa waveguide M1b…Bent waveguide M1m…Modulation section M1s…separation part M2: Second mesa waveguide M2b…Bent waveguide M2m…Modulation section M2s…separation part MK1…Mask MK2…Mask MK3…Mask P1...input port P1ZN…Profile P2…Output port P2FE…Profile P2ZN…Profile PW…AC power supply R1…Resistor R2…Resistance RS…Concave RS1…Top end RS2…lower end RT1…Terminal resistor RT2…Terminal resistor S1…Spot S2…Spot SL: Semiconductor laminate W1…input waveguide W2: Output waveguide

Claims

1. A first mesa waveguide extending in a first direction that is an optical axis direction; a second mesa waveguide; Equipped with the first mesa waveguide comprises a p-type first semiconductor layer provided on a primary surface of a substrate, a core layer provided on the first semiconductor layer, a p-type second semiconductor layer provided on the core layer, and an n-type third semiconductor layer provided on the core layer; the second semiconductor layer and the third semiconductor layer are disposed adjacent to each other in the first direction, an electrode is provided on the third semiconductor layer; a junction surface between the second semiconductor layer and the third semiconductor layer is inclined with respect to a plane perpendicular to the first direction, The optical modulator, wherein the bonding surface is inclined at an angle of 50° to 60° with respect to the main surface of the substrate.

2. 2 . The optical modulator according to claim 1 , wherein the junction surface is inclined such that a length of the third semiconductor layer in the first direction becomes shorter from the electrode toward the core layer.

3. The p-type dopant of the second semiconductor layer is 1×10 １６ cm －３ 3. The optical modulator according to claim 1, having a concentration of at least one of the above.

4. The p-type dopant of the second semiconductor layer is 1×10 １７ cm －３ 4. The optical modulator of claim 1, having the following concentrations:

5. A method for manufacturing an optical modulator including a first mesa waveguide extending in a first direction that is an optical axis direction, and a second mesa waveguide, comprising: A step of forming a semiconductor laminate on a major surface of a substrate, the semiconductor laminate including a p-type first semiconductor layer provided on the substrate, a core layer provided on the first semiconductor layer, and a first conductivity type second semiconductor layer provided on the core layer; forming a recess in the second semiconductor layer by wet etching the second semiconductor layer, the length of the recess in the first direction decreasing from an upper end to a lower end of the recess; forming a third semiconductor layer of a second conductivity type in the recess, wherein a junction surface between the second semiconductor layer and the third semiconductor layer is inclined at an angle of 50° or more and 60° or less with respect to the main surface of the substrate; forming the first mesa waveguide and the second mesa waveguide by etching the second semiconductor layer, the third semiconductor layer, the core layer, and the first semiconductor layer; forming an electrode on the first mesa waveguide, the electrode being formed on an n-type layer of the second semiconductor layer and the third semiconductor layer; A method for manufacturing an optical modulator, comprising:

6. The method for manufacturing an optical modulator according to claim 5 , wherein the third semiconductor layer is an n-type layer.

7. 7. The method for manufacturing an optical modulator according to claim 5, wherein in the step of forming the third semiconductor layer, a length of an upper surface of the third semiconductor layer in the first direction is longer than a length of an upper surface of the second semiconductor layer in the first direction.

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