POWER CONVERSION APPARATUS AND METHOD FOR CONTROLLING POWER CONVERSION APPARATUS

Abstract

To make voltage output by a pulse transformer constant regardless of the size of a load in a power conversion device.SOLUTION: A counter 3 detects a period of a gate signal on the basis of on and off commands of the gate signal and on the basis of a clock CLK and outputs a switching frequency f. A voltage command value calculator 4 outputs a voltage command value Vref on the basis of the switching frequency f. A square wave generating unit 6 outputs first and second square waves in a complementary relation on the basis of a carrier signal. First and second multipliers 7a and 7b multiply the first and second square waves by the voltage command value Vref to output voltage command values for third and fourth semiconductor elements X1 and Y1 and for first and second semiconductor elements U1 and V1. First and second comparators 8a and 8b compare the voltage command values of the third and fourth semiconductor elements X1 and Y1 and the voltage command values of the first and second semiconductor elements U1 and V1 with the carrier signal and output the gate signals of the third and fourth semiconductor elements X1 and Y1 and the gate signals of the first and second semiconductor elements U1 and V1.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a control method for a gate drive circuit for driving semiconductor elements connected in series, and a control method for generating power. [Background technology]

[0002] Figure 5 shows the circuit configuration of the pulse power supply disclosed in Patent Document 1. As shown in Figure 5, the pulse power supply has multiple semiconductor elements connected in series to achieve high voltage resistance. Also, to generate power or gate signals for each gate circuit, multiple toroidal cores are arranged in series with primary windings passing through the centers of the cores. Then, power and gate signals or only power are supplied by passing a current through the primary winding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5221203 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the case of the method of Patent Document 1, since it is necessary to pass multiple transformers (toroidal cores) through one primary winding, the wire length of the primary winding becomes physically long, resulting in a large inductance value.

[0005] When the inductance becomes large, the voltage output to the secondary side of the pulse transformer fluctuates greatly depending on the load power situation. When the load power is low, an excessive voltage is applied, and conversely, when the load power is high, the voltage is insufficient.

[0006] When an undervoltage occurs, there is a risk of increased loss due to insufficient gate voltage in the semiconductor element being driven. Furthermore, because a large voltage is applied during low power consumption, the gate drive circuit must be made to withstand high voltages, which causes various problems such as higher costs and reduced reliability.

[0007] In view of the above, a problem to be solved in a power conversion device is how to make the voltage output by the pulse transformer constant regardless of the magnitude of the load. [Means for solving the problem]

[0008] The present invention has been devised in view of the above-mentioned problems in the related art, and one aspect thereof is a power conversion device including a capacitor, first and second semiconductor elements connected in series between positive and negative electrodes of the capacitor, third and fourth semiconductor elements connected in series between the positive and negative electrodes of the capacitor, a primary winding connected between a connection point of the first and second semiconductor elements and a connection point of the third and fourth semiconductor elements, and a pulse transformer having a plurality of toroidal cores through which the primary winding passes, and a control circuit that outputs gate signals to the first to fourth semiconductor elements, wherein the control circuit includes a counter that detects a period of the gate signal based on an on command and an off command of the gate signal and a clock, and outputs a switching frequency, and a voltage command value based on the switching frequency. a carrier generating unit that outputs a carrier signal based on the clock; a square wave generating unit that outputs a first square wave and a second square wave that are complementary to each other based on the carrier signal; a first multiplier that multiplies the first square wave by the voltage command value to output voltage command values ​​for the third and fourth semiconductor elements; a second multiplier that multiplies the second square wave by the voltage command value to output voltage command values ​​for the first and second semiconductor elements; a first comparator that compares the voltage command values ​​for the third and fourth semiconductor elements with the carrier signal to output gate signals for the third and fourth semiconductor elements; and a second comparator that compares the voltage command values ​​for the first and second semiconductor elements with the carrier signal to output gate signals for the first and second semiconductor elements.

[0009] In one embodiment, the counter includes a first AND element receiving the ON command and the clock, a second AND element receiving the OFF command and the clock, an ON counter circuit measuring an ON time of the gate signal based on an output of the first AND element, an OFF counter circuit measuring an OFF time of the gate signal based on an output of the second AND element, and a frequency calculator calculating the switching frequency based on the ON time and the OFF time, and the ON counter circuit and the OFF counter circuit each receive a clock. a first D-type flip-flop circuit having an output of the first AND element or the second AND element input to a clock terminal, an output of a negative logic output terminal input to a data terminal, and an output of a positive logic output terminal output to the frequency calculator; a third AND element input with an output of a positive logic output terminal of the first D-type flip-flop circuit and an output of a negative logic output terminal of the second D-type flip-flop circuit; a fourth AND element input with an output of a negative logic output terminal of the first D-type flip-flop circuit and an output of a positive logic output terminal of the second D-type flip-flop circuit; a first OR element receiving an output of the D element and an output of the fourth AND element; the second D-type flip-flop circuit having an output of the first OR element input to a data terminal, an output of the first AND element or the second AND element input to a clock terminal, and an output of a positive logic output terminal being output to the frequency calculator; a fifth AND element receiving an output of a positive logic output terminal of the first D-type flip-flop circuit, an output of a positive logic output terminal of the second D-type flip-flop circuit, and an output of a negative logic output terminal of a third D-type flip-flop circuit; a sixth AND element receiving an output of a negative logic output terminal of the second D-type flip-flop circuit and an output of a positive logic output terminal of the third D-type flip-flop circuit; a seventh AND element receiving an output of a negative logic output terminal of the second D-type flip-flop circuit and an output of a positive logic output terminal of the third D-type flip-flop circuit; a second OR element receiving an output of the fifth AND element, an output of the sixth AND element, and an output of the seventh AND element;and the third D type flip-flop circuit, the output of which is output from a positive logic output terminal to the frequency calculator.

[0010] In one aspect, the voltage command value calculator calculates the voltage command value by the following equation (2).

[0011]

number

[0012] Vref: Voltage command value f: switching frequency vref_i: Voltage command value when the rectified DC voltage becomes the rated voltage when the switching frequency f=0 fmax: Maximum switching frequency. Effect of the Invention

[0013] According to the present invention, in a power conversion device, it is possible to stabilize the voltage output by a pulse transformer regardless of the magnitude of the load. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a circuit configuration diagram showing a main circuit of a power conversion device according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing a control circuit of the power conversion device according to the embodiment. [Diagram 3] FIG. 4 is a block diagram showing a counter according to the embodiment. [Figure 4] 4 is a time chart showing an example of a generated waveform in the embodiment. [Diagram 5] FIG. 1 is a circuit diagram showing a gate power supply, a gate circuit, and a high-voltage switch in Patent Document 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of a power conversion device according to the present invention will be described in detail with reference to Figs.

[0016] [Embodiment] Fig. 1 shows the main circuit configuration of a power conversion device in this embodiment. As shown in Fig. 1, the power conversion device has a capacitor C. First and second semiconductor elements U1, V1 are connected in series between the positive and negative electrodes of the capacitor C. In addition, third and fourth semiconductor elements X1, Y1 are connected in series between the positive and negative electrodes of the capacitor C. The first to fourth semiconductor elements U1, V1, X1, Y1 constitute a power converter.

[0017] A primary winding of a pulse transformer Tr is connected between the connection point of the first and second semiconductor elements U1, V1 and the connection point of the third and fourth semiconductor elements X1, Y1. n (n: natural number of 2 or more) toroidal cores 1a-1n are arranged in series, and the primary winding passes through the center of the plurality of toroidal cores 1a-1n. The primary winding and the toroidal cores 1a-1n constitute a pulse transformer Tr. For example, a semiconductor device is connected to the toroidal cores 1a-1n via a rectifier circuit and a gate circuit, respectively.

[0018] Here, the capacitor voltage (DC voltage) is E1, and the voltage of the primary winding of the pulse transformer Tr is V. In addition, the current at the connection point of the third and fourth semiconductor elements X1 and Y1 is i1.

[0019] The circuit in Figure 1 is a circuit for driving a pulse transformer Tr, and is a typical full-bridge inverter.

[0020] A control circuit for the power converter in this embodiment is shown in Fig. 2. The control circuit in Fig. 2 generates gate signals for the first to fourth semiconductor elements U1, V1, X1, and Y1, and controls the main circuit in Fig. 1.

[0021] 2, an ON command for a gate signal, an OFF command obtained by inverting the gate signal by a first NOT element 2, and a clock CLK are input to a counter 3. The counter 3 detects the period of the gate signal of the semiconductor element to be driven that is input from outside, and estimates the switching frequency f.

[0022] The voltage command value calculator 4 generates a voltage command value Vref based on the switching frequency f.

[0023] The carrier generating unit 5 generates a carrier signal based on the clock CLK. The square wave generating unit 6 generates a first square wave and a second square wave that are complementary to each other and synchronized with the carrier signal.

[0024] The multiplier 7a multiplies the voltage command value Vref by the amplitude of the first square wave to adjust the amplitude and generates voltage command values ​​for the third and fourth semiconductor elements X1 and Y1. The multiplier 7b multiplies the voltage command value Vref by the amplitude of the second square wave to adjust the amplitude and generates voltage command values ​​for the first and second semiconductor elements U1 and V1.

[0025] The comparator 8a generates gate signals for the third and fourth semiconductor elements X1 and Y1 by comparing the voltage command values ​​for the third and fourth semiconductor elements X1 and Y1 with the carrier signal. The comparator 8b generates gate signals for the first and second semiconductor elements U1 and V1 by comparing the voltage command values ​​for the first and second semiconductor elements U1 and V1 with the carrier signal.

[0026] The circuit in FIG. 2 estimates the switching frequency f by detecting the period of the gate signal of the semiconductor element to be driven, which is input from outside using the counter 3, and adjusts the output voltage.

[0027] This takes advantage of the fact that the power consumption during gate drive depends on the switching frequency. The power consumption pg of the gate drive circuit can be expressed by the following equation (1), where Qg is the gate charge, Vg is the gate voltage amplitude, and f is the switching frequency.

[0028]

number

[0029] As described above, a proportional relationship holds between the switching frequency f and the load power (power consumption) pg, and therefore, by adjusting the output voltage according to the switching frequency f, it is possible to control the output voltage of the pulse transformer Tr to a constant value regardless of the effects of inductance.

[0030] An example of the counter to be used is shown in Figure 3. The switching frequency f is measured by measuring the on-time and off-time of the gate signal using the counter 3 shown in Figure 3.

[0031] 3, the counter 3 includes first and second AND elements 9a and 9b, an ON counter circuit 10a, an OFF counter circuit 10b, and a frequency calculator 11. The ON counter circuit 10a measures the ON time of the gate signal, and the OFF counter circuit 10b measures the OFF time of the gate signal.

[0032] If the pulse width becomes longer (the frequency becomes lower), this can be accommodated by increasing the number of counter stages (number of bits).

[0033] The first AND element 9a receives an ON command and a clock CLK, and outputs 1 when both are 1, and outputs 0 otherwise. The second AND element 9b receives an OFF command and a clock CLK, and outputs 1 when both are 1, and outputs 0 otherwise.

[0034] Next, the ON counter circuit 10a will be described. The output of the first AND element 9a is input to clock terminals of a first D-type flip-flop circuit 12, a second D-type flip-flop circuit 13, and a third D-type flip-flop circuit 14 of the ON counter circuit 10a.

[0035] The output of a negative logic output terminal (hereinafter referred to as / Q terminal) of the first D-type flip-flop circuit 12 is input to a data terminal (hereinafter referred to as D terminal) of the first D-type flip-flop circuit 12. The output of a positive logic output terminal (hereinafter referred to as Q terminal) of the first D-type flip-flop circuit 12 is input to a frequency calculator 11.

[0036] The output of the Q terminal of the first D-type flip-flop circuit 12 and the output of the / Q terminal of the second D-type flip-flop circuit 13 are input to a third AND element 15, which outputs 1 when both are 1, and outputs 0 otherwise.

[0037] The output of the / Q terminal of the first D-type flip-flop circuit 12 and the output of the Q terminal of the second D-type flip-flop circuit 13 are input to a fourth AND element 16, which outputs 1 when both are 1, and outputs 0 otherwise.

[0038] The output of the third AND element 15 and the output of the fourth AND element 16 are input to the first OR element 17, which outputs 1 when at least one of them is 1, and outputs 0 when both are 0. The output of the first OR element 17 is input to the D terminal of the second D-type flip-flop circuit 13. The output of the Q terminal of the second D-type flip-flop circuit 13 is input to the frequency calculator 11.

[0039] The output of the Q terminal of the first D-type flip-flop circuit 12, the output of the Q terminal of the second D-type flip-flop circuit 13, and the output of the / Q terminal of the third D-type flip-flop circuit 14 are input to a fifth AND element 18, which outputs 1 when all of these are 1, and outputs 0 otherwise.

[0040] The output of the / Q terminal of the first D-type flip-flop circuit 12 and the output of the Q terminal of the third D-type flip-flop circuit 14 are input to a sixth AND element 19, which outputs 1 when both are 1, and outputs 0 otherwise.

[0041] The output of the / Q terminal of the second D-type flip-flop circuit 13 and the output of the Q terminal of the third D-type flip-flop circuit 14 are input to the seventh AND element 20, which outputs 1 when both are 1, and outputs 0 otherwise.

[0042] The outputs of the fifth AND element 18, the sixth AND element 19, and the seventh AND element 20 are input to a second OR element 21, which outputs 1 when at least one of them is 1, and outputs 0 when all are 0. The output of the second OR element 21 is input to a D terminal of a third D type flip-flop circuit 14. The output of a Q terminal of the third D type flip-flop circuit 14 is input to a frequency calculator 11.

[0043] The ON time of the gate signal can be measured from the output of the Q terminal of each of the first to third D-type flip-flop circuits 12 to .

[0044] The OFF counter circuit 10b has the same configuration as the ON counter circuit 10a, so a description thereof will be omitted. The OFF counter circuit 10b is similar to the ON counter circuit 10a except that the input of the OFF counter circuit 10b is the output of the second AND element 9b. The OFF time of the gate signal can be measured from the output of the Q terminal of the first to third D-type flip-flop circuits 12 to 14.

[0045] The ON counter circuit 10a and the OFF counter circuit 10b can calculate the time by multiplying the counted value by the clock frequency. For example, if the output of the first D-type flip-flop circuit 12 is 1, the output of the second D-type flip-flop circuit 13 is 0, and the output of the third D-type flip-flop circuit 14 is 0, the count number is 1, so the counted time is (2^0=1) x clock period, which is the ON time and the OFF time.

[0046] The frequency calculator 11 outputs a switching frequency f based on the outputs (on time, off time) of the first to third D-type flip-flop circuits 12 to 14 of the on-side counter circuit 10a and the off-side counter circuit 10b.

[0047] Next, a method for generating the voltage command value Vref will be described. The voltage command value calculator 4 in Fig. 2 generates the voltage command value Vref based on the switching frequency f calculated by the counter 3. If the maximum switching frequency of the device is fmax, the voltage command value Vref is given by the following equation (2).

[0048]

number

[0049] Here, the constant vref_i is the voltage command value when the DC voltage after rectification becomes the rated voltage (the maximum voltage that can be continuously operated) when the switching frequency f = 0. For vref_i, a value measured in advance under the above-mentioned conditions or a value determined by design shall be used.

[0050] The output voltage can be controlled by adjusting the voltage command value Vref as shown in Figure 4. Figure 4(a) shows the waveforms when the voltage command value Vref is 0, and Figure 4(b) shows the waveforms when the voltage command value Vref is greater than 0.

[0051] A first square wave for the voltage command value of the third and fourth semiconductor elements X1 and Y1 and a second square wave for the voltage command value of the first and second semiconductor elements U1 and V1 are generated based on a carrier signal. Furthermore, the first square wave and the second square wave are multiplied by the voltage command value Vref calculated by equation (2) (see FIG. 2). The value obtained by multiplying the first square wave by the voltage command value Vref becomes the voltage command value of the third and fourth semiconductor elements X1 and Y1, and the value obtained by multiplying the second square wave by the voltage command value Vref becomes the voltage command value of the first and second semiconductor elements U1 and V1.

[0052] At this time, the first square wave and the second square wave are generated from a carrier signal and are synchronized with the carrier signal. As shown in Fig. 4(b), the conduction state (gate signal) of the first and second semiconductor elements U1 and V1 is controlled by comparing the carrier signal with the voltage command values ​​of the first and second semiconductor elements U1 and V1. Also, the conduction state (gate signal) of the third and fourth semiconductor elements X1 and Y1 is controlled by comparing the carrier signal with the voltage command values ​​of the third and fourth semiconductor elements X1 and Y1.

[0053] When the voltage command values ​​for the third and fourth semiconductor elements X1, Y1 are greater than the carrier signal, the gate signal for the third semiconductor element X1 becomes an ON command, and the gate signal for the fourth semiconductor element Y1 becomes an OFF command.

[0054] When the voltage command values ​​for the third and fourth semiconductor elements X1, Y1 are smaller than the carrier signal, the gate signal for the third semiconductor element X1 becomes an OFF command, and the gate signal for the fourth semiconductor element Y1 becomes an ON command.

[0055] When the voltage command values ​​for the first and second semiconductor elements U1, V1 are greater than the carrier signal, the gate signal for the first semiconductor element U1 becomes an OFF command, and the gate signal for the second semiconductor element V1 becomes an ON command.

[0056] When the voltage command values ​​for the first and second semiconductor elements U1, V1 are smaller than the carrier signal, the gate signal for the first semiconductor element U1 becomes an ON command, and the gate signal for the second semiconductor element V1 becomes an OFF command.

[0057] In addition, by controlling the amplitude of the voltage command value for the first and second semiconductor elements U1, V1 and the voltage command value for the third and fourth semiconductor elements X1, Y1, it is possible to control the phase difference between the gate signals of the first and second semiconductor elements U1, V1 and the gate signals of the third and fourth semiconductor elements X1, Y1. When the amplitude of the voltage command value Vref is 0, the phase difference between the gate signals of the first and second semiconductor elements U1, V1 and the gate signals of the third and fourth semiconductor elements X1, Y1 is 0°.

[0058] In the case of FIG. 4(a), the phase difference between the gate signals of the first and second semiconductor elements U1, V1 and the gate signals of the third and fourth semiconductor elements X1, Y1 is 0°, so the voltage V applied to the pulse transformer Tr is a square wave.

[0059] In contrast, in this embodiment, the phase difference between the gate signals of the first and second semiconductor elements U1, V1 and the gate signals of the third and fourth semiconductor elements X1, Y1 is made greater than 0°, so that the voltage V applied to the pulse transformer Tr has a three-stage waveform. This makes it possible to reduce the effective value of the applied voltage, thereby reducing the excitation current and the effective value of the output voltage.

[0060] When the voltage command value Vref is 0, a square wave output voltage is output, so an output voltage corresponding to the DC voltage is output. On the other hand, when the voltage command value Vref is 0 or more, the output voltage becomes a three-stage waveform including a period when the output voltage is 0, so the output voltage can be reduced.

[0061] The magnitude of the output voltage V is controlled by adjusting the phase of the leg of the first and second semiconductor elements U1, V1 and the leg of the third and fourth semiconductor elements X1, Y1, which are switched at a duty of 50%, using the voltage command value Vref. That is, the first and second square waves are multiplied by the voltage command value Vref to obtain the voltage command value of the third and fourth semiconductor elements X1, Y1 and the voltage command value of the first and second semiconductor elements U1, V1, thereby adjusting the phase of the conductive state (gate signal) of the third and fourth semiconductor elements X1, Y1 and the conductive state (gate signal) of the first and second semiconductor elements U1, V1 to control the magnitude of the output voltage V. The maximum voltage output is achieved when the amplitude of the voltage command value Vref (voltage command value of the third and fourth semiconductor elements X1, Y1, voltage command value of the first and second semiconductor elements U1, V1) is 0.

[0062] According to this embodiment, the output voltage of the pulse transformer Tr can be kept constant without being affected by the wiring inductance by adjusting the output voltage according to the load power. As a result, it is possible to reduce the withstand voltage of the components constituting the gate drive circuit, thereby reducing costs, making the device smaller, and improving reliability.

[0063] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims. [Explanation of symbols]

[0064] 1a~1n...Toroidal core 2...First NOT element 3. Counter 4…Voltage command value calculator 5…Carrier generation section 6...Square wave generator 7a, 7b...First and second multipliers 8a, 8b…1st, 2nd comparator 9a, 9b...First and second AND elements 10a, 10b...On-side and off-side counter circuits 11...Frequency calculator 12-14: 1st to 3rd D-type flip-flop circuits 15, 16...3rd and 4th AND elements 17, 21...First and second OR elements 18~20: 5th~7th AND elements

Claims

1. A capacitor; a first semiconductor element and a second semiconductor element connected in series between the positive and negative electrodes of the capacitor; third and fourth semiconductor elements connected in series between the positive and negative electrodes of the capacitor; a pulse transformer having a primary winding connected between a connection point of the first and second semiconductor elements and a connection point of the third and fourth semiconductor elements, and a plurality of toroidal cores through which the primary winding passes; a control circuit that outputs gate signals to the first to fourth semiconductor elements; A power conversion device comprising: The control circuit includes: a counter that detects a period of the gate signal based on an on command and an off command of the gate signal of any one of the first to fourth semiconductor devices and a clock, and outputs a switching frequency; a voltage command value calculator that outputs a voltage command value based on the switching frequency; a carrier generating unit that outputs a carrier signal based on the clock; a square wave generating unit that outputs a first square wave and a second square wave that are complementary to each other based on the carrier signal; a first multiplier that multiplies the first square wave by the voltage command value to output voltage command values ​​for the third and fourth semiconductor elements; a second multiplier that multiplies the second square wave by the voltage command value to output voltage command values ​​for the first and second semiconductor elements; a first comparator that compares the voltage command values ​​of the third and fourth semiconductor elements with the carrier signal and outputs gate signals of the third and fourth semiconductor elements; a second comparator that compares the voltage command values ​​of the first and second semiconductor elements with the carrier signal to output gate signals of the first and second semiconductor elements; A power conversion device comprising:

2. The counter is a first AND element to which the ON command and the clock are input; a second AND element to which the off command and the clock are input; an ON-side counter circuit that measures an ON time of the gate signal based on an output of the first AND element; an OFF-side counter circuit that measures an OFF time of the gate signal based on an output of the second AND element; a frequency calculator that calculates the switching frequency based on the on-time and the off-time, The on-side counter circuit and the off-side counter circuit each include a first D-type flip-flop circuit having a clock terminal to which an output of the first AND element or the second AND element is input, a data terminal to which an output of a negative logic output terminal is input, and a positive logic output terminal to which an output of the positive logic output terminal is output to the frequency calculator; a third AND element to which an output from a positive logic output terminal of the first D-type flip-flop circuit and an output from a negative logic output terminal of the second D-type flip-flop circuit are input; a fourth AND element to which an output from a negative logic output terminal of the first D-type flip-flop circuit and an output from a positive logic output terminal of the second D-type flip-flop circuit are input; a first OR element to which an output of the third AND element and an output of the fourth AND element are input; the second D-type flip-flop circuit, which has a data terminal to which an output of the first OR element is input, a clock terminal to which an output of the first AND element or the second AND element is input, and a positive logic output terminal to which an output of the positive logic output terminal is output to the frequency calculator; a fifth AND element to which an output from a positive logic output terminal of the first D-type flip-flop circuit, an output from a positive logic output terminal of the second D-type flip-flop circuit, and an output from a negative logic output terminal of a third D-type flip-flop circuit are input; a sixth AND element to which an output from a negative logic output terminal of the first D-type flip-flop circuit and an output from a positive logic output terminal of the third D-type flip-flop circuit are input; a seventh AND element to which an output from a negative logic output terminal of the second D-type flip-flop circuit and an output from a positive logic output terminal of the third D-type flip-flop circuit are input; a second OR element receiving an output of the fifth AND element, an output of the sixth AND element, and an output of the seventh AND element; the third D-type flip-flop circuit, which has a data terminal to which an output of the second OR element is input, a clock terminal to which an output of the first AND element or the second AND element is input, and a positive logic output terminal to which an output of the positive logic output terminal is output to the frequency calculator; 2. The power conversion device according to claim 1, further comprising:

3. 3. The power conversion device according to claim 1, wherein the voltage command value calculator calculates the voltage command value according to the following equation (2): [0025] Vref: voltage command value f: switching frequency vref_i: voltage command value when the rectified DC voltage becomes the rated voltage when the switching frequency f = 0 fmax: maximum switching frequency

4. A capacitor; a first semiconductor element and a second semiconductor element connected in series between the positive and negative electrodes of the capacitor; third and fourth semiconductor elements connected in series between the positive and negative electrodes of the capacitor; a pulse transformer having a primary winding connected between a connection point of the first and second semiconductor elements and a connection point of the third and fourth semiconductor elements, and a plurality of toroidal cores through which the primary winding passes; a control circuit that outputs gate signals to the first to fourth semiconductor elements; A control method for a power conversion device comprising: The control circuit includes: a counter detects a period of the gate signal based on an on command and an off command of the gate signal of any one of the first to fourth semiconductor devices and a clock, and outputs a switching frequency; a voltage command value calculator outputs a voltage command value based on the switching frequency; a carrier generating unit that outputs a carrier signal based on the clock; a square wave generating unit outputs a first square wave and a second square wave in a complementary relationship based on the carrier signal; a first multiplier multiplying the first square wave by the voltage command value to output voltage command values ​​for the third and fourth semiconductor elements; a second multiplier multiplying the second square wave by the voltage command value to output voltage command values ​​for the first and second semiconductor elements; a first comparator that compares the voltage command values ​​of the third and fourth semiconductor elements with the carrier signal and outputs gate signals of the third and fourth semiconductor elements; A second comparator compares the voltage command values ​​of the first and second semiconductor elements with the carrier signal and outputs gate signals for the first and second semiconductor elements. A method for controlling a power conversion device comprising:

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