Switch actuator

Abstract

To provide a device for driving a switch capable of shortening dead time without adding a dedicated transmission part for transferring a switching state.SOLUTION: In a drive device, a lower arm drive IC 40L, when it is determined that a lower arm switch SWL is in an OFF state, outputs a lower arm OFF notification signal to a lower arm second isolator 74. An upper arm filter part 52 outputs an upper arm filter signal GLntF on the basis of the lower arm OFF notification signal output from the lower arm second isolator 74. An upper arm AND circuit 51, when the upper arm filter signal GLntF is logic H and an upper arm main drive signal GH* from a microcomputer 30 is an ON command, outputs an upper arm drive signal GHr of an ON command to an upper arm first isolator 53.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a switch drive device that drives an upper arm switch and a lower arm switch. [Background technology]

[0002] As this type of drive device, a switch drive device including an upper arm drive unit that drives an upper arm switch and a lower arm drive unit that drives a lower arm switch is known. The upper arm drive unit drives the upper arm switch based on an upper arm drive signal, and the lower arm drive unit drives the lower arm switch based on a lower arm drive signal. In order to prevent a short circuit between the upper and lower arms, the upper arm drive signal input to the upper arm drive unit and the lower arm drive signal input to the lower arm drive unit are alternately commanded to be on with a dead time therebetween.

[0003] In order to reduce the dead time, it is necessary to quickly grasp that the lower arm switch has been switched to the OFF state so that the upper arm switch can be switched to the ON state, and it is necessary to quickly grasp that the upper arm switch has been switched to the OFF state so that the lower arm switch can be switched to the ON state. Patent Document 1 describes a technology in which a signal that notifies the upper arm driver of the switching state of the lower arm switch in advance is input to the upper arm driver, and a signal that notifies the lower arm driver of the switching state of the upper arm switch in advance is input to the lower arm driver. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-96444 A Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, the upper and lower arm drive units are provided in the high voltage region, and a signal generating unit (e.g., a microcomputer) that generates the upper and lower arm drive signals is provided in the low voltage region. Therefore, in order to transmit the upper and lower arm drive signals to the upper and lower arm drive units, the drive device is provided with a transmitting unit (e.g., an isolator) that transmits signals from the low voltage region to the high voltage region while electrically insulating the low voltage region from the high voltage region.

[0006] A transmission unit is required to transmit a signal notifying in advance of the switching state of the lower arm switch to the upper arm drive unit, and a transmission unit is also required to transmit a signal notifying in advance of the switching state of the upper arm switch to the lower arm drive unit. If a dedicated transmission unit for transmitting switching timing is added to the drive unit, the number of components of the drive unit will increase, and there is a concern that the size of the drive unit will increase.

[0007] A main object of the present invention is to provide a switch drive device capable of shortening the dead time without adding a dedicated transmission section for transmitting the switching state. [Means for solving the problem]

[0008] The present invention relates to a switch drive device for driving an upper arm switch and a lower arm switch, a control unit provided in a first region and configured to output an upper arm main drive signal and a lower arm main drive signal such that the upper arm switch and the lower arm switch are alternately turned on with a dead time therebetween; an upper arm processing unit provided in the first area and configured to output an upper arm drive signal based on the upper arm main drive signal input from the control unit; an upper arm first transmission unit that transmits the upper arm drive signal output from the upper arm processing unit to the second region while electrically insulating the first region and the second region; an upper arm drive unit provided in the second region, which turns the upper arm switch on when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an on command, and turns the upper arm switch off when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an off command; an upper arm second transmission section that transmits a signal including predetermined information of the upper arm switch from the second region side to the first region side while electrically insulating the first region and the second region; a lower arm processing unit provided in the first area and configured to output a lower arm drive signal based on the lower arm main drive signal input from the control unit; a lower arm first transmission unit that transmits the lower arm drive signal output from the lower arm processing unit to the second region while electrically insulating the first region and the second region; a lower arm drive unit provided in the second area, which turns the lower arm switch on when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an on command, and turns the lower arm switch off when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an off command; a lower arm second transmission section that transmits a signal including predetermined information of the lower arm switch from the second region side to the first region side while electrically insulating the first region and the second region; Equipped with When the lower arm drive unit determines that the lower arm switch is in an off state, the lower arm drive unit outputs a lower arm off notification signal indicating that the lower arm switch is in an off state to the lower arm second transmission unit, The upper arm processing section includes: when it is determined that the lower arm switch is in an OFF state based on the lower arm OFF notification signal input via the lower arm second transmission section and when it is determined that the upper arm main drive signal input from the control section is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission section; When it is determined that the upper arm main drive signal input from the control unit is an OFF command, the upper arm drive signal of an OFF command is output to the upper arm first transmission unit, When the upper arm drive unit determines that the upper arm switch is in an off state, the upper arm drive unit outputs an upper arm off notification signal indicating that the upper arm switch is in an off state to the upper arm second transmission unit, The lower arm processing unit is when it is determined that the upper arm switch is in an OFF state based on the upper arm OFF notification signal input via the upper arm second transmission section and that the lower arm main drive signal input from the control section is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission section; When it is determined that the lower arm main drive signal input from the control unit is an OFF command, the lower arm drive signal of an OFF command is output to the lower arm first transmission unit.

[0009] In the present invention, a lower arm off notification signal indicating that the lower arm switch is in the off state is input to an upper arm processing unit that generates an upper arm drive signal via a lower arm second transmission unit that transmits a signal including predetermined information of the lower arm switch. Also, an upper arm off notification signal indicating that the upper arm switch is in the off state is input to a lower arm processing unit that generates a lower arm drive signal via an upper arm second transmission unit that transmits a signal including predetermined information of the upper arm switch. In other words, the transmission unit for transmitting the predetermined information can also be used for transmitting the off notification signal. Therefore, the dead time can be shortened without adding a transmission unit dedicated to transmitting the off state. [Brief description of the drawings]

[0010] [Figure 1] 1 is an overall configuration diagram of a control system according to a first embodiment. [Diagram 2] A diagram showing the configuration of a microcontroller, an interface, and a drive IC. [Diagram 3] 4 is a time chart showing the transitions of the upper and lower arm main drive signals GH*, GL*, etc. [Figure 4] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an on state; [Diagram 5] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an off state; [Figure 6] FIG. 13 is a diagram showing the configuration of a microcomputer, an interface, and a drive IC according to a second embodiment. [Figure 7] 4 is a time chart showing the transitions of the upper and lower arm main drive signals GH*, GL*, etc. [Figure 8] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an on state; [Figure 9] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an off state; [Figure 10] FIG. 13 is a diagram showing the configuration of a microcomputer, an interface, and a drive IC according to a third embodiment. [Figure 11] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an on state; [Figure 12] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an off state; [Figure 13] FIG. 13 is a diagram showing the configuration of a microcomputer, an interface, and a drive IC according to a fourth embodiment. [Figure 14] 4 is a time chart showing transitions of the lower arm signals GLnt and the like when the lower arm switch is in an on state; [Figure 15] 4 is a time chart showing changes in the lower arm signal GLnt etc. when the lower arm switch is in the off state and in an abnormal state. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] First Embodiment A first embodiment of the drive device according to the present invention will be described below with reference to the drawings. A control system equipped with the drive device of this embodiment can be applied to a moving body, a robot (e.g., an industrial robot), a generator, an elevator, etc. The moving body is, for example, an automobile, an aircraft, a ship, or a railroad car.

[0012] As shown in Fig. 1, the control system includes a rotating electric machine 10, an inverter 20, and a DC power supply 21. In this embodiment, the rotating electric machine 10 includes a star-connected three-phase winding 11. The rotating electric machine 10 is, for example, a synchronous machine. When the control system is applied to an automobile, the rotating electric machine 10 may be an in-wheel motor integrally provided on a driving wheel of the automobile, or an on-board motor provided on the body of the automobile, or may be integrated with the inverter 20 and a transmission (not shown).

[0013] The rotating electric machine 10 is connected to a DC power source 21 via an inverter 20. The DC power source 21 is, for example, a secondary battery. The inverter 20 includes a smoothing capacitor 22. The smoothing capacitor 22 may be provided outside the inverter 20.

[0014] The inverter 20 includes a series connection of upper and lower arm switches SWH, SWL of U, V, and W phases. In this embodiment, each switch SWH, SWL is an N-channel MOSFET. Each switch SWH, SWL has a body diode. In each switch SWH, SWL of this embodiment, the high potential side terminal is the drain, and the low potential side terminal is the source. Each switch SWH, SWL may be an IGBT. In this case, a freewheel diode may be connected in inverse parallel to each switch SWH, SWL.

[0015] In each phase, a first end of the winding 11 is connected to a connection point between the source of the upper arm switch SWH and the drain of the lower arm switch SWL. A second end of the winding 11 in each phase is connected to a neutral point.

[0016] The control system includes a microcomputer 30 (corresponding to a "control unit"), an interface 50, and upper and lower arm drive ICs 40H and 40L. The microcomputer 30 performs switching control of the switches SWH and SWL of the inverter 20 to control the control amount of the rotating electric machine 10 to a command value. The control amount is, for example, torque. The microcomputer 30 generates upper and lower arm main drive signals GH* and GL* corresponding to the upper and lower arm switches SWH and SWL in each phase to alternately turn the upper and lower arm switches SWH and SWL on, and outputs them to the interface 50. In this embodiment, each main drive signal GH* and GL* indicates an on command with a logical H and indicates an off command with a logical L.

[0017] The microcomputer 30 is provided in a low voltage region (corresponding to the "first region"), while the rotating electric machine 10, the switches SWH, SWL, the upper and lower arm drive ICs 40H, 40L, the DC power supply 21, and the smoothing capacitor 22 are provided in a high voltage region (corresponding to the "second region").

[0018] Next, the microcomputer 30, the interface 50, and the upper and lower arm drive ICs 40H, 40L will be described with reference to FIG.

[0019] The interface 50 includes an upper arm AND circuit 51, an upper arm filter unit 52, and an upper arm first isolator 53. The upper arm AND circuit 51 and the upper arm filter unit 52 are provided in a low voltage region. In this embodiment, the upper arm AND circuit 51 and the upper arm filter unit 52 correspond to an "upper arm processing unit", and the upper arm first isolator 53 corresponds to an "upper arm first transmission unit".

[0020] The upper arm AND circuit 51 receives the upper arm main drive signal GH* output from the microcomputer 30 and an output signal of the upper arm filter unit 52 (hereinafter, upper arm filter signal GLntF). When the logic of the upper arm main drive signal GH* and the logic of the upper arm filter signal GLntF are H, the upper arm AND circuit 51 outputs an upper arm drive signal GHr of logic H indicating an ON command. On the other hand, when at least one of the logic of the upper arm main drive signal GH* and the logic of the upper arm filter signal GLntF is L, the upper arm AND circuit 51 outputs an upper arm drive signal GHr of logic L indicating an OFF command. The upper arm drive signal GHr is input to the upper arm first isolator 53.

[0021] The upper arm first isolator 53 is provided to straddle the low voltage region and the high voltage region. The upper arm first isolator 53 transmits the upper arm drive signal GHr output from the upper arm AND circuit 51 to the high voltage region while electrically insulating the low voltage region and the high voltage region. In this embodiment, the upper arm first isolator 53 is a digital isolator, for example, a magnetic insulation type isolator having a coil or a capacitive insulation type isolator having a capacitor. Note that the upper arm first isolator 53 may be, for example, a photocoupler of an optical insulation type instead of a digital isolator.

[0022] The control system includes an upper arm drive IC 40H and an upper arm temperature detector 41H. An upper arm drive signal GHr is input to the upper arm drive IC 40H from the upper arm first isolator 53. When the upper arm drive IC 40H determines that the input upper arm drive signal GHr is an ON command, the upper arm drive IC 40H charges the gate charge of the upper arm switch SWH, and makes the gate voltage of the upper arm switch SWH equal to or higher than the threshold voltage Vth. This switches the upper arm switch SWH to the ON state. On the other hand, when the upper arm drive IC 40H determines that the input upper arm drive signal GHr is an OFF command, the upper arm drive IC 40H discharges the gate charge of the upper arm switch SWH, and makes the gate voltage of the upper arm switch SWH less than the threshold voltage Vth. This switches the upper arm switch SWH to the OFF state.

[0023] The upper arm temperature detector 41H is provided in the high voltage region. The upper arm temperature detector 41H detects the temperature of the upper arm switch SWH and outputs the temperature to the upper arm drive IC 40H. In this embodiment, the upper arm temperature detector 41H is a thermistor. The upper arm temperature detector 41H may be, for example, a temperature sensing diode.

[0024] The upper arm drive IC 40H detects the gate voltage VgH of the upper arm switch SWH.

[0025] The interface 50 includes an upper arm second isolator 54. The upper arm second isolator 54 is provided so as to straddle the low voltage region and the high voltage region. The upper arm second isolator 54 transmits the upper arm signal GHnt output from the upper arm drive IC 40H to the low voltage region while electrically insulating between the low voltage region and the high voltage region. In this embodiment, the upper arm second isolator 54 is a digital isolator, for example, a magnetic insulation type isolator including a coil or a capacitive insulation type isolator including a capacitor. Note that the upper arm second isolator 54 may be, for example, a photocoupler of an optical insulation type instead of a digital isolator. In addition, in this embodiment, the upper arm second isolator 54 corresponds to the "upper arm second transmission unit".

[0026] The interface 50 includes an upper arm buffer circuit 55. The upper arm buffer circuit 55 is provided in a low voltage region. The upper arm buffer circuit 55 outputs the upper arm signal GHnt output from the upper arm second isolator 54 to the microcomputer 30 as an upper arm temperature signal THnt.

[0027] The interface 50 includes a lower arm AND circuit 71, a lower arm filter unit 72, and a lower arm first isolator 73. The lower arm AND circuit 71 and the lower arm filter unit 72 are provided in a low-voltage region. In this embodiment, the lower arm AND circuit 71 and the lower arm filter unit 72 correspond to a "lower arm processing unit", and the lower arm first isolator 73 corresponds to a "lower arm first transmission unit".

[0028] The lower arm AND circuit 71 receives the lower arm main drive signal GL* output from the microcomputer 30 and an output signal of the lower arm filter unit 72 (hereinafter, referred to as the lower arm filter signal GHntF). When the logic of the lower arm main drive signal GL* and the logic of the output signal GHntF of the lower arm filter unit 72 are H, the lower arm AND circuit 71 outputs a lower arm drive signal GLr of logic H indicating an ON command. On the other hand, when at least one of the logic of the lower arm main drive signal GL* and the logic of the output signal GHntF of the lower arm filter unit 72 is L, the lower arm AND circuit 71 outputs a lower arm drive signal GLr of logic L indicating an OFF command. The lower arm drive signal GLr is input to the lower arm first isolator 73.

[0029] The lower-arm first isolator 73 is provided to straddle the low-voltage region and the high-voltage region. The lower-arm first isolator 73 transmits the lower-arm drive signal GLr output from the lower-arm AND circuit 71 to the high-voltage region while electrically insulating the low-voltage region and the high-voltage region. In this embodiment, the lower-arm first isolator 73 is a digital isolator of a magnetic insulation type having a coil or a capacitive insulation type having a capacitor, similar to the upper-arm first isolator 53. Note that the lower-arm first isolator 73 may be, for example, a photocoupler of an optical isolation type instead of a digital isolator.

[0030] The control system includes a lower arm drive IC 40L and a lower arm temperature detection unit 41L. A lower arm drive signal GLr is input to the lower arm drive IC 40L from the lower arm first isolator 73. When the lower arm drive IC 40L determines that the input lower arm drive signal GLr is an ON command, the lower arm drive IC 40L charges the gate charge of the lower arm switch SWL, and makes the gate voltage of the lower arm switch SWL equal to or higher than the threshold voltage Vth. This switches the lower arm switch SWL to the ON state. On the other hand, when the lower arm drive IC 40L determines that the input lower arm drive signal GLr is an OFF command, the lower arm drive IC 40L discharges the gate charge of the lower arm switch SWL, and makes the gate voltage of the lower arm switch SWL less than the threshold voltage Vth. This switches the lower arm switch SWL to the OFF state.

[0031] The lower arm temperature detection unit 41L is provided in the high voltage region. The lower arm temperature detection unit 41L detects the temperature of the lower arm switch SWL and outputs the temperature to the lower arm drive IC 40L. In this embodiment, the lower arm temperature detection unit 41L is a thermistor. The lower arm temperature detection unit 41L may be, for example, a temperature sensing diode.

[0032] The lower-arm drive IC 40L detects the gate voltage VgL of the lower-arm switch SWL.

[0033] The interface 50 includes a lower arm second isolator 74. The lower arm second isolator 74 is provided so as to straddle the low voltage region and the high voltage region. The lower arm second isolator 74 transmits the signal GLnt output from the lower arm drive IC 40L to the low voltage region while electrically insulating between the low voltage region and the high voltage region. In this embodiment, the lower arm second isolator 74 is a digital isolator such as a magnetic insulation type having a coil or a capacitive insulation type having a capacitor, similar to the upper arm second isolator 54. Note that the lower arm second isolator 74 may be, for example, a photocoupler of an optical insulation type instead of a digital isolator. In addition, in this embodiment, the lower arm second isolator 74 corresponds to the "lower arm second transmission unit".

[0034] The interface 50 includes a lower arm buffer circuit 75. The lower arm buffer circuit 75 is provided in a low voltage region. The lower arm buffer circuit 75 outputs the lower arm signal GLnt output from the lower arm second isolator 74 to the microcomputer 30 as a lower arm temperature signal TLnt.

[0035] The microcomputer 30, the interface 50, the upper and lower arm drive ICs 40H and 40L, the upper arm temperature detector 41H, and the lower arm temperature detector 41L are provided on a control board.

[0036] As shown in Fig. 3(a) and (b), each of the main drive signals GH* and GL* generated by the microcomputer 30 becomes an ON command once in the switching period Tsw of each of the switches SWH and SWL. In the example shown in Fig. 3, the timing at which the upper arm main drive signal GH* changes to an ON command and the timing at which the lower arm main drive signal GL* changes to an OFF command are set to the same timing. Also, the timing at which the upper arm main drive signal GH* changes to an OFF command and the timing at which the lower arm main drive signal GL* changes to an ON command are set to the same timing. However, this is not limited to this setting, and the timing at which the upper arm main drive signal GH* changes to an ON command may be delayed by a predetermined period with respect to the timing at which the lower arm main drive signal GL* changes to an OFF command. The predetermined period is a period that is very short with respect to the switching period Tsw.

[0037] Returning to the explanation of Fig. 2, the upper arm filter unit 52 receives the lower arm signal GLnt output from the lower arm second isolator 74. The lower arm filter unit 72 receives the upper arm signal GHnt output from the upper arm second isolator 54. Each filter unit 52, 72 outputs a signal obtained by delaying a change in the input signal by performing low-pass filtering on the input signal. The low-pass filter is, for example, a first-order or second-order lag filter, and is an RC filter in this embodiment.

[0038] Next, the transmission of the OFF notification signal by the upper and lower arm drive ICs 40H and 40L will be described. First, the lower arm drive IC 40L will be described.

[0039] The lower-arm drive IC 40L determines whether the lower-arm switch SWL is in the OFF state based on the detected gate voltage VgL. In this embodiment, if the lower-arm drive IC 40L determines that the detected gate voltage VgL is less than the threshold voltage Vth, it determines that the lower-arm switch SWL is in the OFF state, and if the detected gate voltage VgL is equal to or greater than the threshold voltage Vth, it determines that the lower-arm switch SWL is in the ON state.

[0040] When the lower-arm drive IC 40L determines that the lower-arm switch SWL is in the on state, it outputs a lower-arm pulse signal in which H and L are repeated at a predetermined period Td as the lower-arm signal GLnt to the lower-arm second isolator 74 as shown in Fig. 4(a). In this embodiment, for convenience, the voltage level of H is set to 5 V and the voltage level of L is set to 0 V. The predetermined period Td is sufficiently shorter than the switching period Tsw.

[0041] The lower arm pulse signal is a signal that includes temperature information of the lower arm switch SWL. In this embodiment, the number of pulses included in the lower arm pulse signal in a temperature detection period that is sufficiently longer than the predetermined period Td is correlated with the temperature detected by the lower arm temperature detection unit 41L. For example, the lower arm drive IC 40L increases the number of pulses in the temperature detection period as the detected temperature increases. The temperature detection period is, for example, a time of an order different from that of the predetermined period Td. For example, when the predetermined period Td is on the order of μsec, the temperature detection period is on the order of sec or msec. When it is msec, the temperature detection period and the predetermined period Td differ by an order of 10^3.

[0042] Fig. 4(b) shows the transition of the lower arm temperature signal TLnt when a lower arm pulse signal is output from the lower arm drive IC 40L. The microcomputer 30 counts the number of pulses of the lower arm temperature signal TLnt in a temperature detection period, and calculates the temperature of the lower arm switch SWL based on the counted number of pulses. When the microcomputer 30 determines that the calculated temperature exceeds a temperature threshold value, it issues an OFF command to the upper and lower arm main drive signals GH* and GL*, for example. The arrow shown in Fig. 4(b) indicates the timing at which the microcomputer 30 acquires the lower arm temperature signal TLnt.

[0043] FIG. 4(c) shows the transition of the output signal SLF of the low-pass filter of the upper arm filter unit 52 when the lower arm pulse signal is output from the lower arm drive IC 40L. When the output signal SLF is equal to or less than the judgment threshold Jth, the upper arm filter unit 52 outputs the upper arm filter signal GLntF of L. On the other hand, when the output signal SLF exceeds the judgment threshold Jth, the upper arm filter unit 52 outputs the upper arm filter signal GLntF of H. When the lower arm pulse signal is input to the upper arm filter unit 52, the time constant of the low-pass filter of the upper arm filter unit 52 is set so that the output signal SLF does not exceed the judgment threshold Jth during the period from when the lower arm pulse signal input to the upper arm filter unit 52 is switched to H (5V) until a predetermined period Td has elapsed. That is, when the lower arm pulse signal is input to the upper arm filter unit 52, the upper arm filter signal GLntF is maintained at L. When the lower arm pulse signal becomes L, the upper arm filter unit 52 sets the upper arm filter signal GLntF to 0V.

[0044] When the upper arm filter signal GLntF is maintained at L, the upper arm drive signal GHr output from the upper arm AND circuit 51 is maintained at L (OFF command). In other words, when it is determined that the lower arm switch SWL is in the ON state, the upper arm switch SWH is prohibited from being switched to the ON state.

[0045] When the lower arm drive IC 40L determines that the lower arm switch SWL is in the off state, it outputs a lower arm off notification signal fixed to logical H as the lower arm signal GLnt to the lower arm second isolator 74, as shown in Figure 5 (a).

[0046] 5(b) shows the transition of the lower arm temperature signal TLnt when a lower arm off notification signal is output from the lower arm drive IC 40L. If the lower arm temperature signal TLnt does not contain a pulse signal, the microcomputer 30 does not execute the temperature calculation process of the lower arm switch SWL based on the lower arm temperature signal TLnt.

[0047] 5(c) shows the transition of the output signal SLF of the low-pass filter of the upper arm filter unit 52 when the lower arm off notification signal is output from the lower arm drive IC 40L. When the lower arm off notification signal is input to the upper arm filter unit 52, the output signal SLF exceeds the judgment threshold Jth. That is, the upper arm filter signal GLntF is maintained at H (5V). In this case, the upper arm drive signal GHr output from the upper arm AND circuit 51 is switched to an ON command (H) as the upper arm main drive signal GH* from the microcomputer 30 is switched to an ON command (H). That is, when it is determined that the lower arm switch SWL is in the OFF state, the upper arm switch SWH is permitted to be switched to the ON state.

[0048] Next, the upper arm drive IC 40H will be described. Note that the process of the upper arm drive IC 40H is similar to the process of the lower arm drive IC 40L, so the description will be omitted as appropriate.

[0049] The upper arm drive IC 40H determines whether the upper arm switch SWH is in the OFF state based on the detected gate voltage VgH. If the upper arm drive IC 40H determines that the detected gate voltage VgH is less than the threshold voltage Vth, it determines that the upper arm switch SWH is in the OFF state, and if the upper arm drive IC 40H determines that the detected gate voltage VgH is equal to or greater than the threshold voltage Vth, it determines that the upper arm switch SWH is in the ON state.

[0050] When the upper arm drive IC 40H determines that the upper arm switch SWH is in the on state, it outputs an upper arm pulse signal in which H and L are repeated at a predetermined period Td, similar to the signal in Figure 4 (a), as the upper arm signal GHnt to the upper arm second isolator 54.

[0051] The upper arm pulse signal is a signal that includes temperature information of the upper arm switch SWH. In this embodiment, the number of pulses included in the upper arm pulse signal in a temperature detection period that is sufficiently longer than the predetermined period Td is associated with the temperature detected by the upper arm temperature detector 41H. For example, the upper arm drive IC 40H increases the number of pulses in the temperature detection period as the detected temperature increases.

[0052] 4(b), the microcomputer 30 counts the number of pulses of the upper arm temperature signal THnt in a temperature detection cycle and calculates the temperature of the upper arm switch SWH based on the counted number of pulses. When the microcomputer 30 determines that the calculated temperature exceeds the temperature threshold, it issues an OFF command to the upper and lower arm main drive signals GH* and GL*, for example.

[0053] When the output signal SHF of the low-pass filter of the lower arm filter unit 72 is equal to or less than the judgment threshold Jth, the lower arm filter unit 72 outputs a lower arm filter signal GHntF of L. On the other hand, when the output signal SHF of the lower arm filter unit 72 exceeds the judgment threshold Jth, the lower arm filter unit 72 outputs a lower arm filter signal GHntF of H. As in the case shown in FIG. 4(c), when an upper arm pulse signal is input to the lower arm filter unit 72, the time constant of the low-pass filter of the lower arm filter unit 72 is set so that the output signal SHF of the low-pass filter of the lower arm filter unit 72 does not exceed the judgment threshold Jth during the period from when the upper arm pulse signal input to the lower arm filter unit 72 is switched to H until a predetermined period Td has elapsed. In other words, when an upper arm pulse signal is input to the lower arm filter unit 72, the lower arm filter signal GHntF is maintained at L. When the upper arm pulse signal becomes L, the lower arm filter unit 72 sets the lower arm filter signal GHntF to 0 V.

[0054] When the lower arm filter signal GHntF is maintained at L, the lower arm drive signal GLr output from the lower arm AND circuit 71 is maintained at L. In other words, when it is determined that the upper arm switch SWH is in the on state, the lower arm switch SWL is prohibited from being switched on.

[0055] When the upper arm drive IC 40H determines that the upper arm switch SWH is in the off state, it outputs an upper arm off notification signal fixed to logical H as the upper arm signal GHnt to the upper arm second isolator 54, as shown in Figure 5(a).

[0056] As in the case shown in FIG. 5(b), when the upper arm temperature signal THnt does not contain a pulse signal, the microcomputer 30 does not execute the process of calculating the temperature of the upper arm switch SWH based on the upper arm temperature signal THnt.

[0057] 5(c), when an upper arm off notification signal is input to the lower arm filter unit 72, the output signal SHF of the low-pass filter of the lower arm filter unit 72 exceeds the judgment threshold Jth. That is, the lower arm filter signal GHntF is maintained at H (5V). In this case, the lower arm drive signal GLr output from the lower arm AND circuit 71 is switched to an ON command (H) as the lower arm main drive signal GL* from the microcomputer 30 is switched to an ON command (H). That is, when it is determined that the upper arm switch SWH is in the OFF state, the lower arm switch SWL is permitted to be switched to the ON state.

[0058] As described above, in this embodiment, the lower arm off notification signal is input to the upper arm filter unit 52 via the lower arm second isolator 74 that transmits the temperature signal of the lower arm switch SWL. Also, the upper arm off notification signal is input to the lower arm filter unit 72 via the upper arm second isolator 54 that transmits the temperature signal of the upper arm switch SWH. That is, the isolator for transmitting temperature information can also be used for transmitting the off notification signal. Therefore, the dead time can be shortened without adding a dedicated isolator to the interface 50 for transmitting the off state. Also, since there is no need to add a dedicated isolator, the circuit area on the control board can be reduced, and thus the cost of the control system can be reduced.

[0059] The lower arm drive IC 40L outputs a lower arm pulse signal including temperature information of the lower arm switch SWL when the lower arm switch SWL is in the ON state. The temperature of the lower arm switch SWL rises when the lower arm switch SWL is in the ON state and a drain current flows. Therefore, when the lower arm switch SWL is in the ON state, the microcomputer 30 can calculate the temperature of the lower arm switch SWL, and it can be accurately determined whether or not the lower arm switch SWL is overheated. The same applies to the upper arm drive IC 40H.

[0060] <Modification of the first embodiment> The lower arm pulse signal may be a signal in which the duty, which is the ratio of the period of H to the predetermined cycle Td, is associated with the temperature detected by the lower arm temperature detector 41L. In this case, the microcomputer 30 can obtain the temperature of the lower arm switch SWL every predetermined cycle Td. The same applies to the upper arm pulse signal.

[0061] The period of the lower arm pulse signal and the period of the upper arm pulse signal may be different.

[0062] The upper and lower arm off notification signals may be signals fixed at L. In this case, the configuration of each of the filter sections 52 and 72 may be appropriately changed so that the switch off state can be grasped.

[0063] The decision threshold value Jth used in the upper arm filter section 52 and the decision threshold value Jth used in the lower arm filter section 72 may be different.

[0064] <Second embodiment> The second embodiment will be described below with reference to the drawings, focusing on the differences from the first embodiment. Figure 6 shows the configuration of the interface 50 and other components of this embodiment. In Figure 6, the same components as those shown in Figure 2 are denoted by the same reference numerals for convenience.

[0065] In this embodiment, the upper arm second isolator 56 and the lower arm second isolator 76 are isolation amplifiers. The isolation amplifier is an amplifier that can transmit an analog voltage while electrically isolating between a high voltage region and a low voltage region. An upper arm signal GHnt of the upper arm drive IC 40H is input to the upper arm second isolator 56, and a lower arm signal GLnt of the lower arm drive IC 40L is input to the lower arm second isolator 76. In this embodiment, the gain of the output signal Vout with respect to the input signal Vin of the isolation amplifier is 1 (Vout / Vin=1).

[0066] The interface 50 includes upper and lower arm comparators 57 and 77. Each of the comparators 57 and 77 is provided in a low-voltage region. A lower arm output signal GLamp, which is an output signal of the lower arm second isolator 76, is input to a non-inverting input terminal of the upper arm comparator 57. A decision threshold Jth is input to an inverting input terminal of the upper arm comparator 57. An upper arm output signal GHamp, which is an output signal of the upper arm second isolator 56, is input to a non-inverting input terminal of the lower arm comparator 77. A decision threshold Jth is input to an inverting input terminal of the lower arm comparator 77. In this embodiment, the decision threshold Jth input to each of the comparators 57 and 77 is set to a value different from the decision threshold Jth of the first embodiment.

[0067] An upper arm filter signal GLntF, which is an output signal of the upper arm comparator 57, is input to the upper arm AND circuit 51. A lower arm filter signal GHntF, which is an output signal of the lower arm comparator 77, is input to the lower arm AND circuit 71. In this embodiment, the upper arm AND circuit 51 and the upper arm comparator 57 correspond to an "upper arm processing unit", and the lower arm AND circuit 71 and the lower arm comparator 77 correspond to a "lower arm processing unit".

[0068] Next, the transmission of the OFF notification signal by the upper and lower arm drive ICs 40H and 40L will be described. First, the lower arm drive IC 40L will be described.

[0069] Regardless of the determination result of whether the lower arm switch SWL is in the on state or the off state, the lower arm drive IC 40L outputs a lower arm pulse signal in which H and L are repeated at a predetermined period Td as the lower arm signal GLnt to the lower arm second isolator 76 as shown in Figures 7 to 9. The lower arm pulse signal includes temperature information of the lower arm switch SWL, as in the first embodiment.

[0070] When the lower-arm drive IC 40L determines that the lower-arm switch SWL is in the on state, it sets the reference potential of the lower-arm pulse signal to 0V (corresponding to the "first reference potential") as shown in FIG. 8(a).

[0071] On the other hand, when the lower arm drive IC 40L determines that the lower arm switch SWL is in the off state, as shown in Figure 9(a), it sets the reference potential of the lower arm pulse signal to an intermediate potential between H and L (corresponding to the "second reference potential"), which in this embodiment is 2.5 V.

[0072] 8(b) shows the transition of the lower arm temperature signal TLnt when the reference potential of the lower arm pulse signal is 0 V. The microcomputer 30 counts the number of pulses of the lower arm temperature signal TLnt in the input temperature detection period, and calculates the temperature of the lower arm switch SWL based on the counted number of pulses.

[0073] 8(c) shows the transition of the lower arm output signal GLamp of the lower arm second isolator 76 when the reference potential of the lower arm pulse signal is 0V. The lower arm output signal GLamp does not exceed the judgment threshold Jth during the period from when the lower arm pulse signal switches to H (5V) until the predetermined period Td has elapsed. The judgment threshold Jth in this embodiment is set to 2V, which is lower than the above-mentioned intermediate potential (2.5V). The lower arm output signal GLamp does not rise sharply because of, for example, a response delay of the output of the lower arm second isolator 76 relative to the input.

[0074] Because the lower arm output signal GLamp does not exceed the judgment threshold Jth, the upper arm filter signal GLntF of the upper arm comparator 57 is maintained at L. In this case, the upper arm drive signal GHr output from the upper arm AND circuit 51 is maintained at L (OFF command). In other words, when it is determined that the lower arm switch SWL is in the ON state, the upper arm switch SWH is prohibited from being switched to the ON state.

[0075] 9(b) shows the transition of the lower arm temperature signal TLnt when the reference potential of the lower arm pulse signal is 2.5 V. The microcomputer 30 counts the number of pulses of the lower arm temperature signal TLnt in the input temperature detection period, and calculates the temperature of the lower arm switch SWL based on the counted number of pulses. The microcomputer 30 can obtain temperature information of the lower arm switch SWL even when the lower arm switch SWL is in the off state.

[0076] 9(c) shows the transition of the lower arm output signal GLamp when the reference potential of the lower arm pulse signal is 2.5 V. Since the lower arm output signal GLamp always exceeds the judgment threshold Jth, the upper arm filter signal GLntF of the upper arm comparator 57 is maintained at H. In this case, the upper arm drive signal GHr output from the upper arm AND circuit 51 is switched to an ON command (H) when the upper arm main drive signal GH* from the microcomputer 30 is switched to an ON command (H). In other words, when it is determined that the lower arm switch SWL is in the OFF state, the upper arm switch SWH is permitted to be switched to the ON state.

[0077] Next, the upper arm drive IC 40H will be described. Note that the process of the upper arm drive IC 40H is similar to the process of the lower arm drive IC 40L, so the description will be omitted as appropriate.

[0078] Regardless of the determination result of whether the upper arm switch SWH is in an on state or an off state, the upper arm drive IC 40H outputs an upper arm pulse signal in which H and L are repeated at a predetermined period Td as the upper arm signal GHnt to the upper arm second isolator 56, similarly to the cases shown in Figures 7 to 9. The upper arm pulse signal includes temperature information of the upper arm switch SWH, similarly to the first embodiment.

[0079] When the upper arm drive IC 40H determines that the upper arm switch SWH is on, it sets the reference potential of the upper arm pulse signal to 0V (corresponding to the "third reference potential"), as in the case shown in Figure 8(a).

[0080] On the other hand, when the upper arm drive IC 40H determines that the upper arm switch SWH is in the off state, as in the case shown in Figure 9(a), it sets the reference potential of the upper arm pulse signal to the above-mentioned intermediate potential (corresponding to the "fourth reference potential"), which in this embodiment is 2.5 V.

[0081] As in the case shown in FIG. 8(b), the microcomputer 30 counts the number of pulses of the upper arm temperature signal THnt in the input temperature detection period, and calculates the temperature of the upper arm switch SWH based on the counted number of pulses.

[0082] 8(c), when the reference potential of the upper-arm pulse signal is 0V, the upper-arm output signal GHamp of the upper-arm second isolator 56 does not exceed the judgment threshold Jth (2.5V). Therefore, the lower-arm filter signal GHntF of the lower-arm comparator 77 is maintained at L. In this case, the lower-arm drive signal GLr output from the lower-arm AND circuit 71 is maintained at L (OFF command). In other words, when it is determined that the upper-arm switch SWH is in the ON state, the lower-arm switch SWL is prohibited from being switched to the ON state.

[0083] As in the case shown in FIG. 9(b), the microcomputer 30 counts the number of pulses of the upper arm temperature signal THnt in the input temperature detection period, and calculates the temperature of the upper arm switch SWH based on the counted number of pulses.

[0084] 9(c), the upper arm output signal GHamp always exceeds the judgment threshold Jth when the reference potential of the upper arm pulse signal is 2.5 V. Therefore, the lower arm filter signal GHntF of the lower arm comparator 77 is maintained at H. In this case, the lower arm drive signal GLr output from the lower arm AND circuit 71 is switched to an ON command (H) when the lower arm main drive signal GL* from the microcomputer 30 is switched to an ON command (H). In other words, when it is determined that the upper arm switch SWH is in the OFF state, the lower arm switch SWL is permitted to be switched to the ON state.

[0085] According to the present embodiment described above, in addition to the effects of the first embodiment, it is possible to obtain temperature information of the switch even during the period when the switch is in the OFF state.

[0086] <Modification of the second embodiment> The reference potentials of the upper and lower arm pulse signals when the switch is in the on state may be higher than the reference potentials of the upper and lower arm pulse signals when the switch is in the off state. In this case, the interface 50 may be provided with a configuration replacing the comparators 57 and 77 so as to be able to grasp the off state of the switch.

[0087] The determination threshold value Jth input to the upper arm comparator 57 and the determination threshold value Jth input to the lower arm comparator 77 may be different.

[0088] <Third embodiment> The third embodiment will be described below with reference to the drawings, focusing on the differences from the first embodiment. Fig. 10 shows the configuration of the interface 50 and the like of this embodiment. In Fig. 10, the same components as those shown in Fig. 2 are denoted by the same reference numerals for convenience.

[0089] The interface 50 includes upper and lower arm determination units 58 and 78. Each determination unit 58 and 78 includes a latch circuit and is provided in a low voltage region. The upper arm determination unit 58 receives the lower arm signal GLnt output from the lower arm second isolator 74. The lower arm determination unit 78 receives the upper arm signal GHnt output from the upper arm second isolator 54.

[0090] An upper arm filter signal GLntF which is an output signal of the upper arm determination unit 58 is input to the upper arm AND circuit 51. A lower arm filter signal GHntF which is an output signal of the lower arm determination unit 78 is input to the lower arm AND circuit 71. In this embodiment, the upper arm AND circuit 51 and the upper arm determination unit 58 correspond to the "upper arm processing unit", and the lower arm AND circuit 71 and the lower arm determination unit 78 correspond to the "lower arm processing unit".

[0091] Next, the transmission of the OFF notification signal by the upper and lower arm drive ICs 40H and 40L will be described. First, the lower arm drive IC 40L will be described.

[0092] Regardless of the determination result of whether the lower arm switch SWL is in the on state or the off state, the lower arm drive IC 40L outputs, as the lower arm signal GLnt, a lower arm main pulse signal MPL in which H and L are repeated at a predetermined period Td as shown in Figures 11(a) and 12(a), to the lower arm second isolator 74. The lower arm main pulse signal MPL includes temperature information of the lower arm switch SWL, as in the first embodiment.

[0093] When the lower arm drive IC 40L determines that the lower arm switch SWL has been switched to the on state, it outputs a lower arm on-pulse signal S1PL multiple times within a predetermined period Td, instead of the lower arm main pulse signal MPL, as shown in Fig. 11(a). In this embodiment, the lower arm on-pulse signal S1PL is output three times. The pulse width of the lower arm on-pulse signal S1PL is smaller than the pulse width of the lower arm main pulse signal MPL.

[0094] Fig. 11(b) shows the transition of the lower arm temperature signal TLnt corresponding to the case of Fig. 11(a). The microcomputer 30 counts the number of main pulses of the lower arm temperature signal TLnt in the input temperature detection period, and calculates the temperature of the lower arm switch SWL based on the counted number of pulses. At this time, the microcomputer 30 does not count the number of pulses corresponding to the lower arm on-pulse signal S1PL among the pulses constituting the lower arm temperature signal TLnt.

[0095] When the upper arm determination unit 58 determines that three lower arm on-pulse signals S1PL have been input, it switches the upper arm filter signal GLntF from H to L. The upper arm determination unit 58 maintains the upper arm filter signal GLntF at L until it determines that a lower arm off-pulse signal S2PL, which will be described later, has been input multiple times. When the upper arm filter signal GLntF is L, the upper arm drive signal GHr output from the upper arm AND circuit 51 is maintained at L (OFF command). In other words, when it is determined that the lower arm switch SWL is in the ON state, the upper arm switch SWH is prohibited from being switched to the ON state.

[0096] On the other hand, when the lower arm drive IC 40L determines that the lower arm switch SWL has been switched to the off state, it outputs a lower arm off pulse signal S2PL multiple times within a predetermined period Td, the number of pulses of which is different from that of the lower arm on pulse signal S1PL, instead of the lower arm main pulse signal MPL, as shown in Fig. 12(a). In this embodiment, two lower arm off pulse signals S2PL are output. The pulse width of the lower arm off pulse signal S2PL is smaller than the pulse width of the lower arm main pulse signal MPL.

[0097] Fig. 12(b) shows the transition of the lower arm temperature signal TLnt corresponding to the case of Fig. 12(a). The microcomputer 30 counts the number of main pulses of the lower arm temperature signal TLnt in the input temperature detection period, and calculates the temperature of the lower arm switch SWL based on the counted number of pulses. At this time, the microcomputer 30 does not count the number of pulses corresponding to the lower arm off pulse signal S2PL among the pulses constituting the lower arm temperature signal TLnt.

[0098] When the upper arm determination unit 58 determines that two lower arm off-pulse signals S2PL have been input, it switches the upper arm filter signal GLntF from L to H. The upper arm determination unit 58 maintains the upper arm filter signal GLntF at H until it determines that three lower arm on-pulse signals S1PL have been input. The number of pulses of the lower arm off-pulse signal S2PL is smaller than the number of pulses of S1PL. This allows the upper arm determination unit 58 to quickly determine that the lower arm switch SWL has been switched to the off state. This further shortens the dead time.

[0099] When the upper arm filter signal GLntF is H, the upper arm drive signal GHr output from the upper arm AND circuit 51 switches to an ON command (H) when the upper arm main drive signal GH* from the microcomputer 30 switches to an ON command (H). In other words, when it is determined that the lower arm switch SWL is in the OFF state, the upper arm switch SWH is permitted to be switched to the ON state.

[0100] Since the actual temperature of the lower arm switch SWL does not change suddenly, it is sufficient to transmit temperature information from a high pressure region to a low pressure region, for example, on the order of msec or sec. On the other hand, the information that the lower arm switch SWL has been switched to the off state must be transmitted, for example, on the order of μsec. For this reason, the information that the switch has been switched to the off state is transmitted by interrupting the transmission of the temperature information.

[0101] Next, the upper arm drive IC 40H will be described. Note that the process of the upper arm drive IC 40H is similar to the process of the lower arm drive IC 40L, so the description will be omitted as appropriate.

[0102] Regardless of the determination result of whether the upper arm switch SWH is in the on or off state, the upper arm drive IC 40H outputs, as the upper arm signal GHnt to the upper arm second isolator 54, an upper arm main pulse signal MPH in which H and L are repeated at a predetermined period Td, as in the cases shown in Figures 11(a) and 12(a).

[0103] When the upper arm drive IC 40H determines that the upper arm switch SWH has been switched to the on state, it outputs three upper arm on pulse signals S1PH within a predetermined period Td, instead of the upper arm main pulse signal MPH, as in the case shown in Figure 11 (a).

[0104] As in the case shown in FIG. 11(b), the microcomputer 30 counts the number of main pulses of the upper arm temperature signal THnt in a temperature detection period, and calculates the temperature of the upper arm switch SWH based on the counted number of pulses.

[0105] When the lower arm determination unit 78 determines that three upper arm on-pulse signals S1PH have been input, it switches the lower arm filter signal GHntF from H to L. When the lower arm filter signal GHntF is L, the lower arm drive signal GLr output from the lower arm AND circuit 71 is maintained at L (OFF command). In other words, when it is determined that the upper arm switch SWH is in the ON state, the lower arm switch SWL is prohibited from being switched to the ON state.

[0106] On the other hand, when the upper arm drive IC 40H determines that the upper arm switch SWH has been switched to the off state, it outputs two upper arm off pulse signals S2PH within a predetermined period Td, instead of the upper arm main pulse signal MPH, as in the case shown in Figure 12(a).

[0107] When the lower arm determination unit 78 determines that two upper arm off-pulse signals S2PH have been input, it switches the lower arm filter signal GHntF from L to H. When the lower arm filter signal GHntF is H, the lower arm drive signal GLr output from the lower arm AND circuit 71 switches to an ON command (H) when the lower arm main drive signal GL* from the microcomputer 30 switches to an ON command (H). In other words, when it is determined that the upper arm switch SWH is in the OFF state, the lower arm switch SWL is permitted to be switched to the ON state.

[0108] According to the present embodiment described above, it is possible to achieve the same effects as the first embodiment.

[0109] <Modification of the third embodiment> Considering the delay time when transmitting a signal from a high voltage region to a low voltage region, the drive IC may output the off pulse signal at a timing earlier than the timing described in the third embodiment. This can be realized, for example, by setting the threshold value used when determining whether to switch the switch to the off state and compared with the gate voltage to a value slightly higher than the threshold voltage Vth.

[0110] <Fourth embodiment> The fourth embodiment will be described below with reference to the drawings, focusing on the differences from the first embodiment. Fig. 13 shows the configuration of the interface 50 and the like of this embodiment. In Fig. 13, the same components as those shown in Fig. 2 are denoted by the same reference numerals for convenience. Note that in Fig. 13, the second isolators 54, 74 and the buffer circuits 55, 75 are omitted from illustration.

[0111] The lower arm drive IC 40L determines whether or not a drive abnormality occurs in the lower arm switch SWL. In this embodiment, the drive abnormality includes an open or short circuit failure of the switch, an abnormality in a gate circuit that charges and discharges the gate charge of the switch, an overheat abnormality of the switch, and an overcurrent abnormality of the switch.

[0112] When the lower arm drive IC 40L determines that no drive abnormality has occurred in the lower arm switch SWL and that the lower arm switch SWL is in the on state, it outputs a lower arm pulse signal as the lower arm signal GLnt, in which H and L are repeated at a predetermined period Td, as shown in Figure 14(a).

[0113] If the lower arm drive IC 40L determines that no drive abnormality has occurred in the lower arm switch SWL and that the lower arm switch SWL is in the off state, it outputs a lower arm signal GLnt of logic L, as shown by the solid line in Figure 15(a).

[0114] When the lower arm drive IC 40L determines that a drive abnormality has occurred in the lower arm switch SWL, it outputs a lower arm signal GLnt of logic H, as indicated by the dashed line in FIG. 15(a).

[0115] The upper arm drive IC 40H determines whether or not a drive abnormality occurs in the upper arm switch SWH. If the upper arm drive IC 40H determines that no drive abnormality occurs in the upper arm switch SWH and that the upper arm switch SWH is in an ON state, the upper arm drive IC 40H outputs an upper arm pulse signal in which H and L are repeated at a predetermined period Td as the upper arm signal GHnt, similar to the case shown in FIG. 14(a).

[0116] If the upper arm drive IC 40H determines that no drive abnormality has occurred in the upper arm switch SWH and that the upper arm switch SWH is in the off state, it outputs an upper arm signal GHnt of logical L, as shown by the solid line in Figure 15(a).

[0117] If the upper arm drive IC 40H determines that a drive abnormality has occurred in the upper arm switch SWH, it outputs an upper arm signal GHnt of logic H, as in the case indicated by the dashed line in FIG. 15(a).

[0118] The interface 50 includes an upper arm third isolator 59 and a lower arm third isolator 79. In this embodiment, the upper arm third isolator 59 and the lower arm third isolator 79 are isolation amplifiers, similar to the second embodiment. In this embodiment, the gain of the output signal Vout relative to the input signal Vin of the isolation amplifier is 1. An upper arm signal GHnt of the upper arm drive IC 40H is input to the upper arm third isolator 59, and a lower arm signal GLnt of the lower arm drive IC 40L is input to the lower arm third isolator 79. The upper and lower arm third isolators 59 and 79 correspond to the "upper and lower arm second transmission section."

[0119] The interface 50 includes upper and lower arm buffer circuits 60 and 80. The upper arm buffer circuit 60 outputs the upper arm output signal GHamp output from the upper arm third isolator 59 to the microcomputer 30 as an upper arm abnormality notification signal FH. The lower arm buffer circuit 80 outputs the lower arm output signal GLamp output from the lower arm third isolator 79 to the microcomputer 30 as a lower arm abnormality notification signal FL.

[0120] Taking the lower arm side as an example, the microcomputer 30 determines that no drive abnormality has occurred in the upper arm switch SWH when it determines that the upper arm abnormality notification signal FH is a pulse signal having a predetermined period Td as shown in FIG. 14(b) or when it determines that the upper arm abnormality notification signal FH is L as shown by the solid line in FIG. 15(b). On the other hand, when it determines that the upper arm abnormality notification signal FH is H as shown by the dashed line in FIG. 15(b), the microcomputer 30 determines that a drive abnormality has occurred in the upper arm switch SWH. In this case, the microcomputer 30 sets the upper and lower arm main drive signals GH* and GL* to L. Note that when the microcomputer 30 determines that the lower arm abnormality notification signal FL is H, it determines that a drive abnormality has occurred in the lower arm switch SWL. In this case as well, the microcomputer 30 sets the upper and lower arm main drive signals GH* and GL* to L.

[0121] Returning to the explanation of Fig. 13, the interface 50 includes upper and lower arm determination units 61 and 81. Each determination unit 61 and 81 is provided in a low-pressure region. A lower arm output signal GLamp of the lower arm second isolator 79 is input to the upper arm determination unit 61. An upper arm output signal GHamp of the upper arm second isolator 59 is input to the lower arm determination unit 81.

[0122] An upper arm filter signal GLntF which is an output signal of the upper arm determination unit 61 is input to the upper arm AND circuit 51. A lower arm filter signal GHntF which is an output signal of the lower arm determination unit 81 is input to the lower arm AND circuit 71. In this embodiment, the upper arm AND circuit 51 and the upper arm determination unit 61 correspond to an "upper arm processing unit", and the lower arm AND circuit 71 and the lower arm determination unit 81 correspond to a "lower arm processing unit".

[0123] Next, the transmission of the OFF notification signal by the upper and lower arm drive ICs 40H and 40L will be described.

[0124] When the upper arm determination unit 61 determines that the input lower arm output signal GLamp is a pulse signal having a predetermined period Td, it sets the upper arm filter signal GLntF to L, as shown in Fig. 14(c). In this case, the upper arm drive signal GHr output from the upper arm AND circuit 51 is maintained at L (OFF command). In other words, when it is determined that the lower arm switch SWL is in the ON state, the upper arm switch SWH is prohibited from being switched to the ON state.

[0125] When the upper arm determination unit 61 determines that the input lower arm output signal GLamp is L, it sets the upper arm filter signal GLntF to H, as shown by the solid line in Fig. 14(c). In this case, the upper arm drive signal GHr output from the upper arm AND circuit 51 switches to an ON command (H) when the upper arm main drive signal GH* from the microcomputer 30 switches to an ON command (H). In other words, when it is determined that the lower arm switch SWL is in the OFF state, the upper arm switch SWH is permitted to be switched to the ON state.

[0126] When the lower arm determination unit 81 determines that the input upper arm output signal GHamp is a pulse signal having a predetermined period Td, it sets the lower arm filter signal GHntF to L, as in the case shown in Fig. 14(c). In this case, the lower arm drive signal GLr output from the lower arm AND circuit 71 is maintained at L (OFF command). In other words, when it is determined that the upper arm switch SWLH is in the ON state, the lower arm switch SWL is prohibited from being switched to the ON state.

[0127] When the lower arm determination unit 81 determines that the input upper arm output signal GHamp is L, it sets the lower arm filter signal GHntF to H, as in the case shown by the solid line in Fig. 14(c). In this case, the lower arm drive signal GLr output from the lower arm AND circuit 71 is switched to an ON command (H) when the lower arm main drive signal GL* from the microcomputer 30 is switched to an ON command (H). In other words, when it is determined that the upper arm switch SWH is in the OFF state, the lower arm switch SWL is permitted to be switched to the ON state.

[0128] According to the present embodiment described above, it is possible to notify that the switch is in the off state by using an isolator that transmits abnormality information.

[0129] <Modification of the Fourth Embodiment> When the lower arm drive IC 40L determines that no drive abnormality has occurred in the lower arm switch SWL and that the lower arm switch SWL is in an off state, the lower arm drive IC 40L may output a lower arm signal GLnt of L instead of H. Also, when the lower arm drive IC 40L determines that a drive abnormality has occurred in the lower arm switch SWL, the lower arm drive IC 40L may output a lower arm signal GLnt of L instead of H. In this case, the upper arm filter unit 52 in FIG. 2 may be provided in the interface 50 instead of the upper arm determination unit 61. The lower arm output signal GLamp is input to the upper arm filter unit 52. The same applies to the upper arm side.

[0130] <Other embodiments> Each of the above embodiments may be modified as follows.

[0131] In each of the above embodiments, the microcomputer 30 maintains the main drive signal at H throughout the period instructing an ON command, and maintains the main drive signal at L throughout the period instructing an OFF command, but this is not limited to the above. For example, when switching from an OFF command to an ON command, the microcomputer 30 may output an ON pulse signal consisting of H and L, and when switching from an ON command to an OFF command, the microcomputer 30 may output an OFF pulse signal consisting of H and L, the number of pulses of which is different from the number of pulses of the ON pulse signal.

[0132] 2 as an example, an upper arm determination unit is provided in the interface 50 instead of the upper arm AND circuit 51. When the upper arm filter signal GLntF is L, the upper arm determination unit maintains the upper arm drive signal GHr at L even if it determines that an on-pulse signal has been input. On the other hand, when the upper arm filter signal GLntF is H, the upper arm determination unit switches the upper arm drive signal GHr from L to H if it determines that an on-pulse signal has been input.

[0133] The predetermined information transmitted via the second isolator is not limited to the temperature and abnormality information of the switch, but may be, for example, information on the drain-source voltage of the switch or temperature information of the drive IC.

[0134] The parameter used by the drive IC to determine whether the switch is in the off state is not limited to the gate voltage of the switch, but may be, for example, a sense current flowing through a sense terminal of the switch, a drain-source voltage Vds of the switch (a collector-emitter voltage Vce in the case of an IGBT), or a sense voltage which is a voltage drop in a sense resistor connecting a sense terminal and a source of the switch. For example, the drive IC may determine that the switch is in the off state when it determines that the detected sense current or sense voltage is less than a determination value near 0. Also, for example, the drive IC may determine that the switch is in the off state when it determines that the detected drain-source voltage is higher than the determination voltage. The determination voltage may be set to a value slightly lower than the output voltage of the DC power supply 21, for example.

[0135] The power converter may be a DC-DC converter instead of an inverter.

[0136] The control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor and a memory programmed to execute one or more functions embodied in a computer program. Alternatively, the control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described in the present disclosure may be realized by one or more special-purpose computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured with one or more hardware logic circuits. In addition, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executed by the computer. [Explanation of symbols]

[0137] 20...inverter, 30...microcontroller, 50...interface, SWH, SWL...upper and lower arm switches.

Claims

1. In a switch drive device that drives an upper arm switch (SWH) and a lower arm switch (SWL), a control unit (30) provided in a first region and outputting an upper arm main drive signal (GH*) and a lower arm main drive signal (GL*) so that the upper arm switch and the lower arm switch are alternately turned on with a dead time therebetween; an upper arm processing unit (51, 52, 57, 58, 61) provided in the first area and configured to output an upper arm drive signal (GHr) based on the upper arm main drive signal input from the control unit; an upper arm first transmission unit (53) that transmits the upper arm drive signal output from the upper arm processing unit to the second region while electrically insulating the first region and the second region; an upper arm drive unit (40H) provided in the second region, which turns the upper arm switch on when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an on command, and turns the upper arm switch off when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an off command; an upper arm second transmission unit (54, 56, 59) that transmits a signal including predetermined information of the upper arm switch from the second region side to the first region side while electrically insulating the first region and the second region; a lower arm processing unit (71, 72, 77, 78, 81) provided in the first area and configured to output a lower arm drive signal (GLr) based on the lower arm main drive signal input from the control unit; a lower arm first transmission unit (73) that transmits the lower arm drive signal output from the lower arm processing unit to the second region while electrically insulating the first region and the second region; a lower arm drive unit (40L) provided in the second area, which turns the lower arm switch on when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an on command, and turns the lower arm switch off when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an off command; a lower arm second transmission unit (74, 76, 79) that transmits a signal including predetermined information of the lower arm switch from the second region side to the first region side while electrically insulating the first region and the second region; Equipped with When the lower arm drive unit determines that the lower arm switch is in an off state, the lower arm drive unit outputs a lower arm off notification signal indicating that the lower arm switch is in an off state to the lower arm second transmission unit, The upper arm processing section includes: when it is determined that the lower arm switch is in an OFF state based on the lower arm OFF notification signal input via the lower arm second transmission section and when it is determined that the upper arm main drive signal input from the control section is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission section; When it is determined that the upper arm main drive signal input from the control unit is an OFF command, the upper arm drive signal of an OFF command is output to the upper arm first transmission unit, When the upper arm drive unit determines that the upper arm switch is in an off state, the upper arm drive unit outputs an upper arm off notification signal indicating that the upper arm switch is in an off state to the upper arm second transmission unit, The lower arm processing unit includes: when it is determined that the upper arm switch is in an OFF state based on the upper arm OFF notification signal input via the upper arm second transmission section and when it is determined that the lower arm main drive signal input from the control section is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission section; when it is determined that the lower arm main drive signal input from the control unit is an OFF command, the lower arm drive signal of an OFF command is output to the lower arm first transmission unit; The lower arm drive unit is When it is determined that the lower arm switch is in an on state, a lower arm pulse signal, which is a signal including temperature information of the lower arm switch as the predetermined information and in which H and L are repeated at a first predetermined period (Td), is output to the lower arm second transmission section (74); When it is determined that the lower arm switch is in an off state, a signal fixed to either H or L is output to the lower arm second transmission unit as the lower arm off notification signal, The upper arm drive unit is When it is determined that the upper arm switch is in an on state, an upper arm pulse signal, which is a signal including temperature information of the upper arm switch as the predetermined information and in which H and L are repeated at a second predetermined period (Td), is output to the upper arm second transmission unit (54); When it is determined that the upper arm switch is in an off state, a signal fixed to either H or L is output to the upper arm second transmission unit as the upper arm off notification signal, The control unit acquires temperature information of the lower arm switch based on the lower arm pulse signal transmitted via the lower arm second transmission unit, and acquires temperature information of the upper arm switch based on the upper arm pulse signal transmitted via the upper arm second transmission unit.A switch driving device.

2. the upper arm processing unit (51, 52) has an upper arm filter unit (52) that receives as input the lower arm off notification signal transmitted via the lower arm second transmission unit and outputs a signal obtained by delaying a change in the lower arm off notification signal, and when it is determined that the upper arm main drive signal input from the control unit is an on command and that the output signal of the upper arm filter unit has crossed a first determination threshold (Jth), it switches the upper arm drive signal to be output to the upper arm first transmission unit from an off command to an on command, the lower arm processing unit (71, 72) has a lower arm filter unit (72) that receives as input the upper arm off notification signal transmitted via the upper arm second transmission unit and outputs a signal obtained by delaying a change in the upper arm off notification signal, and when it is determined that the lower arm main drive signal input from the control unit is an on command and that the output signal of the lower arm filter unit has crossed a second determination threshold (Jth), it switches the lower arm drive signal to be output to the lower arm first transmission unit from an off command to an on command, When the lower arm off notification signal is input to the upper arm filter unit via the lower arm second transmission unit, an output signal of the upper arm filter unit crosses the first determination threshold during a period from when the lower arm off notification signal starts to be input to when the first predetermined period has elapsed, and when the lower arm pulse signal is input to the upper arm filter unit via the lower arm second transmission unit, an output signal of the upper arm filter unit does not cross the first determination threshold, 2. The switch drive device of claim 1, wherein when the upper arm off notification signal is input to the lower arm filter section via the upper arm second transmission section, the output signal of the lower arm filter section crosses the second decision threshold during a period from when the upper arm off notification signal begins to be input to when the second predetermined period has elapsed, and when the upper arm pulse signal is input to the lower arm filter section via the upper arm second transmission section, the output signal of the lower arm filter section does not cross the second decision threshold.

3. A switch drive device for driving an upper arm switch (SWH) and a lower arm switch (SWL), a control unit (30) provided in a first region and outputting an upper arm main drive signal (GH*) and a lower arm main drive signal (GL*) so that the upper arm switch and the lower arm switch are alternately turned on with a dead time therebetween; an upper arm processing unit (51, 52, 57, 58, 61) provided in the first area and configured to output an upper arm drive signal (GHr) based on the upper arm main drive signal input from the control unit; an upper arm first transmission unit (53) that transmits the upper arm drive signal output from the upper arm processing unit to the second region while electrically insulating the first region and the second region; an upper arm drive unit (40H) provided in the second region, which turns the upper arm switch on when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an on command, and turns the upper arm switch off when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an off command; an upper arm second transmission unit (54, 56, 59) that transmits a signal including predetermined information of the upper arm switch from the second region side to the first region side while electrically insulating the first region and the second region; a lower arm processing unit (71, 72, 77, 78, 81) provided in the first area and configured to output a lower arm drive signal (GLr) based on the lower arm main drive signal input from the control unit; a lower arm first transmission unit (73) that transmits the lower arm drive signal output from the lower arm processing unit to the second region while electrically insulating the first region and the second region; a lower arm drive unit (40L) provided in the second area, which turns the lower arm switch on when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an on command, and turns the lower arm switch off when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an off command; a lower arm second transmission unit (74, 76, 79) that transmits a signal including predetermined information of the lower arm switch from the second region side to the first region side while electrically insulating the first region and the second region; Equipped with When the lower arm drive unit determines that the lower arm switch is in an off state, the lower arm drive unit outputs a lower arm off notification signal indicating that the lower arm switch is in an off state to the lower arm second transmission unit, The upper arm processing section includes: when it is determined that the lower arm switch is in an OFF state based on the lower arm OFF notification signal input via the lower arm second transmission section and when it is determined that the upper arm main drive signal input from the control section is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission section; When it is determined that the upper arm main drive signal input from the control unit is an OFF command, the upper arm drive signal of an OFF command is output to the upper arm first transmission unit, When the upper arm drive unit determines that the upper arm switch is in an off state, the upper arm drive unit outputs an upper arm off notification signal indicating that the upper arm switch is in an off state to the upper arm second transmission unit, The lower arm processing unit includes: when it is determined that the upper arm switch is in an OFF state based on the upper arm OFF notification signal input via the upper arm second transmission section and when it is determined that the lower arm main drive signal input from the control section is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission section; when it is determined that the lower arm main drive signal input from the control unit is an OFF command, the lower arm drive signal of an OFF command is output to the lower arm first transmission unit; the lower arm drive unit outputs a lower arm pulse signal, which is a signal including temperature information of the lower arm switch as the predetermined information and has a first predetermined period (Td), to the lower arm second transmission unit (76); The lower arm drive unit is When it is determined that the lower arm switch is in an on state, a reference potential of the lower arm pulse signal is set to a first reference potential; when it is determined that the lower arm switch is in an off state, a signal in which a reference potential of the lower arm pulse signal is set to a second reference potential different from the first reference potential is output as the lower arm off notification signal; when the upper arm processing unit (51, 57) determines that a reference potential of the lower arm pulse signal input via the lower arm second transmission unit is the second reference potential and that the upper arm main drive signal input from the control unit is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission unit, the upper arm drive unit outputs an upper arm pulse signal, which is a signal including temperature information of the upper arm switch as the predetermined information and has a second predetermined period (Td), to the upper arm second transmission unit (56); The upper arm drive unit is When it is determined that the upper arm switch is in an on state, a reference potential of the upper arm pulse signal is set to a third reference potential; When it is determined that the upper arm switch is in an off state, a signal in which a reference potential of the upper arm pulse signal is set to a fourth reference potential different from the third reference potential is output as the upper arm off notification signal, when the lower arm processing unit (71, 77) determines that a reference potential of the upper arm pulse signal input via the upper arm second transmission unit is the fourth reference potential and that the lower arm main drive signal input from the control unit is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission unit, The control unit acquires temperature information of the lower arm switch based on the lower arm pulse signal transmitted via the lower arm second transmission unit, and acquires temperature information of the upper arm switch based on the upper arm pulse signal transmitted via the upper arm second transmission unit.A switch driving device.

4. A switch drive device for driving an upper arm switch (SWH) and a lower arm switch (SWL), a control unit (30) provided in a first region and outputting an upper arm main drive signal (GH*) and a lower arm main drive signal (GL*) so that the upper arm switch and the lower arm switch are alternately turned on with a dead time therebetween; an upper arm processing unit (51, 52, 57, 58, 61) provided in the first area and configured to output an upper arm drive signal (GHr) based on the upper arm main drive signal input from the control unit; an upper arm first transmission unit (53) that transmits the upper arm drive signal output from the upper arm processing unit to the second region while electrically insulating the first region and the second region; an upper arm drive unit (40H) provided in the second region, which turns the upper arm switch on when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an on command, and turns the upper arm switch off when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an off command; an upper arm second transmission unit (54, 56, 59) that transmits a signal including predetermined information of the upper arm switch from the second region side to the first region side while electrically insulating the first region and the second region; a lower arm processing unit (71, 72, 77, 78, 81) provided in the first area and configured to output a lower arm drive signal (GLr) based on the lower arm main drive signal input from the control unit; a lower arm first transmission unit (73) that transmits the lower arm drive signal output from the lower arm processing unit to the second region while electrically insulating the first region and the second region; a lower arm drive unit (40L) provided in the second area, which turns the lower arm switch on when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an on command, and turns the lower arm switch off when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an off command; a lower arm second transmission unit (74, 76, 79) that transmits a signal including predetermined information of the lower arm switch from the second region side to the first region side while electrically insulating the first region and the second region; Equipped with When the lower arm drive unit determines that the lower arm switch is in an off state, the lower arm drive unit outputs a lower arm off notification signal indicating that the lower arm switch is in an off state to the lower arm second transmission unit, The upper arm processing section includes: when it is determined that the lower arm switch is in an OFF state based on the lower arm OFF notification signal input via the lower arm second transmission section and when it is determined that the upper arm main drive signal input from the control section is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission section; When it is determined that the upper arm main drive signal input from the control unit is an OFF command, the upper arm drive signal of an OFF command is output to the upper arm first transmission unit, When the upper arm drive unit determines that the upper arm switch is in an off state, the upper arm drive unit outputs an upper arm off notification signal indicating that the upper arm switch is in an off state to the upper arm second transmission unit, The lower arm processing unit includes: when it is determined that the upper arm switch is in an OFF state based on the upper arm OFF notification signal input via the upper arm second transmission section and when it is determined that the lower arm main drive signal input from the control section is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission section; when it is determined that the lower arm main drive signal input from the control unit is an OFF command, the lower arm drive signal of an OFF command is output to the lower arm first transmission unit; The lower arm drive unit is a lower arm main pulse signal including temperature information of the lower arm switch as the predetermined information and having a first predetermined period (Td) is output to the lower arm second transmission section (74); when it is determined that the lower arm switch is switched to an off state, a lower arm pulse signal that appears a plurality of times within the first predetermined period is output as the lower arm off notification signal in place of the lower arm main pulse signal; when the upper arm processing unit (51, 58) determines that the lower arm pulse signal is input multiple times and that the upper arm main drive signal input from the control unit is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission unit, The upper arm drive unit is an upper arm main pulse signal having a second predetermined period (Td), the second predetermined period being a signal including temperature information of the upper arm switch as the predetermined information, is output to the upper arm second transmission section (54); when it is determined that the upper arm switch is switched to the off state, an upper arm pulse signal that appears a plurality of times within the second predetermined period is output as the upper arm off notification signal in place of the upper arm main pulse signal; when the upper arm pulse signal is input multiple times and the lower arm main drive signal input from the control unit is determined to be an ON command, the lower arm processing unit (71, 78) outputs the lower arm drive signal of an ON command to the lower arm first transmission unit, The control unit acquires temperature information of the lower arm switch based on the lower arm main pulse signal transmitted via the lower arm second transmission unit, and acquires temperature information of the upper arm switch based on the upper arm main pulse signal transmitted via the upper arm second transmission unit.A switch driving device.

5. A switch drive device for driving an upper arm switch (SWH) and a lower arm switch (SWL), a control unit (30) provided in a first region and outputting an upper arm main drive signal (GH*) and a lower arm main drive signal (GL*) so that the upper arm switch and the lower arm switch are alternately turned on with a dead time therebetween; an upper arm processing unit (51, 52, 57, 58, 61) provided in the first area and configured to output an upper arm drive signal (GHr) based on the upper arm main drive signal input from the control unit; an upper arm first transmission unit (53) that transmits the upper arm drive signal output from the upper arm processing unit to the second region while electrically insulating the first region and the second region; an upper arm drive unit (40H) provided in the second region, which turns the upper arm switch on when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an on command, and turns the upper arm switch off when it is determined that the upper arm drive signal input via the upper arm first transmission unit is an off command; an upper arm second transmission unit (54, 56, 59) that transmits a signal including predetermined information of the upper arm switch from the second region side to the first region side while electrically insulating the first region and the second region; a lower arm processing unit (71, 72, 77, 78, 81) provided in the first area and configured to output a lower arm drive signal (GLr) based on the lower arm main drive signal input from the control unit; a lower arm first transmission unit (73) that transmits the lower arm drive signal output from the lower arm processing unit to the second region while electrically insulating the first region and the second region; a lower arm drive unit (40L) provided in the second area, which turns the lower arm switch on when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an on command, and turns the lower arm switch off when it is determined that the lower arm drive signal input via the lower arm first transmission unit is an off command; a lower arm second transmission unit (74, 76, 79) that transmits a signal including predetermined information of the lower arm switch from the second region side to the first region side while electrically insulating the first region and the second region; Equipped with When the lower arm drive unit determines that the lower arm switch is in an off state, the lower arm drive unit outputs a lower arm off notification signal indicating that the lower arm switch is in an off state to the lower arm second transmission unit, The upper arm processing section includes: when it is determined that the lower arm switch is in an OFF state based on the lower arm OFF notification signal input via the lower arm second transmission section and when it is determined that the upper arm main drive signal input from the control section is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission section; When it is determined that the upper arm main drive signal input from the control unit is an OFF command, the upper arm drive signal of an OFF command is output to the upper arm first transmission unit, When the upper arm drive unit determines that the upper arm switch is in an off state, the upper arm drive unit outputs an upper arm off notification signal indicating that the upper arm switch is in an off state to the upper arm second transmission unit, The lower arm processing unit includes: when it is determined that the upper arm switch is in an OFF state based on the upper arm OFF notification signal input via the upper arm second transmission section and when it is determined that the lower arm main drive signal input from the control section is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission section; when it is determined that the lower arm main drive signal input from the control unit is an OFF command, the lower arm drive signal of an OFF command is output to the lower arm first transmission unit; The lower arm drive unit is When it is determined that the lower arm switch is in the on state, a lower arm pulse signal in which H and L are repeated at a first predetermined period (Td) is output to the lower arm second transmission unit (79) as the lower arm off notification signal, When it is determined that the lower arm switch is in an off state, a lower arm first signal, which is either H or L, is output to the lower arm second transmission section; When it is determined that a drive abnormality has occurred in the lower arm switch, a lower arm second signal, which is a signal of a logic level different from the logic level of the lower arm first signal, out of H and L, and which includes drive abnormality information of the lower arm switch as the predetermined information, is output to the lower arm second transmission section; when the upper arm processing unit (51, 61) determines that the lower arm switch is in an OFF state based on the lower arm first signal input via the lower arm second transmission unit and determines that the upper arm main drive signal input from the control unit is an ON command, it outputs the upper arm drive signal of an ON command to the upper arm first transmission unit, The upper arm drive unit is When it is determined that the upper arm switch is in the on state, an upper arm pulse signal in which H and L are repeated at a second predetermined period (Td) is output to the upper arm second transmission unit (59) as the upper arm off notification signal, When it is determined that the upper arm switch is in an off state, an upper arm first signal, which is either H or L, is output to the upper arm second transmission section; When it is determined that a drive abnormality has occurred in the upper arm switch, an upper arm second signal, which is a signal of a logic level different from the logic level of the upper arm first signal, out of H and L, and which includes drive abnormality information of the upper arm switch as the specified information, is output to the upper arm second transmission section; when the lower arm processing unit (71, 81) determines that the upper arm switch is in an OFF state based on the upper arm first signal input via the upper arm second transmission unit and determines that the lower arm main drive signal input from the control unit is an ON command, it outputs the lower arm drive signal of an ON command to the lower arm first transmission unit, The control unit is When it is determined that the lower arm second signal is input, it is determined that a drive abnormality has occurred in the lower arm switch, A switch drive device that determines that a drive abnormality has occurred in the upper arm switch when it is determined that the upper arm second signal has been input.

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