Signal Conversion Circuit

Abstract

To suppress reduction in the degree of freedom of design.SOLUTION: Disclosed is a signal conversion circuit for converting a first signal and a second signal constituting a differential signal into a single-ended third signal, which includes; a transformer in which a first signal is inputted to one end of a primary winding, a second signal is inputted to the other end of the primary winding, a third signal having the same polarity as that of the first signal is outputted from one end of a secondary winding, and the other end of the secondary winding is electrically connected to a reference potential; a first capacitor electrically connected between one end of the primary winding and the reference potential; and a negative capacitance electrically connected between the other end of the primary winding and one end of the secondary winding.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a signal conversion circuit that converts a differential signal into a single-ended signal. [Background technology]

[0002] When a transformer is used to convert a differential signal output by a power amplifier or other device into a single-ended signal, the parasitic capacitance that exists between the primary winding and the secondary winding causes asymmetry in the input impedance at both ends of the primary winding where the differential signal is input.

[0003] As a related technique, FIG. 6 and the accompanying description of Patent Document 1 below show that when a single-ended signal is converted into a differential signal, asymmetry occurs in the primary winding due to parasitic capacitance between the primary winding and the secondary winding.

[0004] FIG. 7 of Patent Document 1 and its explanation describe how, in order to resolve the above-mentioned asymmetry, the center tap of the primary winding is grounded, a signal is input to one end of the primary winding, and the other end of the primary winding is made floating. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 2938082 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, Patent Document 1 describes a transformer configuration technology that reduces the effects of parasitic capacitance. However, the technology described in Patent Document 1 requires the transformer to be designed taking into account the parasitic capacitance. Therefore, the technology described in Patent Document 1 has problems such as a reduction in design freedom, such as a failure to obtain a sufficiently large impedance conversion ratio.

[0007] The present invention has been made in view of the above, and has an object to suppress a decrease in the degree of freedom in design. [Means for solving the problem]

[0008] A signal conversion circuit according to one aspect of the present invention is a signal conversion circuit that converts a first signal and a second signal that constitute a differential signal into a single-ended third signal, and includes a transformer in which the first signal is input to one end of a primary winding, a second signal is input to the other end of the primary winding, a third signal having the same polarity as the first signal is output from one end of a secondary winding, and the other end of the secondary winding is electrically connected to a reference potential, a first capacitor electrically connected between one end of the primary winding and the reference potential, and a negative capacitance electrically connected between the other end of the primary winding and one end of the secondary winding. Effect of the Invention

[0009] According to the present invention, it is possible to suppress a decrease in the degree of freedom in design. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a configuration of a signal conversion circuit of a comparative example. [Diagram 2] FIG. 2 is a diagram showing the principle of the signal conversion circuit of the present disclosure. [Diagram 3] FIG. 3 is a diagram illustrating a configuration of the signal conversion circuit according to the first embodiment. [Figure 4] FIG. 4 is a schematic plan view of the signal conversion circuit according to the second embodiment. [Diagram 5] FIG. 5 is a diagram illustrating a configuration of a signal conversion circuit according to the third embodiment. [Figure 6] FIG. 6 is a diagram illustrating a configuration of a negative capacitance circuit of a signal conversion circuit according to the third embodiment. [Figure 7] FIG. 7 is a diagram illustrating a configuration of a negative capacitance circuit according to the fourth embodiment. [Figure 8] FIG. 8 is a diagram illustrating a configuration of a negative capacitance circuit according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the signal conversion circuit of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments. Each embodiment is merely an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible.

[0012] <Principle of the present disclosure and comparative examples> The principles of the present disclosure will be described below, but in order to facilitate understanding of the principles of the present disclosure, a comparative example will be described first.

[0013] (Comparative Example) FIG. 1 is a diagram showing a configuration of a signal conversion circuit of a comparative example.

[0014] The signal conversion circuit 201 converts a first input signal 21 and a second input signal 22 that form a differential signal into a single-ended output signal 23 .

[0015] The amplifier 31 includes a transistor 41. The transistor 41 outputs a first input signal 21 of a first polarity from a collector or a drain to a first input terminal IN+ of the signal conversion circuit 201. The first polarity is exemplified by positive polarity, but the present disclosure is not limited thereto.

[0016] The amplifier 32 includes a transistor 42. The transistor 42 outputs a second input signal 22 of a second polarity from a collector or a drain to a second input terminal IN- of the signal conversion circuit 201. The second polarity is exemplified by negative polarity, but the present disclosure is not limited thereto.

[0017] The first input signal 21 and the second input signal 22 have the same amplitude and opposite phases (a phase difference of 180 degrees).

[0018] The signal conversion circuit 201 includes a transformer 10. The transformer 10 includes a first winding 11 and a second winding 12. The first winding 11 and the second winding 12 are electromagnetically coupled to each other.

[0019] One end 11a of the first winding 11 is electrically connected to the first input terminal IN+, and the other end 11b of the first winding 11 is electrically connected to the second input terminal IN-.

[0020] The center tap 11c of the first winding 11 is electrically connected to a high potential end of a DC power supply 51. The low potential end of the DC power supply 51 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0021] The DC power supply 51 applies a bias voltage to the collectors or drains of the transistors 41 and 42 via the first winding 11, but the present disclosure is not limited to this. The bias voltage may be applied to the collectors or drains of the transistors 41 and 42 via a choke coil (not shown) instead of via the first winding 11.

[0022] One end 12a of the secondary winding 12 is electrically connected to the output terminal OUT of the signal conversion circuit 201. The other end 12b of the secondary winding 12 is electrically connected to a reference potential.

[0023] A single-ended output signal 23 is output from the output terminal OUT. The polarity of the output signal is a first polarity. The amplitude of the output signal 23 is relatively large compared to the first input signal 21 and the second input signal 22.

[0024] The transformer 10 is configured by winding together a first winding 11 and a second winding 12. Therefore, a parasitic capacitance C P1 A parasitic capacitance C P2 This results in:

[0025] The voltage waveforms are different between one end 12a and the other end 12b of the second winding 12. Therefore, an asymmetry in operation appears between the first input terminal IN+ side and the second input terminal IN- side.

[0026] That is, the first input terminal IN+ has a parasitic capacitance C P1 On the other hand, the second input terminal IN− is affected by the output signal 23 via the parasitic capacitance C P2 is added as a load, but the parasitic capacitance C P2 is connected to the reference potential and is not affected by the output signal 23.

[0027] As a result, the input impedance of the first input terminal IN+ and the input impedance of the second input terminal IN- become different, that is, the load impedance of the transistor 41 and the load impedance of the transistor 42 become different.

[0028] As a result, the first input signal 21 and the second input signal 22 may have different amplitudes or a phase difference that is different from 180°. Alternatively, the signal waveform of the first input signal 21 or the second input signal 22 may be distorted.

[0029] (Principles of the present disclosure) FIG. 2 is a diagram showing the principle of the signal conversion circuit of the present disclosure.

[0030] The signal conversion circuit 1 has a capacitance C a and negative capacitance -C b and, where C a >0, -C b <0. Although negative capacitance is shown using the symbol for capacitance in Figure 1, it is shown as a capacitance for convenience and is not actually composed of a capacitive element. For example, as described later, it is a circuit composed of transistors or a circuit composed of a material such as hafnium dioxide.

[0031] Capacity C aOne end of the capacitance C is electrically connected to the amplifier 31 and the first input terminal IN+. a The other end is electrically connected to a reference potential.

[0032] Negative capacitance-C b One end of the negative capacitance -C is electrically connected to the second input terminal IN- and the other end 11b of the first winding 11. b The other end of the second winding 12 is electrically connected to one end 12a of the second winding 12 and the output terminal OUT.

[0033] Here, the angular frequency of the first input signal 21, the second input signal 22, and the output signal 23 is ω, the voltage of the first input signal 21 is V1, the voltage of the second input signal 22 is −V1, and the voltage of the output signal 23 is aV1, where a is a positive number.

[0034] Parasitic capacitance C P1 The voltage across both ends of is V1(1-a). Therefore, the parasitic capacitance C P1 Current I 11 is expressed by the following equation (1). I 11 =V1(1-a)ωC P1 (1)

[0035] Parasitic capacitance C P2 The voltage across the two terminals is -V1. Therefore, the parasitic capacitance C P2 Current I 22 is expressed by the following equation (2). I 22 =-V1ωC P2 (2)

[0036] In order to eliminate the asymmetry, the present disclosure takes the following two measures.

[0037] The first measure is to use a capacitance C a One end of the capacitance C is electrically connected to the first input terminal IN+. a The other end is electrically connected to a reference potential.

[0038] Capacity C a The value of the parasitic capacitance CP2 Set it to approximately the same value as the capacitance C a The value of capacitance C p2 (This includes cases where the difference is within ±30% of the value of

[0039] Capacity C a The voltage across the two terminals is V1. Therefore, the capacitance C a Current I 12 is expressed by the following equation (3). I 12 =V1ωC a =V1ωC P2 (3)

[0040] Referring to equations (2) and (3), the current I 12 is the current I 22 The polarity is reversed compared to the current I 12 and current I 22 It is symmetrical with.

[0041] The second measure is to use negative capacitance -C b is electrically connected between the second input terminal IN- and the output terminal OUT.

[0042] Capacity-C b The voltage across both ends is -V1(1+a). Therefore, the capacitance -C b Current I 21 is expressed by the following equation (4). I 21 =V1(1+a)ωC b (4)

[0043] The negative capacitance -C b Set the value of . C b =((a-1) / (a+1))C P1 (5)

[0044] By substituting equation (5) into equation (4), we obtain the following equation (6). I 21 =V1(1+a)ωC b =V1(1+a)ω((a-1) / (a+1))C P1 =V1(a-1)ωC P1 =-V1(1-a)ωC P1 (6)

[0045] Referring to equations (1) and (6), the current I 21 is the current I 11 The polarity is reversed compared to the current I 21 and current I 11 It is symmetrical with.

[0046] As mentioned above, the present disclosure provides a capacitance C a and negative capacitance -C b By adding the parasitic capacitance C P1 and parasitic capacitance C P2 This makes it possible to eliminate the asymmetry caused by the above. As a result, the present disclosure can maintain the symmetry of the input impedances of the first input terminal IN+ and the second input terminal IN-, and can maintain the symmetry of the load impedances of the amplifiers 31 and 32.

[0047] <First embodiment> FIG. 3 is a diagram illustrating a configuration of the signal conversion circuit according to the first embodiment.

[0048] The signal conversion circuit 1A has a negative capacitance -C b As an example, the inductor L a Includes.

[0049] In the signal conversion circuit 1A, the negative capacitance -C b Inductor L that can easily realize a The asymmetry was eliminated using

[0050] Negative capacitance-C b and inductor L a When comparing the impedance with the impedance of the jωL a =j / (ωC b) ···(7)

[0051] That is, the inductor L a If the value of is set as in the following equation (8), the asymmetry can be eliminated at each angular frequency ω. L a =1 / (ω 2 C b ) ···(8)

[0052] Although the signal conversion circuit 1A has frequency dependence, it has a negative capacitance -C b The asymmetry of the load impedance of the amplifier 31 and the amplifier 32 can be eliminated without using the above.

[0053] <Second embodiment> Among the components of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted.

[0054] FIG. 4 is a schematic plan view of the signal conversion circuit according to the second embodiment.

[0055] The second embodiment is a specific example in which the signal conversion circuit 1A (see FIG. 3) is applied to an output matching circuit of a power amplifier and is arranged on a plane.

[0056] The signal conversion circuit 1A is formed on a substrate 61. The first winding 11 and the second winding 12 are formed on different layers of the substrate 61, but the present disclosure is not limited to this. The first winding 11 and the second winding 12 may be formed on the same layer of the substrate 61.

[0057] The first input terminal IN+ and the second input terminal IN- of the first winding 11 are formed on the left side in Fig. 4. The first winding 11 has a substantially circular shape. The center tap 11c of the first winding 11 is located at the right end of the first winding 11 in Fig. 4. A bias voltage is input to the center tap 11c from a DC power supply 51.

[0058] An output terminal OUT of the second winding 12 is formed on the right side in Fig. 4. The second winding 12 makes approximately one turn inside the first winding 11, then straddles the first winding 11 and makes approximately one turn outside the first winding. The other end of the second winding 12 is electrically connected to the reference potential.

[0059] A current 71 flowing through the first winding 11 and a current 72 flowing through the second winding 12 flow in a direction such that the magnetic fields of the first winding 11 and the second winding 12 have a common direction.

[0060] In an output matching circuit, the output impedance (for example, 50Ω) is often larger than the load impedance. Therefore, the inductance value of the secondary winding 12 is often larger than the inductance value of the primary winding 11.

[0061] Capacity C a and inductor L a is, for example, a surface mount device (SMD), but the present disclosure is not limited thereto.

[0062] Capacity C a For example, the capacitance C a For example, the distance between the first input terminal IN+ and the first input terminal IN+ is shorter than the distance between the other components and the first input terminal IN+.

[0063] Inductor L a In many cases, the inductance value of C is relatively large. For example, the signal frequency is 1.85 GHz (gigahertz), the winding ratio of the second winding 12 to the first winding 11 is 2:1, and P1 =C P2 =C a = 1.0 pF (picofarad), the inductor L a The inductance value of the inductor L is 15.5 nH (nanohenry). a can be designed including the inductance values ​​of the wiring 62 and the wiring 63 connected in series.

[0064] In the second embodiment, the signal conversion circuit 1A of the first embodiment can be realized on a substrate 61, and the circuit can be physically realized.

[0065] <Third embodiment> Among the components of the third embodiment, the same components as those of the other embodiments are denoted by the same reference numerals and the description thereof will be omitted.

[0066] FIG. 5 is a diagram illustrating a configuration of a signal conversion circuit according to the third embodiment.

[0067] The signal conversion circuit 1B has a negative capacitance -C b An example of the negative capacitance circuit is a negative capacitance circuit 81. The negative capacitance circuit 81 is an active negative capacitance circuit realized using active elements (transistors).

[0068] As will be described later, the first terminal 81a and the second terminal 81b of the negative capacitance circuit 81 are electrically connected to the power supply potential VCC and have a DC level. DC If necessary, a DC cut capacitor C DC2 You can add:

[0069] FIG. 6 is a diagram illustrating a configuration of a negative capacitance circuit of a signal conversion circuit according to the third embodiment.

[0070] The negative capacitance circuit 81 includes resistors 91 and 92 , transistors 93 and 94 , a capacitor 95 , and constant current sources 96 and 97 .

[0071] The transistors 93 and 94 are bipolar transistors, but the present disclosure is not limited thereto. The transistors 93 and 94 may be FETs (Field Effect Transistors). When the transistors 93 and 94 are FETs, the source corresponds to the emitter, the gate corresponds to the base, and the drain corresponds to the collector.

[0072] The resistance value of resistor 91 and the resistance value of resistor 92 are the same, but the present disclosure is not limited to this. The electrical characteristics of transistor 93 and the electrical characteristics of transistor 94 are the same, but the present disclosure is not limited to this. The current value of constant current source 96 and the current value of constant current source 97 are the same, but the present disclosure is not limited to this.

[0073] The resistance values ​​of the resistors 91 and 92 are set based on the power supply potential VCC, the electrical characteristics of the transistors 93 and 94, and the like.

[0074] One end of the resistor 91 is electrically connected to the power supply potential VCC. The other end of the resistor 91 is electrically connected to the first terminal 81a, the collector of the transistor 93, and the base of the transistor 94.

[0075] One end of the resistor 92 is electrically connected to the power supply potential VCC. The other end of the resistor 92 is electrically connected to the second terminal 81b, the collector of the transistor 94, and the base of the transistor 93.

[0076] The base of the transistor 93 is electrically connected to the second terminal 81b. The base of the transistor 94 is electrically connected to the first terminal 81a.

[0077] One end of the capacitor 95 is electrically connected to the emitter of the transistor 93. The other end of the capacitor 95 is electrically connected to the emitter of the transistor 94.

[0078] A constant current source 96 is electrically connected between the emitter of transistor 93 and a reference potential.

[0079] A constant current source 97 is electrically connected between the emitter of transistor 94 and a reference potential.

[0080] The DC level of the first terminal 81a is the power supply potential VCC minus the voltage drop of resistor 91. Similarly, the DC level of the second terminal 81b is the power supply potential VCC minus the voltage drop of resistor 92.

[0081] In terms of DC, the transistor 93 is given a collector bias voltage and a base bias voltage, and a collector current I 31 and emitter current I 32 Similarly, in the transistor 94, a collector bias voltage and a base bias voltage are applied, and a collector current I 41 and emitter current I 42 flows.

[0082] The operation of the negative capacitance circuit 81 when the voltage at the first terminal 81a drops in an AC manner and the voltage at the second terminal 81b rises in an AC manner will be described.

[0083] As the base voltage of the transistor 93 increases, the collector current I 31 and emitter current I 32 On the other hand, the base voltage of transistor 94 decreases, so the collector current I 41 and emitter current I 42 decreases.

[0084] Emitter current I 32 The increased amount flows to a constant current source 97 via a capacitor 95.

[0085] The current flowing in from the first terminal 81a is the collector current I 31 The current flowing in from the second terminal 81b is the collector current I 41 decreases, so decreases.

[0086] When the voltage at the first terminal 81a increases in an AC manner and the voltage at the second terminal 81b decreases in an AC manner, the operation of the negative capacitance circuit 81 is opposite to that described above.

[0087] Inductor L a When using instead of negative capacitance, at a certain angular frequency ω c Only in ω c L a =1 / (ω c C b In contrast, when the transistors 93 and 94 are used, the negative capacitance circuit 81 can operate in a wide band. a In comparison, a broadband negative capacitance can be realized.

[0088] As a result, the signal conversion circuit 1B can eliminate asymmetry over a wide band, compared to the signal conversion circuit 1 and the signal conversion circuit 1A.

[0089] <Fourth embodiment> Among the components of the fourth embodiment, the same components as those of the other embodiments are given the same reference numerals and the description thereof will be omitted.

[0090] FIG. 7 is a diagram illustrating a configuration of a negative capacitance circuit according to the fourth embodiment.

[0091] The negative capacitance circuit 81A includes transistors 98 and 99 instead of the resistors 91 and 92, as compared with the negative capacitance circuit 81 (see FIG. 6).

[0092] Transistor 98 and transistor 99 are bipolar transistors, although the present disclosure is not limited thereto. Transistor 98 and transistor 99 may be FETs.

[0093] The electrical characteristics of transistor 98 and transistor 99 are assumed to be the same, although the present disclosure is not limited thereto.

[0094] The collector of the transistor 98 is electrically connected to the power supply potential VCC. The base of the transistor 98 is electrically connected to the second terminal 81b. The emitter of the transistor 98 is electrically connected to the base of the transistor 93. That is, the transistor 98 is connected in an emitter-follower configuration.

[0095] The collector of the transistor 99 is electrically connected to the power supply potential VCC. The base of the transistor 99 is electrically connected to the first terminal 81a. The emitter of the transistor 99 is electrically connected to the base of the transistor 94. That is, the transistor 99 is connected in an emitter-follower configuration.

[0096] The negative capacitance circuit 81A includes emitter-follower connected transistors 98 and 99, and thereby can increase the allowable maximum voltage amplitude of the voltage input to the first terminal 81a and the second terminal 81b, compared to the negative capacitance circuit 81. Note that the resistors 91 and 92 shown in FIG. 6 are omitted here. If an appropriate DC bias is applied to the first terminal 81a and the second terminal 81b, the resistors 91 and 92 can be omitted.

[0097] <Fifth embodiment> Among the components of the fifth embodiment, the same components as those of the other embodiments are given the same reference numerals and the description thereof will be omitted.

[0098] FIG. 8 is a diagram illustrating a configuration of a negative capacitance circuit according to the fifth embodiment.

[0099] Compared to the negative capacitance circuit 81 (see FIG. 6), the negative capacitance circuit 81B includes transistors 101 and 102 instead of the resistors 91 and 92 and the transistors 93 and 94. The transistors 101 and 102 are FETs.

[0100] The electrical characteristics of the transistor 101 and the transistor 102 are assumed to be the same, but the present disclosure is not limited to this.

[0101] A drain of the transistor 101 is electrically connected to the first terminal 81a. A gate of the transistor 101 is electrically connected to the second terminal 81b. A source of the transistor 101 is electrically connected to one end of the capacitor 95 and the constant current source 96.

[0102] The drain of the transistor 102 is electrically connected to the second terminal 81b. The gate of the transistor 102 is electrically connected to the first terminal 81a. The source of the transistor 102 is electrically connected to the other end of the capacitor 95 and the constant current source 97.

[0103] In this way, the negative capacitance circuit 81B can be realized by using a FET as an active element. Note that the resistors 91 and 92 shown in Fig. 6 are omitted here. If an appropriate DC bias is applied to the first terminal 81a and the second terminal 81b, the resistors 91 and 92 can be omitted.

[0104] <Additional Notes> In the third to fifth embodiments, the negative capacitance circuit is realized using an active element (transistor), but the present disclosure is not limited to this. The negative capacitance circuit can also be realized using a material having negative capacitance characteristics, such as HfO2 (hafnium dioxide).

[0105] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configurations.

[0106] (1) A signal conversion circuit that converts a first signal and a second signal that constitute a differential signal into a single-ended third signal, a transformer in which a first signal is input to one end of a primary winding, a second signal is input to the other end of the primary winding, a third signal having the same polarity as the first signal is output from one end of a secondary winding, and the other end of the secondary winding is electrically connected to a reference potential; a first capacitor electrically connected between one end of the primary winding and a reference potential; a negative capacitance electrically connected between the other end of the primary winding and one end of the secondary winding; Including, Signal conversion circuit.

[0107] (2) The signal conversion circuit according to (1) above, Negative capacitance is an inductor. Signal conversion circuit.

[0108] (3) The signal conversion circuit according to (1) above, The negative capacitance is An active negative capacitance circuit including an active element, Signal conversion circuit.

[0109] (4) The signal conversion circuit according to (3) above, The active negative capacitance circuit is a first transistor having a collector or drain electrically connected to a first terminal and a base or gate electrically connected to a second terminal; a second transistor having a collector or drain electrically connected to the second terminal and a base or gate electrically connected to the first terminal; a first constant current source electrically connected to the emitter or source of the first transistor; a second constant current source electrically connected to the emitter or source of the second transistor; a second capacitor electrically connected between the emitter or source of the first transistor and the emitter or source of the second transistor; Including, Signal conversion circuit.

[0110] (5) The signal conversion circuit according to (4) above, The active negative capacitance circuit is a third transistor, the emitter or source of which is electrically connected to the base or gate of the first transistor, the base or gate of which is electrically connected to the second terminal, and the collector or drain of which is electrically connected to a power supply potential; a fourth transistor, the emitter or source of which is electrically connected to the base or gate of the second transistor, the base or gate of which is electrically connected to the first terminal, and the collector or drain of which is electrically connected to a power supply potential; Further comprising: Signal conversion circuit.

[0111] The above-described embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0112] 1, 201 Signal conversion circuit 10. Transformer 11 First Winding 12 Second Winding 31, 32 Amplifier 41, 42, 93, 94, 98, 99, 101, 102 Transistors 51 DC power supply 61 Substrate 81 Negative capacitance circuit 91, 92 Resistance 95 Capacitor 96, 97 constant current source C P1 , C P2 parasitic capacitance C a capacity -C b negative capacitance L a Inductors

Claims

1. A signal conversion circuit that converts a first signal and a second signal that constitute a differential signal into a single-ended third signal, a transformer in which the first signal is input to one end of a primary winding, the second signal is input to the other end of the primary winding, the third signal having the same polarity as the first signal is output from one end of a secondary winding, and the other end of the secondary winding is electrically connected to a reference potential; a first capacitor electrically connected between one end of the primary winding and a reference potential; a negative capacitance electrically connected between the other end of the primary winding and one end of the secondary winding; Including, Signal conversion circuit.

2. 2. The signal conversion circuit according to claim 1, The negative capacitance is an inductor. Signal conversion circuit.

3. 2. The signal conversion circuit according to claim 1, The negative capacitance is An active negative capacitance circuit including an active element, Signal conversion circuit.

4. 4. The signal conversion circuit according to claim 3, The active negative capacitance circuit comprises: a first transistor having a collector or drain electrically connected to a first terminal and a base or gate electrically connected to a second terminal; a second transistor having a collector or a drain electrically connected to the second terminal and a base or a gate electrically connected to the first terminal; a first constant current source electrically connected to the emitter or source of the first transistor; a second constant current source electrically connected to the emitter or source of the second transistor; a second capacitor electrically connected between the emitter or source of the first transistor and the emitter or source of the second transistor; Including, Signal conversion circuit.

5. 4. The signal conversion circuit according to claim 3, The active negative capacitance circuit comprises: a first transistor having a collector or a drain electrically connected to a first terminal; a second transistor having a collector or a drain electrically connected to the second terminal; a third transistor, the emitter or source of which is electrically connected to the base or gate of the first transistor, the base or gate of which is electrically connected to the second terminal, and the collector or drain of which is electrically connected to a power supply potential; a fourth transistor, the emitter or source of which is electrically connected to the base or gate of the second transistor, the base or gate of which is electrically connected to the first terminal, and the collector or drain of which is electrically connected to a power supply potential; a first constant current source electrically connected to the emitter or source of the first transistor; a second constant current source electrically connected to the emitter or source of the second transistor; a second capacitor electrically connected between the emitter or source of the first transistor and the emitter or source of the second transistor; Including, Signal conversion circuit.

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