Differential Amplifier Circuit

Abstract

This differential amplification circuit comprises: an amplification unit (5) that includes a differential pair of transistors (Q1, Q2) to which differential signals (VIN) are inputted; and a tail current circuit that is constituted by a short stub (S1) provided between the grounding terminal of the amplification unit (5) and the ground.

Description

[Technical field]

[0001] The present invention relates to a circuit that handles high-frequency electrical signals, and more particularly to a differential amplifier circuit. [Background technology]

[0002] Among amplifier circuits, differential amplifier circuits are known to have various beneficial properties due to their ability to amplify only differential signals and remove common-mode signals. For example, a differential amplifier circuit can remove common-mode components and generate only a completely differential signal. By using this differential signal as the LO signal of a differential mixer, it is possible to remove LO leakage, which is often a problem in mixers (Non-Patent Document 1). The configuration of a typical differential amplifier circuit is shown in Figure 14.

[0003] The operation of the differential amplifier circuit in Fig. 14 will be briefly explained. A differential signal V IN is input, and the amplified signal V OUT is output from the differential output ports OUTP and OUTN. A current source transistor Q3 (tail current source) is connected to point X where the source terminals of the differential pair transistors Q1 and Q2 intersect, in order to provide an appropriate bias current to the transistors Q1 and Q2.

[0004] For transistor Q3 to act as a current source, a bias V GG1 is set to a bias voltage such that transistor Q3 operates in the saturation region. Because the output impedance of transistor Q3 in the saturation region is very high, the impedance when looking at ground potential from point X is also very high. This high impedance is equivalent to the source terminals of transistors Q1 and Q2 being open for the common-mode signal input to transistors Q1 and Q2. Therefore, the gain of the differential amplifier circuit for the common-mode signal (common-mode gain) becomes very small.

[0005] On the other hand, when a differential signal is input, transistors Q1 and Q2 are driven by signals with inverted phase, and the symmetrical configuration in Figure 14 fixes the potential at point X to zero regardless of the impedance of transistor Q3. This is equivalent to the source terminals of transistors Q1 and Q2 being grounded. Fixing point X to zero potential is called the virtual grounding of the differential amplifier circuit. Therefore, the gain of the differential amplifier circuit for the differential signal (differential gain) becomes very large.

[0006] The important point here is that the differential amplifier circuit in Figure 14 has gain selectivity for the input signal mode (in-phase or differential). In other words, even if a signal that is a mixture of in-phase and differential signals is input to the differential input ports INP and INN, only the differential signal is selectively amplified by the differential amplifier circuit, and the differential signal V is output from the differential output ports OUTP and OUTN. OUT This gain selectivity is an important characteristic of a differential amplifier circuit. The common mode rejection ratio (CMRR), which indicates the ratio of the common mode gain to the differential gain, is a characteristic index for the performance of a differential amplifier circuit.

[0007] The problem with the configuration of Figure 14 is power consumption. In the case of the configuration of Figure 14, the bias voltage V GG1 Power supply voltage V DD In other words, there is a problem of an increase in the power supply voltage V DD must be set to a voltage that biases two transistors to the saturation region, so the power consumption is roughly twice that of a normal single-ended amplifier circuit. In particular, at frequencies of 300 GHz or higher, the gain per transistor stage is small, so multi-stage transistors are required, which inevitably increases the power consumption of the differential amplifier circuit. For example, the power consumption of the amplifier circuit disclosed in Non-Patent Document 2 is 2W even with a single-ended design, so if this circuit is made differential as it is, it will consume an extremely large amount of power of 4W or more.

[0008] As a method for solving the power consumption problem, a configuration in which the inductor L1 is used as the tail current circuit as shown in Figure 15 is known. This makes the voltage consumed by the tail current circuit zero, and the power supply voltage V DD is the voltage for one transistor, so power consumption is smaller than that of the configuration in FIG.

[0009] In the case of the configuration of FIG. 15, by setting the inductance of inductor L1 to be sufficiently large at the operating frequency of the differential amplifier circuit, the impedance when looking at the ground potential from point X becomes large, and inductor L1 can be made to equivalently have the same effect as a current source as in the configuration of FIG. 14. However, in frequency bands exceeding 300 GHz, even if inductor L1 is realized using a winding or the like, the self-resonant frequency of inductor L1 is generally lower than 300 GHz, making it difficult to realize inductor L1 itself using an integrated circuit process.

[0010] According to Non-Patent Document 3, the upper limit frequency of an inductor that can be realized by an integrated circuit process is significantly lower than 300 GHz. Even if an inductor can be realized by an integrated circuit process, the layout of the wound inductor will be asymmetric. In a differential amplifier circuit, where symmetry of the layout is important, it is difficult to employ a wound inductor with an asymmetric layout.

[0011] As described above, in the conventional differential amplifier circuit topology, there was no tail current source circuit that could ensure a large CMRR while maintaining low power consumption in the frequency band of 300 GHz or more. [Prior art documents] [Non-patent literature]

[0012] [Non-Patent Document 1] Jeng-Han Tsai,et al.,“A 25-75 GHz Broadband Gilbert-Cell Mixer Using 90-nm CMOS Technology”,IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS,vol.17,no.4,Apr. 2007 [Non-Patent Document 2] H. Hamada,et al.,“300-GHz-band 120 Gb / s Wireless Front-end Based on InP-HEMT PAs and Mixers”,IEEE JOURNAL OF SOLID-STATE CIRCUITS,vol.55,no.9,Sept. 2020 [Non-Patent Document 3] K. Kang, et al., “On-chip vertical tapered solenoid inductor with high self-resonance frequency”, ELECTRONICS LETTERS, vol. 43, no. 16, Aug. 2007 Summary of the Invention [Problem to be solved by the invention]

[0013] The present invention has been made in order to solve the above-mentioned problems, and has an object to provide a differential amplifier circuit capable of ensuring a large CMRR while maintaining low power consumption. [Means for solving the problem]

[0014] The differential amplifier circuit of the present invention includes an amplifier section including a differential pair of transistors to which a differential signal is input, and a tail current circuit including a short stub provided between a ground terminal of the amplifier section and ground. 、 The electrical length of the short stub is characterized in that it is shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit. The differential amplifier circuit of the present invention a tail current circuit including an amplifier section including a differential pair of transistors to which a differential signal is input, and a short stub provided between a ground terminal of the amplifier section and ground;A capacitance provided in parallel with the short stub between the ground terminal of the amplifier and ground. And Preparation The inductance and capacitance of the short stub constitute an LC resonant circuit. When the value of the inductance is L and the value of the capacitance is C, the resonant frequency F=1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit. It is characterized by the above. In addition, the differential amplifier circuit of the present invention comprises an amplifier section including a differential pair transistor to which a differential signal is input, a tail current circuit consisting of a short stub arranged between the ground terminal of the amplifier section and ground, and a capacitance arranged in parallel with the short stub between the ground terminal of the amplifier section and ground, wherein the inductance and the capacitance of the short stub form an LC resonant circuit, and when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F = 1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit, and the electrical length of the short stub is shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit. Moreover, one configuration example of the differential amplifier circuit of the present invention is characterized in that it further comprises a resistor inserted in series with the capacitor between a ground terminal of the amplifier section and ground.

[0015] The differential amplifier circuit of the present invention a tail current circuit including an amplifier section including a differential pair of transistors to which a differential signal is input, and a short stub provided between a ground terminal of the amplifier section and ground; An open stub with one end connected to the ground terminal of the amplifier and the other end open And The electrical length of the open stub is shorter than a quarter wavelength of an operating frequency of the differential amplifier circuit. The inductance of the short stub and the capacitance of the open stub form an LC resonant circuit, and when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F=1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit. It is characterized by the above. In addition, the differential amplifier circuit of the present invention comprises an amplifier section including a differential pair transistor to which a differential signal is input, a tail current circuit consisting of a short stub arranged between the ground terminal of the amplifier section and ground, and an open stub having one end connected to the ground terminal of the amplifier section and the other end open, the electrical length of the open stub is shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit, the inductance of the short stub and the capacitance of the open stub form an LC resonant circuit, when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F = 1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit, and the electrical length of the short stub is shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit. Moreover, one configuration example of the differential amplifier circuit of the present invention is characterized in that it further comprises a resistor inserted in series between a ground terminal of the amplifier section and the open stub. Furthermore, in one configuration example of the differential amplifier circuit of the present invention, the amplifier section is any one of a common-source amplifier circuit including the differential pair transistors, a common-emitter amplifier circuit including the differential pair transistors, and a cascode amplifier circuit including the differential pair transistors and a pair of transistors cascode-connected to the differential pair transistors. Effect of the Invention

[0016] According to the present invention, by providing a tail current circuit consisting of a short stub between the ground terminal of the amplifier section and ground, it is possible to ensure a large CMRR while maintaining low power consumption. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram showing a configuration of a differential amplifier circuit according to the present invention. [Diagram 2] FIG. 2 is a diagram showing a configuration in which differential amplifier circuits according to the present invention are arranged in multiple stages. [Diagram 3] FIG. 3 is a diagram illustrating the gain of the differential amplifier circuit of FIG. [Figure 4] FIG. 4 is a diagram showing the configuration of a differential amplifier circuit that uses a short stub shorter than a quarter wavelength as a tail current circuit. [Diagram 5] FIG. 5 is a diagram showing a change in common-mode gain when the length of the short stub is changed in the differential amplifier circuit of FIG. [Figure 6] FIG. 6 is a diagram showing a configuration of a differential amplifier circuit according to a first embodiment of the present invention. [Figure 7] FIG. 7 is a diagram showing the differential gain and the common-mode gain of the differential amplifier circuit according to the first embodiment of the present invention. [Figure 8] FIG. 8 is a diagram showing a configuration of a differential amplifier circuit according to a second embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing the differential gain and the common-mode gain of the differential amplifier circuit according to the second embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing a configuration of a differential amplifier circuit according to a third embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing a configuration of a differential amplifier circuit according to a fourth embodiment of the present invention. [Figure 12] FIG. 12 is a diagram showing another configuration of the differential amplifier circuit according to the fourth embodiment of the present invention. [Figure 13] FIG. 13 is a diagram showing a configuration of a cascode type differential amplifier circuit. [Figure 14] FIG. 14 is a diagram showing a configuration of a conventional differential amplifier circuit. [Figure 15] FIG. 15 is a diagram showing another configuration of a conventional differential amplifier circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] [Principle of the invention] In the present invention, the above-mentioned problems are solved by applying a circuit based on a transmission line to the tail current source circuit of a differential amplifier circuit. Figure 1 is a diagram showing the configuration of a differential amplifier circuit according to the present invention. The differential amplifier circuit comprises a transistor Q1 having a gate terminal connected to an input port INP and a drain terminal connected to an output port OUTN, a transistor Q2 having a gate terminal connected to the input port INN and a drain terminal connected to the output port OUTP, and a bias voltage V GG2 The bias circuit 1 supplies the power supply voltage V to the drain terminals of the transistors Q1 and Q2. DD and a short stub S1 having one end connected to the source terminals of the transistors Q1 and Q2 and the other end connected to ground.

[0019] The differential pair of transistors Q1 and Q2 constitute an amplifier section 5. The transistors Q1 and Q2 each constitute a common-source amplifier circuit. The gate terminals of the transistors Q1 and Q2 are the input terminals of the amplifier section 5, the drain terminals are the output terminals of the amplifier section 5, and the source terminals are the ground terminals of the amplifier section 5.

[0020] The bias circuit 1 is, for example, a bias voltage V GG2 The resistor applied to the gate terminal of the transistor Q1 and the bias voltage V GG2 to the gate terminal of the transistor Q2. Similarly, the bias circuit 2 is configured with, for example, a power supply voltage V DD The resistance applied to the drain terminal of the transistor Q1 and the power supply voltage V DD to the drain terminal of transistor Q2.

[0021] In the present invention, a short stub S1 made of a transmission line is used as the tail current circuit of the differential amplifier circuit as shown in Fig. 1. By setting the length of the short stub S1 to a quarter wavelength at the operating frequency of the differential amplifier circuit, the impedance when looking at the short stub S1 from point X becomes very high. This is equivalent to the source terminals of the transistors Q1 and Q2 being open, and the differential amplifier circuit in Fig. 1 operates in the same way as the configuration in Fig. 14.

[0022] In the present invention, since a current source transistor is not required, the problem of increased power consumption, which is an issue with conventional differential amplifier circuits, can be resolved. In addition, in the present invention, by using a short stub S1 that can realize a symmetrical structure, the layout problem caused by using an asymmetrical inductor can be resolved.

[0023] However, the configuration of Figure 1 poses a serious problem in terms of integrated circuit layout when applied to a multistage amplifier circuit in a frequency band of 300 GHz or higher. This problem is explained below. In the case of an integrated circuit process using an InP substrate or a Si substrate, the length of a quarter-wavelength line in the 300 GHz band is approximately 100 to 200 μm. This value is unacceptably large when considering multistage differential amplifier circuits.

[0024] Usually, in the frequency band of 300 GHz or more, the gain per transistor is small, so that an amplifier circuit having a significant gain can be configured only by arranging transistors in multiple stages, as described in the above-mentioned Non-Patent Document 2. In such a multi-stage amplifier circuit, reducing the loss of the inter-stage matching circuit connecting the amplifier circuits as much as possible is an extremely important design issue in order to ensure the gain of the multi-stage amplifier circuit. In order to reduce the loss of the inter-stage matching circuit, it is important to shorten the physical length of the inter-stage matching circuit as much as possible, as described in Non-Patent Document 2.

[0025] Figure 2 shows a multi-stage configuration of the differential amplifier circuit in Figure 1. In the example in Figure 2, five differential amplifier circuits are connected in series. As in Figure 1, one end of the short stub S1 in each stage is connected to the source terminals of transistors Q1 and Q2, and the other end is connected to ground.

[0026] The first-stage interstage matching circuits 3 and 4 are inserted between the input ports INP and INN and the gate terminals of the first-stage transistors Q1 and Q2. The first-stage interstage matching circuit 3 matches the impedance of the input port INP to the impedance of the gate terminal of the first-stage transistor Q1 as seen from the input port INP. The first-stage interstage matching circuit 4 matches the impedance of the input port INN to the impedance of the gate terminal of the first-stage transistor Q2 as seen from the input port INN.

[0027] The input terminal of the interstage matching circuit 3 other than the first stage is connected to the drain terminal of the transistor Q1 in the previous stage, and the output terminal is connected to the gate terminal of the transistor Q1 in the subsequent stage. The input terminal of the interstage matching circuit 4 other than the first stage is connected to the drain terminal of the transistor Q2 in the previous stage, and the output terminal is connected to the gate terminal of the transistor Q2 in the subsequent stage. The interstage matching circuit 3 other than the first stage matches the impedance of the drain terminal of the transistor Q1 in the previous stage and the impedance of the gate terminal of the transistor Q1 in the subsequent stage as viewed from the drain terminal. The interstage matching circuit 4 other than the first stage matches the impedance of the drain terminal of the transistor Q2 in the previous stage and the impedance of the gate terminal of the transistor Q2 in the subsequent stage as viewed from the drain terminal.

[0028] The drain terminals of the final stage transistors Q1 and Q2 are connected to the output ports OUTN and OUTP. In the example of FIG. 2, the specific wiring of the bias circuit is not shown, but the bias voltage V GG2 The bias circuit 1 supplies the power supply voltage V to the drain terminals of the transistors Q1 and Q2 in each stage. DD A bias circuit 2 for supplying the

[0029] 2, the length of each of the interstage matching circuits 3 and 4 cannot be made shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit. Therefore, a loss equivalent to a quarter wavelength line (about 1.5 dB) is applied between the stages of the amplifier circuit, making it impossible to configure a high-gain multistage amplifier circuit.

[0030] In order to quantitatively explain the decrease in gain of the differential amplifier circuit in Figure 2, Figure 3 shows the gain of the differential amplifier circuit when a short stub S1 with a length of 140 μm, which corresponds to a quarter wavelength of 300 GHz, is used as the tail current circuit.

[0031] 3 indicates the gain when the interstage matching circuits 3 and 4 are matching circuits with an appropriate physical length (about 20 to 40 μm) as used in Non-Patent Document 2. However, it is practically impossible to arrange the interstage matching circuits 3 and 4 with this length in the layout of FIG. On the other hand, 31 in FIG. 3 indicates the gain in the case of a practically feasible layout in which the length of the inter-stage matching circuits 3 and 4 is set to 140 μm.

[0032] As is clear from Figure 3, when the length of the interstage matching circuits 3 and 4 is set to 140 μm, the gain is significantly reduced due to the loss of the quarter-wavelength line. For example, at 300 GHz, the gain is reduced by 7.5 dB compared to when the interstage matching circuits 3 and 4 are set to the appropriate physical length. In other words, it can be seen that a loss increase of 1.5 dB occurs per stage, which is the loss of the quarter-wavelength line. Furthermore, since the loss of the transmission line increases with increasing frequency, it can be seen that the difference in gain between the cases 30 and 31 in Figure 3 increases with increasing frequency.

[0033] Therefore, it is desirable to make the length of the short stub S1 shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit. Therefore, consider the configuration shown in Figure 4. In the case of the configuration in Figure 4, the source terminals of the transistors Q1 and Q2 are not completely open, and it is equivalent to a configuration in which an inductance is inserted between the source terminals of the transistors Q1 and Q2 and the ground. This inductance has the effect of degeneration of the gain of the source-grounded amplifier circuit.

[0034] Figure 5 shows the change in the common-mode gain of the differential amplifier circuit when the length Ltail of the short stub S1 in Figure 4 is changed from 0 to 140 μm. In the example of Figure 5, the length of the interstage matching circuits 3 and 4 is set to 140 μm. Figure 5 shows that by setting Ltail to 140 μm, which corresponds to a quarter wavelength of the 300 GHz band, the gain is significantly reduced in the range of 200 to 300 GHz.

[0035] It can also be seen that even when a short stub S1 shorter than a quarter wavelength is used, the gain decreases due to the gain degeneracy effect. The gain degeneracy effect caused by making the short stub S1 shorter than a quarter wavelength is very small at low frequencies. However, at around 300 GHz, since the transistor gain is small, it can be seen that the common-mode gain can be kept below 0 dB even when a short stub S1 with a length of 80 μm is used. Therefore, by making the circuit in Figure 4 into multiple stages, a differential amplifier circuit with a large CMRR can be realized even with a stub length of 80 μm.

[0036] As described above, in the present invention, a short stub made of a transmission line is used as a tail current circuit of a differential amplifier circuit. In particular, in order to reduce the matching loss of the interstage matching circuit, which is important when designing a multistage amplifier circuit, a stub length shorter than a quarter wavelength is used, and the short stub acts as an inductor with an equivalent gain degeneration effect to reduce the common-mode gain.

[0037] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 6 is a diagram showing the configuration of a differential amplifier circuit according to a first embodiment of the present invention. This embodiment is a specific example of the configuration described in the principle of the invention. In this embodiment, the short stub S1a and the inter-stage matching circuits 3a and 4a have the same length, and are shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit. In the example of FIG. 6, five stages of differential amplifier circuits are connected in series, similar to FIG. 2.

[0038] As in Figure 2, in the example of Figure 6, a bias voltage V is applied to the gate terminals of the transistors Q1 and Q2 in each stage. GG2 The bias circuit 1 supplies the power supply voltage V to the drain terminals of the transistors Q1 and Q2 in each stage. DD A bias circuit 2 for supplying the

[0039] In this embodiment, the calculation results of the differential gain and common-mode gain of the differential amplifier circuit when the length of the short stub S1a and the inter-stage matching circuits 3a and 4a is set to 80 μm are shown in Fig. 7. In Fig. 7, 70 indicates the differential gain, and 71 indicates the common-mode gain.

[0040] As can be seen from Figure 7, the differential gain is larger than that of the case of 31 in Figure 3 due to the shortening of the interstage matching circuits 3a and 4a. Also, the common-mode gain is suppressed to 0 dB or less. As a result, the CMRR, defined as the ratio of the differential gain to the common-mode gain, is secured at 15 dB at 300 GHz.

[0041] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 8 is a diagram showing the configuration of a differential amplifier circuit according to a second embodiment of the present invention. In this embodiment, in order to obtain a larger common-mode rejection ratio than that of the first embodiment, a capacitance C is added in parallel with the short stub S1a between the source terminals of the transistors Q1 and Q2 and the ground.

[0042] The capacitance C and the inductance L of the short stub S1a form an LC resonant circuit at the following frequency F. Since this LC resonant circuit is a parallel resonant circuit, it is equivalent to an open circuit at the resonant frequency F when viewed from the transistors Q1 and Q2. Therefore, in this embodiment, a very large CMRR can be obtained. F = 1 / (2π√LC) (1)

[0043] This resonant frequency F can be set as the operating frequency of the differential amplifier circuit. The calculation results of the differential gain and common-mode gain of the differential amplifier circuit of this embodiment are shown in Figure 9. As in Figure 7, in the example of Figure 9, the length of the short stub S1a and the inter-stage matching circuits 3a and 4a is 80 μm. The value of the capacitance C is 4 fF. In Figure 9, 90 indicates the differential gain, and 91 indicates the common-mode gain.

[0044] 9 and 7, it is apparent that this embodiment can reduce the common-mode gain by 2 dB or more at 300 GHz, thereby improving the CMRR of the differential amplifier circuit by 2 dB or more.

[0045] Another advantage of this embodiment is that the short stub S1a can be shortened. In other words, if the short stub S1a is shortened within a range where the value of formula (1) is the same as the resonant frequency F, and the capacitance C is increased instead, the same CMRR improvement effect as when the short stub S1a is long can be obtained.

[0046] For example, when it is desired to shorten the interstage matching circuits 3a and 4a, the short stub S1a disposed between the interstage matching circuits 3a and 4a may be shortened. In other words, this can be achieved by reducing the inductance L in formula (1) and increasing the capacitance C. In general, in a frequency band exceeding 300 GHz, the width of the inductance L (length of the short stub S1a) and capacitance C that can be realized by the layout is determined. Therefore, it is only necessary to find the length of the short stub S1a and the value of the capacitance C that can be laid out within the range that satisfies formula (1). In this way, in this embodiment, the length of the short stub S1a and the value of the capacitance C can be appropriately selected to improve the degree of freedom in the layout of the differential amplifier circuit.

[0047] [Third Example] Next, a third embodiment of the present invention will be described. Fig. 10 is a diagram showing the configuration of a differential amplifier circuit according to a third embodiment of the present invention. In this embodiment, instead of the capacitance C in the second embodiment, an open stub S2 is provided, which is a transmission line having one end connected to the source terminals of transistors Q1 and Q2 and the other end open. This embodiment provides a configuration that can be realized when it is necessary to use a small capacitance in the second embodiment.

[0048] Generally, a small capacitance of about several fF has a large fringe effect, making it difficult to estimate an accurate value during layout. Therefore, as shown in Fig. 10, it is possible to replace the capacitance C with an open stub S2. The open stub S2, which is sufficiently shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit, functions equivalently as a parallel capacitance of the short stub S1a in the same manner as in the configuration of Fig. 8. Therefore, this embodiment has the same common mode rejection effect as the second embodiment.

[0049] By determining the length of the open stub S2 so that the equivalent capacitance satisfies equation (1), it is possible to realize a capacitance of several fF with high precision, which is generally difficult to achieve.

[0050] [Fourth Example] Next, a fourth embodiment of the present invention will be described. Fig. 11 is a diagram showing the configuration of a differential amplifier circuit according to a fourth embodiment of the present invention. In this embodiment, a resistor R is inserted in series with a capacitor C between the source terminals of transistors Q1 and Q2 and the ground in the second embodiment.

[0051] According to this embodiment, the Q value of the resonance determined by the formula (1) can be reduced, and the common mode rejection effect can be achieved over a wider band.

[0052] It is also possible to apply a resistor R to the third embodiment as shown in Fig. 12. In the example of Fig. 12, a resistor R is inserted between the source terminals of the transistors Q1 and Q2 and the open stub S2.

[0053] In the first to fourth embodiments, examples of differential amplifier circuits using two transistors Q1 and Q2 that respectively constitute a common-source amplifier circuit have been described, but the present invention may also be applied to a cascode-type differential amplifier circuit. Fig. 13 is a diagram showing the configuration of a cascode-type differential amplifier circuit. The cascode-type differential amplifier circuit comprises a transistor Q1 having a gate terminal connected to the output terminal of an interstage matching circuit 3a and a drain terminal connected to an output port OUTN, a transistor Q2 having a gate terminal connected to the output terminal of an interstage matching circuit 4a and a drain terminal connected to an output port OUTP, and a transistor Q3 having a gate terminal connected to a bias voltage V GG3 is applied to the transistor Q3 whose source terminal is connected to the drain terminal of the transistor Q1 and whose gate terminal is connected to the bias voltage V GG3 is applied to the transistor Q4, whose source terminal is connected to the drain terminal of the transistor Q2, and a short stub S1a, whose one end is connected to the source terminals of the transistors Q1 and Q2 and whose other end is connected to ground. The transistors Q1 and Q2 and the transistors Q3 and Q4, which are cascode-connected to the transistors Q1 and Q2, constitute an amplifier section 5a (cascode amplifier circuit).

[0054] As described in the first to fourth embodiments, the bias circuit 1 applies a bias voltage VGG2 In addition, the bias circuit 6 supplies a bias voltage V GG3 The bias circuit 2 supplies the power supply voltage V to the drain terminals of the transistors Q3 and Q4 of each stage. DD can be supplied.

[0055] When the differential amplifier circuit of Fig. 13 is made multi-stage, the input terminal of the interstage matching circuit 3a other than the first stage is connected to the drain terminal of the transistor Q1 and the source terminal of the transistor Q3 of the previous stage, and the output terminal of the interstage matching circuit 3a is connected to the gate terminal of the transistor Q1 of the next stage. Also, the input terminal of the interstage matching circuit 4a other than the first stage is connected to the drain terminal of the transistor Q2 and the source terminal of the transistor Q4 of the previous stage, and the output terminal of the interstage matching circuit 4a is connected to the gate terminal of the transistor Q2 of the next stage. The drain terminal of the transistor Q1 and the source terminal of the transistor Q3 of the last stage are connected to the output port OUTN. The drain terminal of the transistor Q2 and the source terminal of the transistor Q4 of the last stage are connected to the output port OUTP.

[0056] In Figures 1, 2, 4, 6, 8, and 10 to 13, field effect transistors are used as the transistors Q1 to Q4, but bipolar transistors may be used. When bipolar transistors are used, the gate terminals are replaced with base terminals, the drain terminals with collector terminals, and the source terminals with emitter terminals (ground terminals) in the above description. It goes without saying that when bipolar transistors are used in Figures 1, 2, 4, 6, 8, and 10 to 12, the transistors Q1 and Q2 each constitute a grounded emitter amplifier circuit. [Industrial Applicability]

[0057] The present invention can be applied to a differential amplifier circuit. [Explanation of symbols]

[0058] 1, 2, 6...bias circuit, 3, 3a, 4, 4a...interstage matching circuit, 5, 5a...amplifier section, Q1 to Q4...transistors, C...capacitance, R...resistor, S1, S1a...short stub, S2...open stub.

Claims

1. an amplifier section including a differential pair of transistors to which a differential signal is input; a tail current circuit including a short stub provided between the ground terminal of the amplifier unit and ground; A differential amplifier circuit, wherein the electrical length of the short stub is shorter than a quarter wavelength of an operating frequency of the differential amplifier circuit.

2. An amplifier section including a differential pair transistor to which a differential signal is input; a tail current circuit including a short stub provided between the ground terminal of the amplifier and ground; a capacitance provided in parallel with the short stub between a ground terminal of the amplifier unit and ground, The inductance and capacitance of the short stub form an LC resonant circuit, and when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F = 1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit.

3. An amplifier section including a differential pair transistor to which a differential signal is input; a tail current circuit including a short stub provided between the ground terminal of the amplifier and ground; a capacitance provided in parallel with the short stub between a ground terminal of the amplifier unit and ground, The inductance and capacitance of the short stub constitute an LC resonant circuit, and when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F=1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit, A differential amplifier circuit, wherein the electrical length of the short stub is shorter than a quarter wavelength of an operating frequency of the differential amplifier circuit.

4. 4. The differential amplifier circuit according to claim 2, A differential amplifier circuit further comprising a resistor inserted in series with the capacitance between a ground terminal of the amplifier section and ground.

5. An amplifier section including a differential pair transistor to which a differential signal is input; a tail current circuit including a short stub provided between the ground terminal of the amplifier and ground; an open stub having one end connected to the ground terminal of the amplifier and the other end open; the electrical length of the open stub is shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit; A differential amplifier circuit characterized in that the inductance of the short stub and the capacitance of the open stub form an LC resonant circuit, and when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F = 1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit.

6. An amplifier section including a differential pair transistor to which a differential signal is input; a tail current circuit including a short stub provided between the ground terminal of the amplifier and ground; an open stub having one end connected to the ground terminal of the amplifier and the other end open; the electrical length of the open stub is shorter than a quarter wavelength of the operating frequency of the differential amplifier circuit; The inductance of the short stub and the capacitance of the open stub form an LC resonant circuit, and when the value of the inductance is L and the value of the capacitance is C, the resonant frequency F=1 / (2π√LC) of the LC resonant circuit is set to the operating frequency of the differential amplifier circuit, A differential amplifier circuit, wherein the electrical length of the short stub is shorter than a quarter wavelength of an operating frequency of the differential amplifier circuit.

7. 7. The differential amplifier circuit according to claim 5, 4. A differential amplifier circuit comprising: a first terminal for amplifying a first signal; a second terminal for amplifying a first signal;

8. 8. The differential amplifier circuit according to claim 1, the amplifier section being any one of a common-source amplifier circuit including the differential pair transistors, a common-emitter amplifier circuit including the differential pair transistors, and a cascode amplifier circuit including the differential pair transistors and a pair of transistors cascode-connected to the differential pair transistors.

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