Fault diagnosis circuit, electronic circuit, physical quantity detection circuit, physical quantity sensor, electronic device, and mobile object

Abstract

To provide a physical quantity detection circuit that can reduce the possibility of performing incorrect determination that a circuit for generating a reference voltage has failed even if the reference voltage temporarily fluctuates.SOLUTION: A physical quantity detection circuit comprises: a detection signal generation circuit that, based on an output signal of a physical quantity detection element that detects a physical quantity, generates a detection signal according to the physical quantity; an analog / digital conversion circuit that converts the detection signal into a digital signal; a reference voltage generation circuit that generates a reference voltage to be supplied to the analog / digital conversion circuit; and a fault diagnosis circuit that monitors the reference voltage to perform fault diagnosis of the reference voltage generation circuit, and outputs a fault diagnosis signal indicating a result of the fault diagnosis. The fault diagnosis circuit performs the fault diagnosis at a predetermined timing different from the timing when the reference voltage temporarily fluctuates in accordance with the operation of the analog / digital conversion circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a physical quantity detection circuit, a physical quantity sensor, an electronic device, a mobile object, and a method for diagnosing a fault in the physical quantity sensor. [Background technology]

[0002] Currently, physical quantity sensors capable of detecting various physical quantities, such as gyro sensors that detect angular velocity and acceleration sensors that detect acceleration, are widely used in various systems and electronic devices. In recent years, in order to build a system that requires high reliability, such as a system mounted on a vehicle, a function of diagnosing a malfunction of the physical quantity sensor itself may be required. In addition, in recent years, in order to build a highly reliable system, a physical quantity sensor that outputs detection information of a physical quantity as digital data with high noise resistance has been used. In general, such a physical quantity sensor includes a physical quantity detection element and a physical quantity detection circuit that generates an analog signal corresponding to the detected physical quantity based on a signal output from the physical quantity detection element, converts the analog signal into a digital signal by an A / D conversion circuit, and then performs digital signal processing.

[0003] Patent Document 1 describes a power supply monitoring device for a vehicle electronic circuit that monitors the output voltage of a power supply circuit and outputs a power supply failure signal when the output voltage falls outside a predetermined range. Patent Document 2 describes a failure detection device that includes multiple sensors, an AD converter that converts the output voltages of the multiple sensors into digital values, a reference voltage supplying means that supplies a reference voltage to the multiple sensors and the AD converter, and a means that determines that the reference voltage supplying means has failed when it is detected that at least two of the AD converted values ​​of the output voltages of the multiple sensors fall outside a predetermined range.

[0004] For example, by applying the power supply monitoring device described in Patent Document 1 or the fault detection device described in Patent Document 2, a physical quantity sensor that diagnoses its own faults can be realized. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 58-54830 [Patent Document 2] Japanese Patent Application Publication No. 4-81615 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in a physical quantity sensor that employs the power supply monitoring device described in Patent Document 1 or the fault detection device described in Patent Document 2, if the reference voltage temporarily fluctuates outside a specified range due to the operation of a signal processing circuit that processes a signal output from the physical quantity detection element or an analog / digital conversion circuit that converts the output signal of the signal processing circuit into a digital signal, there is a risk that the circuit that generates the reference voltage will be erroneously determined to have failed. [Means for solving the problem]

[0007] One aspect of the physical quantity detection circuit according to the present invention is a detection signal generating circuit that generates a detection signal corresponding to a physical quantity based on an output signal of a physical quantity detecting element that detects the physical quantity; an analog / digital conversion circuit for converting the detection signal into a digital signal; a reference voltage generation circuit that generates a reference voltage to be supplied to the analog-to-digital conversion circuit; and a fault diagnosis circuit that monitors the reference voltage, performs fault diagnosis on the reference voltage generation circuit, and outputs a fault diagnosis signal indicative of a result of the fault diagnosis, The fault diagnosis circuit performs the fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily varies in accordance with the operation of the analog / digital conversion circuit.

[0008] One aspect of the physical quantity detection circuit according to the present invention is a physical quantity signal processing circuit that outputs a drive signal for driving a physical quantity detection element that detects a physical quantity, and generates a detection signal corresponding to the physical quantity based on an output signal from the physical quantity detection element; a reference voltage generating circuit that generates a reference voltage to be supplied to the physical quantity signal processing circuit; a fault diagnosis circuit that monitors the reference voltage to perform a fault diagnosis on the reference voltage generating circuit and outputs a fault diagnosis signal indicative of a result of the fault diagnosis; The fault diagnosis circuit performs the fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily varies in association with the operation of the physical quantity signal processing circuit.

[0009] One aspect of the physical quantity sensor according to the present invention is An embodiment of the physical quantity detection circuit; The physical quantity detection element.

[0010] One aspect of the electronic device according to the present invention is An embodiment of the physical quantity sensor; and a processing circuit that performs processing based on the output signal of the physical quantity sensor.

[0011] One aspect of the moving body according to the present invention is An embodiment of the physical quantity sensor; and a processing circuit that performs processing based on the output signal of the physical quantity sensor.

[0012] One aspect of a fault diagnosis method for a physical quantity sensor according to the present invention includes: A fault diagnosis method for a physical quantity sensor including a physical quantity detection element that detects a physical quantity, a detection circuit that generates a detection signal corresponding to the physical quantity based on an output signal of the physical quantity detection element, an analog / digital conversion circuit that converts the detection signal into a digital signal, and a reference voltage generation circuit that generates a reference voltage to be supplied to the analog / digital conversion circuit, a fault diagnosis step of monitoring the reference voltage to perform a fault diagnosis on the reference voltage generating circuit and outputting a fault diagnosis signal indicating a result of the fault diagnosis; In the failure diagnosis step, the failure diagnosis is performed at a predetermined timing different from a timing at which the reference voltage temporarily varies in association with the operation of the analog / digital conversion circuit.

[0013] One aspect of a fault diagnosis method for a physical quantity sensor according to the present invention includes: A fault diagnosis method for a physical quantity sensor including a physical quantity detection element that detects a physical quantity, a physical quantity signal processing circuit that outputs a drive signal for driving the physical quantity detection element and generates a detection signal corresponding to the physical quantity based on an output signal of the physical quantity detection element, and a reference voltage generation circuit that generates a reference voltage to be supplied to the physical quantity signal processing circuit, a fault diagnosis step of monitoring the reference voltage to perform a fault diagnosis on the reference voltage generating circuit and outputting a fault diagnosis signal indicating a result of the fault diagnosis; In the fault diagnosis step, the fault diagnosis is performed at a predetermined timing different from a timing at which the reference voltage temporarily varies in association with an operation of the physical quantity signal processing circuit. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a functional block diagram of the physical quantity sensor according to the first embodiment. [Diagram 2] FIG. 2 is a diagram showing a configuration example of a selection circuit and an analog / digital conversion circuit. [Diagram 3] FIG. 1 is a diagram showing an example of a channel configuration for time-division processing using an analog / digital conversion circuit. [Figure 4] 2 is a diagram showing an example of the configuration of a part of a reference voltage generating circuit and a fault diagnosis circuit in the first embodiment. [Diagram 5] 4 is a diagram showing an example of waveforms of various signals when the reference voltage generating circuit is not malfunctioning in the first embodiment. [Figure 6] 5 is a diagram showing an example of waveforms of various signals when a reference voltage generating circuit has a failure in the first embodiment. [Figure 7] FIG. 2 is a flowchart showing an example of a procedure of the fault diagnosis method according to the first embodiment. [Figure 8] FIG. 11 is a functional block diagram of a physical quantity sensor according to a second embodiment. [Figure 9] FIG. 13 is a diagram showing an example of the configuration of a part of a reference voltage generating circuit and a fault diagnosis circuit in a second embodiment. [Figure 10]13 is a diagram showing an example of waveforms of various signals when the reference voltage generating circuit is not malfunctioning in the second embodiment. [Figure 11] 13 is a diagram showing an example of waveforms of various signals when a reference voltage generating circuit has a failure in the second embodiment. [Figure 12] FIG. 11 is a flowchart showing an example of a procedure of a fault diagnosis method according to a second embodiment. [Figure 13] FIG. 2 is a functional block diagram showing an example of the configuration of the electronic device according to the embodiment. [Figure 14] FIG. 1 is a perspective view illustrating a digital camera as an example of an electronic device. [Figure 15] FIG. 2 is a diagram showing an example of a moving body according to the embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0016] In the following, a physical quantity sensor that detects angular velocity and acceleration as physical quantities will be described as an example.

[0017] 1. Physical quantity sensor 1-1. First embodiment 1-1-1. Physical quantity sensor configuration 1 is a functional block diagram of a physical quantity sensor according to the first embodiment. A physical quantity sensor 1 according to the first embodiment includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0018] The acceleration detecting elements 4X and 4Y are physical quantity detecting elements that detect acceleration as a physical quantity. The acceleration detection element 4X detects acceleration in the direction of the X-axis, and the acceleration detection element 4Y detects acceleration in the direction of the Y-axis perpendicular to the X-axis. For example, the acceleration detection elements 4X and 4Y may be elements having a capacitance where a driving electrode and a detection electrode (not shown) are arranged, the amount of charge of the capacitance changes according to the acceleration, and the acceleration detection elements 4X and 4Y may be elements that output a signal according to the amount of charge. For example, the acceleration detection elements 4X and 4Y may be MEMS (Micro Electro Mechanical Systems) elements.

[0019] The angular velocity detection element 3 is a physical quantity detection element that detects angular velocity as a physical quantity. In this embodiment, the angular velocity detection element 3 detects angular velocity around the Z axis that is perpendicular to the X axis and the Y axis. For example, the angular velocity detection element 3 may be an element having a vibrating piece on which a driving electrode and a detection electrode (not shown) are arranged, in which the magnitude of vibration of the vibrating piece changes according to the angular velocity, and a signal corresponding to the magnitude of the vibration is output. For example, the angular velocity detection element 3 may be an element having a so-called double T-type quartz crystal vibrating piece having two T-shaped driving vibrating arms.

[0020] The physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog / digital conversion circuit 60, a digital signal processing circuit 70, a fault diagnosis circuit 80, a control circuit 90, a storage unit 100, an interface circuit 110, and an oscillation circuit 120. The physical quantity detection circuit 2 may be realized, for example, by a one-chip integrated circuit. Note that the physical quantity detection circuit 2 may have a configuration in which some of these elements are omitted or modified, or other elements are added.

[0021] The reference voltage generating circuit 40 generates various reference voltages based on a power supply voltage VDD and a ground voltage VSS supplied from outside the physical quantity detection circuit 2. In this embodiment, the reference voltage generating circuit 40 generates a power supply voltage VGR and a common voltage VCMGR as reference voltages to be supplied to the angular velocity signal processing circuit 10. The reference voltage generating circuit 40 also generates a power supply voltage VACC and a common voltage VCMACC as reference voltages to be supplied to the acceleration signal processing circuit 20. The reference voltage generating circuit 40 also generates a full-scale voltage VFSAD and a common voltage VCMAD as reference voltages to be supplied to the analog / digital conversion circuit 60. The reference voltage generating circuit 40 also generates a power supply voltage VTS and a common voltage VCMTS as reference voltages to be supplied to the temperature sensor 30. The reference voltage generating circuit 40 also generates a power supply voltage VLGC as a reference voltage to be supplied to the logic circuit 200. The reference voltage generating circuit 40 also generates a power supply voltage VOSC as a reference voltage to be supplied to the oscillation circuit 120.

[0022] The oscillation circuit 120 operates based on the power supply voltage VOSC supplied from the reference voltage generation circuit 40, and generates a clock signal MCK. The oscillation circuit 120 may be configured as, for example, a ring oscillator or a CR oscillation circuit.

[0023] The angular velocity signal processing circuit 10 includes a drive circuit 11 and a detection circuit 12, and operates based on a power supply voltage VGR and a common voltage VCMGR supplied from a reference voltage generating circuit 40.

[0024] The driving circuit 11 generates a driving signal DRVGR for exciting and vibrating the angular velocity detection element 3, and supplies it to the angular velocity detection element 3. For example, the driving signal DRVGR is a square wave signal with the power supply voltage VGR at a high level and the ground voltage VSS at a low level. The driving circuit 11 also receives an oscillation current generated by the excitation and vibration of the angular velocity detection element 3, and feedback controls the amplitude level of the driving signal so that the amplitude of the oscillation current is kept constant. When an angular velocity about the Z axis is applied while the angular velocity detection element 3 is being excited and vibrating, the angular velocity detection element 3 detects the angular velocity and outputs a signal corresponding to the angular velocity. In this embodiment, the signal output from the angular velocity detection element 3 is a differential signal.

[0025] The detection circuit 12 is a detection signal generation circuit that generates a detection signal corresponding to the angular velocity around the Z axis based on the output signal of the angular velocity detection element 3. Specifically, the detection circuit 12 detects an angular velocity component included in the signal output from the angular velocity detection element 3, and generates and outputs an angular velocity detection signal GRO1 having a voltage level corresponding to the magnitude of the angular velocity component. The detection circuit 12 also detects a vibration leakage component included in the signal output from the angular velocity detection element 3, and generates and outputs a vibration leakage signal GRO2 having a voltage level corresponding to the magnitude of the vibration leakage component. In this embodiment, the angular velocity detection signal GRO1 and the vibration leakage signal GRO2 are differential signals each based on the common voltage VCMGR.

[0026] In this way, the angular velocity signal processing circuit 10 is a physical quantity signal processing circuit that outputs a drive signal DRVGR that drives the angular velocity detection element 3 and generates a detection signal corresponding to the angular velocity around the Z axis, which is one of the physical quantities, based on the output signal of the angular velocity detection element 3.

[0027] The acceleration signal processing circuit 20 includes a drive circuit 21, a detection circuit 22X, and a detection circuit 22Y, and operates based on a power supply voltage VACC and a common voltage VMACC supplied from a reference voltage generation circuit 40. The acceleration signal processing circuit 20 is controlled based on n control signals CTL1 to CTLn supplied from a control circuit 90, where n is an integer equal to or greater than 1.

[0028] The driving circuit 21 generates a driving signal DRVACC and outputs it to the acceleration detection elements 4X and 4Y to drive the acceleration detection elements 4X and 4Y. For example, the driving signal DRVACC is a square wave signal with the power supply voltage VACC at a high level and the ground voltage VSS at a low level. When acceleration in the X-axis direction is applied in this state, the acceleration detection element 4X detects the acceleration and outputs a signal corresponding to the acceleration. When acceleration in the Y-axis direction is applied, the acceleration detection element 4Y detects the acceleration and outputs a signal corresponding to the acceleration. In this embodiment, the signals output from the acceleration detection elements 4X and 4Y are differential signals.

[0029] The detection circuit 22X is a detection signal generating circuit that generates a detection signal corresponding to the acceleration in the X-axis direction based on the output signal of the acceleration detection element 4X. Specifically, the detection circuit 22X detects the acceleration component included in the signal output from the acceleration detection element 4X, and generates and outputs the X-axis acceleration detection signal AXO having a voltage level corresponding to the magnitude of the acceleration component. In this embodiment, the X-axis acceleration detection signal AXO is a differential signal based on the common voltage VCMACC.

[0030] The detection circuit 22Y is a detection signal generating circuit that generates a detection signal corresponding to the acceleration in the Y-axis direction based on the output signal of the acceleration detection element 4Y. Specifically, the detection circuit 22Y detects the acceleration component included in the signal output from the acceleration detection element 4Y, and generates and outputs the Y-axis acceleration detection signal AYO with a voltage level corresponding to the magnitude of the acceleration component. In this embodiment, the Y-axis acceleration detection signal AYO is a differential signal based on the common voltage VCMACC.

[0031] In this manner, the acceleration signal processing circuit 20 is a physical quantity signal processing circuit that outputs a drive signal DRVACC to drive the acceleration detection elements 4X, 4Y, generates a detection signal corresponding to the acceleration in the X-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4X, and generates a detection signal corresponding to the acceleration in the Y-axis direction, which is one of the physical quantities, based on the output signal of the acceleration detection element 4Y.

[0032] The temperature sensor 30 detects temperature based on the power supply voltage VTS and the common voltage VCMTS supplied from the reference voltage generating circuit 40, and outputs a temperature detection signal TSO having a voltage level according to the temperature. The temperature sensor 30 may be, for example, a circuit that utilizes the temperature characteristics of a band gap reference circuit. In this embodiment, the temperature detection signal TSO is a differential signal based on the common voltage VCMTS.

[0033] The selection circuit 50 selects and outputs one of the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO based on a selection signal SEL from the control circuit 90. In this embodiment, the output signal MXO of the selection circuit 50 is a differential signal.

[0034] The analog / digital conversion circuit 60 operates based on the full-scale voltage VFSAD and common voltage VCMAD supplied from the reference voltage generation circuit 40. The analog / digital conversion circuit 60 converts the output signal MXO of the selection circuit 50 into a digital signal ADO and outputs it based on various control signals supplied from the control circuit 90. Specifically, the analog / digital conversion circuit 60 converts the signal MXO, which is a differential signal, into the digital signal ADO, with the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full scale.

[0035] The digital signal processing circuit 70 processes the digital signal ADO output from the analog / digital conversion circuit 60, based on various control signals supplied from the control circuit 90. For example, the digital signal processing circuit 70 outputs a digital signal DSPO that has been subjected to digital filtering and correction arithmetic processing of the digital signal ADO.

[0036] Fault diagnosis circuit 80 monitors common voltage VCMAD to perform fault diagnosis on reference voltage generation circuit 40, and outputs fault diagnosis signal FLG2 indicating the result of the fault diagnosis. Particularly in this embodiment, fault diagnosis circuit 80 performs fault diagnosis on reference voltage generation circuit 40 at a predetermined timing different from the timing at which common voltage VCMAD temporarily fluctuates in association with the operation of analog-to-digital conversion circuit 60.

[0037] For example, the timing at which the common voltage VCMAD temporarily varies may be the timing at which the analog / digital conversion circuit 60 starts sampling the output signal MXO of the selection circuit 50, and the fault diagnosis circuit 80 may perform fault diagnosis at a predetermined timing different from that timing. Also, for example, the timing at which the common voltage VCMAD temporarily varies may be the timing at which the analog / digital conversion circuit 60 ends sampling the output signal MXO of the selection circuit 50, and the fault diagnosis circuit 80 may perform fault diagnosis at a predetermined timing different from that timing.

[0038] In this embodiment, the fault diagnosis circuit 80 includes an abnormality determination circuit 81 and a fault diagnosis signal output circuit 82.

[0039] The abnormality determination circuit 81 determines whether the common voltage VCMAD is abnormal, and outputs an abnormality determination signal FLG1 indicating the determination result. For example, the abnormality determination signal FLG1 may be a flag signal that is at a high level when the common voltage VCMAD is abnormal and is at a low level when the common voltage VCMAD is normal.

[0040] The fault diagnosis signal output circuit 82 receives the abnormality determination signal FLG1 at a predetermined timing and outputs the fault diagnosis signal FLG2. For example, the fault diagnosis signal FLG2 may be a flag signal that is at a high level when the reference voltage generation circuit 40 is faulty and is at a low level when the reference voltage generation circuit 40 is not faulty. In this embodiment, the fault diagnosis signal output circuit 82 receives the abnormality determination signal FLG1 at the timing of the rising edge of the clock signal WCK supplied from the control circuit 90 and outputs the fault diagnosis signal FLG2. As will be described later, the timing of the rising edge of the clock signal WCK is a predetermined timing different from the timing at which the common voltage VCMAD temporarily varies in accordance with the operation of the analog-to-digital conversion circuit 60.

[0041] The control circuit 90 generates and outputs various control signals for controlling the operations of the analog / digital conversion circuit 60, the digital signal processing circuit 70, etc., a clock signal WCK, a selection signal SEL, and control signals CTL1 to CTLn for controlling the acceleration signal processing circuit 20.

[0042] The storage unit 100 has a non-volatile memory (not shown), and various trimming data for the angular velocity signal processing circuit 10, the acceleration signal processing circuit 20, etc., and coefficient data used in processing by the digital signal processing circuit 70 are stored in the non-volatile memory. The non-volatile memory may be configured as, for example, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). Furthermore, the storage unit 100 may have a register (not shown), and may be configured such that when the physical quantity detection circuit 2 is powered on, that is, when the voltage of the VDD terminal rises from 0V to a desired voltage, various data stored in the non-volatile memory is transferred to and held in the register, and the various data held in the register is supplied to each circuit.

[0043] The interface circuit 110 performs a process of outputting a digital signal DSPO or a fault diagnosis signal FLG2 in response to a request from an external device. The interface circuit 110 also performs a process of reading and outputting data stored in a non-volatile memory or register of the storage unit 100 in response to a request from a device external to the physical quantity detection circuit 2, and a process of writing data input from an external device to a non-volatile memory or register of the storage unit 100. The interface circuit 110 is, for example, an interface circuit for a SPI (Serial Peripheral Interface) bus or an I 2 It may be an interface circuit for an Inter-Integrated Circuit (C) bus.

[0044] The digital signal processing circuit 70, the fault diagnosis signal output circuit 82, the control circuit 90, the storage unit 100, and the interface circuit 110 constitute a logic circuit 200. The logic circuit 200 operates in response to a power supply voltage VLGC supplied from the reference voltage generating circuit 40 and a clock signal MCK.

[0045] 1-1-2. Configuration of the selection circuit and analog / digital conversion circuit FIG. 2 is a diagram showing an example of the configuration of the selection circuit 50 and the analog / digital conversion circuit 60. As shown in FIG. In the example of FIG. 2, the selection circuit 50 includes ten low-pass filters 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, and 55n and a multiplexer 56.

[0046] The differential signals GRO1_P and GRO1_N constituting the angular velocity detection signal GRO1 are low-pass filtered by low-pass filters 51p and 51n, respectively, and then input to the multiplexer 56.

[0047] The differential signals GRO2_P and GRO2_N constituting the vibration leakage signal GRO2 are low-pass filtered by low-pass filters 52p and 52n, respectively, and input to the multiplexer 56.

[0048] The differential signals AXO_P and AXO_N constituting the X-axis acceleration detection signal AXO are low-pass filtered by low-pass filters 53p and 53n, respectively, and then input to the multiplexer 56.

[0049] The differential signals AYO_P and AYO_N constituting the Y-axis acceleration detection signal AYO are low-pass filtered by low-pass filters 54p and 54n, respectively, and then input to the multiplexer 56.

[0050] The differential signals TSO_P and TSO_N constituting the temperature detection signal TSO are low-pass filtered by low-pass filters 55p and 55n, respectively, and then input to the multiplexer 56.

[0051] In response to a selection signal SEL, the multiplexer 56 selects one of the low-pass filtered differential signals GRO1_P, GRO1_N, the low-pass filtered differential signals GRO2_P, GRO2_N, the low-pass filtered differential signals AXO_P, AXO_N, the low-pass filtered differential signals AYO_P, AYO_N, and the low-pass filtered differential signals TSO_P, TSO_N, and outputs the selected differential signal as a differential signal MXO_P, MXO_N.

[0052] In the example of FIG. 2, the analog / digital conversion circuit 60 includes a precharge circuit 61, a programmable gain amplifier 62, a successive approximation register (SAR) type analog / digital converter 63, and a SAR control circuit 64.

[0053] In response to a control signal supplied from a control circuit 90, the precharge circuit 61 charges the input node of the programmable gain amplifier 62 before the conversion process by the successive approximation type analog-to-digital converter 63 is started, thereby assisting in the charging by the differential signals MXO_P, MXO_N.

[0054] The programmable gain amplifier 62 amplifies the differential signals MXO_P, MXO_N and outputs the differential signals PO_P, PO_N. The gain of the programmable gain amplifier 62 is variably set according to the type of differential signal selected as the differential signals MXO_P, MXO_N in response to a control signal supplied from the control circuit 90.

[0055] The successive approximation type analog-to-digital converter 63 converts the voltage difference between the full-scale voltage VFSAD and the ground voltage VSS as the full scale into a digital signal ADO and outputs the digital signal ADO.

[0056] The SAR control circuit 64 operates according to the clock signal MCK, and performs processing such as selecting a voltage that serves as a comparison reference according to the timing of successive approximation by the successive approximation type analog / digital converter 63 and the comparison result.

[0057] 1-1-3.Channel configuration for time-division processing As described above, the analog / digital conversion circuit 60 converts the differential signal selected by the selection circuit 50 based on the selection signal SEL into a digital signal ADO and outputs it. That is, the analog / digital conversion circuit 60 processes the angular velocity detection signal GRO1, the vibration leakage signal GRO2, the X-axis acceleration detection signal AXO, the Y-axis acceleration detection signal AYO, and the temperature detection signal TSO in a time-division manner and converts them into digital signals, respectively.

[0058] FIG. 3 is a diagram showing an example of a channel configuration for time-division processing by the analog / digital conversion circuit 60. As shown in FIG.

[0059] 3, in the first channel, the 3-bit selection signal SEL is "000", and the selection circuit 50 selects the angular velocity detection signal GRO1 as an input signal to the analog / digital conversion circuit 60. Therefore, during the first channel period, the analog / digital conversion circuit 60 converts the angular velocity detection signal GRO1, specifically the voltage difference between the differential signals GRO1_P, GRO1_N, into a digital signal ADO. In this way, in the first channel, processing is performed on the angular velocity detection signal GRO1.

[0060] In the second channel following the first channel, the 3-bit selection signal SEL is "001", and the selection circuit 50 selects the vibration leakage signal GRO2 as an input signal to the analog / digital conversion circuit 60. Therefore, during the second channel period, the analog / digital conversion circuit 60 converts the vibration leakage signal GRO2, specifically the voltage difference between the differential signals GRO2_P, GRO2_N, into the digital signal ADO. In this way, processing is performed on the vibration leakage signal GRO2 in the second channel.

[0061] In the third channel following the second channel, the 3-bit selection signal SEL is "010", and the selection circuit 50 selects the X-axis acceleration detection signal AXO as an input signal to the analog / digital conversion circuit 60. Therefore, during the third channel period, the analog / digital conversion circuit 60 converts the X-axis acceleration detection signal AXO, specifically the voltage difference between the differential signals AXO_P, AXO_N, into a digital signal ADO. In this way, processing is performed on the X-axis acceleration detection signal AXO in the third channel.

[0062] In the fourth channel following the third channel, the 3-bit selection signal SEL is "011", and the selection circuit 50 selects the Y-axis acceleration detection signal AYO as an input signal to the analog / digital conversion circuit 60. Therefore, during the fourth channel period, the analog / digital conversion circuit 60 converts the Y-axis acceleration detection signal AYO, specifically the voltage difference between the differential signals AYO_P, AYO_N, into a digital signal ADO. In this way, in the fourth channel, processing is performed on the Y-axis acceleration detection signal AYO.

[0063] In the fifth channel following the fourth channel, the 3-bit selection signal SEL is "100", and the selection circuit 50 selects the temperature detection signal TSO as an input signal to the analog / digital conversion circuit 60. Therefore, during the fifth channel period, the analog / digital conversion circuit 60 converts the temperature detection signal TSO, specifically the voltage difference between the differential signals TSO_P and TSO_N, into a digital signal ADO. In this way, processing is performed on the temperature detection signal TSO in the fifth channel.

[0064] After the fifth channel, the first channel is started again. That is, a plurality of periods of the first to fifth channels are repeated in order. In the digital signal processing circuit 70, the order and coefficient values ​​of the digital filter, the type and coefficient values ​​of the correction calculation, etc. are changed for each channel according to the signal to be processed.

[0065] 1-1-4. Configuration of fault diagnosis circuit FIG. 4 is a diagram showing an example of the configuration of a part of the reference voltage generating circuit 40 and the fault diagnosis circuit 80. As shown in FIG. In the example of FIG. 4, the reference voltage generating circuit 40 includes a bandgap reference circuit 141, resistors 142 and 143, and an operational amplifier 144.

[0066] The bandgap reference circuit 141 is a circuit that generates a constant full-scale voltage VFSAD that is stable against fluctuations in temperature and power supply voltage VDD by utilizing the bandgap voltage of a semiconductor element. The configuration of the bandgap reference circuit is well known, so illustration and description thereof will be omitted.

[0067] The resistors 142 and 143 have the same resistance value R, and the full-scale voltage VFSAD is divided into 1 / 2 by the resistors 142 and 143 , and the resulting voltage is supplied to the non-inverting input terminal of the operational amplifier 144 .

[0068] The inverting input terminal of the operational amplifier 144 is connected to the output terminal of the operational amplifier 144, and the operational amplifier 144 functions as a voltage follower. Therefore, the output terminal of the operational amplifier 144 has a voltage that is half the full-scale voltage VFSAD, and this voltage is output from the reference voltage generating circuit 40 as the common voltage VCMAD.

[0069] The fault diagnosis circuit 80 includes comparators 181 and 182 , a logical OR circuit 183 , and a D-type flip-flop 184 .

[0070] A common voltage VCMAD is supplied to an inverting input terminal of the comparator 181, and a predetermined threshold voltage VL is supplied to a non-inverting input terminal of the comparator 181. The output terminal of the comparator 181 is at a low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL, and is at a high level when the common voltage VCMAD is lower than the threshold voltage VL.

[0071] A common voltage VCMAD is supplied to a non-inverting input terminal of the comparator 182, and a predetermined threshold voltage VH higher than the threshold voltage VL is supplied to an inverting input terminal of the comparator 182. The output terminal of the comparator 182 is at a low level when the common voltage VCMAD is equal to or lower than the threshold voltage VH, and is at a high level when the common voltage VCMAD is higher than the threshold voltage VH.

[0072] The output signal of comparator 181 and the output signal of comparator 182 are input to OR circuit 183, which outputs a logical OR signal of these signals. That is, the output signal of OR circuit 183 becomes low level when the output signals of comparators 181 and 182 are both low level, and becomes high level when at least one of the output signals of comparators 181 and 182 is high level.

[0073] Therefore, the output signal of the OR circuit 183 becomes low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and becomes high level when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH. The comparators 181, 182 and the OR circuit 183 configure an abnormality determination circuit 81, and the output signal of the OR circuit 183 becomes an abnormality determination signal FLG1. That is, the abnormality determination circuit 81 determines that the common voltage VCMAD is normal when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and determines that the common voltage VCMAD is abnormal when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, and outputs an abnormality determination signal FLG1 indicating the determination result.

[0074] The threshold voltages VL and VH may be fixed values ​​or may be variably set in the storage unit 100.

[0075] The abnormality determination signal FLG1 is input to a data input terminal D of the D-type flip-flop 184, and the clock signal WCK is input to a clock input terminal of the D-type flip-flop 184. The D-type flip-flop 184 takes in the abnormality determination signal FLG1 at the timing of the rising edge of the clock signal WCK and outputs a fault diagnosis signal FLG2.

[0076] 4, the common voltage VCMAD is a voltage obtained by dividing the full-scale voltage VFSAD by 1 / 2 by resistors 142 and 143, so if the full-scale voltage VFSAD is constantly abnormal, the common voltage VCMAD is also constantly abnormal, and the abnormality determination signal FLG1 is always at a high level. Therefore, even if the operational amplifier 144 has failed and the common voltage VCMAD is constantly abnormal, or even if the band gap reference circuit 141 has failed and the full-scale voltage VFSAD is constantly abnormal, the fault diagnosis signal FLG2 becomes a high level, and the fault diagnosis circuit 80 can diagnose that the reference voltage generation circuit 40 has failed.

[0077] Fig. 5 is a diagram showing an example of the waveforms of various signals including the common voltage VCMAD, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generating circuit 40 is not malfunctioning. Fig. 6 is a diagram showing an example of the waveforms of various signals including the common voltage VCMAD, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generating circuit 40 is malfunctioning.

[0078] In the example of Figures 5 and 6, the status signal CONV is at low level during a sampling period in which the analog / digital conversion circuit 60 samples the voltage of the output signal MXO of the selection circuit 50, and the status signal CONV is at high level during a conversion period in which the analog / digital conversion circuit 60 holds the sampled voltage and converts it into a digital signal ADO. As shown in Figures 5 and 6, the analog / digital conversion circuit 60 alternately repeats a sampling period and a conversion period in synchronization with the repetition of the first to fifth channels. Note that the status signal CONV is omitted from the illustration of Figures 1 and 2 described above.

[0079] In this embodiment, in order to reduce the area of ​​the reference voltage generating circuit 40, it is assumed that the supply capability of the full-scale voltage VFSAD to the analog / digital conversion circuit 60 is not necessarily sufficient. Therefore, when the analog / digital conversion circuit 60 switches between the sampling period and the conversion period, the full-scale voltage VFSAD fluctuates greatly, and accordingly, the common voltage VCMAD also fluctuates greatly, as shown in Figures 5 and 6. The timing of switching from the conversion period to the sampling period is the timing when the analog / digital conversion circuit 60 starts sampling the output signal MXO of the selection circuit 50. The timing of switching from the sampling period to the conversion period is the timing when the analog / digital conversion circuit 60 ends sampling the output signal MXO of the selection circuit 50.

[0080] In the example of FIG. 5, the common voltage VCMAD becomes lower than the threshold voltage VL at the timing when the sampling period and the conversion period switch periodically, and as a result, the phenomenon that the abnormality determination signal FLG1 becomes high level only for one cycle of the clock signal MCK is repeated periodically. Even if the common voltage VCMAD becomes lower than the threshold voltage VL temporarily at the timing when the sampling period and the conversion period switch, the operation of the analog-to-digital conversion circuit 60 is not affected, so the reference voltage generation circuit 40 does not malfunction. However, if the common voltage VCMAD temporarily fluctuates and the abnormality determination signal FLG1 temporarily becomes high level at the timing when the fault diagnosis signal output circuit 82 takes in the abnormality determination signal FLG1, it will output a high level fault diagnosis signal FLG2. If an external device reads out the high level fault diagnosis signal FLG2 via the interface circuit 110, the external device will erroneously determine that the reference voltage generation circuit 40 is malfunctioning.

[0081] In the example of FIG. 6, the reference voltage generating circuit 40 fails, and the common voltage VCMAD is higher than the threshold voltage VH. In reality, as in the example of FIG. 5, the common voltage VCMAD fluctuates greatly at the switching between the sampling period and the conversion period of the analog-to-digital conversion circuit 60, so that the common voltage VCMAD temporarily falls within a range between the threshold voltage VL and the threshold voltage VH. Therefore, in the example of FIG. 6, the abnormality determination signal FLG1 temporarily becomes low level at the timing at which the sampling period and the conversion period switch, contrary to the example of FIG. 5. Therefore, if the fault diagnosis signal output circuit 82 takes in the abnormality determination signal FLG1 at the timing at which the abnormality determination signal FLG1 temporarily becomes low level, the fault diagnosis signal FLG2 of low level will be output. If an external device reads out the low level fault diagnosis signal FLG2 via the interface circuit 110, the external device will erroneously determine that the reference voltage generating circuit 40 is not at fault.

[0082] In contrast, in this embodiment, the timing at which the fault diagnosis signal output circuit 82 receives the abnormality determination signal FLG1, i.e., the timing of the rising edge of the clock signal WCK, is set not to overlap with the timing at which the common voltage VCMAD temporarily fluctuates. In this embodiment, the control circuit 90 has a counter (not shown) and generates a control signal for controlling the analog / digital conversion circuit 60 based on the count value CNT of the counter. 5 and 6, the count value CNT is initialized to 0 in each channel, and then increases by 1 from 0 to N, and the operation of the analog / digital conversion circuit 60 is controlled based on the count value CNT. The timing at which the sampling period and conversion period of the analog / digital conversion circuit 60 switch, that is, the timing at which the count value CNT changes from k-1 to k, which does not overlap with the timing at which the common voltage VCMAD temporarily fluctuates, is set to the rising edge timing of the clock signal WCK.

[0083] 5, fault diagnosis signal output circuit 82 does not receive abnormality determination signal FLG1 at the timing when abnormality determination signal FLG1 temporarily goes high level, and fault diagnosis signal FLG2 continues to maintain low level. Therefore, even if an external device reads out fault diagnosis signal FLG2 via interface circuit 110 at any timing, it can correctly determine that reference voltage generation circuit 40 is not at fault.

[0084] 6, fault diagnosis signal output circuit 82 does not receive abnormality determination signal FLG1 at the timing when abnormality determination signal FLG1 temporarily goes low, and fault diagnosis signal FLG2 continues to maintain high level. Therefore, even if an external device reads out fault diagnosis signal FLG2 via interface circuit 110 at any timing, it can correctly determine that reference voltage generation circuit 40 has a fault.

[0085] 1-1-5. Procedure for fault diagnosis method The fault diagnosis method for the physical quantity sensor 1 of the first embodiment includes a fault diagnosis process of monitoring a common voltage VCMAD, which is one of the reference voltages, to perform fault diagnosis of the reference voltage generation circuit 40 and output a fault diagnosis signal FLG2 indicating the result of the fault diagnosis, and in the fault diagnosis process, the fault diagnosis is performed at a predetermined timing different from the timing at which the common voltage VCMAD temporarily fluctuates in accordance with the operation of the analog-to-digital conversion circuit 60.

[0086] Fig. 7 is a flowchart showing an example of the procedure of the failure diagnosis method for the physical quantity sensor 1 according to the first embodiment. Note that in the flowchart of Fig. 7, the processing of each step may be appropriately interchanged.

[0087] 7, when the common voltage VCMAD is within a predetermined voltage range (Y in step S1), that is, when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, the abnormality determination circuit 81 of the physical quantity sensor 1 sets the abnormality determination signal FLG1 to "no abnormality" (step S2). Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a low level.

[0088] On the other hand, if the common voltage VCMAD is not within the predetermined voltage range (N in step S1), that is, if the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH, the abnormality determination circuit 81 of the physical quantity sensor 1 sets the abnormality determination signal FLG1 to indicate that there is an abnormality (step S3). Specifically, the abnormality determination circuit 81 sets the abnormality determination signal FLG1 to a high level.

[0089] The abnormality determination circuit 81 repeats the processes of steps S1, S2, and S3 until the failure diagnosis timing, which is a predetermined timing, arrives (N in step S4). Then, when the failure diagnosis timing arrives (Y in step S4), the failure diagnosis signal output circuit 82 of the physical quantity sensor 1 receives the abnormality determination signal FLG1 and outputs the failure diagnosis signal FLG2 (step S5), and the abnormality determination circuit 81 repeats the processes of steps S1, S2, and S3 again.

[0090] 7 correspond to the fault diagnosis process. Steps S1, S2, and S3 are the fault diagnosis process in which the fault diagnosis circuit 81 determines whether or not the common voltage VCMAD, which is one of the reference voltages, is abnormal and outputs the fault diagnosis signal FLG1 indicating the determination result. Steps S4 and S5 are the fault diagnosis signal output process in which the fault diagnosis signal output circuit 82 receives the fault diagnosis signal FLG1 at a predetermined timing and outputs the fault diagnosis signal FLG2.

[0091] 1-1-6.Effects In the first embodiment described above, the physical quantity detection circuit 2 includes a fault diagnosis circuit 80 that monitors the common voltage VCMAD generated by the reference voltage generation circuit 40 and supplied to the analog / digital conversion circuit 60, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. The fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing different from the timing at which the common voltage VCMAD temporarily varies with the operation of the analog / digital conversion circuit 60. According to this embodiment, the fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing different from the timing at which the common voltage VCMAD temporarily varies with the operation of the analog / digital conversion circuit 60, so that it is possible to reduce the risk of erroneously determining that the reference voltage generation circuit 40 has failed even if the common voltage VCMAD temporarily varies. For example, even if the supply capability of the common voltage VCMAD by the reference voltage generation circuit 40 is relatively low, the risk of the fault diagnosis circuit 80 making a false determination is reduced, so that it is possible to reduce the size of the reference voltage generation circuit 40, which is advantageous for reducing costs.

[0092] In particular, in this embodiment, the fault diagnosis circuit 80 performs fault diagnosis at a predetermined timing that is different from the timing at which the analog / digital conversion circuit 60 starts sampling and the timing at which the sampling ends, when the common voltage VCMAD temporarily fluctuates, thereby reducing the risk of erroneously determining that the reference voltage generation circuit 40 has failed even if the common voltage VCMAD temporarily fluctuates.

[0093] In this embodiment, the fault diagnosis circuit 80 includes an abnormality determination circuit 81 that determines whether the common voltage VCMAD is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result, and a fault diagnosis signal output circuit 82 that receives the abnormality determination signal FLG1 and outputs a fault diagnosis signal FLG2 at a predetermined timing different from the timing at which the common voltage VCMAD temporarily varies in association with the operation of the analog / digital conversion circuit 60. Therefore, according to this embodiment, when the common voltage VCMAD temporarily varies, even if the abnormality determination circuit 81 temporarily outputs the abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal, it is possible to reduce the risk that the fault diagnosis signal output circuit 82 will receive the abnormality determination signal FLG1 indicating that the common voltage VCMAD is abnormal and erroneously output the fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 has a malfunction.

[0094] As described above, according to this embodiment, the risk of erroneously determining that the reference voltage generation circuit 40 is faulty can be reduced, thereby improving the reliability of fault diagnosis of the physical quantity detection circuit 2 and the physical quantity sensor 1.

[0095] 1-2. Second embodiment In the following, for the physical quantity sensor of the second embodiment, components similar to those of the first embodiment are given the same symbols, and explanations of contents that overlap with the first embodiment are omitted or simplified, and mainly the contents that differ from the first embodiment are described.

[0096] 1-2-1. Physical quantity sensor configuration 8 is a functional block diagram of a physical quantity sensor according to the second embodiment. Similar to the first embodiment, the physical quantity sensor 1 according to the second embodiment includes a physical quantity detection circuit 2, an angular velocity detection element 3, an acceleration detection element 4X, and an acceleration detection element 4Y.

[0097] The functions of the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y are similar to those in the first embodiment, and therefore a description thereof will be omitted.

[0098] As in the first embodiment, the physical quantity detection circuit 2 includes an angular velocity signal processing circuit 10, an acceleration signal processing circuit 20, a temperature sensor 30, a reference voltage generation circuit 40, a selection circuit 50, an analog / digital conversion circuit 60, a digital signal processing circuit 70, a control circuit 90, a storage unit 100, an interface circuit 110, an oscillation circuit 120, and a fault diagnosis circuit 130, and may be realized, for example, as a one-chip integrated circuit. Note that the physical quantity detection circuit 2 may have a configuration in which some of these elements are omitted or modified, or other elements are added.

[0099] The functions of the angular velocity signal processing circuit 10, the acceleration signal processing circuit 20, the temperature sensor 30, the reference voltage generation circuit 40, the selection circuit 50, the analog / digital conversion circuit 60, the digital signal processing circuit 70, the control circuit 90, the memory unit 100, the interface circuit 110 and the oscillator circuit 120 are similar to those in the first embodiment, and therefore their description will be omitted.

[0100] The fault diagnosis circuit 130 monitors the common voltage VCMACC, which is one of the reference voltages, to perform fault diagnosis of the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. In particular, in this embodiment, the fault diagnosis circuit 130 performs fault diagnosis of the reference voltage generation circuit 40 at a predetermined timing different from the timing at which the common voltage VCMACC temporarily varies in accordance with the operation of the acceleration signal processing circuit 20, which is one of the physical quantity signal processing circuits.

[0101] For example, the timing at which the common voltage VCMACC temporarily varies may be at least one of the rising edge and the falling edge of the drive signal DRVACC, and the fault diagnosis circuit 130 may perform fault diagnosis at a predetermined timing different from that timing. Also, for example, the timing at which the common voltage VCMACC temporarily varies may be at least one of the rising edge and the falling edge of each of the control signals CTL1-CTLn generated by the control circuit 90, and the fault diagnosis circuit 130 may perform fault diagnosis at a predetermined timing different from that timing.

[0102] In this embodiment, fault diagnosis circuit 130 includes an abnormality determination circuit 131 and a fault diagnosis signal output circuit 132 .

[0103] The abnormality determination circuit 131 determines whether the common voltage VCMACC is abnormal, and outputs an abnormality determination signal FLG1 indicating the determination result. For example, the abnormality determination signal FLG1 may be a flag signal that is at a high level when the common voltage VCMACC is abnormal and is at a low level when the common voltage VCMACC is normal.

[0104] The fault diagnosis signal output circuit 132 receives the abnormality determination signal FLG1 at a predetermined timing and outputs the fault diagnosis signal FLG2. For example, the fault diagnosis signal FLG2 may be a flag signal that is at a high level when the reference voltage generation circuit 40 is faulty and is at a low level when the reference voltage generation circuit 40 is not faulty. In this embodiment, the fault diagnosis signal output circuit 132 receives the abnormality determination signal FLG1 at the timing of the rising edge of the clock signal WCK supplied from the control circuit 90 and outputs the fault diagnosis signal FLG2. As will be described later, the timing of the rising edge of the clock signal WCK is a predetermined timing different from the timing at which the common voltage VCMACC temporarily varies in accordance with the operation of the acceleration signal processing circuit 20.

[0105] 1-2-2. Configuration of fault diagnosis circuit 9 is a diagram showing a configuration example of a part of the reference voltage generating circuit 40 and the fault diagnosis circuit 130. In the example of FIG.

[0106] The bandgap reference circuit 145 is a circuit that uses the bandgap voltage of a semiconductor element to generate a constant power supply voltage VACC that is stable against fluctuations in temperature and power supply voltage VDD. The configuration of the bandgap reference circuit is well known, so illustration and description thereof will be omitted.

[0107] The resistors 146 and 147 have the same resistance R, and the power supply voltage VACC is divided into halves by the resistors 146 and 147 , and the divided voltage is supplied to the non-inverting input terminal of an operational amplifier 148 .

[0108] The inverting input terminal of the operational amplifier 148 is connected to the output terminal of the operational amplifier 148, and the operational amplifier 148 functions as a voltage follower. Therefore, the output terminal of the operational amplifier 148 has a voltage that is half the power supply voltage VACC, and this voltage is output from the reference voltage generation circuit 40 as the common voltage VMACC.

[0109] The fault diagnosis circuit 130 includes comparators 231 and 232 , a logical OR circuit 233 , and a D-type flip-flop 234 .

[0110] A common voltage VCMACC is supplied to an inverting input terminal of the comparator 231, and a predetermined threshold voltage VL is supplied to a non-inverting input terminal of the comparator 231. The output terminal of the comparator 231 is at a low level when the common voltage VCMACC is equal to or higher than the threshold voltage VL, and is at a high level when the common voltage VCMACC is lower than the threshold voltage VL.

[0111] A common voltage VCMACC is supplied to a non-inverting input terminal of the comparator 232, and a predetermined threshold voltage VH higher than the threshold voltage VL is supplied to an inverting input terminal of the comparator 232. The output terminal of the comparator 232 is at a low level when the common voltage VCMACC is equal to or lower than the threshold voltage VH, and is at a high level when the common voltage VCMACC is higher than the threshold voltage VH.

[0112] The output signal of the comparator 231 and the output signal of the comparator 232 are input to the OR circuit 233, and the OR circuit 233 outputs a logical OR signal of these signals. That is, the output signal of the OR circuit 233 becomes low level when the output signal of the comparator 231 and the output signal of the comparator 232 are both low level, and becomes high level when at least one of the output signal of the comparator 231 and the output signal of the comparator 232 is high level.

[0113] Therefore, the output signal of the OR circuit 233 becomes low level when the common voltage VCMAD is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and becomes high level when the common voltage VCMAD is lower than the threshold voltage VL or higher than the threshold voltage VH. The comparators 231, 232 and the OR circuit 233 constitute the abnormality determination circuit 131, and the output signal of the OR circuit 233 becomes the abnormality determination signal FLG1. That is, the abnormality determination circuit 131 determines that the common voltage VCMACC is normal when the common voltage VCMACC is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, and determines that the common voltage VCMACC is abnormal when the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, and outputs the abnormality determination signal FLG1 indicating the determination result.

[0114] The threshold voltages VL and VH may be fixed values ​​or may be variably set in the storage unit 100.

[0115] The D-type flip-flop 234 receives the abnormality determination signal FLG1 at a data input terminal D and receives the clock signal WCK at a clock input terminal. The D-type flip-flop 234 takes in the abnormality determination signal FLG1 at the timing of the rising edge of the clock signal WCK and outputs a fault diagnosis signal FLG2.

[0116] 9, the common voltage VMACC is a voltage obtained by dividing the power supply voltage VACC by half by resistors 146 and 147, so if the power supply voltage VACC is constantly abnormal, the common voltage VMACC is also constantly abnormal, and the abnormality determination signal FLG1 is always at a high level. Therefore, even if the operational amplifier 148 has a failure and the common voltage VMACC is constantly abnormal, or even if the band gap reference circuit 145 has a failure and the power supply voltage VACC is constantly abnormal, the fault diagnosis signal FLG2 becomes a high level, and the fault diagnosis circuit 130 can diagnose that the reference voltage generation circuit 40 has a failure.

[0117] Fig. 10 is a diagram showing an example of the waveforms of various signals including the common voltage VCMACC, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generating circuit 40 is not faulty. Also, Fig. 11 is a diagram showing an example of the waveforms of various signals including the common voltage VCMACC, the abnormality determination signal FLG1, and the fault diagnosis signal FLG2 when the reference voltage generating circuit 40 is faulty.

[0118] In this embodiment, in order to reduce the area of ​​the reference voltage generating circuit 40, it is assumed that the supply capacity of the power supply voltage VACC to the acceleration signal processing circuit 20 is not necessarily sufficient. Since the high level of the drive signal DRVACC is the power supply voltage VACC, the power supply voltage VACC fluctuates greatly at the timing of the rising edge and falling edge of the drive signal DRVACC, and accordingly, the common voltage VMACC also fluctuates greatly as shown in Figures 10 and 11. Similarly, since the high level of the control signals CTL1 to CTLn is the power supply voltage VACC, the power supply voltage VACC fluctuates greatly at the timing of each rising edge and falling edge of the control signals CTL1 to CTLn, and accordingly, the common voltage VMACC also fluctuates greatly as shown in Figures 10 and 11.

[0119] In the example of FIG. 10, the common voltage VCMACC becomes lower than the threshold voltage VL at the timing of the rising edge and the falling edge of the drive signal DRVACC and the timing of the rising edge and the falling edge of each of the control signals CTL1 to CTLn, and as a result, the phenomenon that the abnormality determination signal FLG1 becomes high level only for one cycle of the clock signal MCK is repeated periodically. Even if the common voltage VCMACC becomes lower than the threshold voltage VL temporarily at these edge timings, the operation of the acceleration signal processing circuit 20 is not affected, so the reference voltage generating circuit 40 does not malfunction. However, if the common voltage VCMACC temporarily fluctuates and the fault diagnosis signal output circuit 132 takes in the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes high level, the fault diagnosis signal FLG2 of high level will be output. If an external device reads out the fault diagnosis signal FLG2 of high level via the interface circuit 110, the external device will erroneously determine that the reference voltage generating circuit 40 is malfunctioning.

[0120] In the example of FIG. 11, the reference voltage generating circuit 40 fails, and the common voltage VCMACC is higher than the threshold voltage VH. In reality, as in the example of FIG. 10, the common voltage VCMACC fluctuates greatly at the timing of the rising edge and falling edge of the drive signal DRVACC and the timing of the rising edge and falling edge of each of the control signals CTL1 to CTLn, so that the common voltage VCMACC temporarily falls within a range of the threshold voltage VL or more and the threshold voltage VH or less. Therefore, in the example of FIG. 11, the abnormality determination signal FLG1 temporarily becomes low level at the timing of these edges, contrary to the example of FIG. 10. Therefore, if the fault diagnosis signal output circuit 132 takes in the abnormality determination signal FLG1 at the timing when the abnormality determination signal FLG1 temporarily becomes low level, it will output a low-level fault diagnosis signal FLG2. If an external device reads out the low-level fault diagnosis signal FLG2 via the interface circuit 110, the external device will erroneously determine that the reference voltage generating circuit 40 is not at fault.

[0121] In contrast, in this embodiment, the timing at which the fault diagnosis signal output circuit 132 takes in the abnormality determination signal FLG1, i.e., the timing of the rising edge of the clock signal WCK, is set not to overlap with the timing at which the common voltage VCMACC temporarily fluctuates. In this embodiment, the control circuit 90 has a counter (not shown) and generates control signals CTL1 to CTLn for controlling the acceleration signal processing circuit 20 based on a count value CNT of the counter. The acceleration signal processing circuit 20 generates a drive signal DRVACC based on at least a part of the control signals CTL1 to CTLn. In the example of Figs. 10 and 11, the count value CNT is initialized to 0 during each period when the drive signal DRVACC is at a low level and during each period when the drive signal DRVACC is at a high level, and then increases by 1 from 0 to N, and the operation of the acceleration signal processing circuit 20 is controlled based on the count value CNT. The timing of the rising edge or falling edge of the drive signal DRVACC and the timing of the rising edge or falling edge of each of the control signals CTL1 to CTLn, i.e., the timing at which the count value CNT changes from 2 to 3, which does not overlap with the timing at which the common voltage VCMACC temporarily fluctuates, is set to the timing of the rising edge of the clock signal WCK.

[0122] 10, fault diagnosis signal output circuit 132 does not receive abnormality determination signal FLG1 at the timing when abnormality determination signal FLG1 temporarily goes high level, and fault diagnosis signal FLG2 continues to maintain low level. Therefore, even if an external device reads out fault diagnosis signal FLG2 via interface circuit 110 at any timing, it can correctly determine that reference voltage generation circuit 40 is not at fault.

[0123] 11, fault diagnosis signal output circuit 132 does not receive abnormality determination signal FLG1 at the timing when abnormality determination signal FLG1 temporarily goes to low level, and fault diagnosis signal FLG2 continues to maintain high level. Therefore, even if an external device reads out fault diagnosis signal FLG2 via interface circuit 110 at any timing, it can correctly determine that reference voltage generation circuit 40 has a fault.

[0124] 1-2-3. Procedure for fault diagnosis The fault diagnosis method for the physical quantity sensor 1 of the second embodiment includes a fault diagnosis process of monitoring a common voltage VCMACC, which is one of the reference voltages, to perform fault diagnosis on the reference voltage generation circuit 40 and output a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. In the fault diagnosis process, the fault diagnosis is performed at a predetermined timing different from the timing at which the common voltage VCMACC temporarily fluctuates in accordance with the operation of the acceleration signal processing circuit 20.

[0125] Fig. 12 is a flowchart showing an example of the procedure of the failure diagnosis method for the physical quantity sensor 1 according to the second embodiment. Note that in the flowchart of Fig. 12, the processing of each step may be appropriately interchanged.

[0126] 12, when the common voltage VCMACC is within a predetermined voltage range (Y in step S11), that is, when the common voltage VCMACC is equal to or higher than the threshold voltage VL and equal to or lower than the threshold voltage VH, the abnormality determination circuit 131 of the physical quantity sensor 1 sets the abnormality determination signal FLG1 to "no abnormality" (step S12). Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to a low level.

[0127] On the other hand, if the common voltage VCMACC is not within the predetermined voltage range (N in step S11), that is, if the common voltage VCMACC is lower than the threshold voltage VL or higher than the threshold voltage VH, the abnormality determination circuit 131 of the physical quantity sensor 1 sets the abnormality determination signal FLG1 to indicate that there is an abnormality (step S13). Specifically, the abnormality determination circuit 131 sets the abnormality determination signal FLG1 to a high level.

[0128] The abnormality determination circuit 131 repeats the processes of steps S11, S12, and S13 until a predetermined timing, that is, a fault diagnosis timing, arrives (N in step S14). Then, when the fault diagnosis timing arrives (Y in step S14), the fault diagnosis signal output circuit 132 of the physical quantity sensor 1 receives the abnormality determination signal FLG1 and outputs the fault diagnosis signal FLG2 (step S15), and the abnormality determination circuit 131 repeats the processes of steps S11, S12, and S13 again.

[0129] 12 corresponds to the fault diagnosis process. Steps S11, S12, and S13 are the fault diagnosis process in which the fault diagnosis circuit 131 determines whether or not the common voltage VCMACC, which is one of the reference voltages, is abnormal and outputs the fault diagnosis signal FLG1 indicating the determination result. Steps S14 and S15 are the fault diagnosis signal output process in which the fault diagnosis signal output circuit 132 receives the fault diagnosis signal FLG1 at a predetermined timing and outputs the fault diagnosis signal FLG2.

[0130] In the second embodiment described above, the physical quantity detection circuit 2 includes a fault diagnosis circuit 130 that monitors the common voltage VCMACC generated by the reference voltage generation circuit 40 and supplied to the acceleration signal processing circuit 20, performs fault diagnosis on the reference voltage generation circuit 40, and outputs a fault diagnosis signal FLG2 indicating the result of the fault diagnosis. The fault diagnosis circuit 130 performs fault diagnosis at a predetermined timing different from the timing at which the common voltage VCMACC temporarily varies with the operation of the acceleration signal processing circuit 20. According to this embodiment, the fault diagnosis circuit 130 performs fault diagnosis at a predetermined timing different from the timing at which the common voltage VCMACC temporarily varies with the operation of the acceleration signal processing circuit 20, so that it is possible to reduce the risk of erroneously determining that the reference voltage generation circuit 40 has failed even if the common voltage VCMACC temporarily varies. For example, even if the supply capacity of the common voltage VCMACC by the reference voltage generation circuit 40 is relatively low, the risk of the fault diagnosis circuit 130 making an erroneous determination is reduced, so that it is possible to reduce the size of the reference voltage generation circuit 40, which is advantageous for reducing costs.

[0131] In particular, in this embodiment, the fault diagnosis circuit 130 performs fault diagnosis at a predetermined timing different from the rising and falling edges of the drive signal DRVACC that drives the acceleration detection elements 4X, 4Y and the rising and falling edges of each of the control signals CTL1 to CTLn that control the acceleration signal processing circuit 20, which cause the common voltage VCMACC to temporarily fluctuate, thereby reducing the risk of erroneously determining that the reference voltage generation circuit 40 has failed even if the common voltage VCMACC temporarily fluctuates.

[0132] In this embodiment, the fault diagnosis circuit 130 includes an abnormality determination circuit 131 that determines whether the common voltage VCMACC is abnormal and outputs an abnormality determination signal FLG1 indicating the determination result, and a fault diagnosis signal output circuit 132 that receives the abnormality determination signal FLG1 and outputs a fault diagnosis signal FLG2 at a predetermined timing different from the timing at which the common voltage VCMAD temporarily varies in association with the operation of the analog-to-digital conversion circuit 60. Therefore, according to this embodiment, when the common voltage VCMACC temporarily varies, even if the abnormality determination circuit 131 temporarily outputs the abnormality determination signal FLG1 indicating that the common voltage VCMACC is abnormal, it is possible to reduce the risk that the fault diagnosis signal output circuit 132 will receive the abnormality determination signal FLG1 indicating that the common voltage VCMACC is abnormal and erroneously output the fault diagnosis signal FLG2 indicating that the reference voltage generation circuit 40 has a malfunction.

[0133] As described above, according to this embodiment, the risk of erroneously determining that the reference voltage generation circuit 40 is faulty can be reduced, thereby improving the reliability of fault diagnosis of the physical quantity detection circuit 2 and the physical quantity sensor 1.

[0134] 1-3. Variations For example, in the above first embodiment, the fault diagnosis circuit 80 monitors the common voltage VCMAD, and in the above second embodiment, the fault diagnosis circuit 130 monitors the common voltage VCMACC, but the fault diagnosis circuit may monitor both the common voltage VCMAD and the common voltage VCMACC. In other words, the physical quantity sensor 1 may have a configuration that combines the first and second embodiments.

[0135] In the first embodiment, the fault diagnosis circuit 80 monitors the common voltage VCMAD, but may monitor the full-scale voltage VFSAD, or may monitor any voltage that varies with the variation of the full-scale voltage VFSAD. In the second embodiment, the fault diagnosis circuit 130 monitors the common voltage VCMACC, but may monitor the power supply voltage VACC, or may monitor any voltage that varies with the variation of the power supply voltage VACC. Alternatively, the fault diagnosis circuit may monitor any voltage that varies with the variation of the power supply voltage VGR, such as the common voltage VCMGR, or may monitor the power supply voltage VGR.

[0136] In each of the above embodiments, the physical quantity sensor 1 detects both the angular velocity and the acceleration as the physical quantity, but it may detect either the angular velocity or the acceleration. Also, the physical quantity sensor 1 may detect a physical quantity other than the angular velocity and the acceleration as the physical quantity.

[0137] Furthermore, in each of the above embodiments, the analog / digital conversion circuit 60 receives a differential signal and converts the differential signal into a digital signal ADO, but it may also receive a single-ended signal and convert the single-ended signal into a digital signal ADO.

[0138] In each of the above embodiments, the physical quantity sensor 1 includes the angular velocity detection element 3, the acceleration detection element 4X, and the acceleration detection element 4Y, but the sensor may include only some of these physical quantity detection elements. The physical quantity sensor 1 may also include a physical quantity detection element that detects a physical quantity other than the angular velocity or acceleration, such as an angular acceleration, a velocity, or a force.

[0139] In the above embodiments, the vibrating piece of the angular velocity detection element 3 is a double T-shaped quartz crystal vibrating piece, but the vibrating piece of the physical quantity detection element that detects various physical quantities may be, for example, a tuning fork type or a comb type, or may be a tuning piece type having a triangular prism, a square prism, a cylindrical shape, or the like. In addition, instead of quartz (SiO2), the material of the vibrating piece of the physical quantity detection element may be, for example, a piezoelectric material such as a piezoelectric single crystal such as lithium tantalate (LiTaO3) or lithium niobate (LiNbO3) or a piezoelectric ceramic such as lead zirconate titanate (PZT), or a silicon semiconductor. In addition, the vibrating piece of the physical quantity detection element may have a structure in which a piezoelectric thin film such as zinc oxide (ZnO) or aluminum nitride (AlN) is arranged between driving electrodes on a part of the surface of a silicon semiconductor.

[0140] In addition, in each of the above embodiments, the piezoelectric angular velocity detection element 3 and the capacitance type acceleration detection elements 4X, 4Y are exemplified, but the physical quantity detection elements that detect various physical quantities are not limited to piezoelectric or capacitance type elements, and may be electrodynamic, eddy current, optical, strain gauge, etc. Furthermore, the detection method of the physical quantity detection elements is not limited to vibration type, and may be, for example, optical, rotational, or fluid type.

[0141] 2.Electronic equipment Fig. 13 is a functional block diagram showing an example of the configuration of the electronic device of this embodiment. As shown in Fig. 13, the electronic device 300 of this embodiment includes a physical quantity sensor 310, a processing circuit 320, an operation unit 330, a ROM (Read Only Memory) 340, a RAM (Random Access Memory) 350, a communication unit 360, and a display unit 370. Note that the electronic device of this embodiment may be configured by omitting or changing some of the components of Fig. 13, or by adding other components.

[0142] The physical quantity sensor 310 detects a physical quantity and outputs the detection result to the processing circuit 320. As the physical quantity sensor 310, for example, the physical quantity sensor 1 of the above-described embodiment can be applied.

[0143] The processing circuit 320 performs processing based on the output signal of the physical quantity sensor 310. Specifically, the processing circuit 320 communicates with the physical quantity sensor 310 in accordance with a program stored in the ROM 340 or the like, and performs various calculation processing and control processing using the output signal of the physical quantity sensor 310. In addition, the processing circuit 320 performs various processing in response to an operation signal from the operation unit 330, processing to control the communication unit 360 for performing data communication with an external device, processing to transmit a display signal for displaying various information on the display unit 370, and the like.

[0144] The operation unit 330 is an input device including operation keys, button switches, and the like, and outputs to the processing circuit 320 an operation signal in response to an operation by a user.

[0145] The ROM 340 stores programs, data, and the like for the processing circuit 320 to perform various calculation processes and control processes.

[0146] The RAM 350 is used as a working area for the processing circuit 320, and temporarily stores programs and data read from the ROM 340, data input from the operation unit 330, and the results of calculations executed by the processing circuit 320 in accordance with various programs.

[0147] The communication unit 360 performs various controls to establish data communication between the processing circuit 320 and an external device.

[0148] The display unit 370 is a display device configured with an LCD (Liquid Crystal Display) or the like, and displays various information based on a display signal input from the processing circuit 320. The display unit 370 may be provided with a touch panel that functions as the operation unit 330.

[0149] By applying, for example, the physical quantity sensor 1 of the above-described embodiment as the physical quantity sensor 310, for example, a highly reliable electronic device can be realized.

[0150] Various types of electronic devices are considered as such electronic device 300, and examples of such electronic devices include personal computers such as mobile, laptop, and tablet computers, mobile terminals such as smartphones and mobile phones, inkjet discharge devices such as digital cameras and inkjet printers, storage area network devices such as routers and switches, local area network devices, equipment for mobile terminal base stations, televisions, video cameras, video recorders, car navigation devices, real time clock devices, pagers, electronic notebooks, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, security television monitors, electronic binoculars, POS terminals, medical equipment such as electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasonic diagnostic devices, and electronic endoscopes, fish finders, various measuring devices, instruments for vehicles, aircraft, ships, and the like, flight simulators, head mounted displays, motion tracing, motion tracking, motion controllers, and pedestrian dead reckoning (PDR) devices.

[0151] Fig. 14 is a perspective view showing a digital camera 1300 as an example of the electronic device 300 of this embodiment. Fig. 14 also shows a simplified view of connections to external devices. Here, while a normal camera exposes a silver halide photographic film to a light image of a subject, the digital camera 1300 photoelectrically converts the light image of a subject using an imaging element such as a CCD (Charge Coupled Device) to generate an imaging signal.

[0152] A display unit 1310 is provided on the rear of a case 1302 of the digital camera 1300, and is configured to display an image based on an image signal captured by a CCD, and the display unit 1310 functions as a finder that displays an object as an electronic image. A light receiving unit 1304 including an optical lens and a CCD is provided on the front side of the case 1302. When the photographer checks the object image displayed on the display unit 1310 and presses the shutter button 1306, the image signal captured by the CCD at that time is transferred to and stored in a memory 1308. In addition, in this digital camera 1300, a video signal output terminal 1312 and an input / output terminal 1314 for data communication are provided on a side surface of the case 1302. A television monitor 1430 is connected to the video signal output terminal 1312, and a personal computer 1440 is connected to the input / output terminal 1314 for data communication, as necessary. Furthermore, the configuration is such that an imaging signal stored in the memory 1308 is output to the television monitor 1430 or the personal computer 1440 by a predetermined operation. The digital camera 1300 has a physical quantity sensor 310, and performs processing such as image stabilization using an output signal from the physical quantity sensor 310.

[0153] 3. Mobile Fig. 15 is a diagram showing an example of a moving body of the present embodiment. A moving body 400 shown in Fig. 15 includes a physical quantity sensor 410, processing circuits 440, 450, and 460, a battery 470, and a navigation device 480. Note that the moving body of the present embodiment may be configured such that some of the components in Fig. 15 are omitted or other components are added.

[0154] The physical quantity sensor 410 , the processing circuits 440 , 450 , 460 , and the navigation device 480 operate on a power supply voltage supplied from a battery 470 .

[0155] The physical quantity sensor 410 detects a physical quantity and outputs the detection result to the processing circuits 440 , 450 , and 460 .

[0156] The processing circuits 440, 450, and 460 perform processing based on the output signal of the physical quantity sensor 410. For example, the processing circuits 440, 450, and 460 each use the output signal of the physical quantity sensor 410 to perform various types of control such as an attitude control system, a rollover prevention system, and a braking system.

[0157] The navigation device 480 displays the position, time, and other various information of the moving object 400 on a display based on output information from a built-in GPS receiver. Even when GPS radio waves cannot reach the device, the navigation device 480 identifies the position and orientation of the moving object 400 based on the output signal from the physical quantity sensor 410 and continues to display the necessary information.

[0158] For example, by applying the physical quantity sensor 1 of each of the above-described embodiments as the physical quantity sensor 410, for example, a highly reliable moving body can be realized.

[0159] Various types of moving bodies are conceivable as such a moving body 400, and examples thereof include automobiles such as electric cars, aircraft such as jet planes and helicopters, ships, rockets, and artificial satellites.

[0160] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be appropriately combined.

[0161] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0162] The following can be derived from the above-described embodiment and modifications.

[0163] One aspect of the physical quantity detection circuit is a detection signal generating circuit that generates a detection signal corresponding to a physical quantity based on an output signal of a physical quantity detecting element that detects the physical quantity; an analog / digital conversion circuit for converting the detection signal into a digital signal; a reference voltage generation circuit that generates a reference voltage to be supplied to the analog-to-digital conversion circuit; and a fault diagnosis circuit that monitors the reference voltage, performs fault diagnosis on the reference voltage generation circuit, and outputs a fault diagnosis signal indicative of a result of the fault diagnosis, The fault diagnosis circuit performs the fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily varies in accordance with the operation of the analog-to-digital conversion circuit.

[0164] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily fluctuates with the operation of the analog-to-digital conversion circuit, so that it is possible to reduce the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates. For example, since the risk of the fault diagnosis circuit making an erroneous determination is reduced even if the reference voltage supply capability of the reference voltage generation circuit is relatively low, it is possible to reduce the size of the reference voltage generation circuit, which is advantageous for reducing the cost of the physical quantity detection circuit.

[0165] In one aspect of the physical quantity detection circuit, The timing at which the reference voltage temporarily varies may be a timing at which the analog / digital conversion circuit starts sampling the detection signal.

[0166] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing different from the timing at which the analog-to-digital conversion circuit starts sampling the detection signal, when the reference voltage temporarily fluctuates. This reduces the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates.

[0167] In one aspect of the physical quantity detection circuit, The timing at which the reference voltage temporarily varies may be a timing at which the analog / digital conversion circuit finishes sampling the detection signal.

[0168] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing different from the timing at which the analog-to-digital conversion circuit finishes sampling the detection signal, when the reference voltage temporarily fluctuates. This reduces the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates.

[0169] One aspect of the physical quantity detection circuit is a physical quantity signal processing circuit that outputs a drive signal for driving a physical quantity detection element that detects a physical quantity, and generates a detection signal corresponding to the physical quantity based on an output signal from the physical quantity detection element; a reference voltage generating circuit that generates a reference voltage to be supplied to the physical quantity signal processing circuit; a fault diagnosis circuit that monitors the reference voltage to perform a fault diagnosis on the reference voltage generating circuit and outputs a fault diagnosis signal indicative of a result of the fault diagnosis; The fault diagnosis circuit performs the fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily varies in association with the operation of the physical quantity signal processing circuit.

[0170] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing different from the timing at which the reference voltage temporarily fluctuates with the operation of the physical quantity signal processing circuit, so that it is possible to reduce the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates. For example, since the risk of the fault diagnosis circuit making an erroneous determination is reduced even if the reference voltage supply capability of the reference voltage generation circuit is relatively low, it is possible to reduce the size of the reference voltage generation circuit, which is advantageous for reducing the cost of the physical quantity detection circuit.

[0171] In one aspect of the physical quantity detection circuit, The timing at which the reference voltage temporarily varies may be at least one of a rising edge and a falling edge of the drive signal.

[0172] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing different from at least one of the rising edge and falling edge of the drive signal, at which the reference voltage temporarily fluctuates, thereby reducing the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates.

[0173] One aspect of the physical quantity detection circuit is a control circuit for generating a control signal for controlling the physical quantity signal processing circuit; The timing at which the reference voltage temporarily changes may be at least one of a rising edge and a falling edge of the control signal.

[0174] According to this physical quantity detection circuit, the fault diagnosis circuit performs fault diagnosis at a predetermined timing different from at least one of the rising edge and falling edge of the control signal, at which the reference voltage temporarily fluctuates, thereby reducing the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates.

[0175] In one aspect of the physical quantity detection circuit, The fault diagnosis circuit includes: an abnormality determination circuit that determines whether the reference voltage is abnormal or not and outputs an abnormality determination signal indicative of the determination result; The power supply may further include a fault diagnosis signal output circuit that receives the abnormality determination signal at the predetermined timing and outputs the fault diagnosis signal.

[0176] According to this physical quantity detection circuit, if the reference voltage temporarily fluctuates, even if the abnormality judgment circuit temporarily outputs an abnormality judgment signal indicating that the reference voltage is abnormal, the risk that the fault diagnosis signal output circuit will import the abnormality judgment signal indicating that the reference voltage is abnormal and erroneously output a fault diagnosis signal indicating that the reference voltage generation circuit is faulty can be reduced.

[0177] One aspect of the physical quantity sensor is An embodiment of the physical quantity detection circuit; The physical quantity detection element.

[0178] This physical quantity sensor is equipped with a physical quantity detection circuit that can reduce the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates, thereby achieving high reliability.

[0179] One aspect of the electronic device is An embodiment of the physical quantity sensor; and a processing circuit that performs processing based on the output signal of the physical quantity sensor.

[0180] This electronic device is equipped with a physical quantity sensor equipped with a physical quantity detection circuit that can reduce the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates, thereby achieving high reliability.

[0181] One aspect of the moving body is An embodiment of the physical quantity sensor; and a processing circuit that performs processing based on the output signal of the physical quantity sensor.

[0182] This moving body is equipped with a physical quantity sensor equipped with a physical quantity detection circuit that can reduce the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates, thereby achieving high reliability.

[0183] One aspect of a method for diagnosing a fault in a physical quantity sensor includes: A fault diagnosis method for a physical quantity sensor including a physical quantity detection element that detects a physical quantity, a detection circuit that generates a detection signal corresponding to the physical quantity based on an output signal of the physical quantity detection element, an analog / digital conversion circuit that converts the detection signal into a digital signal, and a reference voltage generation circuit that generates a reference voltage to be supplied to the analog / digital conversion circuit, a fault diagnosis step of monitoring the reference voltage to perform a fault diagnosis on the reference voltage generating circuit and outputting a fault diagnosis signal indicating a result of the fault diagnosis; In the failure diagnosis step, the failure diagnosis is performed at a predetermined timing different from a timing at which the reference voltage temporarily varies in association with the operation of the analog / digital conversion circuit.

[0184] According to this method for diagnosing a fault in a physical quantity sensor, in the fault diagnosis process, fault diagnosis is performed at a predetermined timing different from the timing at which the reference voltage temporarily fluctuates due to the operation of the analog-to-digital conversion circuit, thereby reducing the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates.

[0185] One aspect of a method for diagnosing a fault in a physical quantity sensor includes: A fault diagnosis method for a physical quantity sensor including a physical quantity detection element that detects a physical quantity, a physical quantity signal processing circuit that outputs a drive signal for driving the physical quantity detection element and generates a detection signal corresponding to the physical quantity based on an output signal of the physical quantity detection element, and a reference voltage generation circuit that generates a reference voltage to be supplied to the physical quantity signal processing circuit, a fault diagnosis step of monitoring the reference voltage to perform a fault diagnosis on the reference voltage generating circuit and outputting a fault diagnosis signal indicating a result of the fault diagnosis; In the fault diagnosis step, the fault diagnosis is performed at a predetermined timing different from a timing at which the reference voltage temporarily varies in association with an operation of the physical quantity signal processing circuit.

[0186] According to this method for diagnosing a fault in a physical quantity sensor, in the fault diagnosis process, fault diagnosis is performed at a predetermined timing different from the timing at which the reference voltage temporarily fluctuates due to the operation of the physical quantity signal processing circuit, so that it is possible to reduce the risk of erroneously determining that the reference voltage generation circuit has failed even if the reference voltage temporarily fluctuates. [Explanation of symbols]

[0187] 1...physical quantity sensor, 2...physical quantity detection circuit, 3...angular velocity detection element, 4X...acceleration detection element, 4Y...acceleration detection element, 10...angular velocity signal processing circuit, 11...drive circuit, 12...detection circuit, 20...acceleration signal processing circuit, 21...drive circuit, 22X...detection circuit, 22Y...detection circuit, 30...temperature sensor, 40...reference voltage generation circuit, 50...selection circuit, 51p, 51n, 52p, 52n, 53p, 53n, 54p, 54n, 55p, 55n...low-pass filter, 56...multiplexer, 60...analog / digital conversion circuit, 61...precharge circuit, 62...programmable gain amplifier, 63...successive approximation type analog / digital converter, 64...SAR control circuit, 70...digital signal processing circuit, 80...fault diagnosis circuit, 81...abnormality determination circuit, 82...fault diagnosis signal output circuit, 90...control circuit, 100...storage unit, 110...interface circuit, 120...oscillating circuit, 130...fault diagnosis circuit, 131...abnormality determination circuit, 132...fault diagnosis signal output circuit, 141...bandgap Preference circuit, 142...resistor, 143...resistor, 144...operational amplifier, 145...band gap reference circuit, 146...resistor, 147...resistor, 148...operational amplifier, 181...comparator, 182...comparator, 183...logical OR circuit, 184...D-type flip-flop, 200...logic circuit, 231...comparator, 232...comparator, 233...logical OR circuit, 234...D-type flip-flop, 300...electronic device, 310...physical quantity sensor, 320...processing circuit, 330...operation unit, 340 ...ROM, 350...RAM, 360...communication unit, 370...display unit, 400...mobile body, 410...physical quantity sensor, 440, 450, 460...processing circuit, 470...battery, 480...navigation device, 1300...digital camera, 1302...case, 1304...light receiving unit, 1306...shutter button, 1308...memory, 1310...display unit, 1312...video signal output terminal, 1314...input / output terminal, 1430...television monitor, 1440...personal computer

Claims

1. An abnormality determination circuit that determines whether a reference voltage supplied to an analog / digital conversion circuit is abnormal or not and outputs an abnormality determination signal indicative of the determination result; a fault diagnosis signal output circuit that receives the abnormality determination signal and outputs a fault diagnosis signal at a predetermined timing different from a timing at which the reference voltage temporarily varies in accordance with an operation of the analog-to-digital conversion circuit; Including, performing a fault diagnosis on a reference voltage generating circuit that supplies the reference voltage; The timing of the fault diagnosis is different from the temporarily varying timing, The temporarily varying timing is a timing at which the analog-to-digital conversion circuit starts sampling or ends the sampling; The fault diagnosis signal output circuit includes: a fault diagnosis circuit that outputs the fault diagnosis signal at the rising edge of a clock signal supplied from a control circuit that controls the analog / digital conversion circuit;

2. In claim 1, A fault diagnosis circuit, wherein the timing of a rising edge of the clock signal is different from the timing at which the reference voltage temporarily fluctuates.

3. In claim 2, The abnormality determination circuit includes: a first comparator having an inverting input terminal to which the reference voltage is input; a second comparator having a non-inverting input terminal to which the reference voltage is input; a logical OR circuit that outputs a logical OR signal based on the output signal of the first comparator and the output signal of the second comparator that are input thereto; a fault diagnosis circuit including:

4. A fault diagnosis circuit according to any one of claims 1 to 3; An analog / digital conversion circuit; A reference voltage generating circuit; 2. An electronic circuit comprising:

5. In claim 4, An electronic circuit, including a control circuit.

6. performing a fault diagnosis on a reference voltage generating circuit that supplies a reference voltage to a physical quantity signal processing circuit that generates a detection signal based on an output signal from a physical quantity detection element; The timing of the fault diagnosis is as follows: The timing at which the reference voltage temporarily varies in accordance with the operation of the physical quantity signal processing circuit is different from that at which the reference voltage temporarily varies in accordance with the operation of the physical quantity signal processing circuit. The temporarily varying timing is The fault diagnosis circuit is characterized in that the timing is at least one of a rising edge and a falling edge of a drive signal that drives the physical quantity detection element.

7. performing a fault diagnosis on a reference voltage generating circuit that supplies a reference voltage to a physical quantity signal processing circuit that generates a detection signal based on an output signal from a physical quantity detection element; The timing of the fault diagnosis is as follows: The timing at which the reference voltage temporarily varies in accordance with the operation of the physical quantity signal processing circuit is different from that at which the reference voltage temporarily varies in accordance with the operation of the physical quantity signal processing circuit. The temporarily varying timing is A fault diagnosis circuit, wherein the timing is at least one of a rising edge and a falling edge of a control signal of a control circuit that controls the physical quantity signal processing circuit.

8. In claim 6 or 7, a fault diagnosis circuit including an abnormality determination circuit that determines whether the reference voltage is abnormal and outputs an abnormality determination signal indicative of the determination result;

9. In claim 8, a fault diagnosis signal output circuit that receives the abnormality determination signal and outputs a fault diagnosis signal at a predetermined timing different from the timing at which the reference voltage temporarily fluctuates;

10. In claim 9, The fault diagnosis signal output circuit includes: a fault diagnosis circuit that outputs the fault diagnosis signal at the timing of a rising edge of a clock signal supplied from a control circuit that controls the physical quantity signal processing circuit;

11. In claim 10, A fault diagnosis circuit, wherein the timing of a rising edge of the clock signal is different from the timing at which the reference voltage temporarily fluctuates.

12. In claim 11, The abnormality determination circuit includes: a first comparator having an inverting input terminal to which the reference voltage is input; a second comparator having a non-inverting input terminal to which the reference voltage is input; a logical OR circuit that outputs a logical OR signal based on the output signal of the first comparator and the output signal of the second comparator that are input thereto; a fault diagnosis circuit including:

13. A fault diagnosis circuit according to any one of claims 6 to 12; A physical quantity signal processing circuit; A reference voltage generating circuit; A physical quantity detection circuit comprising:

14. In claim 13, A physical quantity detection circuit including a control circuit.

15. A physical quantity detection circuit according to claim 13 or 14; A physical quantity detection element; A physical quantity sensor including:

16. The physical quantity sensor according to claim 15 ; A processing circuit that performs processing based on an output signal of the physical quantity sensor; Including electronic devices.

17. The physical quantity sensor according to claim 15 ; A processing circuit that performs processing based on an output signal of the physical quantity sensor; Including, a moving object.

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