Adaptive Equalizer

Abstract

To solve the problem that an adaptive equalizer is large in size.SOLUTION: An adaptive equalizer comprises: a convolutional integration part which calculates an equalization signal from an input signal and tap coefficients by tap output points and outputs it; an error calculation part which calculates and outputs an error signal as a difference between the equalization signal and a reference signal; a free-run counter; an error shift selection part which delays the error signal by a predetermined delay time in sequence, and selects and outputs an error signal having a delay quantity corresponding to a count value of the free-run counter; a delay matching part which delays an input signal of a tap output point having a maximum delay quantity by a predetermined quantity and outputs it; a correlation multiplication part which calculates a correlation value from the error signal output from the error shift selection part and the input signal output from the delay matching part and outputs it; and an integration part which integrates the correlation value output from the correlation multiplication part at each timing corresponding to the count value to generate a tap coefficient for each tap output point, and then outputs it to the convolutional integration part.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an adaptive equalizer that adaptively equalizes the waveform of an input signal obtained through digital transmission. [Background technology]

[0002] An example of this type of adaptive equalizer is described in Patent Document 1. The adaptive equalizer described in Patent Document 1 (hereinafter, referred to as the adaptive equalizer related to the present invention) includes an equalization filter section, an error amount calculation section, an input signal selection section, a correlation multiplier, and a tap coefficient selection section. The equalization filter section is formed of a transversal filter having a plurality of tap coefficients, and calculates an equalization signal based on input data and the tap coefficients. The error amount calculation section generates error data based on the equalization signal and reference data. The input signal selection section selects and outputs the input data and the error data for each tap. One correlation multiplier is provided for each of the plurality of taps, and calculates the correlation value between the input data and the error data selected by the input signal selection section, and sequentially calculates each tap coefficient. The tap coefficient selection section sequentially transmits each tap coefficient calculated by the correlation multiplier to the equalization filter section. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-26692 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the number of taps and the number of integrator bits of an adaptive equalizer are increasing with an increase in the number of modulation levels and an increase in transmission rate. Therefore, there is a demand for an adaptive equalizer with a small circuit size and low power consumption. In the adaptive equalizer related to the present invention, a correlation multiplier is shared by multiple taps, so that the circuit size and power consumption can be reduced compared to a configuration in which a correlation multiplier is provided for each tap. However, it is difficult to sufficiently reduce the circuit size of the entire adaptive equalizer by simply sharing a correlation multiplier among multiple taps.

[0005] An object of the present invention is to provide an adaptive equalizer that solves the above-mentioned problem, that is, the problem that it is difficult to sufficiently reduce the circuit size of the entire adaptive equalizer by simply sharing a correlation multiplier among multiple taps. [Means for solving the problem]

[0006] An adaptive equalizer according to an aspect of the present invention comprises: a convolution accumulator that calculates and outputs an equalization signal from an input signal and a tap coefficient for each tap output point; an error calculation unit that calculates and outputs an error signal which is a difference between the equalized signal and a reference signal; A free-running counter; an error shift selection unit that sequentially delays the output error signal by a predetermined delay time and selects and outputs an error signal having a delay amount corresponding to a count value of the free-running counter; a delay matching unit that delays an input signal at a tap output point with the maximum delay by a predetermined amount and outputs the delayed signal; a correlation multiplication unit that calculates and outputs a correlation value from the error signal output from the error shift selection unit and the input signal output from the delay matching unit; an integrating unit that integrates the correlation value output from the correlation multiplying unit for each timing according to the count value to generate a tap coefficient for each tap output point and outputs the generated tap coefficient to the convolution integrating unit; The device is configured to include: Effect of the Invention

[0007] By having the above-mentioned configuration, the present invention can reduce the circuit scale of the adaptive equalizer. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of an adaptive equalizer that is the premise of the present invention. [Figure 2A] FIG. 1 is a diagram showing an example of an integrator that does not have a leak function in an adaptive equalizer that is the premise of the present invention. [Figure 2B] FIG. 1 is a diagram illustrating an example of an integrator having a leak function in an adaptive equalizer that is the premise of the present invention. [Diagram 3] 1 is a diagram illustrating an example of the configuration of an adaptive equalizer according to a first embodiment of the present invention. [Figure 4A] FIG. 2 is a diagram illustrating an example of an enable integrator that does not have a leak function in the adaptive equalizer according to the first embodiment of the present invention. [Figure 4B] FIG. 2 is a diagram illustrating an example of an enable integrator having a leak function in the adaptive equalizer according to the first embodiment of the present invention. [Diagram 5] 4 is a timing chart of the adaptive equalizer according to the first embodiment of the present invention. [Figure 6] FIG. 11 is a diagram illustrating an example of the configuration of an adaptive equalizer according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a diagram illustrating an example of the configuration of an adaptive equalizer according to a third embodiment of the present invention. [Figure 8] 13 is a timing chart of an adaptive equalizer according to a third embodiment of the present invention. [Figure 9] FIG. 1 is a diagram showing a general configuration for generating equalized outputs for two mutually independent data streams. [Figure 10] FIG. 13 is a diagram illustrating an example of the configuration of an adaptive equalizer according to a fourth embodiment of the present invention. [Figure 11] FIG. 13 is a diagram illustrating an example of a multiplexing section and a demultiplexing section provided before and after an adaptive equalizer according to a fourth embodiment of the present invention. [Figure 12] 4 is a timing chart showing multiplexing of signal inputs. [Figure 13] 13 is a timing chart of an adaptive equalizer according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Example of an adaptive equalizer assumed in the present invention] Before describing the embodiments of the present invention, an example of an adaptive equalizer on which the present invention is based will be described.

[0010] Fig. 1 is a diagram showing an example of the configuration of an adaptive equalizer 1 on which the present invention is based. Referring to Fig. 1, the adaptive equalizer 1 is a transversal filter type adaptive equalizer provided in a receiving device that receives a modulated signal according to a multi-level QAM (Quadrature Amplitude Modulation) modulation method. The method of generating tap coefficients uses an LMS (Least Mean Square) algorithm that minimizes the mean square error. This adaptive equalizer 1 includes a convolution accumulator 100, an error calculator 200, a delay matching unit 300, a correlation multiplier 400, and an accumulator 500.

[0011] The convolution accumulation unit 100 includes a tapped delay line 101, a multiplier 102, and an adder 103. The tapped delay line 101 is a cascade connection of a plurality of flip-flops (hereinafter, referred to as FFs) 104, and has N tap output points 105. The FFs 104 and all other FFs operate on a clock with a period T. In FIG. 1, N=5. The delay difference between adjacent tap output points 105 is T seconds corresponding to one sample. A multiplier 102 is provided for each tap output point 105. Therefore, the number of multipliers 102 is N. The multiplier 102 multiplies the input signal of the tap output point 105 by a tap coefficient 106 corresponding to the tap output point 105, and outputs the result to the adder 103. Hereinafter, the tap coefficient 106 of the center tap is denoted as coefficient [0], and the tap coefficients 106 before and after it are denoted as coefficient [-2], coefficient [-1], coefficient [+1], and coefficient [+2]. The adder 103 calculates the sum of the multiplication results of the N multipliers 102, and outputs the calculated sum as an equalized signal.

[0012] The error calculation unit 200 calculates an error of the equalized signal output from the convolution integration unit 100. The error calculation unit 200 includes a convergence point determination unit 201 and a subtractor 202. The convergence point determination unit 201 detects, as a reference signal, a bit string corresponding to a convergence point closest to a signal point of the equalized signal output from the convolution integration unit 100. The subtractor 202 calculates a residual error signal by subtracting the reference signal detected by the convergence point determination unit 201 from the equalized signal output from the convolution integration unit 100. The residual error signal calculated by the error calculation unit 200 is output to the correlation multiplication unit 400.

[0013] Here, it is desirable that the delay difference between the output of the equalization signal by the convolution integrator 100 and the output of the residual error signal by the error calculator 200 is ideally zero. However, in reality, a delay of T seconds or more corresponding to one sample occurs. In the adaptive equalizer 1 shown in FIG. 1, the clock period is T, and a delay of 3T (3 clocks) corresponding to three stages of FFs is set. That is, the equalization signal by the convolution integrator 100 is input to the convergence point determiner 201 via the FF 203. Also, the output of the convergence point determiner 201 is input to the subtractor 202 via the FF 204. Also, the output of the subtractor 202 is input to the correlation multiplier 400 via the FF 205. Also, in order to match the timing of the equalization signal input from the convergence point determiner 201 to the subtractor 202 via the FF 204, the equalization signal output from the FF 203 is input to the subtractor 202 via the FF 206. The output of the FF 206 is output to the subtractor 202 and is also input to the FF 207 , and the output of the FF 207 becomes the signal output of the adaptive equalizer 1 .

[0014] The delay matching unit 300 delays each of the input signals of each tap output point 105 by the same amount of delay as the delay from the output of the equalized signal by the convolution integrator 100 to the output of the residual error signal by the error calculator 200, and outputs the delayed signals to the correlation multiplier 400. For this reason, the delay matching unit 300 includes a delay unit for each tap output point 105. In the example of Fig. 1, the number of tap output points 105 is five, and the delay amount is 3T, so the delay matching unit 300 includes five sets of delay units in which FFs 301 are connected in three stages.

[0015] The correlation multiplication unit 400 calculates and outputs a correlation value from the residual error signal output from the error calculation unit 200 and the input signal of each tap output point 105 output from the delay matching unit 300. The correlation multiplication unit 400 includes a multiplier 401 for each tap output point 105.

[0016] The accumulator 500 accumulates the correlation values ​​output from the multipliers 401 of the correlation multiplier 400, generates tap coefficients corresponding to each tap output point, and outputs the tap coefficients to the convolution accumulator 100. The accumulator 500 includes an accumulator 501 for each tap output point 105.

[0017] 2A is a diagram showing an example of an accumulator 501. The accumulator 501 in this example is an example of an accumulator that does not have a leak function, and includes an adder 5011, a FF 5012, and a lower-bit rounding unit 5013. The adder 5011 adds the correlation value output from the corresponding multiplier 401 and the accumulated value of one sample before held in the FF 5012, and outputs the result to the FF 5012. The FF 5012 holds the addition result of the adder 5011. The lower-bit rounding unit 5013 outputs a value obtained by rounding the lower bits of the accumulated value held in the FF 5012 to the convolution accumulation unit 100 as a tap coefficient of the corresponding tap output point.

[0018] FIG. 2B is a diagram showing another example of the accumulator 501. The accumulator 501 in this example is an example of an accumulator having a leak function, and includes an adder 5011, a FF 5012, a lower-bit rounding unit 5013, an adder 5014, and a leak unit 5015. The leak function is a function for gradually decreasing the absolute value of an accumulated value. The leak unit 5015 outputs a small absolute value having an opposite sign to the accumulated value of one sample before held in the FF 5012 (i.e., a negative number if the accumulated value is positive, and a positive number if the accumulated value is negative) to the adder 5014. The adder 5014 adds the correlation value output from the corresponding multiplier 401 and the value output from the leak unit 5015, and outputs the addition result to the adder 5011. The adder 5011, the FF 5012, and the lower-bit rounding unit 5013 perform the same operations as those in FIG. 2A.

[0019] Now, the adaptive equalizer 1, which is the premise of the present invention described above, requires a multiplier 401 for each tap output point 105 in the correlation multiplication unit 400. Also, the adaptive equalizer 1 requires a delay unit for each tap output point 105 in the delay matching unit 300. Therefore, when the number of tap output points increases, the circuit scale of the adaptive equalizer 1 increases proportionately. If an adaptive equalizer related to the present invention is applied to the adaptive equalizer 1 and the multiplier 401 is shared at a plurality of tap output points, the circuit scale of the correlation multiplication unit 400 can be reduced. However, it is difficult to sufficiently reduce the circuit scale of the entire adaptive equalizer by that alone. The reason is that the adaptive equalizer related to the present invention cannot reduce the circuit scale of the delay matching unit 300. Therefore, in this embodiment, an adaptive equalizer is realized that can reduce the circuit scale of not only the correlation multiplication unit 400 but also the delay matching unit 300.

[0020] Next, an embodiment of the present invention will be described in detail with reference to the drawings. [First embodiment] 3, an adaptive equalizer 2 according to the first embodiment of the present invention is a transversal filter type adaptive equalizer provided in a receiving device that receives a modulated signal according to a multi-level QAM modulation method. The LMS algorithm that minimizes the mean square error is used as a method for generating tap coefficients. This adaptive equalizer 2 includes a convolution integrator 100, an error calculator 200, a delay matching unit 310, a correlation multiplier 410, an integrator 510, a free-running counter 600, and a residual error shift selector 700.

[0021] The convolution integrator 100 and the error calculator 200 are the same as the convolution integrator 100 and the error calculator 200 of the adaptive equalizer 1 shown in Fig. 1. That is, the convolution integrator 100 inputs an input signal to a delay line 101 having N tap output points (in the case of Fig. 3, N=5) with a delay difference of T seconds between adjacent tap output points 105, calculates the sum of the results of multiplying the input signal of each tap output point 105 by the tap coefficient 106 corresponding to each tap output point, and outputs the sum as an equalization signal. Also, the error calculator 200 calculates and outputs a residual error signal which is the difference between the equalization signal and a reference signal.

[0022] The delay matching unit 300 receives an input signal from the tap output point 105 having the maximum delay amount in the convolution integrator 100, delays the input signal by the same amount as the delay difference between the output of the equalized signal by the convolution integrator 100 and the output of the error signal by the error calculator 200, and outputs the delayed signal to the correlation multiplier 410. In the example of Fig. 3, the delay difference is 3T. Therefore, the delay matching unit 300 has a delay unit in which FFs 311 are cascaded in three stages.

[0023] The free-running counter 600 repeatedly performs counting from the initial count value to the final count value overflowing in a constant period nT according to a clock with a period T. Here, n is the number of count values ​​that the free-running counter 600 can take. In this embodiment, n is set to be the same as the number N of tap output points 105 of the convolution integrator 100. That is, in the example of FIG. 3, n=N=5. Hereinafter, the count values ​​that the free-running counter 600 can take and their transitions are assumed to be −2→−1→0→+1→+2→−2. The count value of the free-running counter 600 is supplied to the integrator 510 and the residual error shift selector 700.

[0024] The residual error shift selection unit 700 sequentially delays the residual error signal output from the error calculation unit 200 by delay times 0, 1T, . . . , (N-1)T seconds, and selects and outputs an error signal with a delay amount according to the count value of the free-running counter 600. The residual error shift selection unit 700 includes N-1 FFs 701 to 704 and a selector 705. The residual error signal output from the error calculation unit 200 is input to the "-2" input terminal of the selector 705 and FF701. The residual error signal output from FF701 is input to the "-1" input terminal of the selector 705 and FF702. The residual error signal output from FF702 is input to the "0" input terminal of the selector 705 and FF703. The residual error signal output from FF703 is input to the "+1" input terminal of the selector 705 and FF704. The residual error signal output from the FF 704 is input to the “+2” input terminal of the selector 705. The selector 705 selects the residual error signal of the input terminal corresponding to the count value of the free-running counter 600, and outputs it to the correlation multiplication unit 410.

[0025] As described above, the count value of the free-running counter 600 transitions from -2 to -1 to 0 to +1 to +2 to -2. Therefore, the selector 705 selects the input terminals in the order of the "-2" input terminal, the "-1" input terminal, the "0" input terminal, the "+1" input terminal, the "+2" input terminal, and the "-2" input terminal. Meanwhile, the residual error signal input to the "-2" input terminal is input to the "-1" input terminal via FF701 after T time, input to the "0" input terminal via FF702 after the next T time, input to the "-1" input terminal via FF703 after the next T time, and input to the "-2" input terminal via FF704 after the next T time. As a result, the selector 705 selects the same residual error signal over a period of 5T, and in the next period of 5T, selects the residual error signal output 5T after the previously selected residual error signal. In this way, the residual error shift selection section 700 selects the residual error signal output from the error calculation section 200 once every five times, and continues to output the selected residual error signal over a period of 5T.

[0026] The correlation multiplication unit 410 calculates a correlation value from the residual error signal output from the residual error shift selection unit 700 and the input signal output from the delay matching unit 310. The correlation multiplication unit 410 includes one multiplier 411 for calculating the correlation value. The correlation value calculated by the correlation multiplication unit 410 is output to the accumulation unit 510.

[0027] As described above, the residual error shift selection unit 700 outputs the residual error signal selected once every five times to the correlation multiplication unit 410 over a period of 5T. Meanwhile, the delay matching unit 310 delays and matches five input signals every T time during the period of 5T and sequentially outputs them to the correlation multiplication unit 410. As a result, the multiplier 411 calculates and outputs a correlation value between the residual error signal output from the residual error shift selection unit 700 and five input signals related to the residual error signal every 1T. Here, the five input signals related to the residual error signal refer to the input signals at the five tap output points used in the convolution operation of the equalization output used to generate the residual error signal.

[0028] The accumulator 510 accumulates the correlation value output from the correlation multiplier 410 for each time T at a timing corresponding to the count value of the free-running counter 600, and generates the tap coefficient 106 corresponding to the count value. The accumulator 510 outputs the generated tap coefficient 106 to the convolution accumulator 100.

[0029] The accumulator 510 includes an enable accumulator 511 and an enable signal generator 512 for each tap coefficient. Each enable signal generator 512 compares a preset value with the count value of the free-running counter 600, and sends an enable signal to the corresponding enable accumulator 511 when the count value matches the preset value. For example, the enable signal generator 512 set to "-2" sends an enable signal to the enable accumulator 511 corresponding to the coefficient [-2] when the count value of the free-running counter 600 matches "-2". Similarly, the remaining four enable signal generators 512 set to "-1", "0", "+1", and "+2" send enable signals to the enable accumulators 511 corresponding to the coefficients [-1], [0], [+1], and [+2] when the count value of the free-running counter 600 matches "-1", "0", "+1", and "+2", respectively.

[0030] Each enable integrator 511 integrates the correlation value output from the correlation multiplication unit 410 at the timing of the enable signal, and outputs the integration result to the convolution integration unit 100 as a tap coefficient. For example, the enable integrator 511 corresponding to the tap coefficient [-2] receives the enable signal at the timing of the count value "-2" of the free-running counter 600, and integrates the correlation value output from the correlation multiplication unit 410 at that timing. Similarly, the enable integrator 511 corresponding to the tap coefficients [-1], [0], [+1], and [+2] receives the enable signal at the timing of the count values ​​"-1", "0", "+1", and "+2" of the free-running counter 600, and integrates the correlation value output from the correlation multiplication unit 410 at that timing. As a result, each enable integrator 511 integrates the correlation value of the correlation multiplication unit 410 at a period of 5T.

[0031] 4A is a diagram showing an example of an enable accumulator 511. The enable accumulator 511 in this example is an example of an accumulator that does not have a leak function that gradually reduces an accumulated value, and includes an adder 5111, a selector 5112, a FF 5113, and a lower-bit rounding unit 5114. The adder 5111 adds the correlation value output from the multiplier 411 and the accumulated value of one sample before held in the FF 5113, and outputs the result to one input terminal of the selector 5112. The accumulated value of one sample before held in the FF 5113 is input to the other input terminal of the selector 5112. The selector 5112 selects the output of the adder 5111 at the timing of the enable signal and outputs it to the FF 5113, and selects the output of the FF 5113 at other timings and outputs it to the FF 5113. The lower-order bit rounding unit 5114 rounds the lower-order bits of the integrated value held in the FF 5113 and outputs the rounded value to the convolution integration unit 100 as the tap coefficient of the corresponding tap output point.

[0032] FIG. 4B is a diagram showing another example of the enable accumulator 511. The accumulator 501 in this example is an example of an accumulator having a leak function, and includes a FF 5113, a lower-bit rounding unit 5114, a selector 5115, an adder 5116, and a leak unit 5117. The leak unit 5117 outputs a predetermined value having a small absolute value and an opposite sign to the integrated value of one sample before held in the FF 5113 to one input terminal of the selector 5115. The selector 5115 selects the correlation value output from the multiplier 411 at the timing of the enable signal and outputs it to the adder 5116, and at other timings, selects the output of the leak unit 5117 and outputs it to the adder 5116. The adder 5116 adds the output of the selector 5115 and the integrated value of one sample before held in the FF 5113 to calculate an integrated value, and outputs it to the leak unit 5117 and the lower-bit rounding unit 5114. The lower-order bit rounding unit 5114 rounds the lower-order bits of the integrated value held in the FF 5113 and outputs the rounded value as a tap coefficient of the corresponding tap output point to the convolution integration unit 100. The integrator 501 having a leak function shown in Fig. 2B required two adders 5011 and 5014, but the enable integrator 511 having a leak function shown in Fig. 4B can share an adder, so that it is realized with one adder 5116.

[0033] FIG. 5 is a timing chart of the adaptive equalizer 2 shown in FIG. 3. If the data stream of the signal input is represented as d1, d2, ..., the output of the delay matching unit 310 is delayed by 8 clocks, as shown in FIG. 5. Also, the data stream of the residual error signal is represented as ei-j using the subscripts of the input signal d of the five tap output points used in the convolution operation of the equalization output used to generate the residual error signal. For example, e1-5 means the residual error signal of the equalization output obtained by convolution operation of five input signals d1, d2, d3, d4, and d5. Since there is a delay of 3 clocks from the equalization output to the residual error output, the residual error signals at the "-2", "-1", "0", "+1", and "+2" input terminals of the selector 705 of the residual error shift selection unit 700 are as shown in FIG. 5. Since the input terminal "0" of the selector 705 of the residual error shift selection unit 700 is set to a signal corresponding to the center tap indicated by the tap coefficient [0], the delay of the residual error signal input to the input terminal "0" is 8 clocks. The phase of the signal input data stream of the free-running counter 600 is arbitrary, but if it is the phase shown in FIG. 5, the output of the residual error shift selection unit 700 will be as shown in FIG. 5. If the data stream of correlation values ​​is represented as c1, c2, . . ., c4 to c8 are the correlation values ​​between the input signals d4 to d8 and the residual error signal e4-8, and c9 to c13 are the correlation values ​​between the input signals d9 to d13 and the residual error signal e9-13. Although the integration timing is different, the relationship between the coefficients [-2], [-1], [0], [+1], and [+2] and the correlation values ​​is correct, and there is no problem with the function of the adaptive equalizer. In addition, the timing chart of FIG. 5 uses an enabled integrator 511 without a leak function, and the integrated value is not updated during the non-enabled time period.

[0034] As described above, according to the adaptive equalizer 2 of this embodiment, the multiplier 411 is shared by multiple tap coefficients, so that the circuit scale of the correlation multiplication unit 410 can be reduced to 1 / the number of taps. Also, since the delay matching unit 310 is provided only for the input signal after the maximum tap shift, the circuit scale of the delay matching unit 310 can be reduced to 1 / the number of taps. On the other hand, the residual error shift selection unit 700 and the free-running counter 600 are newly required, but their circuit scale is not proportional to the number of taps. Therefore, the circuit scale of the adaptive equalizer 2 can be significantly reduced compared to the adaptive equalizer 1 on which the present invention is based. Also, according to the adaptive equalizer 2 of this embodiment, the integration period of the integration unit 510 is longer than that of the adaptive equalizer 1 on which the present invention is based, so that the desired smoothing can be achieved with a small number of integrator bits.

[0035] [Second embodiment] 6, an adaptive equalizer 3 according to the second embodiment of the present invention differs from the adaptive equalizer 2 shown in FIG. 3 in that it includes a free-running counter 610 instead of the free-running counter 600 and a residual error shift selection unit 710 instead of the residual error shift selection unit 700, but is otherwise the same as the adaptive equalizer 2.

[0036] The free-running counter 610 repeatedly performs counting from the initial count value to the final count value overflowing in a constant period mT according to a clock with a period T. Here, m is the number of count values ​​that the free-running counter 610 can take. In this embodiment, m is set to a positive value larger than the number N of tap output points 105 of the convolution integrator 100. That is, in the example of FIG. 6, m=N(=5)+1=6. Hereinafter, the count values ​​that the free-running counter 610 can take and their transitions are -2→-1→0→+1→+2→+3→-2. That is, the free-running counter 610 has one state "+3" inserted in the transition of the free-running counter 600's count value from +2 to -2.

[0037] 3 in that it includes a selector 715 instead of the selector 705, but otherwise is the same as the residual error shift selection unit 700. The selector 715 includes five input terminals from "-2" to "+2" to which the same inputs as those of the selector 705 are applied, and further includes a "+3" input terminal. An arbitrary value (0 in the illustrated example) is input to the "+3" input terminal. The selector 715 selects the residual error signal of the input terminal corresponding to the count value of the free-running counter 610 or the value 0, and outputs it to the correlation multiplication unit 410.

[0038] As described above, the count value of the free-running counter 610 transitions from -2 to -1 to 0 to +1 to +2 to +3 to -2. Therefore, the selector 715 selects the input terminals in the order of the "-2" input terminal, the "-1" input terminal, the "0" input terminal, the "+1" input terminal, the "+2" input terminal, the "+3" input terminal, and the "-2" input terminal. As a result, the selector 715 selects the same residual error signal over a period of 5T, selects value 0 in the next 1T, and selects the residual error signal output 6T after the previously selected residual error signal in the next 5T period. In this way, the residual error shift selection unit 710 selects the residual error signal output from the error calculation unit 200 once every six times, and continues to output the selected residual error signal over a period of 5T. As a result, the integration period in the integration unit 510 of the adaptive equalizer 3 becomes longer than that of the adaptive equalizer 2, and as a result, the update speed of the tap coefficients can be reduced.

[0039] In the above example, N=5 and m=6, but N and m are not limited to the above example. For example, N=5 and m=7 may be used. In this case, the free-running counter 610 inserts two states (for example, "+3" and "+4") in the transition of the count value of the free-running counter 600 from +2 to -2. Also, the selector 715 of the residual error shift selection unit 710 has a "+3" input terminal and a "+4" input terminal to which, for example, a value 0 is input, and selects the same residual error signal over a period of 5T, selects a value 0 in the next 2T, and selects the residual error signal output 7T after the previously selected residual error signal in the next period of 5T.

[0040] Also, instead of the free-running counter 610 of the adaptive equalizer 3 shown in Fig. 6, the free-running counter 600 used in the adaptive equalizer 3 shown in Fig. 3 may be used. In this case, the residual error shift selection unit 710 performs the same operation as the residual error shift selection unit 700 shown in Fig. 3. That is, the residual error shift selection unit 710 selects the same residual error signal over a period of 5T, and in the next period of 5T, selects the residual error signal output 5T after the previously selected residual error signal. By adjusting the period of the free-running counter 610 in this way, a desired tap coefficient update speed can be achieved, and therefore, the transmission rate can be flexibly changed. The period of the free-running counter can be adjusted by physically replacing the free-running counter, using a programmable free-running counter whose period can be changed, or the like.

[0041] 3 may be used instead of the residual error shift selection unit 710. In this case, the residual error shift selection unit 700 selects the same residual error signal over a period of 5T, outputs an indefinite value in the next 1T when the count value "+3" is input, and selects the residual error signal output 6T after the previously selected residual error signal in the next period of 5T. However, even if an indefinite value is output from the residual error shift selection unit 700, none of the enable integrators 511 are enabled at that timing, so there is no substantial effect.

[0042] [Third embodiment] 7, the adaptive equalizer 4 according to the third embodiment of the present invention includes a convolution accumulator 100, an error calculator 200, a delay matching unit 310, free-running counters 620 and 630, residual error shift selectors 720 and 730, correlation multipliers 420 and 430, and accumulators 520 and 530. Among these, the convolution accumulator 100, the error calculator 200, and the delay matching unit 310 are the same as those of the adaptive equalizer 2 shown in FIG.

[0043] In the adaptive equalizer 4 according to the present embodiment, N tap coefficients are divided into two groups, and a set of a free-running counter, a residual error shift selection unit, a correlation multiplication unit, and an integrator unit is provided for each group. In the example of Fig. 7, five tap coefficients are divided into two groups: group 1 to which coefficients [-2], [0], and [+2] belong, and group 2 to which coefficients [-1] and [+1] belong.

[0044] To group 1, the free-running counter 620, the residual error shift selection section 720, the correlation multiplication section 420, and the accumulator section 520 are assigned.

[0045] The free-running counter 620 repeatedly counts from the initial count value to the final count value overflowing at a constant period m1T in accordance with a clock with a period T. Here, m1 is the number of count values ​​that the free-running counter 620 can take. In this embodiment, m1=3. Hereinafter, the count values ​​that the free-running counter 620 can take and their transitions are defined as -2→0→+2→-2.

[0046] The residual error shift selection unit 720 sequentially delays the residual error signal output from the error calculation unit 200 by delay times 0, 1T, . . . , (N-1)T seconds, and selects and outputs an error signal with a delay amount according to the count value of the free-running counter 620. The residual error shift selection unit 720 includes N-1 FFs 721 to 724 and a selector 725. The residual error signal output from the error calculation unit 200 is input to the "-2" input terminal of the selector 725 and FF721. The residual error signal output from FF721 is input to FF722 and the residual error shift selection unit 730 of group 2. The residual error signal output from FF722 is input to the "0" input terminal of the selector 725 and FF723. The residual error signal output from FF723 is input to FF724 and the residual error shift selection unit 730 of group 2. The residual error signal output from the FF 724 is input to the “+2” input terminal of the selector 725. The selector 725 selects the residual error signal of the input terminal corresponding to the count value of the free-running counter 620, and outputs it to the correlation multiplication section 420.

[0047] As described above, the count value of the free-running counter 620 transitions from -2 to 0 to +2 to -2. Therefore, the selector 725 selects input terminals in the order of the "-2" input terminal, the "0" input terminal, and the "+2" input terminal. Meanwhile, the residual error signal of the residual error signal 1T before that input to the "-2" input terminal is input to the "0" input terminal 1T later, and the residual error signal of the residual error signal 2T before that input to the "-2" input terminal is input to the "+2" input terminal 2T later. As a result, the selector 725 selects and outputs residual error signals that differ from each other every 1T.

[0048] The correlation multiplication unit 420 calculates a correlation value from the residual error signal output from the residual error shift selection unit 720 and the input signal output from the delay matching unit 310. The correlation multiplication unit 420 includes one multiplier 421 for calculating the correlation value. The correlation value calculated by the correlation multiplication unit 420 is output to the accumulation unit 520.

[0049] As described above, a different residual error signal is output from the residual error shift selection unit 720 to the correlation multiplication unit 420 every T time. Meanwhile, the delay matching unit 310 delays and matches the input signal every T time and sequentially outputs it to the correlation multiplication unit 420. As a result, the multiplier 421 calculates and outputs a correlation value between the residual error signal output from the residual error shift selection unit 720 and the input signal related to the residual error signal every T time. Here, the input signal related to the residual error signal means the input signal used in the convolution operation of the equalization output used to generate the residual error signal.

[0050] The accumulator 520 accumulates the correlation value output from the correlation multiplier 420 for each time T at a timing corresponding to the count value of the free-running counter 620, and generates the tap coefficient 106 corresponding to the count value. The accumulator 520 outputs the generated tap coefficient 106 to the convolution accumulator 100.

[0051] The accumulator 520 includes an enable accumulator 521 and an enable signal generator 522 for each tap coefficient. Each enable signal generator 522 compares a preset value with the count value of the free-running counter 620, and sends an enable signal to the corresponding enable accumulator 521 at the timing when the count value matches the preset value. For example, the enable signal generator 522 set to "-2" sends an enable signal to the enable accumulator 521 corresponding to the coefficient [-2] at the timing when the count value of the free-running counter 620 matches "-2". Similarly, the remaining two enable signal generators 522 set to "0" and "+2" send enable signals to the enable accumulators 521 corresponding to the coefficients [0] and [+2], respectively, at the timing when the count value of the free-running counter 620 matches "0" and "+2", respectively. As a result, each enable accumulator 521 accumulates the correlation value of the correlation multiplier 420 at a period of 3T. Each enable integrator 521 is configured and operates similarly to enable integrator 511 of FIG.

[0052] To group 2, the free-running counter 630, the residual error shift selection section 730, the correlation multiplication section 430, and the accumulator 530 are assigned.

[0053] The free-running counter 630 repeatedly counts from the initial count value to the final count value overflowing in a constant period m2T in accordance with a clock with a period T. Here, m2 is the number of count values ​​that the free-running counter 630 can take. In this embodiment, m2=2. Hereinafter, the count values ​​that the free-running counter 630 can take and the transition thereof will be referred to as -1→+1→-1.

[0054] The residual error shift selection unit 730 receives the residual error signal output from the error calculation unit 200 and sequentially delayed by the delay time 1T, (N-2) seconds in the residual error shift selection unit 720, and selects and outputs a residual error signal with a delay amount according to the count value of the free-running counter 630. The residual error shift selection unit 730 includes a selector 735. The selector 735 has a "-1" input terminal for inputting the residual error signal output from the error calculation unit 200 and delayed by the delay time 1T, and a "+1" input terminal for inputting the residual error signal output from the error calculation unit 200 and delayed by the delay time (N-2). The selector 735 selects the residual error signal of the input terminal corresponding to the count value of the free-running counter 630, and outputs it to the correlation multiplication unit 430.

[0055] As described above, the count value of the free-running counter 630 transitions from -1 to +1 to -1. Therefore, the selector 735 selects the input terminals in the order of the "-1" input terminal and then the "+1" input terminal. Meanwhile, the residual error signal 1T before that which was input to the "-1" input terminal is input to the "+1" input terminal 1T later. As a result, the selector 735 selects and outputs residual error signals which differ from each other every 1T.

[0056] The correlation multiplication unit 430 calculates a correlation value from the residual error signal output from the residual error shift selection unit 730 and the input signal output from the delay matching unit 310. The correlation multiplication unit 430 includes one multiplier 431 for calculating the correlation value. The correlation value calculated by the correlation multiplication unit 430 is output to the accumulation unit 530.

[0057] As described above, a different residual error signal is output from the residual error shift selection unit 730 to the correlation multiplication unit 430 every T time. Meanwhile, the delay matching unit 310 delays and matches the input signal every T time and sequentially outputs it to the correlation multiplication unit 430. As a result, the multiplier 431 calculates and outputs a correlation value between the residual error signal output from the residual error shift selection unit 730 and the input signal related to the residual error signal every T time. Here, the input signal related to the residual error signal means the input signal used in the convolution operation of the equalization output used to generate the residual error signal.

[0058] The accumulator 530 accumulates the correlation value output from the correlation multiplier 430 for each time T at a timing corresponding to the count value of the free-running counter 630, and generates the tap coefficient 106 corresponding to the count value. The accumulator 530 outputs the generated tap coefficient 106 to the convolution accumulator 100.

[0059] The accumulator 530 includes an enable accumulator 531 and an enable signal generator 532 for each tap coefficient. Each enable signal generator 532 compares a preset value with the count value of the free-running counter 630, and sends an enable signal to the corresponding enable accumulator 531 at the timing when the count value matches the preset value. For example, the enable signal generator 532 set to "-1" sends an enable signal to the enable accumulator 531 corresponding to the coefficient [-1] at the timing when the count value of the free-running counter 630 matches "-1". Similarly, the remaining enable signal generators 532 set to "+1" send enable signals to the enable accumulators 531 corresponding to the coefficient [+1] at the timing when the count value of the free-running counter 630 matches "+1". As a result, each enable accumulator 531 accumulates the correlation value of the correlation multiplier 430 in a period of 2T. Each enable integrator 531 is configured and operates similarly to enable integrator 511 of FIG.

[0060] Fig. 8 is a timing chart of the adaptive equalizer 4 shown in Fig. 7. As in Fig. 5, the signal input is represented as di, the residual error signal is represented as ei-j, and the correlation value is represented as ci.

[0061] In group 1, the residual error signals at the "-2", "0", and "+2" input terminals of the selector 725 of the residual error shift selection unit 720 are as shown in Fig. 8. The phase of the signal input of the free-running counter 620 is arbitrary, but if it is the phase shown in Fig. 8, the output of the residual error shift selection unit 720 changes every T time as shown in Fig. 8, and the correlation value ci of the correlation multiplication unit 420 is as shown in Fig. 8. For example, the correlation value c4 of the correlation multiplication unit 420 is the correlation value between the input signal d4 and the residual error signal e4-8, the correlation value c5 is the correlation value between the input signal d5 and the residual error signal e3-7, and the correlation value c6 is the input signal d6 and the residual error signal e2-6. Although the integration timing is different, the relationship between the coefficients [-2], [0], and [+2] and the correlation values ​​is correct, and there is no problem with the function of the adaptive equalizer for group 1. In addition, the timing chart of FIG. 8 uses an enable integrator 521 without a leak function, and the coefficients [-2], [0], and [+2] are updated at a rate of once every 3T.

[0062] In group 2, the residual error signals at the "-1" and "+1" input terminals of the selector 735 of the residual error shift selection unit 730 are as shown in FIG. 8. The phase of the signal input of the free-running counter 630 is arbitrary, but if it is the phase shown in FIG. 8, the output of the residual error shift selection unit 730 changes every T time as shown in FIG. 8, and the correlation value ci of the correlation multiplication unit 430 is as shown in FIG. 8. For example, the correlation value c4 of the correlation multiplication unit 430 is the correlation value between the input signal d4 and the residual error signal e3-7, and the correlation value c5 is the correlation value between the input signal d5 and the residual error signal e2-6. Although the integration timing is different, the relationship between the coefficients [-1] and [+1] and the correlation values ​​is correct, and there is no problem with the function of the adaptive equalizer for group 2. Note that the timing chart in FIG. 8 uses the enable integrator 531 without a leak function, and the coefficients [-1] and [+1] are updated once every 2T.

[0063] As described above, according to the adaptive equalizer 4 of this embodiment, N tap output points are divided into two groups, and each group is provided with a free-running counter, a residual error shift selection unit, a correlation multiplier, and an integrator. Therefore, although the circuit scale of the entire adaptive equalizer 4 increases compared to the adaptive equalizer 2 of the first embodiment, it can be significantly reduced compared to the adaptive equalizer 1 on which the present invention is based. Furthermore, according to the adaptive equalizer 4 of this embodiment, the update speed of the tap coefficients can be made higher compared to the adaptive equalizer 2 of the first embodiment. Therefore, the adaptive equalizer 4 can handle a lower transmission rate than the adaptive equalizer 2. In the above example, five tap output points are divided into two groups, and m1=3 and m2=2, but the values ​​of m1 and m2 are not limited to the above. The values ​​of m1 and m2 may be values ​​according to a desired integration period. Furthermore, in the above example, N tap output points are divided into two groups, but they may be divided into three or more groups.

[0064] [Fourth embodiment] Next, a fourth embodiment of the present invention will be described below. In this embodiment, an adaptive equalizer capable of processing a multiplexed data stream will be described.

[0065] When generating equalized outputs for two mutually independent data streams A and B, it is common to provide an equalizer for each data stream, as shown in Fig. 9. However, such a configuration increases the circuit scale. Therefore, in this embodiment, data streams A and B are multiplexed to generate one multiplexed data stream, and equalized outputs for each of data streams A and B are generated from the multiplexed data stream using a single adaptive equalizer capable of processing the multiplexed data stream.

[0066] Fig. 10 is a block diagram showing an example of an adaptive equalizer 5 capable of processing a multiplexed data stream, and Fig. 11 is a block diagram showing an example of a multiplexing unit 6 and a demultiplexing unit 7 provided before and after the adaptive equalizer 5.

[0067] The multiplexing unit 6 receives data streams A and B, which are independent of each other. Data stream A is composed of data elements A1, A2, A3, . . . as shown in the timing chart of FIG. 12. Data stream B is composed of data elements B1, B2, B3, . . . as shown in FIG. 12. The data transmission rates of data streams A and B are the same and are almost in phase with each other. The multiplexing unit 6 uses a transmission rate enable and a clock (period T seconds) having a frequency twice the transmission rate to generate and output a multiplexed data stream by multiplexing two data streams A and B, for example, as shown in FIG. 12. The transmission rate of the multiplexed data stream is twice that of the original data streams A and B. The multiplexing unit 6 can be composed of, for example, a selector 61.

[0068] The adaptive equalizer 5 receives the multiplexed data stream output from the multiplexer 6 and the above clock, and generates and outputs a multiplexed equalized data stream by multiplexing the equalized outputs of data streams A and B. The transmission rate of the multiplexed equalized data stream is the same as that of the multiplexed data stream.

[0069] The demultiplexer 7 receives the multiplexed equalized data stream output from the adaptive equalizer 5, the transmission rate enable, and a clock, and separates and outputs mutually independent data streams A and B from the multiplexed equalized data stream. The demultiplexer 7 can be composed of FF71 which delays the output of the adaptive equalizer 5 by 1T, FF72 which generates data stream A from the output of FF71 using the transmission rate enable, and FF73 which generates data stream B from the output of the adaptive equalizer 5 using the transmission rate enable. The transmission rates of the data streams A and B output from the demultiplexer 7 are the same as those of the data streams A and B input to the multiplexer 6.

[0070] 10, an example of the adaptive equalizer 5 includes a convolution accumulator 110, an error calculator 200, a delay matching unit 310, a correlation multiplier 410, an accumulator 540, a free-running counter 640, and a residual error shift selector 740. Among these, the error calculator 200, the delay matching unit 310, and the correlation multiplier 410 are the same as those in the adaptive equalizer 2 shown in FIG.

[0071] The convolution accumulator 110 includes a tapped delay line 111, a multiplier 112, and an adder 113. The tapped delay line 111 is formed by cascading five FFs 114, and has three tap output points 115. The FFs 114 and all other FFs operate on a clock with a period T. The multiplexed data stream shown in FIG. 12 is input to the tapped delay line 111. The delay difference between the tap output points 115 is 2T seconds, which corresponds to two samples. Therefore, at a certain timing, three data elements (A1, A2, A3, etc.) of data stream A appear at the three tap output points 115, and after the next T time, three data elements (B1, B2, B3, etc.) of data stream B appear at the three tap output points 115. That is, at the three tap output points 115, the three data elements of data stream A and the three data elements of data stream B appear alternately every T time. A multiplier 112 is provided for each tap output point 115. Therefore, the number of multipliers 112 is three. Tap coefficients corresponding to the tap output points 115 are multiplexed and provided to the multipliers 112. That is, at the timing when a data element of data stream A appears at tap output point 115, the tap coefficient of data stream A is provided to the multiplier 112. Also, at the timing when a data element of data stream B appears at tap output point 115, the tap coefficient of data stream B is provided to the multiplier 112. The multiplier 112 multiplies the input signal of the tap output point 115 by the tap coefficient 116 every T time, and outputs the result to the adder 113. Hereinafter, the tap coefficients of data stream A are denoted as coefficient [0], coefficient [2], and coefficient [4], and the tap coefficients of data stream B are denoted as coefficient [1], coefficient [3], and coefficient [5]. Adder 113 calculates the sum of the multiplication results of the three multipliers 112 and outputs the calculated sum as an equalized signal. As a result, adder 113 alternately outputs an equalized signal for data stream A and an equalized signal for data stream B every T time periods.

[0072] The free-running counter 640 repeatedly performs counting from the initial count value to the overflow at the final count value with a constant period nT according to a clock with a period T. Here, n is the number of count values ​​that the free-running counter 600 can take. In this embodiment, n is set to be twice the number N of the tap output points 105 of the convolution integrator 110. That is, in the example of FIG. 10, n=2N=6. Hereinafter, the count values ​​that the free-running counter 640 can take and the transitions thereof are assumed to be 0→1→2→3→4→5→0. The count value of the free-running counter 640 is supplied to the integrator 540 and the residual error shift selector 740.

[0073] The residual error shift selection unit 740 sequentially delays the residual error signal output from the error calculation unit 200 by delay times of 0, 2T, and 4T seconds, and selects and outputs an error signal with a delay amount according to the count value of the free-running counter 640. The residual error shift selection unit 740 includes four FFs 741 to 744 and a selector 745. The residual error signal output from the error calculation unit 200 is input to the input terminals "0" and "1" of the selector 745 and to FF741. The residual error signal output from FF741 is input to FF742. The residual error signal output from FF742 is input to the input terminals "2" and "3" of the selector 745 and to FF743. The residual error signal output from FF743 is input to FF744. The residual error signal output from FF744 is input to the input terminals "4" and "5" of the selector 745. The selector 745 selects the residual error signal at the input terminal corresponding to the count value of the free-running counter 640 , and outputs it to the correlation multiplication section 410 .

[0074] As described above, the count value of the free-running counter 640 transitions from 0 to 1 to 2 to 3 to 4 to 5 to 0. Therefore, the selector 745 selects the input terminal in the order of the "0" input terminal, the "1" input terminal, the "2" input terminal, the "3" input terminal, the "4" input terminal, the "5" input terminal, and the "0" input terminal. Meanwhile, the residual error signal input to the "0" and "1" input terminals is input to the "2" and "3" input terminals via FFs 741 and 742 after 2T, and is further input to the "4" and "5" input terminals via FFs 743 and 744 after the next 2T. As a result, the selector 745 selects and outputs the same residual error signal of one of the data streams A and B (for example, data stream A) at the first 1T, the third 1T, and the fifth 1T of the consecutive 6T periods. Furthermore, the selector 745 selects and outputs the same residual error signal of the other of data streams A and B (e.g., data stream B) at the second 1T, fourth 1T, and sixth 1T among the consecutive 6T periods. Then, in the next 6T period, the selector 745 selects and outputs the residual error signal three data points after the residual error signal output in the previous 6T period. In this way, the residual error shift selection unit 740 selects the residual error signal output from the error calculation unit 200 for data streams A and B once every three times, and outputs the selected residual error signal alternately for data streams A and B, with the same value three times.

[0075] The correlation multiplication unit 410 calculates a correlation value from the residual error signal output from the residual error shift selection unit 740 and the input signal output from the delay matching unit 310. The correlation multiplication unit 410 includes one multiplier 411 for calculating the correlation value. The correlation value calculated by the correlation multiplication unit 410 is output to the accumulation unit 540.

[0076] As described above, the residual error shift selection unit 740 outputs to the correlation multiplication unit 410, during the period of 6T, the residual error signals selected once every three times for the data streams A and B, alternately three times for the data streams A and B. Meanwhile, the delay matching unit 310 delays and matches three data elements for each of the data streams A and B every T time during the period of 6T, and outputs the delays and matches the three data elements alternately to the correlation multiplication unit 410. As a result, the multiplier 411 calculates and outputs a correlation value between the residual error signal of the data stream A output from the residual error shift selection unit 740 and the three input signals of the data stream A related to the residual error signal every 1T. Similarly, the multiplier 411 calculates and outputs a correlation value between the residual error signal of the data stream B output from the residual error shift selection unit 740 and the three input signals of the data stream B related to the residual error signal every 1T. Here, the three input signals related to the residual error signal of the data stream refer to the input signals of the three tap output points used in the convolution operation of the equalization output used to generate the residual error signal.

[0077] The accumulator 540 accumulates the correlation value output from the correlation multiplier 410 for each time T at a timing corresponding to the count value of the free-running counter 640, and generates the tap coefficient 106 corresponding to the count value. The accumulator 540 outputs the generated tap coefficient 106 to the convolution accumulator 100.

[0078] The accumulator 540 includes an enable accumulator 541 and an enable signal generator 542 for each tap coefficient, and a multiplexer 543 for each tap output point. Each enable signal generator 542 compares a preset value with the count value of the free-running counter 640, and sends an enable signal to the corresponding enable accumulator 541 when the count value matches the preset value. For example, the enable signal generator 542 set to "0" sends an enable signal to the enable accumulator 541 corresponding to the coefficient [0] when the count value of the free-running counter 640 matches "0". Similarly, the remaining five enable signal generators 542 set to "1", "2", "3", "4", and "5" send enable signals to the enable accumulators 541 corresponding to the coefficients [1], [2], [3], [4], and [5] when the count value of the free-running counter 640 matches "1", "2", "3", "4", and "5", respectively.

[0079] Each enable integrator 541 integrates the correlation value output from the correlation multiplication unit 410 at the timing of the enable signal, and outputs the integration result as a tap coefficient to the multiplexing unit 543. For example, the enable integrator 541 corresponding to the tap coefficients [0] and [1] receives the enable signal at the timing of the count values ​​"0" and "1" of the free-running counter 640, integrates the correlation value output from the correlation multiplication unit 410 at that timing, and outputs the integration result to the multiplexing unit 543 corresponding to the tap output points of the coefficients [0] and [1]. Also, the enable integrator 541 corresponding to the tap coefficients [2] and [3] receives the enable signal at the timing of the count values ​​"2" and "3" of the free-running counter 640, integrates the correlation value output from the correlation multiplication unit 410 at that timing, and outputs the integration result to the multiplexing unit 543 corresponding to the tap output points of the coefficients [2] and [3]. 3. Also, enable integrator 541 corresponding to tap coefficients [4] and [5] receives an enable signal at the timing of count values ​​"4" and "5" of free-running counter 640, integrates the correlation value output from correlation multiplication unit 410 at that timing, and outputs the integration result to multiplexer 543 corresponding to the tap output points of coefficients [4] and [5]. As a result, each enable integrator 541 integrates the correlation value of correlation multiplication unit 410 at a period of 6T. Each enable integrator 541 is configured and operates in the same manner as enable integrator 511 in FIG. 3.

[0080] The multiplexing unit 543 multiplexes the tap coefficients input from the two enable integrators 541, and outputs the multiplexed tap coefficients to the multiplier 112 of the corresponding tap output point. For example, the multiplexing unit 543 corresponding to the tap output points of the coefficients [0] and [1] multiplexes the tap coefficient input from the enable integrator 541 corresponding to the coefficient [0] and the tap coefficient input from the enable integrator 541 corresponding to the coefficient [1], and outputs the multiplexed tap coefficients to the multiplier 112 of the tap output points corresponding to the coefficients [0] and [1]. The multiplexing unit 543 corresponding to the tap output points of the coefficients [2] and [3] multiplexes the tap coefficient input from the enable integrator 541 corresponding to the coefficient [2] and the tap coefficient input from the enable integrator 541 corresponding to the coefficient [3], and outputs the multiplexed tap coefficients to the multiplier 112 of the tap output points corresponding to the coefficients [2] and [3]. Furthermore, multiplexing unit 543 corresponding to the tap output points of coefficients [4] and [5] multiplexes the tap coefficient input from enable integrator 541 corresponding to coefficient [4] and the tap coefficient input from enable integrator 541 corresponding to coefficient [5], and outputs the multiplexed result to multiplier 112 at the tap output point corresponding to coefficients [4] and [5]. When multiplexing the tap coefficients, multiplexing unit 543 aligns the tap coefficients with the phase of the input signal to be multiplied.

[0081] FIG. 13 is a timing chart of the adaptive equalizer 5 shown in FIG. 10. If the data stream of the signal input is represented as A1, B1, A2, B2, ..., the output of the delay matching unit 310 is delayed by 8 clocks, as shown in FIG. 13. Also, the data stream of the residual error signal is represented as eAi-j or eBi-j using the input signals of the three tap output points used in the convolution operation of the equalization output used to generate the residual error signal. For example, eA1-3 means the residual error signal of the equalization output obtained by convolution operation of three input signals A1, A2, and A3. Since there is a delay of 3 clocks from the equalization output to the residual error output, the residual error signals at the "0" and "1" input terminals, the "2" and "3" input terminals, and the "4" and "5" input terminals of the selector 745 of the residual error shift selection unit 740 are as shown in FIG. 13. The phase of the free-running counter 640 with respect to the signal input data stream is arbitrary, but if it is the phase shown in Fig. 13, the output of the residual error shift selection unit 740 will be as shown in Fig. 13. If the data stream of correlation values ​​is represented as c1, c2, ..., c5 is the correlation value between the input signal A3 and the residual error signal eA3-5, and the relationship between the correlated input signal and the residual error signal is correct. Below, c6 is the correlation value between the input signal B3 and the residual error signal eB3-5, c7 is the correlation value between the input signal A4 and the residual error signal eA3-5, c8 is the correlation value between the input signal B4 and the residual error signal eB3-5, c9 is the correlation value between the input signal A5 and the residual error signal eA3-5, and c10 is the correlation value between the input signal B5 and the residual error signal eB3-5, and the relationship between the input signal and the residual error signal is correct for these correlation values ​​as well. If the value of the multiplexed coefficient [0] [1] is ki, the value k5 calculated from the integrated value c5 of the coefficient [0] is multiplexed three times in accordance with the phase of the input signal A multiplied by the coefficient [0], and the value k6 calculated from the integrated value c6 of the coefficient [1] is multiplexed three times in accordance with the phase of the input signal B multiplied by the coefficient [1]. Note that the timing chart of Fig. 13 shows the multiplexing timing for selecting the data stream A when the value of the free-running counter 640 is an odd number. Also, the timing chart of Fig. 13 uses the enable integrator 541 without a leak function, and the integrated value is not updated during the non-enabled time period.

[0082] As described above, the adaptive equalizer 5 according to this embodiment includes the convolution integrator 110, the error calculator 200, the free-running counter 640, the residual error shift selector 740, the delay matching unit 310, the correlation multiplier 410, and the integrator 540. The convolution integrator 110 inputs a multiplexed input signal obtained by multiplexing a first input signal (data stream A) and a second input signal (data stream B) to a delay line having a plurality of tap output points, and alternately performs a process of calculating and outputting an equalized signal of the first input signal by taking the sum of results of multiplying the first input signal at each tap output point by the tap coefficient of the first input signal corresponding to each tap output point at the timing when the first input signal appears at each tap output point, and a process of calculating and outputting an equalized signal of the second input signal by taking the sum of results of multiplying the second input signal at each tap output point by the tap coefficient of the second input signal corresponding to each tap output point at the timing when the second input signal appears at each tap output point. The error calculation unit 200 alternately performs a process of calculating and outputting an error signal of a first input signal, which is a difference between an equalization signal of a first input signal and a reference signal, and a process of calculating and outputting an error signal of a second input signal, which is a difference between an equalization signal of a second input signal and a reference signal. The free-running counter 640 repeats counting from an initial count value to an overflow at a final count value with a constant period nT according to a clock with a period T. The residual error shift selection unit 740 alternately performs a process of sequentially delaying the error signal of the first input signal calculated by the error calculation unit 200 by a predetermined delay time, selecting and outputting an error signal of the first input signal with a delay amount according to the count value of the free-running counter 640, and a process of sequentially delaying the error signal of the second input signal calculated by the error calculation unit 200 by a predetermined delay time, selecting and outputting an error signal of the second input signal with a delay amount according to the count value of the free-running counter 640. The delay matching unit 310 delays the input signal at the tap output point with the maximum delay by the same amount as the delay difference between when the equalized signal is output by the convolution integrator 110 and when the error calculator 200 outputs the error signal, and then outputs the delayed signal.The correlation multiplication unit 410 alternately performs a process of calculating and outputting a correlation value of the first input signal from the error signal of the first input signal output from the residual error shift selection unit 740 and the first input signal output from the delay matching unit 310, and a process of calculating and outputting a correlation value of the second input signal from the error signal of the second input signal output from the residual error shift selection unit 740 and the second input signal output from the delay matching unit 310. The accumulator 540 accumulates the correlation value of the first input signal output from the correlation multiplication unit 410 for each timing according to the count value to generate a tap coefficient of the first input signal corresponding to the tap output point according to the count value. The accumulator 540 also accumulates the correlation value of the second input signal output from the correlation multiplication unit 410 for each timing according to the count value to generate a tap coefficient of the second input signal corresponding to the tap output point according to the count value. The accumulator 540 then multiplexes the tap coefficient of the first input signal and the tap coefficient of the second input signal for each tap output point and outputs the multiplexed value to the convolution accumulator 110. With this configuration, the adaptive equalizer 5 can generate and output equalized outputs for the first input signal and the second input signal from a multiplexed input signal in which the first input signal and the second input signal are multiplexed. Therefore, the circuit scale can be significantly reduced compared to a configuration in which an equalizer is provided for each of the first and second input signals.

[0083] Although the present invention has been described above with reference to the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. For example, the adaptive equalizer according to the present invention can be applied to an adaptive equalizer provided in a receiving device that receives digital modulated signals other than those modulated by QAM (Quadrature Amplitude Modulation) modulation. [Industrial Applicability]

[0084] The present invention can be used in an equalizer that compensates for transmission line distortion in a receiving device using digital modulation. [Explanation of symbols]

[0085] 1~5 Adaptive Equalizer 6 Multiplex section 7 Separation section 61 Selector 71~73 FF 100 Convolution Accumulation Unit 101, 111 Tapped Delay Lines 102, 112 multiplier 103, 113 Adder 104, 114 FF 105, 115 tap output points 106, 116 tap coefficients 200 Error calculation section 201 Convergence point judgement unit 202 Subtractor 203~207 FF 300 Delay adjustment unit 301 FF 310 Delay Adjustment Unit 311 FF 400, 410, 420, 430 Correlation multiplication section 401, 411, 421, 431 multipliers 500, 510, 520, 530, 540 Integration section 501 Accumulator 511, 521, 531, 541 Enable Accumulators 512, 522, 532, 542 Enable Signal Generator 543 Multiplex section 600, 610, 620, 630, 640 Free-running counter 700, 710 Residual error shift selection section 701-704, 741-744 FF 705, 715, 745 Selector 5011 Adder 5012 FF 5013 Low-order bit rounding unit 5014 Adder 5015 Leak section 5111 Adder 5112 Selector 5113 FF 5114 Low-order bit rounding unit 5115 Selector 5116 Adder 5117 Leak section

Claims

1. a convolution accumulator that calculates and outputs an equalization signal from an input signal and a tap coefficient for each tap output point; an error calculation unit that calculates and outputs an error signal which is a difference between the equalized signal and a reference signal; A free-running counter; an error shift selection unit that sequentially delays the output error signal by a predetermined delay time and selects and outputs an error signal having a delay amount corresponding to a count value of the free-running counter; a delay matching unit that delays an input signal at a tap output point with the maximum delay by a predetermined amount and outputs the delayed signal; a correlation multiplication unit that calculates and outputs a correlation value from the error signal output from the error shift selection unit and the input signal output from the delay matching unit; an integrating unit that integrates the correlation value output from the correlation multiplying unit for each timing according to the count value to generate a tap coefficient for each tap output point and outputs the generated tap coefficient to the convolution integrating unit; An adaptive equalizer comprising:

2. the free-running counter repeats counting from an initial count value to an overflow at a final count value in a constant period nT in accordance with a clock having a period T, the n being the number of count values ​​that the free-running counter can take, and being set to be the same as the number of tap output points of the convolution accumulation unit; 2. The adaptive equalizer of claim 1.

3. the free-running counter repeats counting from an initial count value to an overflow at a final count value in a constant period nT in accordance with a clock having a period T, the n being the number of count values ​​that the free-running counter can take and being set to be greater than the number of tap output points of the convolution accumulator; 2. The adaptive equalizer of claim 1.

4. The tap output points are divided into a plurality of groups, and each group is provided with the free-running counter, the error shift selection unit, the correlation multiplication unit, and the integrating unit.

2. The adaptive equalizer of claim 1.

5. The free-running counter repeats counting from an initial count value to an overflow at a final count value in a constant period nT in accordance with a clock having a period T, the n being the number of count values ​​that the free-running counter can take, and being set to be equal to the number of the tap output points that belong to the same group as the free-running counter.

5. The adaptive equalizer of claim 4.

6. a convolution integrator that calculates and outputs a multiplexed equalization signal obtained by multiplexing an equalization signal of the first input signal and an equalization signal of the second input signal from a multiplexed input signal obtained by multiplexing a first input signal and a second input signal and a multiplexed tap coefficient for each tap output point obtained by multiplexing a tap coefficient of the first input signal and a tap coefficient of the second input signal; an error calculation unit that calculates and outputs an error signal that is a difference between an equalization signal and a reference signal in the multiplexed equalization signal; A free-running counter; an error shift selection unit that sequentially delays the output error signal by a predetermined delay time and selects and outputs an error signal having a delay amount corresponding to a count value of the free-running counter; a delay matching unit that delays an input signal at a tap output point with the maximum delay by a predetermined amount and outputs the delayed signal; a correlation multiplication unit that calculates and outputs a correlation value from the error signal output from the error shift selection unit and the input signal output from the delay matching unit; an integrating unit that integrates the correlation values ​​output from the correlation multiplying unit at each timing according to the count value to generate tap coefficients of a first input signal and a second input signal for each tap output point, multiplexes the tap coefficients, and outputs the multiplexed tap coefficients to the convolution integrating unit; An adaptive equalizer comprising:

7. the integrator includes an enable integrator for each tap coefficient, and the enable integrator updates the tap coefficient by integrating the correlation value output from the correlation multiplication unit at a timing when the count value coincides with a count value set for each enable integrator.

7. An adaptive equalizer according to claim 1 or 6.

8. the enable integrator does not update the integrated value during a period in which the count value does not match a count value set for each enable integrator; 8. The adaptive equalizer of claim 7.

9. the enable integrator gradually decreases the integrated value during a period in which the count value does not match a count value set for each enable integrator; 8. The adaptive equalizer of claim 7.

Images