Semiconductor Device

Abstract

To provide a semiconductor device with the higher voltage withstanding property.SOLUTION: A semiconductor device according to an embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, structures, a gate electrode, and a high resistance part. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. An insulation part of the structure exists beside a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region. A conduction part of the structure includes a portion provided in the insulation part and facing the first semiconductor region. A gate electrode faces the second semiconductor region. The high resistance part has higher electric resistance than the first semiconductor region. The structures are provided along a second direction and a third direction. The structures include first to third structures. The high resistance part overlaps in a first direction with a circle center of a virtual circle passing a center of each of the first structure, the second structure, and the third structure in the second direction and the third direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as vertical metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. There is a demand for improved breakdown voltage for these semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-47742 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a structure, a gate electrode, and a high resistance portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The structure includes an insulating portion and a conductive portion. The insulating portion is aligned with a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region, and in a third direction perpendicular to the first direction and intersecting the second direction. The conductive portion is provided in the insulating portion and has a portion facing the first semiconductor region in the second direction and the third direction. The gate electrode faces the second semiconductor region in the second direction and the third direction. The high resistance portion is provided in the first semiconductor region and has a higher electrical resistance than the first semiconductor region. A plurality of the structures are provided along the second direction and the third direction. The plurality of structures include the first structure, a second structure, and a third structure. The second structure is adjacent to the first structure in the second direction. The third structure is adjacent to the first structure in the third direction. The high resistance portion overlaps in the first direction with a center of a virtual circle passing through centers of the first structure, the second structure, and the third structure in the second direction and the third direction. [Brief description of the drawings]

[0006] [Figure 1] 1 is a plan view illustrating a portion of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Diagram 3] FIG. 11 is a plan view illustrating a portion of a semiconductor device according to a second embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The symbols p and p indicate the relative level of each impurity concentration. That is, a symbol with a "+" indicates a relatively higher impurity concentration than a symbol without either a "+" or a "-" and a symbol with a "-" indicates a relatively lower impurity concentration than a symbol without either. When both an acceptor impurity and a donor impurity are included in each region, these symbols indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] (First embodiment) FIG. 1 is a plan view showing a part of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II of FIG. The semiconductor device 100 according to the first embodiment is, for example, a vertical MOSFET. The semiconductor device 100 is a so-called dot structure MOSFET.

[0009] As shown in FIG. 1 and FIG. 2, the semiconductor device 100 has n - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + Source region 3 (third semiconductor region), n + The semiconductor device includes a drain region 5, a gate electrode 10, a structure 20, and a high resistance portion 30.

[0010] In the following description of each embodiment, a first direction D1, a second direction D2, and a third direction D3 are used. - The direction from the n-type drift region 1 toward the p-type base region 2 is defined as a first direction D1. A direction perpendicular to the first direction D1 is defined as a second direction D2. A direction perpendicular to the first direction D1 and intersecting with the second direction D2 is defined as a third direction D3. - The direction from the p-type drift region 1 to the p-type base region 2 is called "up" and the opposite direction is called "down". - The positional relationship between the p-type drift region 1 and the p-type base region 2 is based on the relative positions thereof and is independent of the direction of gravity.

[0011] As shown in FIG. 1 and FIG. 2, the semiconductor device 100 has a lower portion including n + A drain region 5 is provided. + Above the drain region 5, there is an n - A drift region 1 is provided. - A p-type base region 2 is provided on the n-type drift region 1. + A source region 3 is optionally provided.

[0012] The structure 20 includes an insulating portion 21 and a conductive portion 22. The insulating portion 21 has a length of n - A part of the p-type drift region 1, the p-type base region 2, and the n + The conductive portion 22 is disposed in the insulating portion 21. At least a portion of the conductive portion 22 is aligned with the n-type source region 3 in the second direction D2 and the third direction D3. - A part of the conductive portion 22 is aligned with a part of the p-type drift region 1. A part of the conductive portion 22 is aligned with the p-type base region 2 and the n-type drift region 1 in the second direction D2 and the third direction D3. + It may further be aligned with the source region 3 .

[0013] In the semiconductor device 100, the gate electrode 10 is also provided in the insulating portion 21. The gate electrode 10 is provided around an upper portion of the conductive portion 22 in the second direction D2 and the third direction D3. A part of the insulating portion 21 is provided between the gate electrode 10 and the conductive portion 22. As a result, the gate electrode 10 and the conductive portion 22 are electrically isolated from each other.

[0014] The gate electrode 10 faces the p-type base region 2 via the gate insulating layer 11 in the second direction D2 and the third direction D3. - Drift region 1 and n + It may further face the source region 3. In the semiconductor device 100, a part of the insulating portion 21 functions as the gate insulating layer 11.

[0015] The high resistance portion 30 is - In this example, the high resistance portion 30 is provided in the n-type drift region 1. - In the p-type drift region 1, in the p-type base region 2, and in the n + The high resistance portion 30 is provided in the source region 3. The high resistance portion 30 does not overlap with the structure 20 in the first direction D1. The electrical resistance of the high resistance portion 30 is n - The electrical resistance of the drift region 1 is higher than that of the

[0016] n - The drift region 1 is n + The n-type drain region 5 is electrically connected to the drain electrode 41. The drain electrode 41 is, for example, + The gate electrode 1 is provided below the drain region 5 .

[0017] p-type base region 2 and n + The p-type source region 3 is electrically connected to a source electrode 42. The conductive portion 22 is electrically connected to the source electrode 42. The source electrode 42 is, for example, + A source region 3 , a gate electrode 10 and a structure 20 are provided above the source region 3 .

[0018] The gate electrode 10 is electrically connected to a gate pad 43. The gate pad 43 is electrically isolated from the source electrode .

[0019] 1, in the semiconductor device 100, the conductive portion 22 has a regular hexagonal prism shape. When viewed from the first direction D1, the gate electrode 10 surrounds the conductive portion 22. The gate electrode 10 has a regular hexagonal cylindrical shape. The outer surface of the structure 20 has a regular hexagonal prism shape. When viewed from the first direction D1, the structure 20 has a hexagonal shape. The structure 20 has a hexagonal shape. The cross-sectional shape of the structure 20 in a plane along the second direction D2 and the third direction D3 is a hexagon.

[0020] 1, the gate electrodes 10 and the structures 20 are provided in a plurality of units along the second direction D2 and the third direction D3. + A p-type source region 3 is provided around the structure 20. A p-type base region 2 and an n-type + The source region 3 is disposed between the structures 20 and surrounds each of the structures 20 .

[0021] The multiple structures 20 aligned along the second direction D2 and the third direction D3 include a first structure 20a, a second structure 20b, and a third structure 20c. The first structure 20a is one of the multiple structures 20. The second structure 20b is adjacent to the first structure 20a in the second direction D2. The third structure 20c is adjacent to the first structure 20a in the third direction D3. In this example, the angle between the second direction D2 and the third direction D3 is 60 degrees.

[0022] In FIG. 1, the first center C1 represents the center of the first structure 20a in the second direction D2 and the third direction D3. The second center C2 represents the center of the second structure 20b in the second direction D2 and the third direction D3. The third center C3 represents the center of the third structure 20c in the second direction D2 and the third direction D3. Here, consider a virtual circle IC1 passing through the first center C1, the second center C2, and the third center C3. In the semiconductor device 100, the first center C1, the second center C2, and the third center C3 exist on the circumference of one virtual circle IC1. The distance between the center C0 and the first center C1 of the virtual circle IC1 is equal to the distance between the center C0 and the second center C2, and the distance between the center C0 and the third center C3, respectively.

[0023] The angle between the first line direction LD1 connecting the circle center C0 and the first center C1 and the second line direction LD2 connecting the circle center C0 and the second center C2 is 120 degrees. The angle between the first line direction LD1 and the third line direction LD3 connecting the circle center C0 and the third center C3 is 120 degrees. The angle between the second line direction LD2 and the third line direction LD3 is 120 degrees. That is, in this example, the triangle formed by connecting the first center C1, the second center C2, and the third center C3 is an equilateral triangle. In other words, in this example, the first structure 20a, the second structure 20b, and the third structure 20c are arranged in an equilateral triangle when viewed along the first direction D1.

[0024] The distance between the first center C1 and the second center C2 is equal to the distance between the first center C1 and the third center C3, and the distance between the second center C2 and the third center C3. That is, the first structure 20a, the second structure 20b, and the third structure 20c are arranged at regular intervals in the second direction D2 and the third direction D3. For example, if the distance between the first center C1 and the second center C2 is P1 and the width of the first structure 20a (second structure 20b) in the second direction D2 is W1, the distance L1 between the first structure 20a and the second structure 20b is expressed as L1=P1-W1.

[0025] The high resistance section 30 is provided at a position overlapping with the center C0 in the first direction D1. In this example, the cross-sectional shape of the high resistance section 30 in a plane along the second direction D2 and the third direction D3 is an equilateral triangle centered on the center C0. This equilateral triangle faces the opposite side to the equilateral triangle formed by connecting the first center C1, the second center C2, and the third center C3. The length of one side of this equilateral triangle is, for example, equal to or less than the distance L1.

[0026] The high resistance portion 30 may be provided in the entire area between adjacent structures 20, or may be provided only in a portion between adjacent structures 20. In other words, for example, the high resistance portion 30 may not be provided between another structure adjacent to the first structure 20a and the second structure 20b, and between the first structure 20a and the second structure 20b.

[0027] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 31 relative to the source electrode 32, a voltage equal to or greater than the threshold is applied to the gate electrode 10. As a result, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 enters an ON state. Electrons flow through the channel from the source electrode 32 to the drain electrode 31. Thereafter, when the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 enters an OFF state.

[0028] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 41 with respect to the source electrode 42 increases. - The potential difference between the n-type drift region 1 and the conductive portion 22 increases. - From the interface with drift region 1, n - The depletion layer spreads toward the n-type drift region 1. That is, the conductive portion 22 functions as an FP (field plate) electrode. The depletion layer reaches the high resistance portion 30. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage of the semiconductor device 100. -By increasing the concentration of impurities that act as donors in the drift region 1, the on-resistance of the semiconductor device 100 can be reduced.

[0029] An example of the material of each component of the semiconductor device 100 will be described. n - p-type drift region 1, p-type base region 2, n + shaped source region 3, and n + The semiconductor material of the drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, the donor impurity may be arsenic, phosphorus, or antimony. The acceptor impurity may be boron.

[0030] The gate electrode 10 and the conductive portion 22 include a conductive material such as polysilicon. The conductive material may be doped with impurities. The insulating portion 21 includes an insulating material. For example, the insulating portion 21 includes silicon oxide or silicon nitride. The drain electrode 41 and the source electrode 42 include a metal such as aluminum or copper.

[0031] The high resistance portion 30 includes, for example, an insulating material. More specifically, the high resistance portion 30 includes, for example, at least one of silicon oxide and silicon nitride. Alternatively, the high resistance portion 30 includes, for example, a semiconductor material. More specifically, the high resistance portion 30 includes, for example, at least one of silicon and silicon germanium. When the high resistance portion 30 includes a semiconductor material, the concentration of impurities included in the high resistance portion 30 is n - The concentration of impurities is lower than the concentration of impurities contained in the drift region 1. The high resistance portion 30 preferably has, for example, a tensile stress along the first direction D1.

[0032] The effects of the semiconductor device 100 according to the first embodiment will be described. In a dot-type structure in which a plurality of structures 20 are provided along the second direction D2 and the third direction D3, for example, the symmetry of the extension of the depletion layer, which is ensured in a stripe-type structure in which the structures extend along the third direction D3, is lost, and a region that is difficult to deplete is generated between adjacent structures 20. If the voltage is further increased to deplete this region, there is a problem that the electric field strength increases and the breakdown voltage decreases.

[0033] According to the semiconductor device 100 of the first embodiment, by providing the high resistance portion 30 in a region that is difficult to be depleted, it is possible to suppress a decrease in breakdown voltage caused by a region that is not depleted. In addition, by providing the high resistance portion 30 having a tensile stress along the first direction D1, - A tensile strain can be generated along the first direction D1 in the drift region 1. This generates a tensile strain along the first direction D1 in which carriers flow, thereby improving the mobility of carriers and reducing the on-resistance.

[0034] Furthermore, when the first structure 20a, the second structure 20b, and the third structure 20c are arranged in an equilateral triangle when viewed along the first direction D1, the cross-sectional shape of the high resistance section 30 in a plane along the second direction D2 and the third direction D3 can be made to be an equilateral triangle centered on the center C0, thereby more effectively suppressing the decrease in breakdown voltage.

[0035] Furthermore, by making the high resistance portion 30 contain an insulating material (for example, at least one of silicon oxide and silicon nitride), the decrease in the withstand voltage can be more effectively suppressed.

[0036] Furthermore, by making the high resistance portion 30 contain a semiconductor material with a low impurity concentration (for example, at least one of silicon and silicon germanium), it is possible to more effectively suppress a decrease in the breakdown voltage.

[0037] Second embodiment FIG. 3 is a plan view illustrating a portion of the semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. The semiconductor device 200 according to the second embodiment is, for example, a vertical MOSFET. The semiconductor device 200 is a so-called dot structure MOSFET.

[0038] As shown in FIGS. 3 and 4, the semiconductor device 200 has n - p-type drift region 1, p-type base region 2, n + Shape source region 3, n + The semiconductor device includes a drain region 5, a gate electrode 10, a structure 20, and a high resistance portion 30.

[0039] 3, in the semiconductor device 200, the conductive portion 22 has a shape of a regular square prism. Moreover, when viewed from the first direction D1, the gate electrode 10 surrounds the conductive portion 22. Moreover, the shape of the gate electrode 10 is a regular square cylinder. Moreover, the shape of the outer surface of the structure 20 is a regular square prism. The shape of the structure 20 is a rectangle when viewed along the first direction D1. The cross-sectional shape of the structure 20 in a plane along the second direction D2 and the third direction D3 is a rectangle.

[0040] The multiple structures 20 aligned along the second direction D2 and the third direction D3 include a first structure 20a, a second structure 20b, a third structure 20c, and a fourth structure 20d. The first structure 20a is one of the multiple structures 20. The second structure 20b is adjacent to the first structure 20a in the second direction D2. The third structure 20c is adjacent to the first structure 20a in the third direction D3. The fourth structure 20d is adjacent to the third structure 20c in the second direction D2 and adjacent to the second structure 20b in the third direction D3. In this example, the angle between the second direction D2 and the third direction D3 is 90 degrees.

[0041] In FIG. 3, the first center C11 represents the center of the first structure 20a in the second direction D2 and the third direction D3. The second center C12 represents the center of the second structure 20b in the second direction D2 and the third direction D3. The third center C13 represents the center of the third structure 20c in the second direction D2 and the third direction D3. The fourth center C14 represents the center of the fourth structure 20d in the second direction D2 and the third direction D3. Here, consider a virtual circle IC2 that passes through the first center C11, the second center C12, the third center C13, and the fourth center C14. In the semiconductor device 200, the first center C11, the second center C12, the third center C13, and the fourth center C14 exist on the circumference of one virtual circle IC2. The distance between the center C10 of the imaginary circle IC2 and the first center C12 is equal to the distance between the center C10 and the second center C12, the distance between the center C10 and the third center C13, and the distance between the center C10 and the fourth center C14.

[0042] The angle between the first line direction LD11 connecting the circle center C10 and the first center C11 and the second line direction LD12 connecting the circle center C10 and the second center C12 is 90 degrees. The angle between the first line direction LD11 and the third line direction LD13 connecting the circle center C10 and the third center C13 is 90 degrees. The angle between the second line direction LD12 and the fourth line direction LD14 connecting the circle center C10 and the fourth center C14 is 90 degrees. The angle between the third line direction LD13 and the fourth line direction LD14 is 90 degrees. That is, in this example, the quadrangle formed by connecting the first center C11, the second center C12, the third center C13, and the fourth center C14 is a square. In other words, in this example, the first structure 20a, the second structure 20b, the third structure 20c, and the fourth structure 20d are arranged in a square when viewed along the first direction D1.

[0043] The distance between the first center C11 and the second center C12 is equal to the distance between the first center C11 and the third center C13, the distance between the second center C12 and the fourth center C14, and the distance between the third center C13 and the fourth center C14. That is, the first structure 20a, the second structure 20b, the third structure 20c, and the fourth structure 20d are arranged at regular intervals in the second direction D2 and the third direction D3. For example, if the distance between the first center C11 and the second center C12 is P2 and the width of the first structure 20a (second structure 20b) in the second direction D2 is W2, the distance L2 between the first structure 20a and the second structure 20b is expressed as L2=P2-W2. Moreover, the distance L3 between the first structure 20a and the fourth structure 20d is expressed as L3=(√2)×(P2-W2).

[0044] The high resistance portion 30 is provided at a position overlapping the center C10 in the first direction D1. In this example, the cross-sectional shape of the high resistance portion 30 in a plane along the second direction D2 and the third direction D3 is a cross shape centered on the center C10 and extending in the second direction D2 and the third direction D3. The length of the cross shape in the second direction D2 is, for example, equal to or greater than the distance L2. The length of the cross shape in the third direction D3 is, for example, equal to or greater than the distance L2. That is, the high resistance portion 30 is located between the first structure 20a and the third structure 20c in the third direction D3. The high resistance portion 30 is also located between the second structure 20b and the fourth structure 20d in the third direction D3. The high resistance portion 30 is also located between the first structure 20a and the second structure 20b in the second direction D2. Moreover, the high resistance portion 30 is located between the third structure 20c and the fourth structure 20d in the second direction D2. The length of the cross-shaped first structure 20a in the direction connecting the fourth structure 20d is, for example, equal to or less than the distance L3.

[0045] In the semiconductor device 200 as well, the high resistance portion 30 may be provided entirely between adjacent structures 20, or may be provided only partially between adjacent structures 20.

[0046] In the semiconductor device 200 according to the second embodiment, by providing the high resistance portion 30 in a region that is difficult to be depleted, it is possible to suppress a decrease in the breakdown voltage caused by a region that is not depleted. - A tensile strain can be generated along the first direction D1 in the drift region 1. This generates a tensile strain along the first direction D1 in which carriers flow, thereby improving the mobility of carriers and reducing the on-resistance.

[0047] Furthermore, when the first structure 20a, the second structure 20b, the third structure 20c, and the fourth structure 20d are arranged in a square when viewed along the first direction D1, the cross-sectional shape of the high resistance section 30 in a plane along the second direction D2 and the third direction D3 can be made to be a cross shape centered on the center C10 and extending in the second direction D2 and the third direction D3, thereby more effectively suppressing the decrease in the breakdown voltage.

[0048] As described above, according to the embodiment, a semiconductor device capable of improving the breakdown voltage is provided.

[0049] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0050] 1n - 1 p-type drift region, 2 p-type base region, 3 n + Shape source area, 5 n +shaped drain region, 10 gate electrode, 11 gate insulating layer, 20 structure, 20a first structure, 20b second structure, 20c third structure, 20d fourth structure, 21 insulating portion, 22 conductive portion, 30 high resistance portion, 41 drain electrode, 42 source electrode, 43 gate pad, 100, 200 semiconductor device, C0, C10 circle center, C1, C11 first center, C2, C12 second center, C3, C13 third center, C14 fourth center, D1 first direction, D2 second direction, D3 third direction, IC1, IC2 virtual circle, LD1, LD11 first line direction, LD2, LD12 second line direction, LD3, LD13 third line direction, LD14 fourth line direction

Claims

1. a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; an insulating portion aligned with a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region, and in a third direction perpendicular to the first direction and intersecting the second direction; a conductive portion provided in the insulating portion and having a portion facing the first semiconductor region in the second direction and the third direction; A structure having a gate electrode facing the second semiconductor region in the second direction and the third direction; a high resistance portion provided in the first semiconductor region and having an electrical resistance higher than that of the first semiconductor region; Equipped with The structure is provided in a plurality of parts along the second direction and the third direction, the plurality of structures include a first structure, a second structure adjacent to the first structure in the second direction, and a third structure adjacent to the first structure in the third direction, the high resistance portion overlaps in the first direction with a center of a virtual circle passing through centers of the first structure, the second structure, and the third structure in the second direction and the third direction, the first structure, the second structure, and the third structure are arranged in an equilateral triangle when viewed along the first direction, a cross-sectional shape of the high resistance portion in a plane along the second direction and the third direction is an equilateral triangle with the center of the circle as its center.

2. The semiconductor device according to claim 1 , wherein the shape of said structure is a hexagon when viewed along said first direction.

3. the plurality of structures further include a fourth structure adjacent to the third structure in the second direction and adjacent to the second structure in the third direction; the first structure, the second structure, the third structure, and the fourth structure are arranged in a square shape when viewed along the first direction, 2 . The semiconductor device according to claim 1 , wherein a cross-sectional shape of said high resistance portion in a plane along said second direction and said third direction is a cross shape centered on said center of the circle and extending in said second direction and said third direction.

4. The semiconductor device according to claim 3 , wherein the shape of the structure is a rectangle when viewed in the first direction.

5. 5. The semiconductor device according to claim 1, wherein the high resistance portion includes an insulating material.

6. 6. The semiconductor device according to claim 5, wherein said high resistance portion includes at least one of silicon oxide and silicon nitride.

7. the high resistance portion includes a semiconductor material; 5. The semiconductor device according to claim 1, wherein a concentration of an impurity contained in said high resistance portion is lower than a concentration of an impurity contained in said first semiconductor region.

8. 8. The semiconductor device according to claim 7, wherein said high resistance portion includes at least one of silicon and silicon germanium.

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