Light emitting diode chip structure having reflective elements - Patents.com

Abstract

A light-emitting diode (LED) chip structure having a cup-shaped reflective element is provided. The LED chip structure includes a substrate, an isolation element, and a mesa including an LED surrounded by the isolation element. The isolation element includes an upper isolation portion and a lower isolation portion. The lower isolation portion is disposed within the substrate, and the upper isolation portion protrudes from the surface of the substrate. A reflective layer is disposed on a sidewall of the upper isolation portion, and the lower portion of the reflective layer does not contact the mesa. The cup-shaped reflective element includes at least the isolation element having the reflective layer.

Description

[Technical field]

[0001] Related Applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 013,370, filed April 21, 2020, and entitled "LIGHT-EMITTING DIODE CHIP STRUCTURES WITH REFLECTIVE ELEMENTS," which is incorporated herein by reference.

[0002] Technical Field This disclosure relates generally to light emitting diode (LED) display devices, and more particularly to LED chip structures having one or more reflective elements. [Background technology]

[0003] background

[0003] With the recent development of mini-LED and micro-LED technology, consumer devices and applications such as augmented reality (AR), projection, head-up display (HUD), mobile device display, wearable device display, and automotive display require LED panels with improved resolution and brightness. LEDs can be miniaturized and act as pixel emitters in display systems, for example in micro-display systems. When trying to achieve better resolution and brightness on small displays, it can be difficult to meet both resolution and brightness requirements. That is, pixel resolution and brightness can be difficult to balance at the same time because they can have an inverse relationship. For example, obtaining high brightness for each pixel can cause low resolution. On the other hand, obtaining high resolution can reduce brightness.

[0004]

[0004] Furthermore, the light emitted by the micro LED may be generated by spontaneous emission, and thus may not be directional, resulting in a large divergence angle. The large divergence angle may cause various problems in the micro LED display. On the one hand, the large divergence angle may allow only a small portion of the light emitted by the micro LED to be utilized. This may significantly reduce the efficiency and brightness of the micro LED display system. On the other hand, the large divergence angle may cause the light emitted by one micro LED pixel to illuminate its neighboring pixels, resulting in optical crosstalk between pixels, loss of clarity, and loss of contrast. Conventional solutions to reduce the large divergence angle may not be able to effectively handle the light emitted from the micro LED as a whole, and may only utilize the central portion of the light emitted from the micro LED, leaving the remaining portion of the light emitted at more oblique angles unused.

[0005]

[0005] As a result, it would be desirable to provide an LED structure for a display device that, among other things, addresses the above-mentioned shortcomings. Summary of the Invention [Means for solving the problem]

[0006] overview

[0006] Exemplary embodiments of the present disclosure are directed to an LED chip structure having one or more reflective elements, hi some embodiments, the reflective element is a cup-shaped structure that surrounds the LED pixel unit.

[0007]

[0007] An exemplary embodiment of the LED chip structure in the present disclosure includes an isolation element including an upper isolation portion and a lower isolation portion. The exemplary embodiment also includes a reflective layer disposed directly or indirectly on the upper isolation portion. The isolation element can reduce the divergence of light emitted from the mesa including the LED pixel unit and reduce optical crosstalk between adjacent pixels. For example, the isolation element and the reflective layer can utilize light from an oblique angle. In this way, a higher efficiency can be achieved in collecting and focusing this light to obtain a brighter and more power-efficient display than conventional solutions. In addition, the isolation element can block the light emitted from the LED in the adjacent pixel, which can effectively suppress the crosstalk between the pixels and improve the color contrast and sharpness. The exemplary embodiment of the present disclosure can improve the brightness and contrast of the projection, thereby reducing the power consumption in the projection application. The exemplary embodiment of the present disclosure can also improve the directionality of the light emission of the display, thereby providing the user with better image quality in direct-view applications and protecting the user's privacy.

[0008]

[0008] The exemplary embodiments of the present disclosure can provide multiple advantages. One advantage is that the exemplary embodiments of the present disclosure can suppress optical crosstalk between pixels and enhance brightness. For example, pitch refers to the distance between the centers of adjacent pixels on a display panel. The pitch can vary from about 40 microns to about 20 microns, about 10 microns, and / or about 5 microns or less. When the pitch specification is determined, a single pixel area is fixed. The exemplary embodiments of the present disclosure can suppress optical crosstalk between pixels at a smaller pitch while increasing the brightness within a single pixel in a power-efficient manner. Another advantage is that the exemplary embodiments of the present disclosure can directly bond light-emitting diodes onto a substrate with a pixel driver without introducing an intermediate substrate, which can improve heat dissipation and therefore enhance the reliability and performance of the LED chip.

[0009]

[0009] Accordingly, the present disclosure includes, without limitation, the following exemplary embodiments.

[0010]

[0010] Some exemplary embodiments provide a first LED chip structure. The first LED chip structure includes a substrate and an isolation element. The isolation element includes an upper isolation portion and a lower isolation portion. The lower isolation portion is disposed within the substrate, and the upper isolation portion protrudes from a surface of the substrate. The first LED chip structure also includes a reflective layer disposed on a sidewall of the upper isolation portion. The first LED chip structure further includes a mesa including an LED component surrounded by the isolation element, and a lower portion of the reflective layer does not contact the mesa.

[0011] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the substrate includes a semiconductor wafer and a bonding metal layer on the semiconductor wafer.

[0012]

[0012] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, a reflective layer is disposed on the sidewalls and top surface of the upper isolation portion, and a lower portion of the reflective layer extends in a direction from the isolation element to the mesa.

[0013]

[0013] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the first LED chip structure further includes a dielectric layer disposed on a lower portion of the sidewall of the mesa, the dielectric layer being covered by a lower portion of the reflective layer.

[0014]

[0014] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the height of the upper isolation portion is greater than the height of the lower isolation portion.

[0015]

[0015] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, a bottom width of the top isolation portion is greater than or equal to a top width of the bottom isolation portion.

[0016]

[0016] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the lower width of the upper isolation portion is longer than the upper width of the lower isolation portion and shorter than twice the upper width of the lower isolation portion, and two protrusions are formed at each lower end of the upper isolation portion, and the width of each of the two protrusions is less than half the upper width of the lower isolation portion.

[0017] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, when viewed from the side, the cross section of the upper isolation portion is trapezoidal, the cross section of the lower isolation portion is inverted trapezoidal, and the lower portion of the upper isolation portion covers the upper portion of the lower isolation portion. In some embodiments, the lower area of ​​the upper isolation portion exceeds the upper area of ​​the lower isolation portion.

[0018] In some example embodiments of the first LED chip structure or any combination of the preceding example embodiments, the upper isolation portion and the lower isolation portion are axisymmetric and coaxial.

[0019]

[0019] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the height of the upper isolation portion relative to the surface of the substrate is greater than the height of the mesa, and the inclination angle of the sidewall of the upper isolation portion relative to an axis perpendicular to the surface of the substrate is greater than the inclination angle of the sidewall of the mesa.

[0020]

[0020] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the mesa sidewall has a slope angle less than 45° and the upper isolated portion has a slope angle greater than 45°.

[0021]

[0021] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, a dielectric layer covers the top surface and sidewalls of the mesa, and the top surface of the mesa includes areas that are not covered by the dielectric layer or that are free of the dielectric layer.

[0022] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the dielectric layer is transparent to the light emitted from the first LED chip structure.

[0023]

[0023] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the dielectric layer includes one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer.

[0024]

[0024] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the silicon-containing dielectric layer comprises an oxide or nitride of silicon, the aluminum-containing dielectric layer comprises an oxide of aluminum, and the titanium-containing dielectric layer comprises an oxide of titanium.

[0025]

[0025] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the oxide of titanium is Ti3O5.

[0026] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the reflective layer includes a multi-layer structure.

[0027] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the multi-layer structure includes a stack of one or more reflective material layers and one or more dielectric material layers.

[0028] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the reflective layer includes one or more metallic conductive materials having a high reflectivity. In some embodiments, the high reflectivity is greater than 70%. In some embodiments, the high reflectivity is greater than 80%. In some embodiments, the high reflectivity is greater than 90%.

[0029] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the one or more metallic conductive materials include one or more of aluminum, gold, or silver.

[0030] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the top surface and sidewall of the mesa and the top surface and sidewall of the upper isolation portion are fully or partially covered by the conductive layer. In some embodiments, the conductive layer is continuous.

[0031] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the conductive layer is transparent to light emitted from the first LED chip structure.

[0032] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the isolation element includes a photosensitive dielectric material.

[0033] In some exemplary embodiments of the first LED chip structure or any combination of the preceding exemplary embodiments, the photosensitive dielectric material is SU-8 or photosensitive polyimide (PSPI).

[0034]

[0034] Another exemplary embodiment provides a second LED chip structure. The second LED chip structure includes a substrate, an isolation element, a mesa, a dielectric layer, and a conductive layer. The isolation element includes an upper isolation portion and a lower isolation portion. The lower isolation portion is disposed in the substrate, and the upper isolation portion protrudes from the surface of the substrate. The mesa including the LED component is surrounded by the isolation element. The dielectric layer covers the top surface and the sidewall of the mesa, and the top surface of the mesa further includes an area not covered by the dielectric layer, for example an area without the dielectric layer. A conductive layer covers the dielectric layer, the top surface of the mesa having the area without the dielectric layer, and at least the sidewall of the upper isolation portion. A reflective layer is disposed at least on the conductive layer covering the sidewall of the upper isolation portion, and a lower portion of the reflective layer does not contact the mesa.

[0035] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the substrate includes a semiconductor wafer and a bonding metal layer on the semiconductor wafer.

[0036]

[0036] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, a conductive layer is disposed on the upper surface and sidewall of the upper isolation portion, a reflective layer is disposed on the conductive layer disposed on the upper surface and sidewall of the upper isolation portion, and a lower portion of the reflective layer extends from the isolation element to the mesa.

[0037]

[0037] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the height of the upper isolation portion is greater than the height of the lower isolation portion.

[0038]

[0038] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the bottom width of the upper isolation portion is greater than or equal to the top width of the lower isolation portion.

[0039]

[0039] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the lower width of the upper isolation portion is longer than the upper width of the lower isolation portion and shorter than twice the upper width of the lower isolation portion, and two protrusions are formed at each lower end of the upper isolation portion, and the width of each of the two protrusions is less than half the upper width of the lower isolation portion.

[0040] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, when viewed from the side, the cross section of the upper isolation portion is trapezoidal, the cross section of the lower isolation portion is inverted trapezoidal, and the lower portion of the upper isolation portion covers the upper portion of the lower isolation portion. In some embodiments, the lower area of ​​the upper isolation portion exceeds the upper area of ​​the lower isolation portion.

[0041] In some example embodiments of the second LED chip structure or any combination of the preceding example embodiments, the upper isolation portion and the lower isolation portion are axisymmetric and coaxial.

[0042]

[0042] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the height of the upper isolation portion relative to the surface of the substrate is greater than the height of the mesa, and the inclination angle of the sidewall of the upper isolation portion relative to an axis perpendicular to the surface of the substrate is greater than the inclination angle of the sidewall of the mesa.

[0043]

[0043] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the slope angle of the sidewall of the mesa is less than 45° and the slope angle of the sidewall of the upper isolation portion is greater than 45°. nothing.

[0044] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the dielectric layer is transparent to the light emitted from the second LED chip structure.

[0045]

[0045] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the dielectric layer includes one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer.

[0046]

[0046] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the silicon-containing dielectric layer comprises an oxide or nitride of silicon, the aluminum-containing dielectric layer comprises an oxide of aluminum, and the titanium-containing dielectric layer comprises an oxide of titanium.

[0047]

[0047] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the oxide of titanium is Ti3O5.

[0048] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the reflective layer includes a multi-layer structure.

[0049] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the multi-layer structure includes a stack of one or more reflective material layers and one or more dielectric material layers.

[0050] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the reflective layer includes one or more metallic conductive materials having high reflectivity. In some embodiments, the high reflectivity is greater than 70%. In some embodiments, the high reflectivity is greater than 80%. In some embodiments, the high reflectivity is greater than 90%.

[0051] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the one or more metallic conductive materials include one or more of aluminum, gold, or silver.

[0052] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the conductive layer is transparent to the light emitted from the second LED chip structure.

[0053] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the isolation element includes a photosensitive dielectric material.

[0054] In some exemplary embodiments of the second LED chip structure or any combination of the preceding exemplary embodiments, the photosensitive dielectric material is SU-8 or photosensitive polyimide (PSPI).

[0055]

[0055] These and other features, aspects, and advantages of the present disclosure will become apparent upon reading the following detailed description together with the accompanying drawings, which are briefly described below. The present disclosure includes any combination of two or more features or elements described in the present disclosure, regardless of whether such features or elements are expressly combined or recited in a specific embodiment example described herein. The present disclosure is intended to be read holistically, and therefore any separable features or elements of the present disclosure should be considered combinable in any of its aspects and exemplary embodiments, unless otherwise required by the context of the present disclosure.

[0056]

[0056] Therefore, it is understood that this brief summary is merely provided to summarize some exemplary embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it is understood that the above exemplary embodiments are merely examples and should not be interpreted to narrow the scope or spirit of the present disclosure in any way. Other examples of embodiments, aspects, and advantages will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate by way of example the principles of some exemplary embodiments described.

[0057] BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order that the present disclosure may be more fully understood, a more particular description may be had by reference to the features of the various embodiments, some of which are illustrated in the accompanying drawings, which are merely illustrative of the relevant features of the present disclosure and therefore should not be considered limiting, as the present description may admit of other useful features. [Brief description of the drawings]

[0058] [Figure 1]

[0058] A top view of an LED chip structure according to some example embodiments is shown. [Diagram 2]

[0059] 1 illustrates a cross-sectional view of an LED chip structure according to some exemplary embodiments. [Diagram 3]

[0060] 1 illustrates a cross-sectional view of another LED chip structure according to some exemplary embodiments. [Figure 4]

[0061] 1 illustrates a cross-sectional view of a reflective layer having a multi-layer structure, according to some example embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059]

[0062] According to common practice, the various features illustrated may not be drawn to scale. Accordingly, dimensions of various features may be arbitrarily increased or decreased for clarity. In addition, some of the drawings may not depict all of the components of a given system, method, or apparatus. Finally, like reference numerals may be used to denote like features throughout the specification and drawings.

[0060] Detailed Description

[0063] Some embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, which show some, but not all, embodiments of the present disclosure. Indeed, various embodiments of the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein, but rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. For example, unless otherwise specified, referring to something as first, second, etc. should not be construed to imply a particular order. Furthermore, something may be described as being above something else, but instead (unless otherwise specified) it can be below, and vice versa, and similarly something described as being to the left of something else can instead be to the right, and vice versa. Like reference numbers refer to like elements throughout.

[0061]

[0064] Exemplary embodiments of the present disclosure relate generally to LED display devices, and are specifically directed to an LED chip structure having a reflective layer.

[0062]

[0065] FIG. 1 illustrates a top view of an LED chip structure 100 according to some exemplary embodiments. As illustrated, in some embodiments, the LED chip structure 100 includes one or more mesas 101 (e.g., mesas 101a, 101b, and 101c). Each of the mesas 101 may include an LED or a micro-LED. Each of the mesas 101 has an upper portion and a lower portion. For example, circle 120a may represent the upper portion of mesa 101b, circle 120b may represent the lower portion of mesa 101b, and a surface connecting the upper portion of mesa 101b to the lower portion of mesa 101b, i.e., a sidewall of the mesa, as illustrated in the figure by the space between circle 120a and circle 120b. In some embodiments, the diameter of the upper portion of each of the mesas 101 may be in the range of 1 μm to 8 μm, and the diameter of the lower portion of each of the mesas may be in the range of 3 μm to 10 μm. In some embodiments, the diameter of the top of each mesa 101 may be in the range of 8 μm to 25 μm, and the diameter of the bottom of each mesa may be in the range of 10 μm to 35 μm. The distance between the centers of two adjacent mesas may be in the range of 1 μm to 10 μm. In some embodiments, the distance between the centers of two adjacent mesas may vary from about 40 μm to about 20 μm, to about 10 μm, and / or to about 5 μm or less. The size of the mesas and the distance between the mesas depend on the resolution of the display. For example, for a 5000 pixels per inch (PPI) display panel, the diameter or width of the top of mesa 101b may be 1.5 μm, and the diameter or width of the bottom of mesa 101b may be 2.7 μm. The height of the mesa is about 1.3 μm. The distance between the nearest bottom end of mesa 101a and mesa 101b may be 2.3 μm.

[0063]

[0066] In some embodiments, mesa 101 may be surrounded by at least one isolation element 102. Isolation element 102 may isolate light emitted from various mesas. For example, if the height of isolation element 102 is greater than the height of mesas 101a and / or 101c, isolation element 102 may isolate at least a portion of light emitted from mesas 101a and / or 101c from light emitted from mesa 101b. Isolation element 102 may thus suppress optical crosstalk between pixels and improve the contrast of the LED display.

[0064]

[0067] In some embodiments, the LED chip structure 100 also includes one or more reflective layers 103 (e.g., reflective layers 103a, 103b, and 103c). Each of the reflective layers 103 may be disposed on a sidewall of the isolation element 102. For example, as shown in FIG. 1, the reflective layer 103b may be disposed on a circular sidewall of the isolation element 102 surrounding the mesa 101b. The reflective layer 103 may reflect light emitted from the mesa 101, thus enhancing the brightness and luminous efficiency of the LED display. For example, the light emitted from the mesa 101b may reach the reflective layer 103b and be reflected upward by the reflective layer 103b.

[0065]

[0068] The reflective layer 103 together with the isolation element 102 can utilize the reflection direction and / or reflection intensity of the light emitted from the mesa 101. For example, the sidewall of the isolation element 102 can be tilted at a certain angle, and thus the reflective layer 103b disposed on the sidewall of the isolation element 102 is tilted at the same angle (within manufacturing tolerance). When the light emitted from the mesa 101b reaches the reflective layer 103b, the light emitted from the mesa 101b is reflected by the reflective layer 103b according to the angle of the sidewall of the isolation element 102. The material of the reflective layer 103 can be highly reflective, so that most (e.g., more than 60%) of the light emitted from the mesa 101, e.g., mesa 101b, can be reflected. For the sake of simplicity, some elements of the LED chip structure 100 are omitted in FIG. 1. Some embodiments of the LED chip structure with further details are described below with reference to FIG. 2-FIG. 4.

[0066]

[0069] FIG. 2 illustrates a cross-sectional view of an LED chip structure 200 according to some exemplary embodiments. In some embodiments, the cross-section of the LED chip structure 200 is taken along line AA in FIG. 1. As shown, in some embodiments, the LED chip structure 200 includes a substrate 208 including a wafer 207 and one or more bonding metal layers 206 on the wafer 207. The bonding metal layers 206 (e.g., bonding metal layers 206a, 206b, and 206c) can be disposed on the wafer 207 to electrically bond the wafer 207. In some embodiments, the bonding metal layer 206 has a thickness of about 0.1 microns to about 3 microns. For example, for a 5000 PPI display panel, the bonding metal layer 206 has a thickness of about 1.3 μm. In some examples, two metal layers are included in the bonding metal layer 206. One of the metal layers is deposited on the mesa 201. The other bonding metal layer is also deposited on the wafer 207. In some embodiments, the composition of the bonded metal layer 206 includes Au-Au bond, Au-Sn bond, Au-In bond, Ti-Ti bond, Cu-Cu bond, or a mixture thereof. For example, if Au-Au bond is selected, two layers of Au require a Cr coating as an adhesive layer and a Pt coating as a diffusion barrier layer, respectively. The Pt coating is between the Au layer and the Cr layer. The Cr layer and the Pt layer are disposed on the top and bottom of the two bonded Au layers. In some embodiments, if the thickness of the two Au layers is approximately the same, the interdiffusion of Au on both layers will bond the two layers under high pressure and high temperature. Examples of techniques that may be used are eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding.

[0067]

[0070] In some embodiments, the LED chip structure 200 may include a pixel driver integrated circuit (IC) integrated within the wafer 207. The wafer 207 may include silicon as a carrier material with high thermal conductivity, which may facilitate heat dissipation and allow for low thermal expansion.

[0068]

[0071] In some embodiments, the LED chip structure 200 also includes at least one isolation element 202 similar to the isolation element 102 described above with respect to FIG. 1. As shown in FIG. 2, in some embodiments, the isolation element 202 may include one or more upper isolation portions 204 (e.g., upper isolation portions 204a and 204b) and one or more lower isolation portions 205 (e.g., lower isolation portions 205a and 205b). For example, as shown in FIG. 2, the isolation element 202 includes the upper isolation portion 204a and the lower isolation portion 205a. In some embodiments, the upper isolation portion 204a and the lower isolation portion 205a are integrally formed as one part as shown in FIG. 2. The lower isolation portion 205a is disposed in the substrate 208, for example, in the region of the bonding metal layer 206. The upper isolation portion 204a protrudes from the surface of the substrate 208, for example, from the top surface of the bonding metal layer 206, and is disposed on top of the lower isolation portion 205a.

[0069]

[0072] In one embodiment, the upper isolation portions 204 (e.g., upper isolation portions 204a and 204b) may be electrically connected to each other, such as by using a conductive material or by extending the upper isolation portions to contact or overlap each other. In another embodiment, the upper isolation portions 204 (e.g., upper isolation portions 204a and 204b) may be isolated from each other, such as by using a buffer space disposed between adjacent upper isolation portions.

[0070]

[0073] In some embodiments, the LED chip structure 200 also includes one or more mesas 201 (e.g., mesas 201a, 201b, and 201c) surrounded by isolation element 202, similar to that described above with respect to Figure 1. For example, as shown in Figure 2, mesa 201b is surrounded by isolation element 202, e.g., by upper isolation portions 204a and 204b and by lower isolation portions 205a and 205b. The mesas 201 can be disposed on a substrate 208, e.g., on a bonding metal layer 206, and can be driven individually or collectively by a pixel driver IC.

[0071]

[0074] In some embodiments, mesa 201 may be electrically connected to wafer 207 by bonding metal layer 206. For example, although not shown in FIG. 2, the p-electrode of mesa 201 and the output of the drive transistor may be disposed under mesa 201 and electrically connected by bonding metal layer 206. The mesa current driving signal connection (between the mesa p-electrode and the output of the pixel driver), ground connection (between the n-electrode and system ground), Vdd connection (between the source of the pixel driver and system Vdd), and control signal connection to the gate of the pixel driver may be made according to various embodiments, such as those described in U.S. Patent Application Serial No. 15 / 135,217 (U.S. Patent Application Publication No. 2017 / 0179192), entitled "Semiconductor Devices with Integrated Thin-Film Transistor Circuitry," which is incorporated herein by reference.

[0072]

[0075] Mesa 201 can be an LED or micro LED that provides a wide divergence of light. For example, mesa 201b can be an LED or micro LED, or a group of LEDs or micro LEDs. In one embodiment, the amount of light emitted from the sidewalls of mesa 201 exceeds the amount of light emitted from the top of mesa 201. This can cause a wide divergence of the emitted light and a large angular range of the far-field profile, possibly up to 180 degrees, that creates optical crosstalk between pixels. Isolation element 202 can suppress optical crosstalk between pixels. As shown in FIG. 2, in some embodiments, mesa 201b is surrounded by upper isolation portions 204a and 204b and by lower isolation portions 205a and 205b. Isolation element 202 can function as an optical isolation that isolates at least a portion of the light emitted from mesa 201. For example, a portion of the light emitted from mesa 201b can be isolated by upper isolation portions 204a and 204b, thereby preventing light emitted from mesas 201a and / or 201c from illuminating the light emitted from mesa 201b.

[0073]

[0076] In some embodiments, the LED chip structure 200 further includes one or more reflective layers 203 (e.g., reflective layers 203a, 203b, and 203c), similar to that described above with respect to FIG. 1. Each of the reflective layers 203 is disposed on one or more sidewalls of one or more upper isolated portions of the isolation element 202. For example, as shown in FIG. 2, the reflective layer 203b is disposed on the sidewall of the upper isolated portion 204a, and is also disposed on the sidewall of the upper isolated portion 204b. In some embodiments, each of the reflective layers 203, including the lower portion of each of the reflective layers, does not directly contact each of the mesas 201. For example, the lower portion of the reflective layer 203b does not contact or directly hit the mesa 201b or the other mesas 201a and 201c. The reflective layer 203 can function as a passive optical component that reflects a portion of the light emitted from the mesa 201. For example, light emitted from mesa 201b can reach reflective layer 203b and be reflected upwards by reflective layer 203b, thereby reducing the divergence of the light emitted by mesa 201b.

[0074]

[0077] In some embodiments, the reflective layer 203 is disposed on one or more sidewalls of one or more of the upper isolation portions 204 and / or on the top surface of one or more of the upper isolation portions 204. For example, as shown in FIG. 2, the reflective layer 203b can be disposed on the sidewalls of the upper isolation portions 204a and 204b, and the reflective layers 203d and 203e can be disposed on the tops of the upper isolation portions 204a and 204b, respectively. The lower portion of the reflective layer 203 extends from the isolation element 202 to the mesa. For example, the lower portion of the reflective layer 203b extends from the upper isolation portions 204a and 204b to the mesa 201b. In one embodiment, the reflective layers 203a-203e can be the same reflective layer formed in the same process using the same materials.

[0075]

[0078] In some embodiments, the reflective layer 203 may include one or more metallic conductive materials that have a high reflectivity to the light emitted from the LED chip structure 200. In some embodiments, the high reflectivity is greater than 70%. In some embodiments, the high reflectivity is greater than 80%. In some embodiments, the high reflectivity is greater than 90%. In these embodiments, the one or more metallic conductive materials may include one or more of aluminum, gold, or silver. In some embodiments, the reflective layer 203 may be fabricated by one or more of an electron beam evaporation or sputtering process.

[0076]

[0079] In some embodiments, the LED chip structure 200 further includes one or more dielectric layers 209 (e.g., dielectric layers 209a, 209b, and 209c). Each of the dielectric layers 209 may be disposed on the upper portion of the bonding metal layer 206 between the mesas 201 at the lower portion of the sidewall of each of the mesas 201. For example, in a 5000 PPI display panel, the width of the upper portion of the bonding metal layer 206 is 0.55 μm at one bottom end of the mesas 201. The lower portion of the dielectric layer 209 on the upper portion of the bonding metal layer 206 is covered by the lower portion of each of the reflective layers 203. For example, as shown in FIG. 2, the dielectric layer 209b is disposed on the upper portion of the bonding metal layer 206b between the mesas 201 at the lower portion of the sidewall of the mesa 201b. The lower portion of the dielectric layer 209b on the upper portion of the bonding metal layer 206b is covered by the lower portion of each of the reflective layers 203b. In some embodiments, the dielectric layer 209 may be fabricated by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering.

[0077]

[0080] In some embodiments, each of the dielectric layers 209 may further cover the top and sidewalls of each of the mesas 201, while the top of each of the mesas 201 may include areas that are not covered by the corresponding dielectric layer, i.e., areas that are free of the dielectric layer. For example, as shown in FIG. 2, the dielectric layer 209b covers the sidewalls of the mesa 201b as well as the top surface of the mesa 201b. The top surface of the mesa 201b includes areas or openings that are not covered by the dielectric layer 209b. The use of the dielectric layer 209 may ensure that the bottom of each of the reflective layers 203 does not directly contact the mesa 201.

[0078]

[0081] In some embodiments, the dielectric layer 209 may be transparent. In some embodiments, the dielectric layer 209 is transparent to the light emitted from the LED chip structure 200. In some embodiments, the dielectric layer 209 may include one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer. In these embodiments, for the dielectric layer 209, the silicon-containing dielectric layer may include an oxide or nitride of silicon, the aluminum-containing dielectric layer may include an oxide of aluminum, and the titanium-containing dielectric layer may include an oxide of titanium. In one embodiment, for the dielectric layer 209, the oxide of titanium is Ti3O5.

[0079]

[0082] In some embodiments, the LED chip structure 200 further includes at least one conductive layer 210. The top and sidewalls of each of the mesas 201 and the top and sidewalls of each of the upper isolated portions 204 are covered by the conductive layer 210. For example, as shown in FIG. 2, the conductive layer 210 directly or indirectly covers the top and sidewalls of the upper isolated portions 204a and 205a and the top and sidewalls of the mesa 201b. In some embodiments, the conductive layer 210 is transparent. In some embodiments, the conductive layer 210 is transparent to the light emitted from the LED chip structure 200. In some embodiments, the conductive layer 210 may include a transparent conductive oxide (TCO) layer including one or more of indium tin oxide (ITO) or ZnO.

[0080]

[0083] In some embodiments, the conductive layer 210 may be fabricated by one or more of thermal evaporation or sputtering processes. The conductive layer 210 may be fabricated before or after the formation of the reflective layer 203, as long as the current in the conductive layer 210, e.g., the current for the N-electrode, can be distributed quickly and evenly by the reflective layer 203. For example, the conductive layer 210 may be on top of the reflective layer 203 (as shown in FIG. 2) or may be covered by the reflective layer 203 (as shown in FIG. 3). In some embodiments, the dielectric layer 209 may be fabricated before or after the formation of the isolation element 202, as long as the isolation element 202 and the conductive layer 210 are insulated from the bonding metal layer 206, e.g., the current for the N-electrode in the conductive layer 210 and the reflective layer 203 is insulated from the bonding metal layer 206 that is connected to the P-electrode. The conductive layer 210 may conduct current, for example, between the mesa 201b and the system Vdd.

[0081]

[0084] As explained above, when the isolation element 202 is taller than the mesa 201, the isolation element 202 can isolate light emitted from one mesa (e.g., mesa 201a) from light emitted from another mesa (e.g., mesa 201b). In some embodiments, for the isolation element 202, the height of each of the upper isolation portions 204 is determined as the distance from the top surface of the upper isolation portion 204 to the top surface of the bonding metal layer 206. In some embodiments, for the isolation element 202, the height of each of the lower isolation portions 205 is determined as the distance from the bottom surface of the lower isolation portion 205 to the top surface of the bonding metal layer 206. In some embodiments, for the isolation element 202, the height of the upper isolation portion 204 can be taller than the height of the lower isolation portion 205. For example, as shown in FIG. 2, the height of the upper isolation portion 204a is taller than the height of the lower isolation portion 205a. In other embodiments, the height of the upper isolation portion 204 can be the same as or less than the height of the lower isolation portion 205. In addition, the heights of the upper isolation portions can be different. For example, the height of upper isolation portion 204a may be different than the height of upper isolation portion 204b. The height of lower isolation portion 205 may also be different. For example, the height of lower isolation portion 205a may be different than the height of lower isolation portion 205b.

[0082]

[0085] In some embodiments, for the isolation element 202, the bottom width of each of the upper isolation portions 204 can be equal to or greater than the top width of each of the lower isolation portions 205. For example, as shown in FIG. 2, the bottom width of the upper isolation portion 204a can be equal to or greater than the top width of the lower isolation portion 205b. For example, in a 5000 PPI display panel, the bottom width of the upper isolation portion 204b is about 1.7 μm, the top width of the lower isolation portion 205b is about 1.2 μm, and the bottom width of the lower isolation portion 205b is about 0.3 μm. In these embodiments, there is a difference between the bottom width of the upper isolation portion 204a and the top width of the lower isolation portion 205a, thus forming two protrusions at the bottom of the upper isolation portion 204a. The bottom width of the upper isolation portion 204a can exceed the top width of the lower isolation portion 205a by less than the top width of the lower isolation portion 205a. The total bottom width of the upper isolated portion 204a is longer than the top width of the lower isolated portion 204a, but is less than twice the top width of the lower isolated portion 204a. In some embodiments, the width of each of the protrusions is less than half the top width of the lower isolated portion 204a. In other embodiments, the width of each of the two protrusions may be different. For example, the width of the lower left protrusion of the upper isolated portion 204a is different from the width of the lower right protrusion of the upper isolated portion 204a. For example, in a 5000 PPI display panel, the width of the lower left protrusion of the upper isolated portion 204a is about 0.2 μm.

[0083]

[0086] In some embodiments, for the isolation element 202, the cross section of each of the upper isolation portions 204 is a trapezoid, the cross section of each of the lower isolation portions 205 is an inverted trapezoid, and the lower portion of each of the upper isolation portions 204 covers the upper portion of each of the lower isolation portions 205. In some embodiments, the lower area of ​​the upper isolation portion 204 exceeds the upper area of ​​the lower isolation portion 205. For example, as shown in FIG. 2, the cross section of the upper isolation portion 204a is a trapezoid, and the cross section of the lower isolation portion 205a is an inverted trapezoid. The lower portion of the upper isolation portion 204a covers the upper portion of the lower isolation portion 205a. In addition, the trapezoid and the inverted trapezoid may be isosceles or right-angled. For example, the upper isolation portion 204a may be a trapezoid, and the lower isolation portion 205a may be an inverted trapezoid, and both may be isosceles. In other embodiments, the upper isolation portion (e.g., the upper isolation portion 204a) and the corresponding lower isolation portion (e.g., the lower isolation portion 205a) may be axisymmetric and / or coaxial.

[0084]

[0087] In some embodiments, the height of each upper isolation portion 204 relative to the plane of bond metal layer 206 can be greater than the height of each of the mesas 201. In some embodiments, the slope angle of the sidewall of each of the upper isolation portions 204 relative to an axis perpendicular to the plane of the wafer 207 can be greater than the slope angle of the sidewall of each of the mesas 201.

[0085]

[0088] For example, as shown in FIG. 2, the height of the upper isolated portion 204a can be greater than the height of the mesa 201b relative to the plane of the bonded metal layer 206. The height of the upper isolated portion 204a can also be greater than the rest of the mesa 201 (i.e., mesas 201a and 201c). As further shown in FIG. 2, the inclination angle α of the sidewall of the upper isolated portion 204a relative to the top surface of the bonded metal layer 206 can be less than 90°, and the inclination angle β of the sidewall of the mesa 201a relative to the top surface of the bonded metal layer 206 can be less than 90°. The inclination angle α of the sidewall of the upper isolated portion 204a can be less than the inclination angle β of the sidewall of the mesa 201a. In some embodiments, the inclination angle β of the sidewall of the mesa 201a can be greater than 45°, and the inclination angle α of the sidewall of the upper isolated portion 204a can be less than 45°.

[0086]

[0089] In some embodiments, isolation element 202 comprises a dielectric material, such as silicon oxide. In some embodiments, isolation element 202 comprises a photosensitive dielectric material. In some embodiments, the photosensitive dielectric material comprises SU-8 or photosensitive polyimide (PSPI). In other embodiments, isolation element 202 comprises photoresist. Additionally, in some embodiments, isolation element 202 may be fabricated by a photolithography process.

[0087]

[0090] The LED chip structure 200 can increase the overall collimation of the light produced by the mesa 201. Light beams that are already significantly collimated (such as light beams emitted from the top of the mesa) do not hit the isolation element 202 and come out of the LED chip structure 200 without being redirected by the isolation element 202. In contrast, light beams that are not sufficiently collimated (such as light beams emitted from the sidewall of the mesa 201) hit the isolation element 202 and are redirected to more collimated directions, including the same direction as the light beams emitted from the top of the mesa 201. Thus, the divergence angle is reduced while increasing the overall collimation of the light produced by the mesa 201, including the forward direction (perpendicular to the LED chip surface). The luminous efficiency at small angles and the brightness of the LED chip structure 200 are also increased.

[0088]

[0091] FIG. 3 illustrates a cross-sectional view of an LED chip structure 300 according to some exemplary embodiments. In some embodiments, the cross-section of the LED chip structure 300 is taken along the line AA in FIG. 1. As shown, in some embodiments, the LED chip structure 300 includes a substrate 308 including a wafer 307 and one or more bonding metal layers 306 and on top of the wafer 307. Each bonding metal (e.g., bonding metal layers 306a, 306b, and 306c) may be formed on the wafer 307. The material and structure of the bonding metal layer 306 are similar to the bonding metal layer 206 described in FIG. 2. In some embodiments, the LED chip structure 300 may include a pixel driver IC integrated on the wafer 307. The wafer 307 may include silicon as a carrier material with high thermal conductivity, which facilitates heat dissipation and provides low thermal expansion.

[0089]

[0092] In some embodiments, the LED chip structure 300 also includes at least one isolation element 302 similar to the isolation element 102 described above with respect to FIG. 1. As shown in FIG. 3, in some embodiments, the isolation element 302 may include one or more upper isolation portions 304 (e.g., upper isolation portions 304a and 304b) and one or more lower isolation portions 305 (e.g., lower isolation portions 305a and 305b). For example, as shown in FIG. 3, the isolation element 302 includes the upper isolation portion 304a and the lower isolation portion 305a. In some embodiments, the upper isolation portion 304a and the lower isolation portion 305a are integrally formed as one part as shown in FIG. 3. The lower isolation portion 305a is disposed in the substrate 308, for example, in the region of the bonding metal layer 306. The upper isolation portion 304a protrudes from the surface of the substrate 308, for example, from the top surface of the bonding metal layer 306, and is disposed on top of the lower isolation portion 305a.

[0090]

[0093] In some embodiments, the isolation elements 302 include a photosensitive dielectric material. In other embodiments, the photosensitive dielectric material can be SU-8 or photosensitive polyimide (PSPI). In addition, in some embodiments, the isolation elements 302 can be made by a photolithography process. In one embodiment, the upper isolation portions 304 (e.g., upper isolation portions 304a and 304b) can be electrically connected to each other, for example, by using a conductive material or by extending the upper isolation portions to contact or overlap each other. In another embodiment, the upper isolation portions 304 (e.g., upper isolation portions 304a and 304b) can be isolated from each other, for example, by using a buffer space disposed between adjacent upper isolation portions.

[0091]

[0094] In some embodiments, LED chip structure 300 also includes one or more mesas 301 (e.g., mesas 301a, 301b, and 301c) surrounded by isolation element 302, similar to that described above with respect to Figure 1. For example, as shown in Figure 3, mesa 301b is surrounded by isolation element 302, e.g., by upper isolation portions 304a and 304b and by lower isolation portions 305a and 305b. Mesas 301 can be disposed on a substrate 308, e.g., on a bonding metal layer 306, and can be driven individually or collectively by a pixel driver IC.

[0092]

[0095] In some embodiments, the mesa 301 may be electrically connected to the wafer 307 by the bonding metal layer 306. For example, although not shown in FIG. 3, the p-electrode of the mesa 301 and the output of the driving transistor may be disposed under the mesa 301 and electrically connected by the bonding metal layer 306. The mesa 301 may be an LED or micro LED that provides a widely diverging light. For example, the mesa 301b may be an LED or micro LED, or may be a group of LEDs or micro LEDs. The isolation element 302 may suppress crosstalk between pixels. As shown in FIG. 3, in some embodiments, the mesa 301b is surrounded by upper isolation portions 304a and 304b and by lower isolation portions 305a and 305b. The isolation element 302 may function as an optical isolation that isolates a portion of the light emitted from the mesa 301. For example, a portion of the light emitted from the mesa 301b may be isolated by the upper isolation portions 304a and 304b, thereby inhibiting optical crosstalk between pixels.

[0093]

[0096] In some embodiments, the LED chip structure 300 further includes one or more dielectric layers 309 (e.g., dielectric layers 309a, 309b, and 309c). Each of the dielectric layers 309 may be disposed on the top portion of the bonding metal layer 306 between the mesas 301 at the bottom of the sidewalls of each of the mesas 301. For example, for a 5000 PPI display panel, the width of the top portion of the bonding metal layer 306 is 0.55 μm at the bottom end of one of the mesas 301. The bottom portion of the dielectric layer 309 on the top portion of the bonding metal layer 306 is covered by the bottom portion of each of the conductive layers 310 as described below.

[0094]

[0097] In some embodiments, each of the dielectric layers 309 may cover the top and sidewalls of each of the mesas 301, while the top of each of the mesas 301 may include areas that are not covered by the corresponding dielectric layer. For example, as shown in FIG. 3, the dielectric layer 309b covers the sidewalls of the mesa 301b as well as a portion of the top of the mesa 301b. In addition, the top of the mesa 301b includes areas or openings that are not covered by the dielectric layer 309b. The use of the dielectric layer 309 may ensure that the bottom of the conductive layer 310 or the reflective layer 303, respectively, does not directly contact the mesa 301. In some embodiments, the dielectric layer 309 may be made by one or more of a CVD, ALD, or sputtering process.

[0095]

[0098] In some embodiments, the dielectric layer 309 may be transparent. In some embodiments, the dielectric layer 309 is transparent to the light emitted from the LED chip structure 300. In some embodiments, the dielectric layer 309 may include one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer. In these embodiments, with respect to the dielectric layer 309, the silicon-containing dielectric layer may include an oxide or nitride of silicon, the aluminum-containing dielectric layer may include an oxide of aluminum, and the titanium-containing dielectric layer may include an oxide of titanium. In other embodiments, the oxide of titanium may be Ti3O5.

[0096]

[0099] In some embodiments, the LED chip structure 300 further includes at least one conductive layer 310. As shown in FIG. 3, the conductive layer 310 covers the dielectric layer 309, the top surface of each of the mesas 301 with the area not covered by the dielectric layer 309, and the sidewalls of each of the upper isolated portions 304 (e.g., upper isolated portions 304a and 304b). In some embodiments, the conductive layer 310 covers the top surfaces and sidewalls of the upper isolated portions 304a and 304b and the top surfaces and sidewalls of the mesas, such as mesa 301b, as shown in FIG. 3. In some embodiments, the conductive layer 310 is transparent. In some embodiments, the conductive layer 310 is transparent to the light emitted from the LED chip structure 300. In some embodiments, the conductive layer 310 may include a transparent conductive oxide (TCO) layer including one or more of indium tin oxide (ITO) or ZnO.

[0097]

[0100] In some embodiments, the conductive layer 310 may be fabricated by one or more of thermal evaporation or sputtering processes. The conductive layer 310 may be fabricated before or after the formation of the reflective layer 303, as long as the current in the conductive layer 310, e.g., the current for the N-electrode, can be distributed quickly and evenly by the reflective layer 303. For example, the conductive layer 310 may be on top of the reflective layer 303 (as shown in FIG. 2) or may be covered by the reflective layer 303 (as shown in FIG. 3). In some embodiments, the dielectric layer 309 may be fabricated before or after the formation of the isolation element 302, as long as the isolation element 302 and the conductive layer 310 are insulated from the bonding metal layer 206, e.g., the current for the N-electrode in the conductive layer 310 and the reflective layer 303 is insulated from the bonding metal layer 306 that is connected to the P-electrode. The conductive layer 310 may conduct current, for example, between the mesa 301b and the system Vdd.

[0098]

[0101] In some embodiments, the LED chip structure 300 further includes one or more reflective layers 303 (e.g., reflective layers 303a, 303b, and 303c), similar to that described above with respect to FIG. 1. Each of the reflective layers 303 is disposed on at least one or more sidewalls of one or more upper isolated portions 304 of the isolation element 302, and the lower portion of each of the reflective layers 303 may not contact the mesa 301. For example, as shown in FIG. 3, the reflective layer 303b is disposed on the sidewall of the upper isolated portion 304a as well as the sidewall of the upper isolated portion 304b. In some embodiments, each of the reflective layers 303, including the lower portion of each of the reflective layers 303, does not directly contact each of the mesas 301. The lower portion of the reflective layer 303b may not contact or directly hit the mesa 301b. The reflective layer 303 can function as a passive optical component that reflects a portion of the light emitted from the mesa 301. For example, light emitted from mesa 301b can reach reflective layer 303b and be reflected upward by reflective layer 303b, thereby reducing the divergence of the light emitted by mesa 301b and enhancing the brightness and luminous efficiency.

[0099]

[0102] In some embodiments, the reflective layer 303 may include one or more metallic conductive materials that have a high reflectivity to the light emitted from the LED chip structure 300. In some embodiments, the high reflectivity is greater than 70%. In some embodiments, the high reflectivity is greater than 80%. In some embodiments, the high reflectivity is greater than 90%. In these embodiments, the one or more metallic conductive materials may include one or more of aluminum, gold, or silver. In some embodiments, the reflective layer 303 may be fabricated by one or more of an electron beam evaporation or sputtering process.

[0100]

[0103] In some embodiments, a conductive layer 310 may be disposed on a top surface and sidewalls of each of the upper isolated portions 304 (e.g., upper isolated portions 304a and 304b), and a reflective layer may be disposed on the conductive layer disposed on the top surface and sidewalls of each of the upper isolated portions. For example, as shown in FIG. 3, the top surface and sidewalls of the upper isolated portions 304a and 304b are covered by the conductive layer 310, which further covers the conductive layer 310 that covers the top surface and sidewalls of the upper isolated portions 304a and 304b. In some embodiments, a lower portion of each reflective layer 303 may extend from the isolation element 302 to the corresponding mesa. For example, as shown in FIG. 3, a lower portion of the reflective layer 303b extends from the upper isolated portions 304a and 304b of the isolation element 302 to the mesa 301b.

[0101]

[0104] As explained above, the height of the isolation element 302 can isolate light emitted from mesas 301a and / or 301c from light emitted from mesa 301b. In some embodiments, for the isolation element 302, the height of each of the upper isolation portions 304 is determined as the distance from the top surface of the upper isolation portion 304 to the top surface of the bonding metal layer 306. In some embodiments, for the isolation element 302, the height of each of the lower isolation portions 305 is determined as the distance from the bottom surface of the lower isolation portion 305 to the top surface of the bonding metal layer 306. In some embodiments, for the isolation element 302, the height of the upper isolation portion 304 can be greater than the height of the lower isolation portion 305. For example, as shown in FIG. 3, the height of the upper isolation portion 304a is greater than the height of the lower isolation portion 305a. In other embodiments, the height of the upper isolation portion 304 can be the same as or less than the height of the lower isolation portion 305. In addition, the heights of the upper isolation portions can be different. For example, the height of the upper isolation portion 304a can be different from the height of the upper isolation portion 304b. The heights of the lower isolation portions 305 may also differ from one another. For example, the height of lower isolation portion 305a may differ from the height of lower isolation portion 305b.

[0102]

[0105] In some embodiments, for the isolation element 302, the bottom width of each of the upper isolation portions 304 can be equal to or greater than the top width of each of the lower isolation portions 305. For example, as shown in FIG. 3, the bottom width of the upper isolation portion 304a can be equal to or greater than the top width of the lower isolation portion 305b. For example, in a 5000 PPI display panel, the bottom width of the upper isolation portion 304b is about 1.7 μm, the top width of the lower isolation portion 305b is about 1.2 μm, and the bottom width of the lower isolation portion 305b is about 0.3 μm. In these embodiments, there is a difference between the bottom width of the upper isolation portion 304a and the top width of the lower isolation portion 305a, thus forming two protrusions at the bottom of the upper isolation portion 304a. The bottom width of the upper isolation portion 304a can exceed the top width of the lower isolation portion 305a by less than the top width of the lower isolation portion 305a. The total bottom width of the upper isolated portion 304a is longer than the top width of the lower isolated portion 304a, but is less than twice the top width of the lower isolated portion 304a. In some embodiments, the width of each of the protrusions is less than half the top width of the lower isolated portion 304a. In other embodiments, the width of each of the two protrusions may be different. For example, the width of the lower left protrusion of the upper isolated portion 304a is different from the width of the lower right protrusion of the upper isolated portion 304a. For example, in a 5000 PPI display panel, the width of the lower left protrusion of the upper isolated portion 304a is about 0.2 μm.

[0103]

[0106] In some embodiments, for the isolation element 302, the cross section of each of the upper isolation portions 304 is a trapezoid, the cross section of each of the lower isolation portions 305 is an inverted trapezoid, and the lower portion of each of the upper isolation portions 304 covers the upper portion of each of the lower isolation portions 305. In some embodiments, the lower area of ​​the upper isolation portion 304 exceeds the upper area of ​​the lower isolation portion 305. For example, as shown in FIG. 3, the cross section of the upper isolation portion 304a is a trapezoid, and the cross section of the lower isolation portion 305a is an inverted trapezoid. The lower portion of the upper isolation portion 304a covers the upper portion of the lower isolation portion 305a. In addition, the trapezoid and the inverted trapezoid may be isosceles or right-angled. For example, the upper isolation portion 304a may be a trapezoid, and the lower isolation portion 305a may be an inverted trapezoid, and both may be isosceles. In other embodiments, the upper isolation portion (e.g., the upper isolation portion 304a) and the corresponding lower isolation portion (e.g., the lower isolation portion 305a) may be axisymmetric and / or coaxial.

[0104]

[0107] In some embodiments, the height of each upper isolation portion 304 relative to the plane of bonding metal layer 306 can be greater than the height of each of the mesas 301 (e.g., mesas 301a, 301b, and 301c), and the inclination angle of the sidewall of each of the upper isolation portions 304 relative to an axis perpendicular to the plane of wafer 307 can be greater than the inclination angle of the sidewall of each of the mesas 301 (e.g., mesas 301a, 301b, and 301c).

[0105]

[0108] For example, as shown in FIG. 3, the height of the upper isolated portion 304a can be greater than the height of the mesa 301b relative to the plane of the bonded metal layer 306. The height of the upper isolated portion 304a can also be greater than the rest of the mesa 301 (i.e., mesas 301a and 301c). As further shown in FIG. 3, the inclination angle α of the sidewall of the upper isolated portion 304a relative to the top surface of the bonded metal layer 306 can be less than 90°, and the inclination angle β of the sidewall of the mesa 301a relative to the top surface of the bonded metal layer 306 can be less than 90°. The inclination angle α of the sidewall of the upper isolated portion 304a can be less than the inclination angle β of the sidewall of the mesa 301a. In some embodiments, the inclination angle β of the sidewall of the mesa 301a can be greater than 45°, and the inclination angle α of the sidewall of the upper isolated portion 304a can be less than 45°.

[0106]

[0109] 1, 2, and 3 only show the LED chip structure according to some embodiments. In other embodiments, the LED chip structure may include a different number of mesas 101 and / or a different number of reflective layers 103. In other embodiments, each of the mesas 101 may include multiple individual optical elements, such as multiple LEDs or micro-LEDs connected in parallel or stacked individually. In other embodiments, the mesas 101 may not be circular when viewed from above. In other embodiments, the sidewalls of the isolation elements 102 surrounding each of the mesas 101 may not be circular when viewed from above. That is, the sidewalls of the isolation elements 102 surrounding each of the mesas 101 may have other shapes when viewed from above, including but not limited to triangular, square, rectangular, pentagonal, hexagonal, and octagonal. In other embodiments, the isolation elements 102 may include multiple separate or isolated sub-elements, each sub-element may surround one mesa. A buffer space may be provided between the multiple separate or isolated sub-elements.

[0107]

[0110] FIG. 4 shows a cross-sectional view of a reflective layer 400 having a multi-layer structure according to some exemplary embodiments. In the LED chip structure described above, the reflective layer 400 may include a multi-layer structure. The multi-layer structure may include a stack of one or more reflective material layers and one or more dielectric material layers. In an exemplary embodiment, as shown in FIG. 4, the reflective layer 400 includes a multi-layer structure including one reflective material layer 401 and one dielectric material layer 402. In other embodiments, the multi-layer structure may include two reflective material layers and one dielectric material layer disposed between the two reflective material layers. In yet some other embodiments, the multi-layer structure may include two dielectric material layers and one reflective material layer disposed between the two dielectric material layers. In some embodiments, the multi-layer structure may include two or more metal layers. For example, the metal layer may include one or more of TiAu, CrAl, or TiWAg.

[0108]

[0111] In some embodiments, the multilayer structure may be a multilayer omnidirectional reflector (ODR) including a metal layer and a transparent conductive oxide (TCO). For example, the multilayer structure may include a dielectric material layer, a metal layer, and a TCO layer. In some embodiments, the multilayer structure may include two or more dielectric material layers that are alternated to form a distributed Bragg reflector (DBR). For example, the multilayer structure may include a dielectric material layer, a metal layer, and a transparent dielectric layer. The transparent dielectric layer may include one or more of SiO2, Si3N4, or Al2O3. The multilayer structure may further include a dielectric material layer, a TCO, and a DBR. In other embodiments, the reflective layer 400 may include one or more metal conductive materials having a high reflectivity. In some embodiments, the high reflectivity is greater than 70%. In some embodiments, the high reflectivity is greater than 80%. In some embodiments, the high reflectivity is greater than 90%. In these embodiments, the one or more metal conductive materials may include one or more of aluminum, gold, or silver.

[0109]

[0112] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the appended claims and the principles and novel features disclosed herein.

[0110]

[0113] Various types of display panels can be manufactured according to one or more of the embodiments of the present disclosure. For example, the resolution of the display panel can range from 8x8 to 3840x2160. Common display resolutions include QVGA with a resolution of 320x240 and an aspect ratio of 4:3, XGA with a resolution of 1024x768 and an aspect ratio of 4:3, D with a resolution of 1280x720 and an aspect ratio of 16:9, FHD with a resolution of 1920x1080 and an aspect ratio of 16:9, UHD with a resolution of 3840x2160 and an aspect ratio of 16:9, and 4K with a resolution of 4096x2160. There can also be a wide range of pixel sizes, ranging from sub-micron to 10mm or more. The size of the overall display area can also vary from as small as tens of microns or less to hundreds of inches or more.

[0111]

[0114] Exemplary applications include display screens, optical engines for home / office projectors, and portable electronics such as smartphones, laptops, wearable electronics, AR and VR glasses, and retinal projection. Power consumption can vary from as low as a few milliwatts for retinal projectors to as high as several kilowatts for large outdoor displays, projectors, and smart car headlights. In terms of frame rate, the fast response (nanoseconds) of inorganic LEDs allows frame rates as high as KHz, and even as high as MHz for smaller resolutions.

[0112]

[0115] Features of the present invention may be implemented by, using, or with the aid of a computer program product, such as a storage medium or computer-readable storage medium having stored thereon / in which instructions usable to program a processing system to perform any of the features described herein. The storage medium may include high-speed random access memory, such as, but not limited to, DRAM, SRAM, DDR RAM, or other random access solid-state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. The memory optionally includes one or more storage devices located remotely from the CPU. The memory or non-volatile memory devices within the memory include non-transitory computer-readable storage media.

[0113]

[0116] Stored on any machine-readable medium, features of the present invention may be embodied in software and / or firmware for controlling the hardware of a processing system and for enabling the processing system to interact with other mechanisms utilizing the results of the present invention. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments / containers.

[0114]

[0117] It will be understood that although the terms "first," "second," etc. may be used herein to refer to various elements, these elements are not to be limited by these terms, but are merely used to distinguish one element from another.

[0115]

[0118] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the claims. When used in the description of the embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprise" and / or "comprising" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0116]

[0119] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining that" or "in response to detecting that" the stated antecedent condition is true, depending on the context. Similarly, the phrases "if it is determined" or "if" or "when the stated antecedent condition is true" may be interpreted to mean "upon determining" or "in response to determining" or "in accordance with a determination" or "upon detecting" or "in response to detecting" the stated antecedent condition is true, depending on the context.

[0117]

[0120] The above description has been set forth for purposes of illustration with respect to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been chosen and described in order to best explain the principles of operation and practical application, thereby enabling others skilled in the art to best utilize the invention and its various embodiments.

Claims

1. A substrate; an isolation element including an upper isolation portion and a lower isolation portion, the lower isolation portion being disposed within the substrate and the upper isolation portion protruding from a surface of the substrate; a mesa including an LED component surrounded by the isolation element; a dielectric layer covering a top surface and sidewalls of the mesa, the top surface of the mesa including an area free of the dielectric layer; a continuous conductive layer covering the dielectric layer, the top surface of the mesa including all of the areas free of the dielectric layer, and at least a sidewall of the upper isolated portion; a reflective layer disposed at least on the continuous conductive layer covering the sidewall of the upper isolation portion, a lower portion of the reflective layer not contacting the mesa; A light emitting diode (LED) chip structure comprising:

2. 2. The LED chip structure of claim 1, wherein the continuous conductive layer is disposed on a top surface and a sidewall of the upper isolation portion, the reflective layer is disposed on the continuous conductive layer disposed on the top surface and the sidewall of the upper isolation portion, and the lower portion of the reflective layer extends from the isolation element toward the mesa.

3. 2. The LED chip structure as claimed in claim 1, wherein a height of said upper isolation portion is greater than a height of said lower isolation portion.

4. 2. The LED chip structure as claimed in claim 1, wherein a bottom width of said top isolation portion is equal to or greater than a top width of said bottom isolation portion.

5. 5. The LED chip structure as claimed in claim 4, wherein the lower width of the upper isolation portion is longer than the upper width of the lower isolation portion and shorter than twice the upper width of the lower isolation portion, and two protrusions are formed at the lower ends of each of the upper isolation portions, and the width of each of the two protrusions is less than half of the upper width of the lower isolation portion.

6. 5. The LED chip structure as claimed in claim 4, wherein, in side view, a cross section of the upper isolation portion is a trapezoid, a cross section of the lower isolation portion is an inverted trapezoid, and the lower portion of the upper isolation portion covers the upper portion of the lower isolation portion.

7. 5. The LED chip structure as claimed in claim 4, wherein said upper isolation portion and said lower isolation portion are axisymmetric and coaxial.

8. 2. The LED chip structure of claim 1, wherein a height of the upper isolation portion relative to a surface of the substrate is greater than a height of the mesa, and a slope angle of the sidewall of the upper isolation portion relative to an axis perpendicular to the surface of the substrate is greater than a slope angle of the sidewall of the mesa.

9. 9. The LED chip structure as claimed in claim 8, wherein the slope angle of the sidewalls of the mesa is less than 45° and the slope angle of the sidewalls of the upper isolation portion is greater than 45°.

10. 10. The LED chip structure of claim 1, wherein said dielectric layer is transparent to light emitted from said LED chip structure.

11. 10. The LED chip structure as claimed in claim 1, wherein the dielectric layer comprises one or more of a silicon-containing dielectric layer, an aluminum-containing dielectric layer, or a titanium-containing dielectric layer.

12. 12. The LED chip structure as claimed in claim 11, wherein the silicon-containing dielectric layer comprises an oxide or nitride of silicon, the aluminum-containing dielectric layer comprises an oxide of aluminum, and the titanium-containing dielectric layer comprises an oxide of titanium.

13. The oxide of titanium is Ti ３ O ５ 13. The LED chip structure of claim 12, wherein:

14. 10. The LED chip structure of claim 1, wherein the reflective layer comprises a multi-layer structure.

15. 15. The LED chip structure as claimed in claim 14, wherein the multi-layer structure comprises a stack of one or more reflective material layers and one or more dielectric material layers.

16. 10. The LED chip structure as claimed in claim 1, wherein said reflective layer comprises one or more metallic conductive materials with a high reflectivity of over 80%.

17. 17. The LED chip structure as claimed in claim 16, wherein the one or more metallic conductive materials include one or more of aluminum, gold, or silver.

18. 10. The LED chip structure of claim 1, wherein said continuous conductive layer is transparent to light emitted from said LED chip structure.

19. 10. The LED chip structure as claimed in claim 1, wherein said isolation element comprises a photosensitive dielectric material.

20. 20. The LED chip structure as claimed in claim 19, wherein said photosensitive dielectric material is SU-8 or photosensitive polyimide (PSPI).

21. 10. The LED chip structure of claim 1, wherein the substrate comprises a semiconductor wafer and a bonding metal layer on the semiconductor wafer.

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