Semiconductor device and its manufacturing method

Abstract

The purpose of the present disclosure is to provide a semiconductor device and a manufacturing method therefor, whereby reliability can be enhanced. A semiconductor device according to the present disclosure comprises: a silicon carbide substrate of a first conductivity type; a drift layer of the first conductivity type formed on the silicon carbide substrate; a plurality of well regions of a second conductivity type formed selectively on a surface layer of the drift layer; a source region of the first conductivity type formed selectively on a surface layer of each of the well regions; a low resistance region formed on the surface layer of the drift layer, between the well regions adjacent when viewed planarly, and having an impurity concentration higher than that of the drift layer; a gate insulating film formed throughout on the source region, on the well regions, and on the low resistance region; and a gate electrode formed on the gate insulating film. The gate insulating film includes a first region contacting the well regions, and a second region contacting the low resistance region. The density of a positive fixed charge in the second region is higher than the density of a positive fixed charge in the first region.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device having a high-voltage MOSFET and a manufacturing method thereof. [Background technology]

[0002] As semiconductor devices for power control, semiconductor devices having a gate electrode of a MOS structure (hereinafter also referred to as "semiconductor switching element"), such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), are widely used.

[0003] To achieve energy savings in power electronics devices such as inverters, it is necessary to reduce losses in semiconductor switching elements such as MOSFETs.Since losses in semiconductor switching elements are determined by the conduction loss and switching loss of the element, in order to reduce these losses, development of semiconductor switching elements using wide bandgap semiconductor materials such as silicon carbide (SiC) or gallium nitride (GaN) is underway.

[0004] On the other hand, in order to control high power, it is necessary to improve the reliability and stabilization of semiconductor switching elements. In particular, SiC-MOSFETs have a higher dielectric breakdown resistance than Si-MOSFETs, so the drift concentration can be set to a high concentration, but when a high voltage is applied to the drain during MOSFET off operation, a large electric field is applied to the gate insulating film. When a large voltage is applied to the gate insulating film, it causes deterioration and destruction of the gate insulating film, that is, a decrease in the breakdown voltage of the semiconductor switching element. Here, SiC-MOSFET refers to a MOSFET that uses SiC, and Si-MOSFET refers to a MOSFET that uses Si.

[0005] As conventional semiconductor devices, for example, the following Patent Documents 1 to 4 are disclosed.

[0006] Patent Document 1 proposes a structure in which a p-type electric field relaxation region is provided in a JFET (Junction Field-Effect Transistor) region formed in an n-type epitaxial layer in contact with the gate insulating film, thereby relaxing the electric field strength applied to the gate insulating film during the off operation of a SiC-MOSFET.

[0007] Patent Document 2 aims to improve the reliability of the gate oxide film during MOSFET off operation, and proposes a structure in which a negative fixed charge is set in the gate insulating film above the JFET section to reduce the electric field strength applied to the gate insulating film above the JFET section.

[0008] In order to improve the switching characteristics of a semiconductor device, it is effective to reduce the electrostatic capacitance. Patent Document 3 proposes a structure in which the gate insulating film on the JFET region is thickened in order to suppress the reduction in the drain current and improve the switching characteristics.

[0009] In the SiC-MOS structure, there is a high interface state density at the interface between the gate insulating film and the semiconductor layer, and the channel mobility is extremely low. Therefore, in the SiC-MOS structure, the channel resistance increases, and the on-resistance also increases accordingly. Patent Document 4 discloses the application of a process technology that introduces an appropriate amount of nitrogen into the interface between the gate insulating film and the drift layer. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Patent No. 5895750 [Patent Document 2] Patent No. 5995701 [Patent Document 3] JP 2014-60272 A [Patent Document 4] JP 2011-82454 A Summary of the Invention [Problem to be solved by the invention]

[0011] In the structure of Patent Document 1, when the MOSFET is in an on-state, the current between the drain and source is hindered by the depletion layer that spreads from the electric field relaxation region, and the resistance value of the well region (so-called JFET resistance value) becomes large. In particular, in the SiC-MOSFET, the film thickness of the epitaxial layer, which is the drift region, can be made thin and the carrier density in the epitaxial layer can be made high, so the drift resistance is small and the JFET resistance and channel resistance account for a large part of the on-resistance of the entire MOSFET. In Patent Document 1, an attempt is made to suppress the resistance by setting the film thickness of the electric field relaxation layer thin, but the resistance value is not sufficiently low. Therefore, in the SiC-MOSFET disclosed in Patent Document 1, the reliability of the gate insulating film is improved, but the reduction of the on-resistance is an issue.

[0012] When a negative bias is applied as a gate voltage while the MOSFET is in the off state, holes are injected from the JFET section into the gate insulating film. This hole injection may damage the gate insulating film. Patent Document 2 discloses setting a negative fixed charge in the gate insulating film, but the negative fixed charge increases the amount of holes injected from the JFET section into the gate insulating film, which may damage the gate insulating film.

[0013] In Patent Document 3, since increasing the thickness of the gate insulating film on the well reduces the drain current flowing through the channel, only the gate insulating film on the JFET region is thickened. In Patent Document 3, the gate insulating film on the JFET region is thickened to reduce capacitance, and there is no mention of fixed charge. From the viewpoint of gate insulating film reliability, electric field relaxation by thickening the gate insulating film is effective, but in order to suppress hole injection, it is effective to set a positive fixed charge in the gate insulating film in addition to electric field relaxation.

[0014] In Patent Document 4, an appropriate amount of nitrogen is introduced into the interface between the gate insulating film on the well of the SiC-MOSFET and the drift layer, but as the nitrogen concentration increases, the amount of positive fixed charge also increases, so there is a problem that the threshold voltage drops drastically when the nitrogen concentration is set to a high concentration. Therefore, there is an upper limit to the nitrogen concentration that can be introduced into the interface between the gate insulating film on the well of the SiC-MOSFET and the drift layer. In addition, Patent Document 4 does not mention the reliability of the gate insulating film in the MOSFET or JFET section.

[0015] As described above, conventional semiconductor devices are unable to achieve both low resistance during on-state operation and suppression of a decrease in the breakdown voltage of the gate insulating film during off-state operation, and there is room for improvement in order to improve reliability.

[0016] The present disclosure has been made to solve such problems, and has an object to provide a semiconductor device capable of improving reliability and a manufacturing method thereof. [Means for solving the problem]

[0017] In order to solve the above problems, a semiconductor device according to the present disclosure includes a silicon carbide substrate of a first conductivity type, a drift layer of the first conductivity type formed on the silicon carbide substrate, a plurality of well regions of a second conductivity type selectively formed in a surface layer of the drift layer, a source region of the first conductivity type selectively formed in a surface layer of each well region, a low-resistance region formed in the surface layer of the drift layer between adjacent well regions in a planar view and having an impurity concentration higher than an impurity concentration of the drift layer, a gate insulating film formed across the source region, each well region, and the low-resistance region, and a gate electrode formed on the gate insulating film, the gate insulating film including a first region in contact with each well region and a second region in contact with the low-resistance region, and a density of positive fixed charges in the second region is higher than a density of positive fixed charges in the first region. The second region of the gate insulating film contains an element different from the first region of the gate insulating film, and a concentration peak of the element in the second region of the gate insulating film is located at the interface between the second region and the low resistance region or within 10 nm of the interface in the second region. . Effect of the Invention

[0018] According to the present disclosure, it is possible to improve the reliability of a semiconductor device by achieving both a low resistance during on-state operation and suppression of a decrease in the breakdown voltage of a gate insulating film during off-state operation.

[0019] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0020] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1A to 1C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Diagram 3] 1A to 1C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 4] 1A to 1C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Diagram 5] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the second embodiment. [Figure 6] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the second embodiment. [Figure 7] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the second embodiment. [Figure 8] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the second embodiment. [Figure 9] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the second embodiment. [Figure 10] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing the results of a device simulation showing the relationship between the fixed charge in the gate oxide film and the electric field passing through the gate oxide film on the JFET region according to the second embodiment. [Figure 12] FIG. 11 is a diagram showing the result of a device simulation showing the relationship between the fixed charge in the gate oxide film and the current passing through the gate oxide film on the JFET region according to the second embodiment. [Figure 13] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 14] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 15] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the fourth embodiment. [Figure 16] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the fourth embodiment. [Figure 17] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the fourth embodiment. [Figure 18] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the fourth embodiment. [Figure 19] 11A to 11C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to the fourth embodiment. [Figure 20] 13 is a flowchart showing an example of a method for manufacturing a module including the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Note that the drawings are shown in a schematic manner, and the size and positional relationship of images shown in different drawings are not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description thereof may be omitted.

[0022] In the following description, terms that indicate specific positions and directions, such as "top", "bottom", "side", "bottom", "front" or "back", may be used. These terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0023] In the present disclosure, the term "fixed charge" refers to a substance that does not substantially move during operation of the semiconductor device according to the present disclosure in the practical temperature range, and is in a positively or negatively charged state, or is in a positively or negatively charged state, etc. The fixed charge may be, for example, a charged state caused by crystal distortion or defects, a charged state caused by distortion or defects of interatomic bonds, a positively or negatively charged atom, molecule, particle, microcrystal, etc., a positively charged state caused by electrons being released from a donor level created by impurities, etc., or a negatively charged state caused by electrons being captured at an acceptor level, etc.

[0024] <Embodiment 1> <Configuration> 1 is a cross-sectional view showing an example of a configuration of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 is an n-channel SiC-MOSFET.

[0025] 1, an n-type drift layer 3 is formed on an n-type (first conductivity type) silicon carbide substrate 1. A p-type (second conductivity type) well region 6 is selectively formed on a surface layer of the drift layer 3.

[0026] An n-type source region 5 is formed on the surface layer of the well region 6, and a p-type well contact region 9 is formed adjacent to the source region 5. The well contact region 9 is provided to equalize the potential of the source region 5 and the well region 6. By providing the well contact region 9, the operation of a parasitic transistor can be suppressed.

[0027] A low-resistance region 20 having an impurity concentration higher than the impurity concentration of the drift layer 3 is formed in a surface layer of the drift layer 3 between adjacent well regions 6 in a plan view. The low-resistance region 20 is included in the JFET region 4.

[0028] The drift layer 3 , the source region 5 , the well region 6 , the well contact region 9 , and the low resistance region 20 constitute the semiconductor layer 2 .

[0029] An insulating gate insulating film 7 is formed from a part on the source region 5 to the drift layer 3, and a gate electrode 8 is formed on the gate insulating film 7. In order to separate the gate electrode 8 from the source electrode 11, an interlayer insulating film 13 is formed so as to cover the gate electrode 8. The interlayer insulating film 13 is not formed on the well contact region 9 in order to provide a contact hole 31. A barrier metal 32 is formed on the interlayer insulating film 13 and the well contact region 9. A source electrode 11 is formed on the barrier metal 32. In addition, a drain electrode 12 is formed on the back surface of the silicon carbide substrate 1.

[0030] Nitrogen is present at the interface between the gate insulating film 7 and the well region 6, and a positive fixed charge 41 is provided by the nitrogen. Nitrogen is also present at the interface between the gate insulating film 7 and a JFET region 4 described later, and a positive fixed charge 40 is provided by the nitrogen. The fixed charge 41 is provided in the gate insulating film 7 near the interface between the gate insulating film 7 and the well region 6. The fixed charge 40 is provided in the gate insulating film 7 near the interface between the gate insulating film 7 and the JFET region 4. The gate insulating film 7 includes a first region in contact with the well region 6 and a second region in contact with the JFET region 4. The interface between the gate insulating film 7 and the JFET region 4 is synonymous with the interface between the gate insulating film 7 and the low-resistance region 20.

[0031] The nitrogen concentration at the interface between the gate insulating film 7 and the JFET region 4 is higher than the nitrogen concentration at the interface between the gate insulating film 7 and the well region 6. In other words, the fixed charges 40 at the interface between the gate insulating film 7 and the JFET region 4 have a higher density than the fixed charges 41 at the interface between the gate insulating film 7 and the well region 6.

[0032] The characteristics of a MOSFET during on-state operation when a gate voltage is applied to the gate electrode are determined by the amount of carriers formed at the gate insulating film interface on the well region and their mobility. For example, as disclosed in Patent Document 4, the interface between the gate insulating film and the well region in a conventional SiC-MOSFET has a high interface state density, and the channel mobility of the MOSFET is extremely low, so the channel resistance increases and the on-resistance increases accordingly. As a countermeasure to such problems, Patent Document 4 improves the characteristics by applying a process technology that introduces an appropriate amount of nitrogen into the interface between the gate insulating film and the well region. However, as the nitrogen concentration introduced into the interface between the gate insulating film and the well region increases, the amount of positive fixed charge also increases, and a new problem occurs in that the threshold voltage drops drastically when the concentration is set high. Therefore, there is an upper limit to the nitrogen concentration introduced into the interface between the gate insulating film and the well region.

[0033] On the other hand, although the resistance value of the JFET region affects the on-characteristics of the MOSFET, the amount of fixed charge at the interface between the gate insulating film and the JFET region does not directly affect the characteristics of the MOSFET. During off-state operation, the reliability of the gate insulating film must be taken into consideration, and it is effective to provide a higher concentration of nitrogen at the interface between the gate insulating film and the JFET region than the nitrogen concentration that limits the characteristics of the MOSFET.

[0034] <Operation of the semiconductor device 100> The operation of the semiconductor device 100 will now be described.

[0035] In the semiconductor device 100, when a positive voltage is applied to the gate electrode 8, a current path is formed at the interface between the gate electrode 8 and the gate insulating film 7 in the well region 6. When a positive voltage is applied to the drain electrode 12 in this state, a current flows from the drain electrode 12 through the silicon carbide substrate 1, the drift layer 3, the well region 6, and the source region 5 to the source electrode 11.

[0036] In particular, in the semiconductor device 100 using a wide band gap semiconductor material such as SiC, the drift layer 3 can be made highly concentrated and thin, and has low resistance, so reducing the resistance (JFET resistance) of the current path (JFET region 4) between adjacent well regions 6 in a planar view and the resistance (channel resistance) of the channel portion is very effective in reducing the conduction loss of the semiconductor device 100.

[0037] On the other hand, when the positive voltage applied to the gate electrode 8 is removed or a negative voltage is applied to the gate electrode 8, the well region 6 near the interface with the gate insulating film 7 is depleted. This makes it possible to cut off the current between the drain electrode 12 and the source electrode 11 even when a high voltage is applied to the drain electrode 12.

[0038] At this time, the gate insulating film 7 is exposed to a high electric field, but since positive fixed charges 40 are formed at the interface between the gate insulating film 7 and the JFET region 4 where the electric field is most concentrated, the amount of holes flowing in from the drift layer 3 due to the electric field applied to the gate insulating film 7 can be reduced, and the reliability of the gate insulating film 7 is ensured. In particular, when SiC is used as a semiconductor material, the dielectric breakdown field becomes large, so that the drift layer 3 is often designed to be applied with a high electric field, and the electric field strength applied to the gate insulating film 7 also becomes large accordingly. Therefore, the structure of the semiconductor device 100 according to the first embodiment is effective from the viewpoint of ensuring the reliability of the gate insulating film 7, since the positive fixed charges 40 suppress the inflow of holes.

[0039] <Method of Manufacturing Semiconductor Device 100> A method for manufacturing the semiconductor device 100 will be described with reference to FIGS.

[0040] 2, an n-type low-resistance silicon carbide substrate 1 is prepared (first step), and an n-type drift layer 3 is formed on the silicon carbide substrate 1 by epitaxial growth (second step). In the first embodiment, the n-type impurity concentration of the drift layer 3 is 1×10 13 cm -3 ~1×10 18 cm -3The thickness of the drift layer 3 is set to 4 μm to 200 μm.

[0041] 3, p-type well regions 6 spaced apart from each other are selectively formed in the surface layer of the drift layer 3 (third step). Then, n-type source regions 5 are selectively formed in the surface layer of the well regions 6 (fourth step). Specifically, using a resist or an oxide film processed by photolithography as a mask, Al ions are implanted to form the p-type well regions 6, and N ions are implanted to form the n-type source regions 5.

[0042] The impurity concentration in the well region 6 is 1×10 15 cm -3 ~1×10 18 cm -3 The implantation depth of the Al ions implanted when forming the well region 6 is about 0.3 μm to 2.0 μm.

[0043] The source region 5 is formed so that its bottom surface is not deeper than the bottom surface of the well region 6. The impurity concentration in the source region 5 is higher than the impurity concentration in the well region 6 and is 1×10 17 cm -3 ~1×10 21 cm -3 That's about it.

[0044] A well contact region 9 is formed in a surface layer of the well region 6 so as to be adjacent to the source region 5 in a plan view. The impurity concentration of the well contact region 9 is higher than the impurity concentration of the well region 6.

[0045] In a region where no well region 6 is formed, i.e., in the surface layer of the drift layer 3 and between adjacent well regions 6 in a plan view, an n-type low resistance region 20 is formed (fifth step). Specifically, N ions are implanted to form the n-type low resistance region 20. The impurity concentration in the low resistance region 20 is 1×10 18 cm -3 ~1×10 21 cm -3The implantation depth of N ions implanted when forming the low-resistance region 20 is 0.3 μm to 1.0 μm. The impurity concentration of the low-resistance region 20 becomes higher as it approaches the gate insulating film 7 in the depth direction. By forming the low-resistance region 20, the impurity concentration in the vicinity of the outermost surface of the drift layer 3 becomes high, and the JFET resistance can be reduced.

[0046] Next, annealing is performed in an inert gas atmosphere such as Ar gas using a heat treatment device. The annealing is performed at 1300°C to 1900°C for about 30 seconds to 1 hour. By performing this annealing, the ion-implanted n-type impurities such as N and p-type impurities such as Al are activated.

[0047] Next, as shown in FIG. 4, a gate insulating film 7 and a gate electrode 8 are formed (sixth and seventh steps). The gate insulating film 7 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 7 may be formed by a deposition method, or by performing a heat treatment in a nitrogen or ammonia atmosphere after the formation of the gate insulating film 7. The gate insulating film 7 may also be formed by performing high-temperature annealing on the surface of the drift layer 3 in a hydrogen atmosphere before the formation of the gate insulating film 7.

[0048] Specifically, a silicon dioxide film is formed by thermal oxidation in a high-temperature oxidizing atmosphere to form the gate insulating film 7. Alternatively, after a silicon dioxide deposition film is formed by CVD (Chemical Vapor Deposition), the gate insulating film 7 is formed by nitriding the silicon dioxide film in a high-temperature ammonia (NH3), nitrous oxide (N2O) gas atmosphere, or nitric oxide (NO) gas atmosphere.

[0049] In the step of forming the gate insulating film 7, positive fixed charges 41 are formed at the interface between the gate insulating film 7 and the well region 6, and positive fixed charges 40 are formed at the interface between the gate insulating film 7 and the JFET region 4. Since a high concentration of nitrogen is implanted into the drift layer 3 (low resistance region 20) of the JFET region 4 before the gate insulating film 7 is formed, more nitrogen is segregated therein than at the interface between the gate insulating film 7 and the well region 6. A higher concentration of positive fixed charges 40 is formed at the interface between the gate insulating film 7 and the JFET region 4, where nitrogen is segregated at a high concentration, than at the interface between the gate insulating film 7 and the well region 6.

[0050] Since the gate insulating film 7 is formed in the same oxidation process, the thickness of the gate insulating film 7 formed on the well region 6 is approximately the same as that of the gate insulating film 7 formed on the JFET region 4. However, if a high concentration of impurities is injected into the low-resistance region 20 before forming the gate insulating film 7, an injection damage layer is formed in the surface layer of the drift layer 3, and the gate insulating film 7 formed on the JFET region 4 can be thickened by accelerated oxidation caused by oxidizing the injection damage layer.

[0051] The gate electrode 8 is formed by depositing polysilicon by a CVD method and etching it using a resist processed by photolithography as a mask. The polysilicon may contain impurities such as phosphorus and boron. By containing impurities in the gate electrode 8, it is possible to realize a low resistance of the gate electrode 8.

[0052] Finally, an interlayer insulating film 13 is formed, followed by forming a source electrode 11 and a drain electrode 12, thereby completing a high-voltage MOSFET (semiconductor device 100) as shown in FIG. 1 (tenth and eleventh steps).

[0053] The wiring for extracting the gate electrode 8 and the source electrode 11 are formed by depositing metals such as Al, Cu, Ti, Ni, Mo, W, Ta, their nitrides, their laminated films, and their alloy layers by sputtering or vapor deposition, and then patterning them. The drain electrode 12 is formed by sputtering or vapor deposition of a metal film such as Ti, Ni, Ag, or Au.

[0054] <Embodiment 2> In the first embodiment, in the semiconductor device 100, the gate insulating film 7 on the well region 6 and the gate insulating film 7 on the JFET region 4 are formed in the same process. In the second embodiment, an example in which the gate insulating film on the JFET region 4 is formed in multiple processes so as to be thicker than the gate insulating film on the well region 6 will be described.

[0055] <Method of Manufacturing Semiconductor Device 101> A method for manufacturing the semiconductor device 101 according to the second embodiment will be described with reference to FIGS.

[0056] 5, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed by epitaxial growth on the silicon carbide substrate 1. In the second embodiment, the n-type impurity concentration in the drift layer 3 is 1×10 13 cm -3 ~1×10 18 cm -3 The drift layer 3 has a thickness of 4 μm to 200 μm.

[0057] 6, p-type well regions 6 spaced apart from each other are formed in the surface layer of the drift layer 3. Then, n-type source regions 5 are formed in the surface layer of the well regions 6. Specifically, using a resist or an oxide film processed by photolithography as a mask, Al ions are implanted to form the p-type well regions 6, and N ions are implanted to form the n-type source regions 5.

[0058] The impurity concentration in the well region 6 is 1×10 15 cm -3~1×10 18 cm -3 The implantation depth of the Al ions implanted when forming the well region 6 is about 0.3 μm to 2.0 μm.

[0059] The source region 5 is formed so that its bottom surface is not deeper than the bottom surface of the well region 6. The impurity concentration in the source region 5 is higher than the impurity concentration in the well region 6 and is 1×10 17 cm -3 ~1×10 21 cm -3 That's about it.

[0060] A well contact region 9 is formed in a surface layer of the well region 6 so as to be adjacent to the source region 5 in a plan view. The impurity concentration of the well contact region 9 is higher than the impurity concentration of the well region 6.

[0061] An n-type low resistance region 20 is formed in a region where no well region 6 is formed, i.e., in the surface layer of the drift layer 3 and between adjacent well regions 6 in a plan view. Specifically, N ions are implanted to form the n-type low resistance region 20. The impurity concentration in the low resistance region 20 is 1×10 18 cm -3 ~1×10 21 cm -3 The implantation depth of N ions implanted when forming low-resistance region 20 is 0.3 μm to 1.0 μm. By forming low-resistance region 20, the impurity concentration in the vicinity of the outermost surface of drift layer 3 becomes high, and the JFET resistance can be reduced.

[0062] Next, annealing is performed in an inert gas atmosphere such as Ar gas using a heat treatment device. The annealing is performed at 1300°C to 1900°C for about 30 seconds to 1 hour. By performing this annealing, the ion-implanted n-type impurities such as N and p-type impurities such as Al are activated.

[0063] 7, a gate insulating film 15 (first gate insulating film) is formed. The gate insulating film 15 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 15 may be formed by a deposition method, or may be formed by performing a heat treatment in a nitrogen or ammonia atmosphere after the gate insulating film 15 is formed. The gate insulating film 15 may also be formed by performing high-temperature annealing on the surface of the drift layer 3 in a hydrogen atmosphere before the gate insulating film 15 is formed.

[0064] Specifically, the gate insulating film 15 is formed by forming a silicon dioxide film by thermal oxidation in a high-temperature oxidizing atmosphere. Alternatively, after forming a silicon dioxide deposition film by CVD, the gate insulating film 15 is formed by nitriding in a high-temperature ammonia atmosphere (NH3), nitrous oxide (N2O) gas atmosphere, or nitric oxide (NO) gas atmosphere. By performing the step of forming the gate insulating film 15, positive fixed charges are formed at the interface between the gate insulating film 15 and the well region 6 and at the interface between the gate insulating film 15 and the JFET region 4.

[0065] Thereafter, using a resist or an oxide film processed by photolithography as a mask, only the gate insulating film 15 on the JFET region 4 is left and the other gate insulating film 15 is removed (step 8). The gate insulating film 15 may be removed by a wet process using hydrofluoric acid or by dry etching.

[0066] Next, as shown in FIG. 8, a gate insulating film 16 (second gate insulating film) is formed by dry thermal oxidation at 1150° C. or higher (ninth step). The gate insulating film 16 may be formed by a deposition method. After the gate insulating film 16 is formed, a heat treatment is performed in a nitrogen or ammonia atmosphere. By performing the step of forming the gate insulating film 16, it is possible to thicken only the gate insulating film on the JFET region 4. That is, the gate insulating film formed on the JFET region 4 is two layers, the gate insulating films 15 and 16, and is thicker than the gate insulating film 16 formed outside the JFET region 4.

[0067] Since nitrogen is introduced into the interface between the gate insulating film 15 and the JFET region 4 by the two nitridation steps, the nitrogen concentration is higher than that at the interface between the gate insulating film 16 and the well region 6. Therefore, the positive fixed charges 40 at the interface between the gate insulating film 15 and the JFET region 4 have a higher density than the positive fixed charges 41 at the interface between the gate insulating film 16 and the well region 6.

[0068] The subsequent steps are the same as those in the first embodiment. As shown in Fig. 9, the gate electrode 8 is formed by depositing polysilicon by a CVD method and etching it using a resist processed by photolithography as a mask. The polysilicon may contain impurities such as phosphorus and boron. By containing impurities in the gate electrode 8, it is possible to realize a low resistance of the gate electrode 8.

[0069] Finally, an interlayer insulating film 13 is formed, and then a source electrode 11 and a drain electrode 12 are formed, thereby completing a high-voltage MOSFET (semiconductor device 101) as shown in FIG.

[0070] The wiring for extracting the gate electrode 8 and the source electrode 11 are formed by depositing metals such as Al, Cu, Ti, Ni, Mo, W, Ta, their nitrides, their laminated films, and their alloy layers by sputtering or vapor deposition, and then patterning them. The drain electrode 12 is formed by sputtering or vapor deposition of a metal film such as Ti, Ni, Ag, or Au.

[0071] <Hole current injected into the gate oxide film> Fig. 11 shows the result of a device simulation showing the relationship between the fixed charge of the gate oxide film and the electric field passing through the gate oxide film on the JFET region according to the second embodiment. Fig. 12 shows the result of a device simulation showing the relationship between the fixed charge of the gate oxide film and the current passing through the gate oxide film on the JFET region according to the second embodiment. Here, the gate oxide film corresponds to the gate insulating film 15. The current passing through the gate oxide film refers to the hole current injected into the gate oxide film.

[0072] Gate oxide film thickness (T OX ) are two types, 40 nm and 60 nm, and the results of calculations for three types of fixed charge at the interface between the gate oxide film and the JFET region, positive, negative, and zero, are compared.

[0073] As shown in Figure 11, thickening the gate oxide film reduces the electric field. Also, as shown in Figure 12, when we look at the hole current that affects the breakdown life of the gate oxide film, we can see that a positive fixed charge is effective. The amount of hole current injected into the gate oxide film can be set based on the relationship between the film thickness of the gate oxide film on the JFET region 4 and the fixed charge. Figures 11 and 12 show that it is most effective to thicken the gate oxide film and set a positive fixed charge.

[0074] <Embodiment 3> In the semiconductor device 100 according to the first embodiment, the gate insulating film 7 on the well region 6 and the gate insulating film 7 on the JFET region 4 are formed in the same process, have approximately the same film thickness, and have different amounts of positive fixed charges. In the semiconductor device 102 according to the third embodiment, an example will be described in which the gate insulating film 7 on the JFET region 4 is formed by an enhanced oxidation technique to be significantly thicker than the gate insulating film 7 on the well region 6.

[0075] <Method of Manufacturing Semiconductor Device 102> A method for manufacturing a semiconductor device 102 according to the second embodiment will be described with reference to FIGS.

[0076] 13, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed on the silicon carbide substrate 1 by epitaxial growth. In the first embodiment, the n-type impurity concentration of the drift layer 3 is 1×10 13 cm -3 ~1×10 18 cm -3 The thickness of the drift layer 3 is set to 4 μm to 200 μm.

[0077] 14, p-type well regions 6 spaced apart from each other are formed in the surface layer of the drift layer 3. Then, n-type source regions 5 are formed in the surface layer of the well regions 6. Specifically, using a resist or an oxide film processed by photolithography as a mask, Al ions are implanted to form the p-type well regions 6, and N ions are implanted to form the n-type source regions 5.

[0078] An n-type low resistance region 20 is formed in a region where no well region 6 is formed, i.e., in the surface layer of the drift layer 3 and between adjacent well regions 6 in a plan view. Specifically, N ions are implanted to form the n-type low resistance region 20. The impurity concentration in the low resistance region 20 is 1×10 18 cm -3 ~1×10 21 cm -3 The implantation depth of N ions implanted when forming low-resistance region 20 is 0.3 μm to 1.0 μm. By forming low-resistance region 20, the impurity concentration in the vicinity of the outermost surface of drift layer 3 becomes high, and the JFET resistance can be reduced.

[0079] Then, a 1×10 ion implantation was performed on the outermost surface of the drift layer 3 (low resistance region 20) of the JFET region 4 to a depth of about 20 nm. 19 cm -3 ~1×10 21 cm -3 N ions are implanted at low energy so that the thickness of the implanted layer is about 20 nm. Since the implanted layer is about 20 nm, in the subsequent step of forming the gate insulating film 7, the region where the N ions are implanted is entirely oxidized to become the gate insulating film 7. The presence of this implanted layer makes the accelerated oxidation more pronounced, and it becomes possible to form a thicker gate insulating film 7 on the JFET region 4.

[0080] In addition, instead of implanting N ions to a depth of about 20 nm from the surface of the drift layer 3 (JFET region 4, low resistance region 20), silicon, oxygen, and fluorine are simultaneously implanted to a concentration of 1×10 19 cm -3 ~1×10 21 cm -3In this case, a larger implantation damage layer can be formed in the implantation region on the surface, so that the gate insulating film 7 on the JFET region 4 can be formed thicker.

[0081] By forming the gate insulating film 7 so that the outermost surface of the drift layer 3 (i.e., the JFET region 4, low-resistance region 20) has the highest concentration, the concentration of N ions at the interface between the gate insulating film 7 and the JFET region 4 becomes high in the JFET region 4. To reduce the concentration of the JFET region 4, the impurity profile in the depth direction of the JFET region 4 does not need to be uniform, and low resistance is possible if there is even a partially high-concentration region.

[0082] The subsequent steps are the same as those in the first or second embodiment.

[0083] <Nitrogen concentration peak position> As described in the first to third embodiments, before the gate insulating film is formed, nitrogen is implanted into the JFET region, and the implanted JFET region is oxidized to form the gate insulating film, and nitrogen is segregated at the interface between the gate insulating film and the JFET region.

[0084] In addition, after the gate insulating film is formed, a nitriding process or the like is performed to segregate nitrogen at the interface between the gate insulating film and the JFET region. In either of these manufacturing methods, forming a nitrogen concentration peak on the gate insulating film side near the interface between the gate insulating film and the JFET region is the most effective way to form positive fixed charges. The vicinity of the interface between the gate insulating film and the JFET region includes the interface or the gate insulating film side about 10 nm from the interface.

[0085] <Fourth embodiment> In the first to third embodiments, a positive fixed charge is set by nitrogen at the interface between the gate insulating film and the JFET region. In the fourth embodiment, an impurity other than nitrogen will be described.

[0086] <Method of Manufacturing the Semiconductor Device 103> A method for manufacturing a semiconductor device 103 according to the fourth embodiment will be described with reference to FIGS.

[0087] 15, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed by epitaxial growth on the silicon carbide substrate 1. In this embodiment, the n-type impurity concentration of the drift layer 3 is 1×10 13 cm -3 ~1×10 18 cm -3 The thickness is set to 4 μm to 200 μm.

[0088] 15, an n-type low-resistance silicon carbide substrate 1 is prepared, and an n-type drift layer 3 is formed on the silicon carbide substrate 1 by epitaxial growth. In the present embodiment 1, the n-type impurity concentration of the drift layer 3 is 1×10 13 cm -3 ~1×10 18 cm -3 The thickness of the drift layer 3 is set to 4 μm to 200 μm.

[0089] 16, p-type well regions 6 spaced apart from each other are formed in the surface layer of the drift layer 3. Then, n-type source regions 5 are formed in the surface layer of the well regions 6. Specifically, using a resist or an oxide film processed by photolithography as a mask, Al ions are implanted to form the p-type well regions 6, and N ions are implanted to form the n-type source regions 5.

[0090] An n-type low resistance region 20 is formed in a region where no well region 6 is formed, i.e., in the surface layer of the drift layer 3 and between adjacent well regions 6 in a plan view. Specifically, N ions are implanted to form the n-type low resistance region 20. The impurity concentration in the low resistance region 20 is 1×10 18 cm -3 ~1×10 21 cm -3The implantation depth of N ions implanted when forming low-resistance region 20 is 0.3 μm to 1.0 μm. By forming low-resistance region 20, the impurity concentration in the vicinity of the outermost surface of drift layer 3 becomes high, and the JFET resistance can be reduced.

[0091] Next, annealing is performed in an inert gas atmosphere such as Ar gas using a heat treatment device. The annealing is performed at 1300°C to 1900°C for about 30 seconds to 1 hour. By performing this annealing, the ion-implanted n-type impurities such as N and p-type impurities such as Al are activated.

[0092] Next, as shown in FIG. 17, the gate insulating film 17 is formed. The gate insulating film 17 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 17 may also be formed by deposition. Cesium (Cs) ions are implanted into the formed gate insulating film 17. Then, annealing is performed before the step of forming the semiconductor exposed region, and the cesium that becomes a region containing fixed charge due to thermal diffusion is redistributed to a region closer to the semiconductor.

[0093] Thereafter, using a resist processed by photolithography as a mask, the other insulating films are removed, leaving only the gate insulating film 17 on the JFET region 4. The gate insulating film 17 may be removed by a wet process using hydrofluoric acid, or may be removed by dry etching.

[0094] Next, as shown in FIG. 18, the gate insulating film 18 is formed by dry thermal oxidation at 1150° C. or higher. The gate insulating film 18 is formed by a deposition method at about 700° C. to 900° C. After the gate insulating film 18 is formed, a heat treatment is performed in a nitrogen or ammonia atmosphere. By performing the step of forming the gate insulating film 18, only the gate insulating films 17 and 18 on the JFET region 4 become thick and become insulating films containing cesium. The gate insulating film 17 contains an element different from the gate insulating film 18.

[0095] The subsequent steps are the same as those in the second embodiment. As shown in Fig. 19, the gate electrode 8 is formed by depositing polysilicon by a CVD method and etching it using a resist processed by photolithography as a mask. The polysilicon may contain impurities such as phosphorus and boron. By containing impurities in the gate electrode 8, it is possible to realize a low resistance of the gate electrode 8.

[0096] In the above description, a case has been described in which cesium is implanted as an impurity (element) that becomes a fixed charge into the gate insulating film 17 on the JFET region 4, but the present invention is not limited to this. By making the gate insulating film 17 on the JFET region 4 contain at least one of barium (Ba), rubidium (Rb), and strontium (Sr), the formation of a fixed charge in the gate insulating film 17 can be realized.

[0097] Cesium, barium, rubidium, and strontium belong to the alkali metal or alkaline earth metal group, and therefore have a small first ionization energy and tend to become positively charged ions. Also, unlike light elements such as sodium, which are mobile even at room temperature, cesium, barium, rubidium, and strontium have large atomic numbers, so their charges do not move in the normal device operating temperature range. Therefore, cesium, barium, rubidium, and strontium are materials that act as positive fixed charges.

[0098] In FIG. 17, the case where the gate insulating film 17 is silicon oxide has been described. However, materials (insulating materials) having a higher dielectric constant than silicon oxide include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3, Al2O, etc.), tantalum oxide (Ta2O5), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), aluminum oxynitride (AlO x N y ), tantalum oxynitride (TaO x N y), and those having a composite composition of these materials (hafnium aluminate oxide, hafnium aluminate oxynitride, etc.), or those containing elements contained in semiconductor substrates such as silicon (hafnium oxide silicate, hafnium aluminate silicate). Also, it may be a laminated film of silicon oxide and a material having a higher dielectric constant than silicon oxide, or a laminated film of silicon oxynitride and a material having a higher dielectric constant than silicon oxide. These laminated films may contain cesium, barium, rubidium, or strontium.

[0099] 18, the gate insulating film 18 is silicon oxide, but the material with a high dielectric constant may be hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, hafnium oxynitride, zirconium oxynitride, aluminum oxynitride, tantalum oxynitride, or a composite composition of these materials (hafnium aluminate oxide, hafnium aluminate oxynitride, etc.), or a material containing an element contained in a semiconductor substrate such as silicon (hafnium oxide silicate, hafnium aluminate silicate).Furthermore, the material may be a laminated film of silicon oxide and a material with a higher dielectric constant than silicon oxide, or a laminated film of silicon oxynitride and a material with a higher dielectric constant than silicon oxide.

[0100] In the case of a laminated film, a silicon oxide film or a silicon oxynitride film is used as the film in contact with the silicon carbide substrate 1. The interface between the gate insulating film 18 and the well region 6 becomes the channel of the MOSFET, and therefore, by preventing deterioration of the carrier mobility, a lower resistance can be achieved.

[0101] In the above, a structure has been described in which the gate insulating films 17, 18 are deposited on the JFET region 4 in two or more steps to make the gate insulating film thicker than the gate insulating film 18 on the well region 6. Since the amount of fixed charge formed in the gate insulating film 17 can be controlled by the dose of an element introduced into the gate insulating film 17, if the gate insulating film 17 on the JFET region 4 is dosed with a high concentration of an element, it can be made to have the same thickness as the gate insulating film 18 on the well region 6. However, in this case, the gate insulating film 18 is not formed on the JFET region 4, and only the gate insulating film 17 is formed.

[0102] <Evaluation of Electrical Characteristics of Semiconductor Device 103> After forming the MOSFET on the silicon carbide substrate 1, a module is formed. After the MOSFET is formed, the electrical characteristics of the MOSFET are evaluated to determine the quality of the element (semiconductor device 103). The MOSFET is then cut (diced) and divided into individual elements (chips). When assembling a power module, good elements are used. A good element is an element that meets the expected characteristics when the electrical characteristics of the MOSFET are evaluated.

[0103] 20 is a flowchart showing an example of a method for manufacturing a module including the semiconductor device 103 according to embodiment 4. Note that, although a method for manufacturing a module including the semiconductor device 103 according to embodiment 4 will be described here, the same method can be used for manufacturing modules including each of the semiconductor devices 100, 101, and 102 described in embodiments 1 to 3.

[0104] In step S101, a MOSFET is formed on a silicon carbide substrate 1.

[0105] In step S102, the electrical characteristics of the MOSFET are evaluated.

[0106] In step S103, an electrical stress is applied to the interface between the gate insulating film 17 and the JFET region 4 in the MOSFET to form a fixed charge.

[0107] In step S104, a wafer on which a plurality of semiconductor devices 103 are formed is diced to extract one semiconductor device 103 (chip).

[0108] In step S105, the chips are selected based on the electrical characteristics evaluated in step S102.

[0109] In step S106, a power module is assembled using the chips selected in step S105.

[0110] The method of applying electrical stress in step S103 will be described. The source electrode 11 and the gate electrode 8 are shorted to 0 V. A voltage of 80% of the MOSFET's element breakdown voltage is applied to the drain electrode 12 for several seconds to several hours (step 12). This voltage may be applied at room temperature or at a high temperature of about 150°C.

[0111] Under the above voltage conditions, since there is no potential difference between the source electrode 11 and the gate electrode 8, no stress is applied to the gate insulating film 18 in the channel region. On the other hand, electrical stress is applied to the gate insulating film 17 on the JFET region 4 by the drain electric field. This stress allows positive fixed charges 40 to be formed only on the JFET region 4, that is, only at the interface between the gate insulating film 17 and the JFET region 4. Since the amount of charge increases with the voltage application time, the time and temperature for forming the designed amount of charge can be selected. If it is desired to shorten the application time and increase the throughput, a high temperature is applied. It may also be applied to multiple elements simultaneously.

[0112] Within the scope of the present disclosure, the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0113] Although the present disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned. [Explanation of symbols]

[0114] 1 silicon carbide substrate, 2 semiconductor layer, 3 drift layer, 4 JFET region, 5 source region, 6 well region, 7 gate insulating film, 8 gate electrode, 9 well contact region, 11 source electrode, 12 drain electrode, 13 interlayer insulating film, 15 gate insulating film, 16 gate insulating film, 17 gate insulating film, 18 gate insulating film, 20 low resistance region, 31 contact hole, 32 barrier metal, 40 fixed charge, 41 fixed charge, 100 semiconductor device.

Claims

1. a silicon carbide substrate of a first conductivity type; a drift layer of a first conductivity type formed on the silicon carbide substrate; a plurality of well regions of a second conductivity type selectively formed on a surface layer of the drift layer; a first conductivity type source region selectively formed on a surface layer of each of the well regions; a low-resistance region that is formed in a surface layer of the drift layer between adjacent well regions in a plan view and has an impurity concentration higher than an impurity concentration of the drift layer; a gate insulating film formed over the source region, each of the well regions, and the low resistance region; a gate electrode formed on the gate insulating film; Equipped with the gate insulating film includes a first region in contact with each of the well regions and a second region in contact with the low resistance region; a density of positive fixed charges in the second region is higher than a density of positive fixed charges in the first region; the second region of the gate insulating film contains an element different from the first region of the gate insulating film, a concentration peak of the element in the second region of the gate insulating film is located at an interface between the second region and the low resistance region, or within 10 nm of the interface in the second region.

2. 2. The semiconductor device according to claim 1, wherein the element in the second region of the gate insulating film includes at least one of cesium, barium, strontium, and rubidium.

3. A first conductivity type silicon carbide substrate; a drift layer of a first conductivity type formed on the silicon carbide substrate; a plurality of well regions of a second conductivity type selectively formed on a surface layer of the drift layer; a first conductivity type source region selectively formed on a surface layer of each of the well regions; a low-resistance region that is formed in a surface layer of the drift layer between adjacent well regions in a plan view and has an impurity concentration higher than an impurity concentration of the drift layer; a gate insulating film formed over the source region, each of the well regions, and the low resistance region; a gate electrode formed on the gate insulating film; Equipped with the gate insulating film includes a first region in contact with each of the well regions and a second region in contact with the low resistance region; a density of positive fixed charges in the second region is higher than a density of positive fixed charges in the first region; The second region of the gate insulating film includes an insulating material different from that of the first region of the gate insulating film.

4. 4. The semiconductor device according to claim 3, wherein the insulating material in the second region of the gate insulating film includes at least one of silicon nitride, silicon oxynitride, hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, aluminum oxide, aluminum oxynitride, tantalum oxide, and tantalum oxynitride.

5. 5. The semiconductor device according to claim 1, wherein the low resistance region has an impurity concentration that increases toward the gate insulating film in a depth direction.

6. The semiconductor device according to claim 1 , wherein the second region of the gate insulating film is thicker than the first region of the gate insulating film.

7. 7. The semiconductor device according to claim 1, wherein a nitrogen concentration at an interface between the second region of the gate insulating film and the low resistance region is higher than a nitrogen concentration at an interface between the first region of the gate insulating film and each of the well regions.

8. A first step of preparing a silicon carbide substrate of a first conductivity type; a second step of forming a drift layer of a first conductivity type on the silicon carbide substrate; a third step of selectively forming a plurality of well regions of a second conductivity type in a surface layer of the drift layer; a fourth step of selectively forming a first conductivity type source region in a surface layer of each of the well regions; a fifth step of forming a low-resistance region having an impurity concentration higher than an impurity concentration of the drift layer between the well regions adjacent to each other in a plan view in a surface layer of the drift layer; a sixth step of forming a gate insulating film over the source region, the well regions, and the low resistance region; a seventh step of forming a gate electrode on the gate insulating film; Equipped with the gate insulating film includes a first region in contact with each of the well regions and a second region in contact with the low resistance region; a density of positive fixed charges in the second region is higher than a density of positive fixed charges in the first region; The sixth step comprises: an eighth step of forming a first gate insulating film only on the low resistance region; a ninth step of forming a second gate insulating film over the source region, each of the well regions, and the first gate insulating film after the eighth step; A method for manufacturing a semiconductor device comprising the steps of:

9. The method for manufacturing a semiconductor device according to claim 8 , wherein the first gate insulating film contains an insulating material different from that of the second gate insulating film.

10. A method for manufacturing a semiconductor device comprising: a first step of preparing a silicon carbide substrate of a first conductivity type; a second step of forming a drift layer of a first conductivity type on the silicon carbide substrate; a third step of selectively forming a plurality of well regions of a second conductivity type in a surface layer of the drift layer; a fourth step of selectively forming a first conductivity type source region in a surface layer of each of the well regions; a fifth step of forming a low-resistance region having an impurity concentration higher than an impurity concentration of the drift layer between the well regions adjacent to each other in a plan view in a surface layer of the drift layer; a sixth step of forming a gate insulating film over the source region, the well regions, and the low resistance region; a seventh step of forming a gate electrode on the gate insulating film; Equipped with the gate insulating film includes a first region in contact with each of the well regions and a second region in contact with the low resistance region; a density of positive fixed charges in the second region is higher than a density of positive fixed charges in the first region; a tenth step of forming a source electrode on the source region; An eleventh step of forming a drain electrode on a back surface of the silicon carbide substrate; a twelfth step of applying a voltage of 0 V or less to the source electrode and the gate electrode, and applying a voltage of 80% or more of a predetermined element breakdown voltage for 5 seconds or more; The method for manufacturing a semiconductor device further comprises:

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein in said twelfth step, a voltage of 0 V is applied to said source electrode and said gate electrode.

12. 12. The method for manufacturing a semiconductor device according to claim 8, wherein the fifth step includes a step of forming the low-resistance region by injecting a first conductivity type impurity a plurality of times with different injection energies into a surface layer of the drift layer and between the well regions adjacent to each other in a planar view.

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