Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device comprises a silicon carbide substrate having a first main surface and a second main surface on the opposite side from the first main surface. The silicon carbide substrate has a drift region, a body region, and a source region. The first main surface is provided with a gate trench defined by side surfaces passing through the source region and the body region to the drift region, and a bottom surface that is continuous with the side surfaces. The silicon carbide substrate furthermore has a first field relaxation region provided between the bottom surface and the second main surface, the first field relaxation region having a second conductivity type. The source region has a first region that contacts the side surfaces and has a first thickness, and a second region that sandwiches the first region against the side surfaces and has a second thickness that is greater than the first thickness. The silicon carbide substrate furthermore has a contact electrode having an ohmic bond with the second region.

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority to Japanese Application No. 2019-204196, filed on November 11, 2019, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] 2. Description of the Related Art As one type of silicon carbide semiconductor device, a trench-type metal oxide semiconductor field effect transistor (MOSFET) in which an electric field shielding region is provided below a gate trench formed in a main surface has been disclosed (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-41990 [Patent Document 2] Japanese Patent Application Publication No. 2017-139441 Summary of the Invention

[0005] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type. The first main surface includes a gate trench defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface. The silicon carbide substrate further includes a first electric field relaxation region having the second conductivity type and provided between the bottom surface and the second main surface. The source region includes a first region in contact with the side surface and having a first thickness, and a second region that sandwiches the first region between the side surface and the first region and has a second thickness greater than the first thickness. The silicon carbide semiconductor device further includes a contact electrode that is ohmic-contacted with the second region. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 2A] FIG. 2A is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2B] FIG. 2B is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 2C] FIG. 2C is a cross-sectional view (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 2D] FIG. 2D is a cross-sectional view (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2E] FIG. 2E is a cross-sectional view (part 5) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2F] FIG. 2F is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2G]FIG. 2G is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2H] FIG. 2H is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2I] FIG. 2I is a cross-sectional view (part 9) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2J] FIG. 2J is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2K] FIG. 2K is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2L] FIG. 2L is a cross-sectional view (part 12) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2M] FIG. 2M is a thirteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2N] FIG. 2N is a cross-sectional view (part 14) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2O] FIG. 2O is a cross-sectional view (part 15) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing an example of the relationship between a source region, a gate insulating film, a barrier metal film, and a contact electrode. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Problem that this disclosure aims to solve] To reduce costs, it is desirable to form the electric field shielding region shallower with respect to the main surface. However, in the configuration of conventional silicon carbide semiconductor devices, forming the electric field shielding region shallower results in degradation of characteristics.

[0008] In view of the above, an object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing costs while suppressing deterioration of characteristics.

[0009] [Effects of this disclosure] According to the present disclosure, it is possible to reduce costs while suppressing deterioration of characteristics.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are represented by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0012] [1] A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region to be separated from the drift region and having the first conductivity type, the first main surface having a gate trench defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the silicon carbide substrate further having a first electric field relief region having the second conductivity type provided between the bottom surface and the second main surface, the source region having a first region in contact with the side surface and having a first thickness, and a second region sandwiching the first region between the side surface and the first region and having a second thickness greater than the first thickness, and further having a contact electrode in ohmic contact with the second region.

[0013] The contact electrode is in ohmic contact with the second region. Even if a part of the second region is consumed during heat treatment for the ohmic contact, the consumption of the first region is suppressed. Therefore, the function of the source region can be ensured. Therefore, the peak depth of the effective concentration of the second conductive type impurity in the first electric field relaxation region based on the first main surface can be reduced, and excellent characteristics can be obtained. When the peak depth is small, regrowth of the epitaxial layer is not required after the formation of the first electric field relaxation region. Therefore, the cost associated with the regrowth of the epitaxial layer can be reduced. Furthermore, high-energy ion implantation is not required when forming the first electric field relaxation region. Therefore, the increase in cost associated with high-energy ion implantation can be avoided. Furthermore, the smaller the first thickness is, the more the short-circuit current is reduced and the short-circuit resistance can be improved. Furthermore, the smaller the area in contact with the side surface of the drift region is, the more the feedback capacitance is suppressed. By reducing the feedback capacitance, the switching loss can be reduced and the switching speed can be improved.

[0014] [2] In [1], the contact electrode may have a side end surface facing the gate trench in a direction parallel to the first main surface, and the side end surface may be spaced apart from the gate trench by a boundary surface between the first region and the second region when viewed in a plan view from a direction perpendicular to the first main surface. By having the side end surface spaced apart from the gate trench by a boundary surface, consumption of the first region can be more reliably suppressed.

[0015] [3] In the configuration of [2], the semiconductor device may further include a gate insulating film in contact with the side surface and the bottom surface, a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the silicon carbide substrate and the gate insulating film, and an interlayer insulating film provided so as to cover the gate electrode, and the gate insulating film or the interlayer insulating film may be in direct contact with the first region. By having the gate insulating film or the interlayer insulating film in direct contact with the first region, consumption of the first region can be more reliably suppressed.

[0016] [4] In any one of [1] to [3], the body region may have a third region having a first lower end surface connected to the side surface, and a fourth region having a second lower end surface connected to the first lower end surface, sandwiching the third region between the side surface and the fourth region, wherein a second distance of the second lower end surface from the first main surface is equal to or greater than a first distance of the first lower end surface from the first main surface, and the second lower end surface may overlap with the second region and be wider than the second region when viewed in a plan view perpendicular to the first main surface. By including a fourth region having a second lower end surface in the body region in addition to the third region having the first lower end surface, punch-through between the second region and the drift region can be suppressed.

[0017] [5] In [4], the silicon carbide substrate may further include a second electric field relaxation region having the second conductivity type and provided between the second lower end surface and the second main surface. By providing the second electric field relaxation region between the second lower end surface and the second main surface, it is possible to suppress dielectric breakdown of a gate insulating film and obtain an excellent dielectric strength voltage.

[0018] [6] In [5], the upper end surface of the second electric field buffer region and the second lower end surface may be in contact with each other. By having the upper end surface of the second electric field buffer region and the second lower end surface of the fourth region in contact with each other, it is possible to more reliably obtain an excellent dielectric strength voltage.

[0019] [7] In any of [1] to [6], the second thickness may be equal to or greater than 0.2 μm. By making the second thickness equal to or greater than 0.2 μm, a short circuit between the contact electrode and the body region can be more reliably suppressed.

[0020] [8] In any of [1] to [7], the second thickness may be 1.1 to 5.0 times the first thickness. By having the second thickness be 1.1 to 5.0 times the first thickness, it is possible to reduce costs while more reliably suppressing deterioration of characteristics.

[0021] [9] In any of [1] to [8], the first electric field buffer region may have a peak depth of an effective concentration of the second conductive type impurity of 1.0 μm or less with respect to the first main surface. By having the peak depth of the effective concentration of the second conductive type impurity of the first electric field buffer region of 1.0 μm or less with respect to the first main surface, it is possible to more reliably reduce costs.

[0022]

[10] In any one of [1] to [9], the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0023] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). Fig. 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to an embodiment.

[0024] As shown in FIG. 1, the MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type (first conductivity type). First main surface 1 of silicon carbide substrate 10 has a maximum diameter of, for example, 100 mm or more, and preferably 150 mm or more.

[0025] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0026] The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, a first electric field relief region 16, a second electric field relief region 17, and a contact region .

[0027] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 mainly includes, for example, a fifth region 11E, a sixth region 11F, and a seventh region 11G.

[0028] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type (second conductivity type) conductivity. The body region 12 mainly includes, for example, a third region 12C and a fourth region 12D.

[0029] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 13 constitutes the first main surface 1. The source region 13 mainly includes, for example, a first region 13A and a second region 13B.

[0030] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the contact region 18 is higher than the effective concentration of the p-type impurities in the body region 12. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact region 18 constitutes the first main surface 1. The effective concentration of the p-type impurities in the contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0031] The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, and the drift region 11 to the first electric field relaxation region 16. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the first electric field relaxation region 16. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. An angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The gate trench 5 extends, for example, in a stripe shape along a direction parallel to the first main surface 1. The gate trench 5 may extend in a honeycomb shape or may be scattered in an island shape.

[0032] The first electric field relaxation region 16 contains p-type impurities such as Al, and has p-type conductivity. The first electric field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the first electric field relaxation region 16 includes, for example, the bottom surface 4 of the gate trench 5. A part of the upper end surface of the first electric field relaxation region 16 faces a part of the lower end surface of the body region 12. The first electric field relaxation region 16 may be electrically connected to the source electrode 60. The effective concentration of the p-type impurity in the first electric field relaxation region 16 is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3or less. With respect to the first main surface 1, a peak depth D1 of the effective concentration of the p-type impurity in the first electric field buffer region 16 is, for example, 1.0 μm or less. The peak depth D1 may be 0.8 μm or more and 1.0 μm or less. The thickness of the first electric field buffer region 16 in a direction perpendicular to the first main surface 1 may be 0.4 μm or more and 0.6 μm or less.

[0033] The second electric field relaxation region 17 contains p-type impurities such as Al, and has p-type conductivity. The second electric field relaxation region 17 is in contact with the drift region 11. The second electric field relaxation region 17 may also be in contact with the body region 12. The second electric field relaxation region 17 is located closer to the second main surface 2 than the body region 12. The effective concentration of the p-type impurity in the second electric field relaxation region 17 may be approximately the same as the effective concentration of the p-type impurity in the first electric field relaxation region 16. The effective concentration of the p-type impurity in the second electric field relaxation region 17 is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3 The peak depth of the effective concentration of the p-type impurity in the second electric field buffer region 17 with respect to the first main surface 1 may be, for example, 1 μm or less. The thickness of the second electric field buffer region 17 in the direction perpendicular to the first main surface 1 may be 0.4 μm or more and 0.6 μm or less.

[0034] The fifth region 11E of the drift region 11 is sandwiched between the body region 12 and the first electric field relaxation region 16. The fifth region 11E is in contact with both the body region 12 and the first electric field relaxation region 16. The fifth region 11E is located closer to the second main surface 2 than the body region 12. The fifth region 11E is located closer to the first main surface 1 than the first electric field relaxation region 16. The effective concentration of n-type impurities in the fifth region 11E is, for example, 5×10 15 cm -3 5×10 or more 16 cm -3 The following is the result.

[0035] The sixth region 11F is located closer to the second major surface 2 than the fifth region 11E. The sixth region 11F is continuous with the fifth region 11E. The sixth region 11F is sandwiched between the first electric field relaxation region 16 and the second electric field relaxation region 17. The sixth region 11F is in contact with each of the first electric field relaxation region 16 and the second electric field relaxation region 17. The sixth region 11F, the first electric field relaxation region 16, and the second electric field relaxation region 17 may be located in the same plane parallel to the second major surface 2. The effective concentration of n-type impurities in the sixth region 11F may be higher than the effective concentration in the fifth region 11E. The effective concentration of n-type impurities in the sixth region 11F may be, for example, 5×10 16 cm -3 5×10 or more 17 cm -3 The following is the result.

[0036] The seventh region 11G is located closer to the second main surface 2 than the sixth region 11F. The seventh region 11G is continuous with the sixth region 11F. The seventh region 11G is in contact with each of the first electric field relaxation region 16 and the second electric field relaxation region 17. The seventh region 11G is located closer to the second main surface 2 than the first electric field relaxation region 16 and the second electric field relaxation region 17. The seventh region 11G may be sandwiched between the sixth region 11F and the silicon carbide single crystal substrate 50. The seventh region 11G may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the seventh region 11G may be lower than the effective concentration of n-type impurities in the sixth region 11F. The effective concentration of n-type impurities in the seventh region 11G may be, for example, 5×10 15 cm -3 5×10 or more 16 cm -3 The following is the result.

[0037] The third region 12C of the body region 12 is sandwiched between the source region 13 and the fifth region 11E in a direction perpendicular to the second major surface 2. The third region 12C is in contact with each of the source region 13 and the fifth region 11E. The third region 12C is located closer to the second major surface 2 than the source region 13. The third region 12C is located closer to the first major surface 1 than the fifth region 11E. The third region 12C is also in contact with the side surface 3. The third region 12C has a first lower end surface 93 connected to the side surface 3. The first lower end surface 93 is in contact with an upper end surface of the fifth region 11E. A distance H1 of the first lower end surface 93 from the first major surface 1 is, for example, not less than 0.2 μm and not more than 0.5 μm. The effective concentration of p-type impurities in the third region 12C is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3 The short channel effect (punch-through) can occur when a depletion layer spreads from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. By increasing the effective concentration of p-type impurities in the third region 12C, the spread of the depletion layer formed in the channel region can be reduced. The effective concentration of p-type impurities in the third region 12C may be higher than the effective concentration of n-type impurities in the fifth region 11E.

[0038] The fourth region 12D sandwiches the third region 12C between itself and the side surface 3 when viewed in a plan view from a direction perpendicular to the first main surface 1. That is, the third region 12C is sandwiched between the side surface 3 and the fourth region 12D in a direction parallel to the first main surface 1. The fourth region 12D is located on the side farther away from the gate trench 5 than the third region 12C. The fourth region 12D is sandwiched between the source region 13 and the second electric field relaxation region 17 in a direction perpendicular to the second main surface 2. The fourth region 12D is in contact with each of the contact region 18, the source region 13, the third region 12C, and the fifth region 11E. The fourth region 12D may further be in contact with the second electric field relaxation region 17. The fourth region 12D may further be in contact with the sixth region 11F. The fourth region 12D is located closer to the second main surface 2 than the source region 13. The fourth region 12D is located closer to the first main surface 1 than the second electric field buffer region 17. The fourth region 12D has a second lower end surface 94 connected to the first lower end surface 93. The second lower end surface 94 and the upper end surface 95 of the second electric field buffer region 17 may be in contact with each other. The second lower end surface 94 may be in contact with the upper end surface of the sixth region 11F. The distance H2 of the second lower end surface 94 from the first main surface 1 is equal to or greater than the distance H1 of the first lower end surface 93 from the first main surface 1. The distance H2 of the second lower end surface 94 from the first main surface 1 is, for example, 0.7 μm or more and 0.9 μm or less. The effective concentration of p-type impurities in the fourth region 12D may be lower than the effective concentration of p-type impurities in the third region 12C. The effective concentration of p-type impurities in the fourth region 12D may be lower than the effective concentration of p-type impurities in the second electric field buffer region 17. The effective concentration of the p-type impurity in the fourth region 12D is, for example, 5×10 16 cm -3 5×10 or more 18 cm -3 The following is the result.

[0039] The first region 13A of the source region 13 is on the body region 12 in a direction perpendicular to the second major surface 2. The first region 13A is in contact with the body region 12. The first region 13A is closer to the first major surface 1 than the body region 12. The first region 13A is also in contact with the side surface 3. The first region 13A has a first thickness T1. The first thickness T1 is, for example, not less than 0.1 μm and not more than 0.3 μm. A part of the first region 13A may be on the third region 12C, and another part may be on the fourth region 12D. The first region 13A is covered with the gate insulating film 81. The first region 13A is in direct contact with the gate insulating film 81. The effective concentration of n-type impurities in the first region 13A is, for example, 5×10 18 cm -3 5×10 or more 19 cm -3 The following is the result.

[0040] The second region 13B sandwiches the first region 13A between itself and the side surface 3. That is, the first region 13A is sandwiched between the side surface 3 and the second region 13B in a direction parallel to the first main surface 1. The second region 13B is located on the side farther away from the gate trench 5 than the first region 13A. The second region 13B is on the fourth region 12D of the body region 12 in a direction perpendicular to the second main surface 2. The second region 13B is in contact with the fourth region 12D. The second region 13B is located closer to the first main surface 1 than the fourth region 12D. When viewed in a plan view from a direction perpendicular to the first main surface 1, the second lower end surface 94 of the fourth region 12D overlaps with the second region 13B and is wider than the second region 13B. The second region 13B has a second thickness T2 that is greater than the first thickness T1. The second region 13B may be 1.1 times or more and 5.0 times or less than the first thickness T1. The second thickness T2 is, for example, 0.2 μm or more. The second thickness T2 may be 0.2 μm or more and 0.5 μm or less. A contact electrode 61 is provided on the second region 13B. The second region 13B is in contact with the contact electrode 61. The effective concentration of n-type impurities in the second region 13B may be approximately the same as the effective concentration of n-type impurities in the first region 13A. The effective concentration of n-type impurities in the second region 13B may be, for example, 5×10 18 cm -3 5×10 or more 19 cm -3 The following is the result.

[0041] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the first electric field relief region 16 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the first region 13A of the source region 13 at the first main surface 1. The gate insulating film 81 may further be in contact with the second region 13B of the source region 13 at the first main surface 1.

[0042] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A part of the gate electrode 82 may be disposed on the first main surface 1.

[0043] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0044] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with each of the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0045] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 may be in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing nickel silicide (NiSi), for example. The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is in ohmic junction with the second region 13B. The contact electrode 61 may be in ohmic junction with the contact region 18. The contact electrode 61 is separated from the first region 13A when viewed in a plan view from a direction perpendicular to the first main surface 1. The contact electrode 61 has a side end surface 92 facing the gate trench 5 in a direction parallel to the first main surface 1. For example, when viewed in a plan view from a direction perpendicular to first main surface 1, side end surface 92 is farther away from gate trench 5 than boundary surface 91 between first region 13A and second region 13B. Source wiring 62 covers an upper surface and side surfaces of barrier metal film 84 and an upper surface of contact electrode 61. Source wiring 62 is in contact with each of barrier metal film 84 and contact electrode 61. Source wiring 62 is made of a material containing, for example, Al.

[0046] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

[0047] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing NiSi, for example. The drain electrode 70 may be made of a material containing Ti, Al, and Si. The drain electrode 70 is in ohmic junction with the silicon carbide single crystal substrate 50.

[0048] In a direction perpendicular to the second main surface 2, the upper end surface of the first electric field relaxation region 16 may be spaced from the bottom surface 4. In this case, for example, the bottom surface 4 may be located in the drift region 11, and the side surface 3 may reach the drift region 11 through the source region 13 and the body region 12. For example, a fifth region 11E may be present between the upper end surface of the first electric field relaxation region 16 and the bottom surface 4.

[0049] An upper end surface 95 of the second electric field reduction region 17 may be spaced apart from a second lower end surface 94 of the fourth region 12D in a direction perpendicular to the second main surface 2. For example, a fifth region 11E may be present between the upper end surface 95 and the second lower end surface 94.

[0050] A buffer layer containing an n-type impurity such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and seventh region 11G. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in seventh region 11G.

[0051] In addition, in the direction parallel to the first main surface 1, the end of the gate insulating film 81 may be separated from the barrier metal film 84, and the interlayer insulating film 83 may be in direct contact with the first region 13A. For example, the interlayer insulating film 83 may be formed so as to be inserted between the end of the gate insulating film 81 and the barrier metal film 84.

[0052] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. Figures 2A to 2O are cross-sectional views illustrating the method for manufacturing the MOSFET 100 according to the embodiment.

[0053] First, as shown in FIG. 2A, a step of preparing a silicon carbide single crystal substrate 50 is performed. For example, a silicon carbide ingot (not shown) manufactured by a sublimation method is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by a chemical vapor deposition (CVD) method using a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0054] 2A, a step of forming epitaxial layer 21 is performed. For example, epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into epitaxial layer 21. Epitaxial layer 21 has n-type conductivity. The effective concentration of n-type impurities in epitaxial layer 21 may be lower than the effective concentration of n-type impurities in the buffer layer.

[0055] Next, as shown in FIG. 2B, a step of forming the first electric field relaxation region 16 and the second electric field relaxation region 17 is performed. For example, a mask layer (not shown) having an opening on the region where each of the first electric field relaxation region 16 and the second electric field relaxation region 17 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the first electric field relaxation region 16 and the second electric field relaxation region 17. Each of the first electric field relaxation region 16 and the second electric field relaxation region 17 is formed inside the epitaxial layer 21 so as not to be exposed on the surface of the epitaxial layer 21. The first electric field relaxation region 16 and the second electric field relaxation region 17 may be formed simultaneously or separately. The implantation energy of the p-type impurity ions when forming the first electric field relaxation region 16 and the second electric field relaxation region 17 may be 700 keV or more and 1200 keV or less. The peak depth of the effective concentration of the p-type impurity in first electric field buffer region 16 and second electric field buffer region 17 with respect to first main surface 1 may be set to, for example, not less than 0.8 μm and not more than 1.0 μm.

[0056] Next, as shown in FIG. 2C, a step of forming the sixth region 11F is performed. For example, a mask layer (not shown) having an opening is formed on the region where the sixth region 11F is to be formed, that is, on the region between the first electric field buffer region 16 and the second electric field buffer region 17 in the direction parallel to the second main surface 2. Next, n-type impurity ions capable of imparting n-type, such as nitrogen, are implanted into the epitaxial layer 21. This forms the sixth region 11F. Of the epitaxial layer 21, a portion closer to the silicon carbide single crystal substrate 50 than the first electric field buffer region 16, a portion closer to the silicon carbide single crystal substrate 50 than the sixth region 11F, and a portion closer to the silicon carbide single crystal substrate 50 than the second electric field buffer region 17 form the seventh region 11G. The effective concentration of the n-type impurity in the sixth region 11F is higher than the effective concentration of the n-type impurity in the seventh region 11G. The implantation energy of the n-type impurity ions when forming the sixth region 11F may be set to be not less than 400 keV and not more than 800 keV.

[0057] 2D, a step of forming the third region 12C and a part of the fourth region 12D of the body region 12 is performed. For example, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the entire surface of the epitaxial layer 21. This forms the p-type impurity region 112A constituting the third region 12C and a part of the fourth region 12D of the body region 12. The implantation energy of the p-type impurity ions when forming the p-type impurity region 112A may be 200 keV or more and 400 keV or less. The thickness of the p-type impurity region 112A is, for example, 0.2 μm or more and 0.5 μm or less.

[0058] Next, as shown in FIG. 2E, a step of forming the remainder of the fourth region 12D is performed. For example, a mask layer (not shown) having an opening on the region where the fourth region 12D is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the p-type impurity region 112B constituting the remainder of the fourth region 12D. The implantation energy of the p-type impurity ions when forming the p-type impurity region 112B may be 300 keV or more and 500 keV or less. The lower end surface of the p-type impurity region 112B may contact the upper end surface 95 of the second electric field relaxation region 17. A part of the p-type impurity region 112B may overlap the p-type impurity region 112A.

[0059] In this manner, the body region 12 is formed, including the p-type impurity region 112A and the p-type impurity region 112B. The fourth region 12D is composed of the p-type impurity region 112B and a portion of the p-type impurity region 112A that overlaps with the p-type impurity region 112B when viewed in a plan view from a direction perpendicular to the first main surface 1. The third region 12C is composed of the remaining portion of the p-type impurity region 112A.

[0060] In the epitaxial layer 21, a portion between the body region 12 and the first electric field buffer region 16, the second electric field buffer region 17, or the sixth region 11F becomes the fifth region 11E. For example, the effective concentration of n-type impurities in the fifth region 11E is lower than the effective concentration of n-type impurities in the sixth region 11F.

[0061] Next, as shown in FIG. 2F, a step of forming the first region 13A and a part of the second region 13B of the source region 13 is performed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus, are implanted into the entire surface of the epitaxial layer 21. This forms an n-type impurity region 113A constituting the first region 13A and a part of the second region 13B. The implantation energy of the n-type impurity ions when forming the n-type impurity region 113A may be 50 keV or more and 150 keV or less. The thickness of the n-type impurity region 113A is, for example, 0.1 μm or more and 0.3 μm or less.

[0062] Next, as shown in FIG. 2G, a step of forming the remainder of the second region 13B is performed. For example, a mask layer (not shown) having an opening on the region where the second region 13B is to be formed is formed. Next, n-type impurity ions capable of imparting n-type, such as phosphorus, are implanted into the epitaxial layer 21. This forms the n-type impurity region 113B constituting the remainder of the second region 13B. The implantation energy of the n-type impurity ions when forming the n-type impurity region 113B may be 100 keV or more and 300 keV or less. A part of the n-type impurity region 113B may overlap the n-type impurity region 113A.

[0063] In this manner, source region 13 is formed, including n-type impurity region 113A and n-type impurity region 113B. Second region 13B is composed of n-type impurity region 113B and a portion of n-type impurity region 113A that overlaps with n-type impurity region 113B when viewed in a plan view from a direction perpendicular to first main surface 1. First region 13A is composed of the remaining portion of n-type impurity region 113A.

[0064] 2H, a step of forming contact region 18 is performed. For example, a mask layer (not shown) having an opening on a region where contact region 18 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into source region 13 and body region 12. This forms contact region 18 in contact with body region 12. The implantation energy of p-type impurity ions when forming contact region 18 may be 50 keV or more and 300 keV or less.

[0065] Next, activation annealing is performed to activate the impurity ions implanted into silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500° C. or higher and 1900° C. or lower, for example, about 1700° C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere of the activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0066] Next, as shown in FIG. 2I, a step of forming a gate trench 5 is performed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1 including the source region 13 and the contact region 18. Using the mask layer, a part of the source region 13, a part of the body region 12, and a part of the drift region 11 are removed by etching. For example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used as the etching method. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as a reactive gas can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and is substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0067] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask layer formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 800°C or more and 900°C or less. The reactive gas may include a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, or helium gas can be used as the carrier gas.

[0068] By the above thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is formed by a source region 13, a body region 12, and a drift region 11. The bottom surface 4 is formed by a first electric field relief region 16. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0069] 2J, a step of forming a gate insulating film 81 is performed. For example, the silicon carbide substrate 10 is thermally oxidized to form the gate insulating film 81 in contact with the source region 13, the body region 12, the drift region 11, the first electric field relaxation region 16, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. As a result, the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed.

[0070] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held, for example, for about one hour under conditions of 1100° C. or higher and 1400° C. or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of an interface state in the interface region is suppressed, and channel mobility can be improved.

[0071] After the NO annealing, Ar annealing may be performed using argon (Ar) as the atmospheric gas. The heating temperature of the Ar annealing is, for example, equal to or higher than the heating temperature of the NO annealing. The time of the Ar annealing is, for example, about one hour. This further suppresses the formation of an interface state in the interface region between the gate insulating film 81 and the body region 12. Note that, instead of Ar gas, other inert gases such as nitrogen gas may be used as the atmospheric gas.

[0072] 2K, a step of forming a gate electrode 82 is performed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.

[0073] Next, as shown in FIG. 2L, a step of forming an interlayer insulating film 83 is performed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0074] Next, as shown in FIG. 2M, a step of forming a barrier metal film 84, a contact electrode 61, and a drain electrode 70 is performed. For example, etching is performed to form an opening in the interlayer insulating film 83 and the gate insulating film 81, so that the second region 13B of the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 at the opening. The first region 13A of the source region 13 is preferably left covered by the gate insulating film 81 and the interlayer insulating film 83. Next, a barrier metal film 84 is formed to cover the upper surface and side surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. When viewed in a plan view from a direction perpendicular to the first main surface 1, it is preferable that the first region 13A is located inside a side end surface 96 of the barrier metal film 84. The barrier metal film 84 is made of a material containing, for example, TiN. The barrier metal film 84 is formed by, for example, film formation by a sputtering method and reactive ion etching (Reactive Ion Etching: RIE). Next, a metal film (not shown) for the contact electrode 61 is formed on the first main surface 1 in contact with the second region 13B and the contact region 18. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of a material containing, for example, Ni. Next, a metal film (not shown) for the drain electrode 70 is formed on the second main surface 2 in contact with the silicon carbide single crystal substrate 50. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of a material containing, for example, Ni.

[0075] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 react with silicon contained in the silicon carbide substrate 10 to be silicided. As a result, the contact electrode 61 that makes an ohmic junction with the second region 13B of the source region 13 and the drain electrode 70 that makes an ohmic junction with the silicon carbide single crystal substrate 50 are formed. When viewed in a plan view from a direction perpendicular to the first main surface 1, if the first region 13A is inside the side end surface 96 of the barrier metal film 84, the contact electrode 61 is formed so that the side end surface 92 is farther away from the gate trench 5 than the boundary surface 91 between the first region 13A and the second region 13B. Although a part of the second region 13B is consumed by the silicidation, the first region 13A is not consumed because the first region 13A is covered with the gate insulating film 81 and the interlayer insulating film 83. The contact electrode 61 may form an ohmic junction with the contact region 18. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

[0076] Next, as shown in FIG. 2N, a step of forming a source wiring 62 is performed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed, for example, by film formation using a sputtering method and RIE. The source wiring 62 is made of a material containing aluminum, for example. In this manner, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0077] 2O, a step of forming a passivation film 85 is performed. Specifically, the passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material including, for example, polyimide. The passivation film 85 is formed by, for example, a coating method.

[0078] In this manner, the MOSFET 100 according to the embodiment is completed.

[0079] Next, the effects of the MOSFET according to this embodiment will be described.

[0080] In the MOSFET 100 according to this embodiment, the contact electrode 61 is in ohmic contact with the second region 13B. Even if a part of the second region 13B is consumed during the heat treatment for the ohmic contact, the consumption of the first region 13A is suppressed. Therefore, the function of the source region 13 can be ensured. Therefore, the peak depth D1 of the effective concentration of the p-type impurity in the first electric field relaxation region 16 based on the first main surface 1 can be made small, and excellent characteristics can be obtained even when the peak depth D1 is 0.8 μm or more and 1.0 μm or less, for example. When the peak depth D1 is small, the regrowth of the epitaxial layer is not required after the formation of the first electric field relaxation region 16, as in the above manufacturing method. Therefore, the cost associated with the regrowth of the epitaxial layer can be reduced. Moreover, high-energy ion implantation is not required when the first electric field relaxation region 16 is formed. Therefore, the increase in cost associated with high-energy ion implantation can be avoided. Moreover, the smaller the first thickness T1 of the first region 13A, the more the drain current during a short circuit is reduced, and the more the short circuit resistance can be improved. Furthermore, the feedback capacitance is suppressed as the area of ​​the fifth region 11E in contact with the side surface 3 is reduced. The reduction in feedback capacitance reduces switching loss and can improve switching speed.

[0081] In this way, according to this embodiment, it is possible to reduce costs while suppressing deterioration of characteristics.

[0082] When viewed in a plan view from a direction perpendicular to the first main surface 1, the side end surface 92 is farther away from the gate trench 5 than the boundary surface 91 is, so that consumption of the first region 13A can be more reliably suppressed. The gate insulating film 81 is in direct contact with the first region 13A, so that consumption of the first region 13A can be more reliably suppressed. Even if the interlayer insulating film 83, instead of the gate insulating film 81, is in direct contact with a part of the first region 13A, consumption of the first region 13A can be more reliably suppressed.

[0083] Since the body region 12 includes the fourth region 12D having the second lower end surface 94 in addition to the third region 12C having the first lower end surface 93, punch-through between the second region 13B and the drift region 11 can be suppressed even when a high voltage is applied to the drain electrode 70. In other words, an excellent drain breakdown voltage can be obtained.

[0084] By providing the second electric field relaxation region 17 between the second lower end surface 94 and the second main surface 2, it is possible to suppress dielectric breakdown of the gate insulating film 81 and obtain an excellent dielectric strength voltage. By bringing the upper end surface 95 of the second electric field relaxation region 17 and the second lower end surface 94 of the fourth region 12D into contact with each other, it is possible to obtain an excellent dielectric strength voltage more reliably.

[0085] The second thickness T2 of the second region 13B is preferably 0.2 μm or more in order to more reliably suppress a short circuit between the contact electrode 61 and the body region 12 even if consumed in the ohmic contact with the contact electrode 61. The second thickness T2 is more preferably 0.3 μm or more.

[0086] The second thickness T2 is preferably 1.1 times or more and 5.0 times or less than the first thickness T1. If the second thickness T2 is less than 1.1 times the first thickness T1, the first thickness T1 may be too large or the second thickness T2 may be too small. If the first thickness T1 is too large, it is difficult to form the first electric field relaxation region 16 at low cost in order to ensure a sufficient thickness for the body region 12 and the drift region 11. If the second thickness T2 is too small, a short circuit is likely to occur between the contact electrode 61 and the body region 12. If the second thickness T2 is more than 5.0 times the first thickness T1, the first thickness T1 may be too small or the second thickness T2 may be too large. If the first thickness T1 is too small, it is difficult to ensure the function of the source region 13 sufficiently. If the second thickness T2 is too large, the body region 12 is also formed deep, and the cost of ion implantation is likely to increase. Therefore, the second thickness T2 is preferably 1.1 to 5.0 times the first thickness T1, and more preferably 1.2 to 4.0 times the first thickness T1.

[0087] It is preferable that the peak depth D1 of the effective concentration of the p-type impurity in the first electric field buffer region 16 with respect to the first main surface 1 is 1.0 μm or less, because this allows for low-cost manufacturing.

[0088] When the side surface 3 of the gate trench 5 includes a {0-33-8} plane, excellent mobility can be obtained in the channel, and the channel resistance can be reduced.

[0089] 3, the gate insulating film 81 may have a side end surface 97 facing a side end surface 92 of the contact electrode 61, and the side end surface 97 may be located on the gate trench 5 side of the boundary surface 91 when viewed in a plan view from a direction perpendicular to the first main surface 1. In this case, it is preferable that a side end surface 96 of the barrier metal film 84 in contact with the contact electrode 61 is located on the side away from the gate trench 5 with respect to the boundary surface 91. FIG. 3 is a cross-sectional view showing an example of the relationship between the source region 13, the gate insulating film 81, the barrier metal film 84, and the contact electrode 61.

[0090] [Variations] Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 4 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to the modified example of the embodiment.

[0091] 4, in a MOSFET 300 according to the modification, a gate trench 5 is a vertical trench. That is, an angle θ1 of a side surface 3 with respect to a plane including a bottom surface 4 may be 90°. The other configurations are the same as those of the embodiment.

[0092] Even with such a modification, the same effects as those of the embodiment can be obtained.

[0093] In the above embodiment and reference example, n type is the first conductivity type and p type is the second conductivity type, but p type may be the first conductivity type and n type may be the second conductivity type. In the above embodiment and reference example, MOSFET is exemplified as the silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT). The effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the impurity regions can be measured by, for example, a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. The position of the boundary surface (i.e., the pn junction interface) between the p-type region and the n-type region can be identified by, for example, the SCM method or the SIMS method. The distribution of the effective concentration of majority carriers in the current spreading region can be determined based on the distribution of the thickness of the depletion layer generated by the pn junction between the current spreading region and the body region, for example, without measuring the effective concentration. The thickness of the depletion layer can be determined by, for example, the SCM method or the SIMS method.

[0094] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0095] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 10 Silicon carbide substrate 11 Drift Region 11E 5th area 11F Area 6 11G 7th area 12 Body Region 12C 3rd area 12D 4th area 13 Source Area 13A 1st area 13B 2nd area 16 First electric field relaxation region 17 Second electric field relaxation region 18 Contact Area 21 Epitaxial layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation Film 91 Boundary 92, 96, 97 side end face 93 1st lower end surface 94 Second lower end surface 95 Upper end surface 100, 300 Silicon carbide semiconductor device (MOSFET) 112A, 112B p-type impurity region 113A, 113B n-type impurity region D1 Depth H1, H2 distance T1 First thickness T2 Second thickness θ1 angle

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region to be separated from the drift region; having a gate trench is provided in the first main surface, the gate trench being defined by a side surface that passes through the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface; the silicon carbide substrate further includes a first electric field relief region having the second conductivity type and provided between the bottom surface and the second main surface; The source region is a first region adjacent the side and having a first thickness; a second region having a second thickness greater than the first thickness and sandwiching the first region between the side surface and the second region; having a contact electrode in ohmic contact with the second region, The body region is a third region having a first lower end surface connected to the side surface; a fourth region including a second lower end surface connected to the first lower end surface with the third region sandwiched between the side surface and the fourth region; having an effective concentration of the second conductivity type impurity in the fourth region is lower than an effective concentration of the second conductivity type impurity in the third region.

2. the contact electrode has a side end surface facing the gate trench in a direction parallel to the first main surface, 2 . The silicon carbide semiconductor device according to claim 1 , wherein, when viewed in a plan view from a direction perpendicular to the first main surface, the side end surface is farther away from the gate trench than a boundary surface between the first region and the second region.

3. a gate insulating film in contact with the side surface and the bottom surface; a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate electrode and the silicon carbide substrate; an interlayer insulating film provided so as to cover the gate electrode; and The silicon carbide semiconductor device according to claim 2 , wherein the first region is in direct contact with the gate insulating film or the interlayer insulating film.

4. A second distance of the second lower end surface from the first main surface is equal to or greater than a first distance of the first lower end surface from the first main surface; 4 . The silicon carbide semiconductor device according to claim 1 , wherein, when viewed in a plan view from a direction perpendicular to said first main surface, said second lower end surface overlaps with said second region and is larger than said second region.

5. 5 . The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide substrate further includes a second electric field relief region having the second conductivity type, the second electric field relief region being provided between the second lower end surface and the second main surface.

6. The silicon carbide semiconductor device according to claim 5 , wherein an upper end surface of said second electric field relief region and said second lower end surface are in contact with each other.

7. The silicon carbide semiconductor device according to claim 1 , wherein the second thickness is equal to or greater than 0.2 μm.

8. The silicon carbide semiconductor device according to claim 1 , wherein the second thickness is not less than 1.1 times and not more than 5.0 times the first thickness.

9. 9. The silicon carbide semiconductor device according to claim 1, wherein a peak depth of an effective concentration of the second conductivity type impurity in the first electric field relaxation region is 1.0 μm or less with respect to the first main surface.

10. 10. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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