Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device according to the present invention comprises a silicon carbide substrate which has a first main surface and a second main surface that is on the reverse side of the first main surface. The first main surface is provided with a gate trench which is defined by a lateral surface that penetrates through the source region and the body region to the drift region, and a bottom surface that is continuous with the lateral surface, and which extends in a first direction that is parallel to the first main surface. The silicon carbide substrate additionally has: an electric field attenuated region which is provided between the bottom surface and the second main surface and extends in the first direction, while having the second conductivity type; and a connection region which electrically connects a contact region and the electric field attenuated region to each other, while having the second conductivity type. When viewed in plan from a direction that is perpendicular to the first main surface, the gate trench and the electric field attenuated region are on a virtual straight line that extends in the first direction, and the connection region is in contact with the electric field attenuated region on the virtual straight line.

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority to Japanese Application No. 2019-230976, filed on December 20, 2019, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] 2. Description of the Related Art As one type of silicon carbide semiconductor device, a trench-type metal oxide semiconductor field effect transistor (MOSFET) in which an electric field shielding region is provided below a gate trench formed in a main surface has been disclosed (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-41990 [Patent Document 2] Japanese Patent Application Publication No. 2012-169385 Summary of the Invention

[0005] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, and a contact region provided on the body region and having the second conductivity type. The first main surface includes a gate trench defined by a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending in a first direction parallel to the first main surface, and further includes a source electrode connected to the source region and the contact region. The silicon carbide substrate further includes an electric field relaxation region having the second conductivity type, extending in the first direction and provided between the bottom surface and the second main surface, and a connection region having the second conductivity type and electrically connecting the contact region and the electric field relaxation region. When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are on an imaginary line extending in the first direction, and the connection region contacts the electric field relaxation region on the imaginary line. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a perspective cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing the configuration of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 6]FIG. 6 is a cross-sectional view (part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a fourth cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a fifth cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 9A] FIG. 9A is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9B] FIG. 9B is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9C] FIG. 9C is a cross-sectional view (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9D] FIG. 9D is a cross-sectional view (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9E] FIG. 9E is a cross-sectional view (part 5) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10A] FIG. 10A is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10B] FIG. 10B is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10C] FIG. 10C is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10D] FIG. 10D is a cross-sectional view (part 9) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10E] FIG. 10E is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10F] FIG. 10F is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10G] FIG. 10G is a cross-sectional view (part 12) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11A] FIG. 11A is a cross-sectional view (part 13) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11B] FIG. 11B is a cross-sectional view (part 14) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11C] FIG. 11C is a cross-sectional view (part 15) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11D] FIG. 11D is a cross-sectional view (part 16) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11E] FIG. 11E is a cross-sectional view (part 17) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11F] FIG. 11F is a cross-sectional view (part 18) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11G] FIG. 11G is a cross-sectional view (part 19) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11H] FIG. 11H is a cross-sectional view (part 20) illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a first modification of the embodiment. [Figure 13] FIG. 13 is a diagram showing a configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a second modification of the embodiment. In FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a second modification of the embodiment. [Figure 15] FIG. 15 is a diagram showing a configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a third modification of the embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a third modification of the embodiment. [Figure 17] FIG. 17 is a diagram showing a configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a fourth modification of the embodiment. In FIG. [Figure 18]FIG. 18 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a fourth modification of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Problem that this disclosure aims to solve] In a conventional silicon carbide semiconductor device provided with an electric field shield region, feedback capacitance is large and conduction between the source electrode and the electric field shield region is inhibited, resulting in large switching losses.

[0008] In view of the above, an object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing feedback capacitance and switching loss.

[0009] [Effects of this disclosure] According to the present disclosure, feedback capacitance and switching loss can be reduced.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are represented by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0012] [1] A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, a source region provided on the body region to be separated from the drift region and having the first conductivity type, and a contact region provided on the body region and having the second conductivity type, the first main surface having a side surface that penetrates the source region and the body region to reach the drift region, and a bottom surface that is continuous with the side surface. the silicon carbide substrate further has a gate trench extending in a first direction parallel to the first main surface, and a source electrode connected to the source region and the contact region, the silicon carbide substrate further has an electric field relaxation region provided between the bottom surface and the second main surface, extending in the first direction, and having the second conductivity type, and a connection region having the second conductivity type electrically connecting the contact region and the electric field relaxation region, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are on a virtual straight line extending in the first direction, and the connection region contacts the electric field relaxation region on the virtual straight line.

[0013] The contact region and the electric field relaxation region are electrically connected by the connection region. The contact region is electrically connected to the source electrode. Therefore, the electric field relaxation region is electrically connected to the source electrode. This reduces feedback capacitance and efficiently supplies carriers from the source electrode to the electric field relaxation region, and accelerates the operation of the depletion layer that extends from the electric field relaxation region to the drift region during switching operation, thereby reducing switching loss. In addition, the gate trench and the electric field relaxation region are on a virtual straight line, and the connection region is in contact with the electric field relaxation region on the virtual straight line. Therefore, the connection region is less likely to obstruct the current flowing along the portion of the side of the gate trench that is parallel to the first direction. This ensures sufficient current when the device is on.

[0014] [2] In [1], a plurality of the gate trenches may be provided at regular intervals so as to overlap with the virtual straight line, and the connection region may be provided between adjacent gate trenches in the first direction when viewed in a plan view from a direction perpendicular to the first main surface. By providing the connection region between adjacent gate trenches in the first direction when viewed in a plan view from a direction perpendicular to the first main surface, it is easy to ensure a large connection region and to reduce electrical resistance in the connection region.

[0015] [3] In the device of [2], further comprising a gate insulating film in contact with the side surface and the bottom surface, a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the silicon carbide substrate and the gate insulating film, and an interlayer insulating film provided to cover the gate electrode, wherein, in a plan view from a direction perpendicular to the first main surface, the contact region has a first region provided apart from the interlayer insulating film in a second direction perpendicular to the first direction, and a second region provided between the gate trenches adjacent to each other in the first direction, the source electrode is connected to the first region, and a first dimension of the first region in the first direction may be larger than a second dimension of the second region in the first direction. By making the first dimension larger than the second dimension, a range through which a current flows when the device is on can be secured widely while reducing a contact resistance between the first region and the source electrode.

[0016] [4] In [3], the first dimension may be more than 1 time and not more than 6 times the second dimension. By having the first dimension be more than 1 time and not more than 6 times the second dimension, it is possible to reduce the contact resistance between the first region and the source electrode, while ensuring a wide range through which current flows when the device is on, and further to keep the contact resistance between the source region and the source electrode low.

[0017] [5] In the configuration of [3] or [4], the source regions and the first regions may be provided alternately in the first direction, and the first dimension may be larger than a third dimension in the first direction of the source regions. By making the first dimension larger than the third dimension, it is possible to keep low the contact resistance between the first regions and the source electrode and the contact resistance between the source regions and the source electrode.

[0018] [6] In [3] or [4], the source regions and the first regions may be alternately provided in the first direction, and the first dimension may be 0.2 to 0.6 times the sum of the first dimension and a third dimension of the source region in the first direction. By setting the first dimension to 0.2 to 0.6 times the sum of the first dimension and the third dimension, it is possible to keep low each of the contact resistance between the first region and the source electrode and the contact resistance between the source region and the source electrode.

[0019] [7] In any one of [3] to [6], the second region may be exposed from the interlayer insulating film, and the source electrode may be connected to the second region as well. By connecting the source electrode to the second region as well, the contact resistance between the contact region and the source electrode can be further reduced.

[0020] [8] In any of [3] to [7], the contact region may have the first region on both sides of the gate trench in the second direction. By having the contact region have the first region on both sides of the gate trench in the second direction, electrical resistance between the source electrode and the electric field relaxation region can be easily suppressed.

[0021] [9] In any of [3] to [7], the contact region may have the first region on only one side of the gate trench in the second direction. By having the contact region have the first region on only one side of the gate trench in the second direction, a contact hole on a side where the first region is not provided may be narrower than a contact hole on a side where the first region is provided, making it easier to narrow the cell pitch in the second direction.

[0022]

[10] In any of [1] to [9], a first effective concentration of the second conductivity type impurity in the contact region may be higher than a second effective concentration of the second conductivity type impurity in the connection region. The first effective concentration being higher than the second effective concentration makes it easier to suppress a leak current while suppressing a contact resistance between the contact region and a source electrode.

[0023]

[11] In any one of [1] to

[10] , the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0024] [Embodiments of the present disclosure] The embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). FIGS. 1 and 2 are perspective cross-sectional views showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a perspective view showing a part of the internal structure of the silicon carbide semiconductor device. FIG. 3 is a view showing the configuration of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to an embodiment. FIGS. 4 to 8 are cross-sectional views showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIGS. 3, 7, and 8. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIGS. 3, 7, and 8. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIGS. 3, 7, and 8. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIGS. 3, 4, 5, and 6. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIGS. 3, 4, 5, and 6.

[0025] As shown in FIGS. 1 to 8, the MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type (first conductivity type). First main surface 1 of silicon carbide substrate 10 has a maximum diameter of, for example, 100 mm or more, and preferably 150 mm or more.

[0026] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0027] The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, an electric field reduction region 16, a connection region 17, and a contact region .

[0028] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 mainly includes, for example, a third region 11C, a fourth region 11D, and a fifth region 11E.

[0029] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type (second conductivity type) conductivity. The effective concentration of the p-type impurities in the body region 12 is about 5×10 17 cm -3 This is all. The short channel effect (punch-through) can occur when a depletion layer spreads from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. By increasing the effective concentration of the p-type impurity in the body region 12, the spread of the depletion layer formed in the channel region can be reduced. The thickness of the body region 12 may be less than 0.7 μm, for example. The effective concentration of the p-type impurity in the body region 12 may be less than 1×10 18 cm -3 That's about it.

[0030] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurity in the source region 13 may be higher than the effective concentration of the p-type impurity in the body region 12. The effective concentration of the n-type impurity in the source region 13 is, for example, 1×10 19 cm -3 That's about it.

[0031] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 constitutes the first main surface 1. The contact region 18 mainly includes, for example, a first region 18A and a second region 18B. The effective concentration of the p-type impurity in the contact region 18 is higher than, for example, the effective concentration of the p-type impurity in the body region 12 and the effective concentration of the p-type impurity in the connection region 17. The contact region 18 penetrates the source region 13 and contacts the body region 12. The effective concentration of the p-type impurity in the contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0032] The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, and the drift region 11 to reach the electric field relaxation region 16. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the electric field relaxation region 16. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. An angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0033] As shown in FIG. 3 in particular, when viewed from a direction perpendicular to the first main surface 1, the gate trench 5 overlaps with an imaginary straight line L1 extending in a first direction parallel to the first main surface 1. When viewed from a direction perpendicular to the first main surface 1, the gate trench 5 is on the imaginary straight line L1. A plurality of gate trenches 5 are provided at regular intervals on the imaginary straight line L1. When viewed from a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are also provided at regular intervals in a second direction perpendicular to the first direction. A plurality of gate trenches 5 may be provided, for example, in an array.

[0034] The electric field relaxation region 16 includes a p-type impurity such as Al and has a p-type conductivity. The electric field relaxation region 16 is between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 16 includes, for example, the bottom surface 4 of the gate trench 5. A part of the upper end surface of the electric field relaxation region 16 faces a part of the lower end surface of the body region 12. The electric field relaxation region 16 overlaps with the virtual line L1 when viewed in a plan view from a direction perpendicular to the first main surface 1, similar to the gate trench 5. When viewed in a plan view from a direction perpendicular to the first main surface 1, the electric field relaxation region 16 is on the virtual line L1. On the virtual line L1, the electric field relaxation region 16 may be provided in common to a plurality of gate trenches 5. Moreover, when viewed in a plan view from a direction perpendicular to the first main surface 1, a plurality of electric field relaxation regions 16 are provided at regular intervals in a second direction perpendicular to the first direction. A plurality of electric field relaxation regions 16 may be provided in a stripe pattern. The effective concentration of the p-type impurity in the electric field relaxation region 16 is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3 The following is the result.

[0035] The third region 11C of the drift region 11 is sandwiched between the body region 12 and the electric field relaxation region 16. The third region 11C is in contact with both the body region 12 and the electric field relaxation region 16. The third region 11C is located closer to the second main surface 2 than the body region 12. The third region 11C is located closer to the first main surface 1 than the electric field relaxation region 16. The effective concentration of n-type impurities in the third region 11C is, for example, 5×10 15 cm -3 5×10 or more 16 cm -3 The following is the result.

[0036] The fourth region 11D is located closer to the second major surface 2 than the third region 11C. The fourth region 11D is continuous with the third region 11C. The fourth region 11D is in contact with the electric field relaxation region 16 in a direction parallel to the second major surface 2. The fourth region 11D and the electric field relaxation region 16 may be located in the same plane parallel to the second major surface 2. The effective concentration of n-type impurities in the fourth region 11D may be higher than the effective concentration of n-type impurities in the third region 11C. The effective concentration of n-type impurities in the fourth region 11D is, for example, 5×10 16 cm -3 5×10 or more 17 cm -3 The following is the result.

[0037] The fifth region 11E is located closer to the second main surface 2 than the fourth region 11D. The fifth region 11E is continuous with the fourth region 11D. The fifth region 11E is in contact with the electric field relaxation region 16. The fifth region 11E is located closer to the second main surface 2 than the electric field relaxation region 16. The fifth region 11E may be sandwiched between the fourth region 11D and the silicon carbide single crystal substrate 50. The fifth region 11E may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the fifth region 11E may be lower than the effective concentration of n-type impurities in the fourth region 11D. The effective concentration of n-type impurities in the fifth region 11E may be, for example, 5×10 15 cm -3 5×10 or more 16 cm -3 The following is the result.

[0038] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the electric field reduction region 16 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0039] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A part of the gate electrode 82 may be disposed on the first main surface 1.

[0040] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0041] The interlayer insulating film 83 overlaps with the virtual line L1 when viewed in a plan view from a direction perpendicular to the first main surface 1, similar to the gate trench 5 and the electric field reduction region 16. On the virtual line L1, the interlayer insulating film 83 may be provided in common to a plurality of gate trenches 5. When viewed in a plan view from a direction perpendicular to the first main surface 1, the interlayer insulating film 83 and the gate insulating film 81 have contact holes 90 formed at regular intervals in the second direction. When viewed in a plan view from a direction perpendicular to the first main surface 1, the contact holes 90 are provided so that the gate trench 5 is located between the contact holes 90 adjacent to each other in the second direction. The contact holes 90 extend in the first direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. The dimension of the contact holes 90 in the second direction may be, for example, 1 μm or less.

[0042] As particularly shown in FIG. 3, the first region 18A of the contact region 18 is exposed from the interlayer insulating film 83 through the contact hole 90. The first region 18A may be provided between the gate trenches 5 adjacent to each other in the second direction. The first region 18A and the source region 13 may be provided alternately in the first direction between two gate trenches 5 adjacent to each other in the second direction. For example, the first region 18A may be provided near the end of the gate trench 5 in the first direction, and the source region 13 may be provided near the center of the gate trench 5 in the first direction. The first region 18A is provided on both sides of the gate trench 5 in the second direction. The first region 18A and the source region 13 may be exposed from all the contact holes 90.

[0043] The second region 18B is provided between adjacent gate trenches 5 in the first direction. The second region 18B is covered with an interlayer insulating film 83 and a barrier metal film 84. The second region 18B is connected to the first region 18A in the second direction. The first region 18A and the second region 18B are provided alternately in the second direction. For example, a first dimension Wp1 in the first direction of the first region 18A is larger than a second dimension Wp2 in the first direction of the second region 18B.

[0044] The connection region 17 contains p-type impurities such as Al and has a p-type conductivity. The connection region 17 electrically connects the contact region 18 and the electric field relaxation region 16. The connection region 17 is in contact with the electric field relaxation region 16 on the virtual straight line L1. The connection region 17 is in contact with the body region 12 or the contact region 18. The connection region 17 may be in contact with each of the body region 12 and the contact region 18. The connection region 17 is between the electric field relaxation region 16 and the contact region 18. The connection region 17 is closer to the second main surface 2 than the contact region 18. The connection region 17 is closer to the first main surface 1 than the electric field relaxation region 16. For example, in a direction perpendicular to the second main surface 2, the connection region 17 may be between the second region 18B and the electric field relaxation region 16 and in contact with each of the second region 18B and the electric field relaxation region 16. When connection region 17 is between second region 18B and electric field relaxation region 16 in the direction perpendicular to second main surface 2 and is in contact with both second region 18B and electric field relaxation region 16, the series resistance between second region 18B and electric field relaxation region 16 is reduced. The effective concentration of p-type impurities in connection region 17 may be approximately the same as the effective concentration of p-type impurities in electric field relaxation region 16. The effective concentration of p-type impurities in connection region 17 may be, for example, 5×10 17 cm -3 5×10 or more 18 cm -3 The following is the result.

[0045] If the multiple gate trenches 5 aligned in the first direction are considered to be one gate trench assembly, the gate trench assembly can be considered to be divided into multiple gate trenches 5 by the second region 18B and the connection region 17.

[0046] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with each of the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0047] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the first region 18A of the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing nickel silicide (NiSi), for example. The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is in ohmic junction with the source region 13 and the first region 18A of the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing Al, for example.

[0048] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

[0049] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing NiSi, for example. The drain electrode 70 may be made of a material containing Ti, Al, and Si. The drain electrode 70 is in ohmic junction with the silicon carbide single crystal substrate 50.

[0050] In a direction perpendicular to the second main surface 2, the upper end surface of the electric field relaxation region 16 may be spaced from the bottom surface 4. In this case, for example, the bottom surface 4 may be located in the drift region 11, and the side surface 3 may reach the drift region 11 through the source region 13 and the body region 12. For example, a third region 11C may be present between the upper end surface of the electric field relaxation region 16 and the bottom surface 4.

[0051] A buffer layer containing an n-type impurity such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and fifth region 11E. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in fifth region 11E.

[0052] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. FIGS. 9A to 9E, 10A to 10G, and 11A to 11H are cross-sectional views showing a method for manufacturing the MOSFET 100 according to the embodiment. FIGS. 9A to 9E show changes common to the cross section shown in FIG. 4 and the cross section shown in FIG. 6. FIGS. 10A to 10G show changes in the cross section shown in FIG. 4. FIGS. 11A to 11H show changes in the cross section shown in FIG. 6.

[0053] First, as shown in Fig. 9A, a step of preparing a silicon carbide single crystal substrate 50 is performed. For example, a silicon carbide ingot (not shown) manufactured by a sublimation method is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by a chemical vapor deposition (CVD) method using a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0054] Next, as also shown in Fig. 9A, a step of forming first epitaxial layer 21 is performed. For example, by a CVD method using a mixed gas of silane and propane as a source gas and, for example, hydrogen as a carrier gas, first epitaxial layer 21 is formed on silicon carbide single crystal substrate 50. During epitaxial growth, an n-type impurity such as nitrogen is introduced into first epitaxial layer 21. First epitaxial layer 21 has n-type conductivity. The effective concentration of n-type impurity in first epitaxial layer 21 may be lower than the effective concentration of n-type impurity in the buffer layer.

[0055] 9B, a step of forming electric field relaxation region 16 is performed. For example, a mask layer (not shown) having an opening on a region where electric field relaxation region 16 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into first epitaxial layer 21. As a result, electric field relaxation region 16 is formed.

[0056] 9C, a step of forming the fourth region 11D is performed. For example, a mask layer (not shown) having an opening is formed on the region where the fourth region 11D is to be formed, that is, on the side of the electric field relaxation region 16 in the direction parallel to the second main surface 2. Next, n-type impurity ions capable of imparting n-type, such as nitrogen, are implanted into the first epitaxial layer 21. This forms the fourth region 11D. Of the first epitaxial layer 21, a portion closer to the silicon carbide single crystal substrate 50 than the electric field relaxation region 16 and a portion closer to the silicon carbide single crystal substrate 50 than the fourth region 11D form the fifth region 11E. The effective concentration of the n-type impurity in the fourth region 11D is higher than the effective concentration of the n-type impurity in the fifth region 11E.

[0057] Next, as shown in FIG. 9D, a step of forming a second epitaxial layer 22 is performed. For example, the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using a mixed gas of silane and propane as a raw material gas and hydrogen as a carrier gas. During epitaxial growth, an n-type impurity such as nitrogen is introduced into the second epitaxial layer 22. The second epitaxial layer 22 has an n-type conductivity. The thickness of the second epitaxial layer 22 is, for example, 0.8 μm or more and 1.2 μm or less. For example, the effective concentration of the n-type impurity in the second epitaxial layer 22 is set lower than the effective concentration of the n-type impurity in the fourth region 11D.

[0058] 9E, a step of forming body region 12 is performed. For example, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the entire surface of second epitaxial layer 22. Thus, body region 12 is formed.

[0059] 9E, a step of forming the source region 13 is performed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus, are implanted into the entire surface of the second epitaxial layer 22. Thus, the source region 13 is formed.

[0060] 11A, a step of forming connection region 17 is performed. For example, a mask layer (not shown) having an opening on a region where connection region 17 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into source region 13, body region 12, and third region 11C. As a result, connection region 17 in contact with body region 12 and electric field relaxation region 16 is formed.

[0061] 11B, a step of forming contact region 18 is performed. For example, a mask layer (not shown) having an opening on a region where contact region 18 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into connection region 17. As a result, contact region 18 in contact with body region 12 and connection region 17 is formed.

[0062] Next, activation annealing is performed to activate the impurity ions implanted into silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500° C. or higher and 1900° C. or lower, for example, about 1700° C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere of the activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0063] Next, as shown in FIG. 10A, a step of forming a gate trench 5 is performed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1 including the source region 13 and the contact region 18. Using the mask layer, a part of the source region 13, a part of the body region 12, and a part of the drift region 11 are removed by etching. For example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used as the etching method. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as a reactive gas can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and is substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0064] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask layer formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 800°C or more and 900°C or less. The reactive gas may include a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, or helium gas can be used as the carrier gas.

[0065] By the above thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is composed of a source region 13, a body region 12, and a drift region 11. The bottom surface 4 is composed of an electric field relaxation region 16. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0066] 10B and 11C, a step of forming a gate insulating film 81 is performed. For example, silicon carbide substrate 10 is thermally oxidized to form gate insulating film 81 in contact with source region 13, body region 12, drift region 11, electric field relaxation region 16, and contact region 18. Specifically, silicon carbide substrate 10 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. As a result, gate insulating film 81 in contact with first main surface 1, side surface 3, and bottom surface 4 is formed.

[0067] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held, for example, for about one hour under conditions of 1100° C. or higher and 1400° C. or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of an interface state in the interface region is suppressed, and channel mobility can be improved.

[0068] 10C and 11D, a step of forming a gate electrode 82 is performed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed to face each of the source region 13, the body region 12, and the drift region 11.

[0069] 10D and 11E, a step of forming an interlayer insulating film 83 is performed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0070] Next, as shown in FIG. 10E and FIG. 11F, a process of forming a barrier metal film 84, a contact electrode 61, and a drain electrode 70 is performed. For example, etching is performed so that a contact hole 90 is formed in the interlayer insulating film 83 and the gate insulating film 81, and the source region 13 and the first region 18A are exposed from the interlayer insulating film 83 and the gate insulating film 81 in the contact hole 90. Next, a barrier metal film 84 is formed to cover the upper surface and side surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is made of a material containing TiN, for example. The barrier metal film 84 is formed by film formation by a sputtering method and reactive ion etching (Reactive Ion Etching: RIE), for example. Next, a metal film (not shown) for the contact electrode 61 that contacts the source region 13 and the first region 18A on the first main surface 1 is formed. The metal film for the contact electrode 61 is formed by a sputtering method, for example. The metal film for the contact electrode 61 is made of a material containing Ni, for example. Next, a metal film (not shown) for the drain electrode 70 is formed in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of a material containing, for example, Ni.

[0071] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 react with silicon contained in the silicon carbide substrate 10 and are silicided. As a result, the contact electrode 61 that makes ohmic contact with the source region 13 and the first region 18A, and the drain electrode 70 that makes ohmic contact with the silicon carbide single crystal substrate 50 are formed. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

[0072] Next, as shown in FIG. 10F and FIG. 11G, a step of forming a source wiring 62 is performed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed, for example, by film formation using a sputtering method and RIE. The source wiring 62 is made of a material containing aluminum, for example. In this manner, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0073] Next, as shown in FIG. 10G and FIG. 11H, a step of forming a passivation film 85 is performed. Specifically, a passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide. The passivation film 85 is formed by, for example, a coating method. The passivation film 85 may also be formed by a plasma CVD method.

[0074] In this manner, the MOSFET 100 according to the embodiment is completed.

[0075] Next, the effects of the MOSFET according to this embodiment will be described.

[0076] In the MOSFET 100 according to this embodiment, the contact region 18 and the electric field relaxation region 16 are electrically connected by the connection region 17. The contact region 18 is electrically connected to the source electrode 60. Therefore, the electric field relaxation region 16 is electrically connected to the source electrode 60. This allows carriers to be supplied from the source electrode 60 to the electric field relaxation region 16, thereby reducing the feedback capacitance. The reduction in feedback capacitance reduces switching loss and improves switching speed.

[0077] Moreover, the gate trench 5 and the electric field relaxation region 16 are on the virtual line L1. That is, the gate trench 5 and the electric field relaxation region 16 overlap with the virtual line L1. The connection region 17 is in contact with the electric field relaxation region 16 on the virtual line L1. Therefore, the connection region 17 is unlikely to obstruct the drain current that flows along the portion of the side surface 3 that is parallel to the first direction, that is, the portion of the side surface 3 that is separated from the end of the gate trench 5 in the first direction. Therefore, a sufficient drain current can be ensured when the device is on.

[0078] When viewed in a plan view from a direction perpendicular to the first main surface 1, the connection region 17 is provided between adjacent gate trenches 5 in the first direction. When viewed in a plan view from a direction perpendicular to the first main surface 1, the connection region 17 may be provided so as to overlap with the gate trench 5. However, when the connection region 17 is provided between the gate trenches 5, the volume of the connection region 17 can be made larger and the electrical resistance in the connection region 17 can be made lower. Furthermore, if the source region 13, the body region 12, and the drift region 11 are present between the end of the gate trench 5 in the first direction and the second region 18B, a drain current can also flow in the region between the gate trench 5 and the second region 18B in the first direction.

[0079] In this embodiment, the semiconductor region provided near the upper end of the gate trench 5 is an n-type source region 13. Although a p-type contact region 18 may be provided near the upper end of the gate trench 5, the gate insulating film 81 is likely to be thinner on the p-type contact region 18 than on the n-type source region 13. In addition, an electric field is likely to concentrate near the upper end of the gate trench 5. Since the semiconductor region provided near the upper end of the gate trench 5 is the n-type source region 13, a thick gate insulating film 81 is easily formed, and dielectric breakdown of the gate insulating film 81 due to electric field concentration near the upper end of the gate trench 5 can be suppressed.

[0080] The first region 18A is provided on both sides of the gate trench 5 in the second direction. Therefore, the electrical resistance between the source electrode 60 and the electric field relaxation region 16 can be suppressed compared to the case where the first region 18A is provided on only one side of the gate trench 5 in the second direction.

[0081] In a direction perpendicular to the second main surface 2, the connection region 17 is located between the second region 18B and the electric field relaxation region 16, and is in contact with both the second region 18B and the electric field relaxation region 16, thereby reducing the series resistance between the second region 18B and the electric field relaxation region 16.

[0082] The first effective concentration of the p-type impurity in the contact region 18 is preferably higher than the second effective concentration of the p-type impurity in the connection region 17. The high first effective concentration can suppress the contact resistance between the contact region 18 and the contact electrode 61. If the second effective concentration is as high as the first effective concentration, there is a risk that leakage current will be more likely to flow due to the introduction of crystal defects.

[0083] The first dimension Wp1 in the first direction of the first region 18A is preferably larger than the second dimension Wp2 in the first direction of the second region 18B. Since the contact electrode 61 is ohmic-contacted to the first region 18A, the larger the first dimension Wp1, the more the contact resistance between the first region 18A and the contact electrode 61 can be reduced. On the other hand, since the second region 18B is provided between adjacent gate trenches 5 in the first direction, if the second dimension Wp2 is as large as the first dimension Wp1, the range through which the drain current flows is narrowed, and it may be difficult to obtain a sufficient drain current. By making the first dimension Wp1 larger than the second dimension Wp2, the contact resistance between the first region 18A and the source electrode 60 can be reduced while ensuring a wide range through which the drain current flows when the device is on. Therefore, it is preferable that the first dimension Wp1 is larger than the second dimension Wp2.

[0084] For example, the first dimension Wp1 is preferably more than 1 time and not more than 6 times the second dimension Wp2. If the first dimension Wp1 is more than 6 times the second dimension Wp2, the area where the contact electrode 61 makes ohmic contact with the source region 13 inside the contact hole 90 becomes small, and the contact resistance between the source region 13 and the contact electrode 61 may become high. By making the first dimension Wp1 more than 1 time and not more than 6 times the second dimension Wp2, the contact resistance between the first region 18A and the source electrode 60 can be reduced while ensuring a wide range through which the drain current flows when the device is on, and further the contact resistance between the source region 13 and the source electrode 60 can be kept low. Therefore, it is more preferable that the first dimension Wp1 is more than 2 times and not more than 5 times the second dimension Wp2.

[0085] For example, the first dimension Wp1 is preferably larger than the third dimension Wn in the first direction of the source region 13. In general, p-type impurities are more difficult to activate than n-type impurities. By making the first dimension Wp1 larger than the third dimension Wn, the contact resistance between the first region 18A and the contact electrode 61 and the contact resistance between the source region 13 and the contact electrode 61 can be kept low.

[0086] For example, the first dimension Wp1 is preferably 0.2 to 0.6 times the sum Wch of the first dimension Wp1 and the third dimension Wn. If the first dimension Wp1 is less than 0.2 times the sum Wch, the contact resistance between the first region 18A and the contact electrode 61 may be too high. If the first dimension Wp1 is more than 0.6 times the sum Wch, the contact resistance between the source region 13 and the contact electrode 61 may be too high. By setting the first dimension Wp1 to 0.2 to 0.6 times the sum Wch, the contact resistance between the first region 18A and the contact electrode 61 and the contact resistance between the source region 13 and the contact electrode 61 can be kept low. It is more preferable that the first dimension Wp1 is 0.3 to 0.6 times the sum Wch.

[0087] When the side surface 3 of the gate trench 5 includes a {0-33-8} plane, excellent mobility can be obtained in the channel, and the channel resistance can be reduced.

[0088] [First Modification] Next, a first modified example of the embodiment will be described. The first modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 12 is a cross-sectional view showing a configuration of a MOSFET (silicon carbide semiconductor device) according to the first modified example of the embodiment. Fig. 12 shows a cross section similar to the cross section taken along line IV-IV in Fig. 3.

[0089] 12, in a MOSFET 110 according to the first modification, a gate trench 5 is a vertical trench. That is, an angle θ1 of a side surface 3 with respect to a plane including a bottom surface 4 may be 90°. The other configurations are similar to those of the embodiment.

[0090] The first modified example described above can also provide the same effects as those of the embodiment.

[0091] [Second modified example] Next, a second modified example of the embodiment will be described. The second modified example differs from the embodiment mainly in the position of the first region 18A. FIG. 13 is a diagram showing a configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a second modified example of the embodiment. FIG. 14 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the second modified example of the embodiment. FIG. 14 corresponds to a cross-sectional view taken along line XIV-XIV in FIG. 13.

[0092] In the MOSFET 120 according to the second modification, as shown in FIG. 13 and FIG. 14, the first region 18A is provided only on one side of the gate trench 5 in the second direction. A contact hole 91 and a contact hole 92 are formed in the interlayer insulating film 83. The contact holes 91 and the contact holes 92 are alternately arranged in the second direction. The first region 18A is provided in a portion of the first main surface 1 exposed through the contact hole 91, and may not be provided in a portion of the first main surface 1 exposed through the contact hole 92. The first region 18A and the source region 13 may be exposed from the contact hole 91. Only the source region 13 may be exposed from the contact hole 92. Inside the contact hole 91, the contact electrode 61 is in ohmic junction with each of the source region 13 and the first region 18A. Inside the contact hole 92, the contact electrode 61 is in ohmic junction with the source region 13. The other configurations are the same as those of the embodiment.

[0093] The second modification also reduces the feedback capacitance, which reduces switching loss and improves switching speed. The second modification also ensures a sufficient drain current. The second modification also suppresses dielectric breakdown of the gate insulating film 81 caused by electric field concentration near the upper end of the gate trench 5. The second modification also reduces the series resistance between the second region 18B and the electric field relaxation region 16.

[0094] [Third Modification] Next, a third modified example of the embodiment will be described. The third modified example differs from the embodiment mainly in the configuration of contact region 18. Fig. 15 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to the third modified example of the embodiment. Fig. 16 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the third modified example of the embodiment. Fig. 16 corresponds to a cross-sectional view taken along line XVI-XVI in Fig. 15.

[0095] 15 and 16, in a MOSFET 140 according to the third modification, contact region 18 is composed of first region 18A, and contact region 18 does not include second region 18B. Between gate trenches 5 adjacent to each other in the first direction, below interlayer insulating film 83 and barrier metal film 84, connection region 17 may form first main surface 1. Connection region 17 may be in contact with gate insulating film 81 and barrier metal film 84. The other configurations are similar to those of the embodiment.

[0096] The third modification also reduces the feedback capacitance, which in turn reduces switching loss and improves switching speed. The third modification also ensures a sufficient drain current. The third modification also suppresses dielectric breakdown of the gate insulating film 81 caused by electric field concentration near the upper end of the gate trench 5. The third modification also reduces the electrical resistance between the source electrode 60 and the electric field relaxation region 16, compared to when the first region 18A is provided on only one side of the gate trench 5 in the second direction.

[0097] [Fourth Variation] Next, a fourth modified example of the embodiment will be described. The fourth modified example differs from the embodiment mainly in the configuration of the gate trench 5. FIG. 17 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to the fourth modified example of the embodiment. FIG. 18 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the fourth modified example of the embodiment. FIG. 18 corresponds to a cross-sectional view taken along line XVIII-XVIII in FIG. 17.

[0098] 17 and 18, in a MOSFET 150 according to the fourth modification, a gate trench 5A is formed by connecting a plurality of gate trenches 5 arranged on a virtual straight line L1 in the embodiment. The second region 18B and the connection region 17 are provided on both sides of the gate trench 5A in the second direction. The second region 18B and the connection region 17 may be in contact with the side surface 3. The other configurations are similar to those of the embodiment.

[0099] The fourth modification also reduces the feedback capacitance, which reduces switching loss and improves switching speed. The fourth modification also ensures a sufficient drain current. The fourth modification also reduces the electrical resistance between the source electrode 60 and the electric field relaxation region 16 compared to the case where the first region 18A is provided on only one side of the gate trench 5 in the second direction. The fourth modification also reduces the series resistance between the second region 18B and the electric field relaxation region 16.

[0100] In the above embodiment and reference example, n type is the first conductivity type and p type is the second conductivity type, but p type may be the first conductivity type and n type may be the second conductivity type. In the above embodiment and reference example, MOSFET is exemplified as the silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT). The effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the impurity regions can be measured by, for example, a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. The position of the boundary surface (i.e., the pn junction interface) between the p-type region and the n-type region can be identified by, for example, the SCM method or the SIMS method. The distribution of the effective concentration of majority carriers in the current spreading region can be determined based on the distribution of the thickness of the depletion layer generated by the pn junction between the current spreading region and the body region, for example, without measuring the effective concentration. The thickness of the depletion layer can be determined by, for example, the SCM method or the SIMS method.

[0101] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0102] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5, 5A Gate Trench 10 Silicon carbide substrate 11 Drift Region 11C Third area 11D 4th area 11E 5th area 12 Body Region 13 Source Area 16 Electric field relaxation region 17 Connection Area 18 Contact Area 18A 1st area 18B 2nd area 21 First epitaxial layer 22 Second epitaxial layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation Film 90, 91, 92 Contact holes 100, 110, 120, 140, 150 Silicon carbide semiconductor device (MOSFET) Wp1 1st dimension Wp2 2nd dimension Wn 3rd dimension Wch sum θ1 angle

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region to be separated from the drift region; a contact region provided on the body region and having the second conductivity type; having a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, and the gate trench extends in a first direction parallel to the first main surface; a source electrode connected to the source region and the contact region; The silicon carbide substrate is an electric field relaxation region provided between the bottom surface and the second main surface, extending in the first direction, and having the second conductivity type; a connection region electrically connecting the contact region and the electric field reduction region and having the second conductivity type; and When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relief region are on a virtual straight line extending in the first direction, the connection region is in contact with the electric field relaxation region on the virtual straight line, The connection region does not contact a side surface of an end portion of the gate trench in the first direction.

2. A plurality of the gate trenches are provided at regular intervals so as to overlap with the virtual straight line, The silicon carbide semiconductor device according to claim 1 , wherein the connection region is provided between the gate trenches adjacent to each other in the first direction when viewed in a plan view from a direction perpendicular to the first main surface.

3. A silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region to be separated from the drift region; a contact region provided on the body region and having the second conductivity type; having a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, and the gate trench extends in a first direction parallel to the first main surface; a source electrode connected to the source region and the contact region; The silicon carbide substrate is an electric field relaxation region provided between the bottom surface and the second main surface, extending in the first direction, and having the second conductivity type; a connection region electrically connecting the contact region and the electric field reduction region and having the second conductivity type; and When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relief region are on a virtual straight line extending in the first direction, the connection region is in contact with the electric field relaxation region on the virtual straight line, A plurality of the gate trenches are provided at regular intervals so as to overlap with the virtual straight line, the connection region is provided between the gate trenches adjacent to each other in the first direction when viewed in a plan view from a direction perpendicular to the first main surface, a gate insulating film in contact with the side surface and the bottom surface; a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the gate electrode and the silicon carbide substrate; an interlayer insulating film provided so as to cover the gate electrode; and When viewed in a plan view from a direction perpendicular to the first main surface, The contact region is a first region provided apart from the interlayer insulating film in a second direction perpendicular to the first direction; a second region provided between the gate trenches adjacent to each other in the first direction; having the source electrode is connected to the first region; a first dimension in the first direction of the first region is larger than a second dimension in the first direction of the second region;

4. The silicon carbide semiconductor device according to claim 3 , wherein the first dimension is more than 1 time and not more than 6 times the second dimension.

5. The source regions and the first regions are alternately provided in the first direction, The silicon carbide semiconductor device according to claim 3 , wherein the first dimension is greater than a third dimension in the first direction of the source region.

6. The source regions and the first regions are alternately provided in the first direction, 5 . The silicon carbide semiconductor device according to claim 3 , wherein the first dimension is equal to or greater than 0.2 and equal to or less than 0.6 times a sum of the first dimension and a third dimension of the source region in the first direction.

7. the second region is exposed from the interlayer insulating film, The silicon carbide semiconductor device according to claim 3 , wherein the source electrode is also connected to the second region.

8. The silicon carbide semiconductor device according to claim 3 , wherein the contact region has the first region on both sides of the gate trench in the second direction.

9. The silicon carbide semiconductor device according to claim 3 , wherein the contact region has the first region on only one side of the gate trench in the second direction.

10. 10 . The silicon carbide semiconductor device according to claim 1 , wherein a first effective concentration of the impurity of the second conductivity type in the contact region is higher than a second effective concentration of the impurity of the second conductivity type in the connection region.

11. 11. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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