Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device 100, provided with: a semiconductor substrate 101; a first conductivity-type semiconductor layer 102 laminated on the surface of the semiconductor substrate; a trench 104 formed on the surface of the semiconductor layer; an insulating film 107a covering the bottom surface and the side surfaces of the trench; a conductor 108 filling the interior of the trench covered by the insulating film; a second conductivity-type region 102P formed in the semiconductor layer; and a metal film 109a electrically connected to the conductor, the metal film 109a forming a Schottky barrier with the surface 102a of the semiconductor layer. The second conductivity-type region is disposed below the trench, and is within the region of the trench when the semiconductor substrate is viewed in plan view.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, such as a diode or transistor, having a trench structure, and a method for manufacturing the semiconductor device. [Background technology]

[0002] As described in JP 2016-502270 A, a semiconductor device has been known that has a trench structure in which a second conductivity type low concentration region is formed in a region within a semiconductor layer located at the bottom of a trench formed from the surface of a first conductivity type semiconductor layer that forms a Schottky barrier. Summary of the Invention [Problem to be solved by the invention]

[0003] In the above-described conventional semiconductor device, when the semiconductor substrate is viewed in plan, the second conductivity type low concentration region at the bottom of the trench protrudes outside the trench. In such a structure in which the second conductivity type low concentration region extends outward from the bottom of the trench, the second conductivity type low concentration region extends into the forward current conduction region, which can lead to an increase in on-resistance and therefore degradation of the forward characteristics. If the second-conductivity-type low-concentration region is formed in an attempt to improve the breakdown voltage, or if the region is made large, the breakdown voltage is improved, but the on-resistance increases. For this reason, it is difficult to improve the breakdown voltage while suppressing the increase in on-resistance. [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate, a semiconductor layer of a first conductivity type stacked on a surface of the semiconductor substrate, a trench formed on the surface of the semiconductor layer, an insulating film covering a bottom and side surfaces of the trench, a conductor filling the inside of the trench covered with the insulating film, a second conductivity type region formed in the semiconductor layer, and a metal film electrically connected to the conductor and forming a Schottky barrier with a surface of the semiconductor layer, the second conductivity type region being disposed below the trench and being contained within the trench when the semiconductor substrate is viewed in a plan view, and the second conductivity type region being a gas-phase diffusion The structure was formed by introducing a second conductivity type impurity by a method.

[0005] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate, a semiconductor layer of a first conductivity type stacked on a surface of the semiconductor substrate, a trench formed on the surface of the semiconductor layer, an insulating film covering a bottom and side surfaces of the trench, a conductor filling the inside of the trench coated with the insulating film, a second conductivity type region formed in the semiconductor layer, and a metal film electrically connected to the conductor and forming a Schottky barrier with a surface of the semiconductor layer, the method including the step of providing a doping mask pattern that covers the surface of the semiconductor layer around the trench and the outer edge and side surfaces of the bottom of the trench and exposes a central portion of the bottom surface, and a doping step of introducing a second conductivity type impurity into the semiconductor layer from the central portion of the bottom surface using the insulating mask pattern as a mask. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Diagram 2] FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Diagram 3] FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Figure 4]FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Diagram 5] FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Figure 7] FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present disclosure. [Figure 8] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 9] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 10] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 11] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 12] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 13] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 14] FIG. 4 is a schematic cross-sectional view for explaining a second embodiment of the present disclosure. [Figure 15] 1 is a graph comparing examples of the present invention with comparative examples with respect to forward voltage and withstand voltage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, one embodiment of the present disclosure will be described with reference to the drawings.

[0008] [First embodiment] First, the method for manufacturing a semiconductor device and the semiconductor device according to the first embodiment will be described. (Manufacturing method) A semiconductor device is manufactured as follows. A trench formation process is carried out as shown in Fig. 1. That is, an insulating mask pattern 103 for forming a trench is formed in a semiconductor layer 102 on a semiconductor substrate 101, and a trench 104 is formed by etching using the insulating mask pattern 103 as a mask. The semiconductor substrate 101 is an N-type high-concentration silicon substrate. The semiconductor layer 102 is an N-type low-concentration semiconductor layer laminated on the surface of the semiconductor substrate 101 by epitaxial growth. The insulator mask pattern 103 is a mask pattern for etching that opens in regions where trenches are to be formed on the surface of the semiconductor layer 102. Examples of insulating materials that form the insulator mask pattern 103 include silicon oxide, silicon nitride, and TEOS (tetraethyl orthosilicate). The insulator mask pattern 103 is deposited, for example, by chemical vapor deposition (CVD). The number of trenches 104 is arbitrary. The semiconductor substrate 101 and the semiconductor layer 102 may be made of any of the following semiconductor materials: SiC (silicon carbide), GaN (gallium nitride), and Ga2O3 (gallium oxide).

[0009] Next, a doping mask formation step for introducing P-type impurities under the trenches 104 is performed, followed by a doping step. In the doping mask forming step, first, an insulator layer 105 is formed as shown in FIG. 2. The insulator layer 105 is laminated on the insulator mask pattern 103 in the above trench forming step. At the same time, the bottom and side surfaces of the trench 104 are covered with the insulator layer 105. Examples of insulating materials constituting the insulator layer 105 include silicon oxide, silicon nitride, and TEOS (tetraethyl orthosilicate). For example, chemical vapor deposition (CVD) is used as a method for laminating the insulator layer 105. Next, the entire surface is etched as shown in Figure 3. Anisotropic etching is applied. For anisotropic etching, a reactive etching method is applied in which the etching speed in the vertical direction perpendicular to the surface is faster than the etching speed in the horizontal direction parallel to the surface. 3, it is possible to expose the central portion 104c of the bottom surface of the trench 104 while leaving the sidewall insulator 105S of the portion of the insulator layer 105 that covers the outer edge portion 104a and the side surface 104b of the bottom surface of the trench 104. This is because when the insulator on the central portion 104c of the bottom surface of the trench 104 is removed by vertical etching, the sidewall insulator 105S remains. Since the etching of the sidewall insulator 105S progresses more rapidly in a portion closer to the opening of the trench 104, the thickness of the sidewall insulator 105S increases as it approaches the bottom surface from the opening of the trench 104.

[0010] Moreover, on the surface of the semiconductor layer 102 around the trench 104, the insulator mask pattern 103 is covered with the insulator layer 105 in the stage before etching shown in Fig. 2. Therefore, when the insulator on the central portion 104c of the bottom surface of the trench 104 is removed by vertical etching, the insulator mask pattern 103 also remains. The insulating mask pattern 103 remaining after the above anisotropic etching and the sidewall insulator 105S are combined to form an insulating mask pattern 106. 3, the insulating mask pattern 106 is a pattern that covers the surface of the semiconductor layer 102 around the trench 104, as well as the outer edge portion 104a and the side surface 104b of the bottom of the trench 104, and exposes the center portion 104c of the bottom. This insulating mask pattern 106 is used as a mask for the next doping.

[0011] Next, a doping step is carried out. 4, the doping process is performed by introducing impurities of the second conductivity type (P type in this embodiment) into the semiconductor layer 102 from the center portion 104c of the bottom surface of the trench 104 using the insulator mask pattern 106 as a mask. An ion implantation method is applied as the impurity introduction method. Since the sidewall insulator 105S is present in the trench 104, the ion implantation into the semiconductor layer 102 is limited to the center portion 104c inside the sidewall insulator 105S. After the impurity introduction, annealing is performed to activate the P-type impurities and form P-type regions 102 P. This annealing causes the P-type impurities to diffuse more in the semiconductor layer 102 than during ion implantation, but the lateral direction is contained within the width of the trench 104, and the P-type regions 102 P do not protrude outward from the trench 104.

[0012] Next, the insulator mask pattern 106 is removed as shown in Fig. 5, and insulating films (thermal oxide films) 107a and 107b are formed on the surface of the semiconductor layer 102 including inside the trench 104 as shown in Fig. 6, and then a conductor 108 is buried in the trench 104. The material of the conductor 108 may be polysilicon or a metal material. 7, a Schottky metal film 109a is bonded to the surface 102a of the semiconductor layer 102 to form a Schottky barrier, and a front electrode metal film 109b is formed to connect the Schottky metal film 109a and the conductor 108. Furthermore, a rear electrode metal film 110 is formed.

[0013] (Semiconductor Device) For example, a semiconductor device 100 that can be manufactured by the above manufacturing method includes, as shown in FIG. 7, a semiconductor substrate 101 of a first conductivity type and having a relatively high concentration, a semiconductor layer 102 of a first conductivity type and having a relatively low concentration stacked on the surface of the semiconductor substrate 101, a trench 104 formed on the surface of the semiconductor layer 102, an insulating film 107a covering the bottom and side surfaces of the trench 104, a conductor 108 filling the inside of the trench 104 covered by the insulating film 107a, a second conductivity type region 102P formed in the semiconductor layer 102, and a Schottky metal film 109a electrically connected to the conductor 108 and forming a Schottky barrier with the surface 102a of the semiconductor layer 102. The second conductivity type region 102P is disposed below the trench 104, and is contained within the region of the trench 104 when the semiconductor substrate 101 is viewed in plan. Moreover, when the semiconductor substrate 101 is viewed from above, the second conductivity type region 102P is contained within the region of the trench 104 at a distance from the outer edge without contacting the outer edge of the region of the trench 104. The second-conductivity type region 102P is contained within the width of the bottom of the trench 104, and the corners of the bottom of the trench 104 are not covered by the second-conductivity type region 102P. The corners of the bottom of the trench 104 may be rounded. This has the effect of mitigating localized concentration of an electric field when a reverse voltage is applied.

[0014] The region in the semiconductor layer 102, outside the region of the trench 104 when the semiconductor substrate 101 is viewed in plan, is occupied by a region of the first conductivity type (N type). Therefore, a large conductive region for forward current can be secured under the Schottky junction.

[0015] The second conductivity type region 102P is a region formed by ion implantation. The ion implanted surface appearing at the bottom of the trench 104 corresponds to the central portion 104c in FIG. 4. When the semiconductor substrate 101 is viewed in plan, the central portion 104c is contained within the trench 104 without contacting the outer edge of the trench 104. The ion implanted surface 102b appearing at the bottom of the trench 104 is narrower than the final diffusion width of the second conductivity type region 102P in FIG. 7. The outline of the sidewall insulator 105S in FIG. 4 is also shown by a dashed line in FIG. 7. The inside of the dashed line corresponds to the ion implanted surface 102b.

[0016] The second-conductivity-type (P-type) impurity concentration distribution in the second-conductivity-type region 102P has a maximum value at a depth (point 102M in FIG. 7) away from the bottom surface of the trench 104. This is due to ion implantation, and forming a peak at a deep position improves the effect of alleviating electric field. The P-type impurities also diffuse laterally from the ion implantation surface 102b, but are distributed at a lower concentration than the ion implantation surface 102b.

[0017] The semiconductor device 100 can be applied to a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and the like in addition to a Schottky diode (SBD). When configuring a MOSFET, the P body, gate, etc. are formed in the center, the front electrode metal film 109b becomes the source electrode, and the back electrode metal film 110 becomes the drain electrode. In the case of an IGBT, a P-type high-concentration substrate is further applied as the semiconductor substrate 101, the front electrode metal film 109b becomes the emitter electrode, and the back electrode metal film 110 becomes the collector electrode.

[0018] Second Embodiment Next, a method for manufacturing a semiconductor device and a semiconductor device according to a second embodiment will be described. (Manufacturing method) A semiconductor device is manufactured as follows. A trench formation process is carried out as shown in Fig. 8. That is, an insulating mask pattern 203 for forming a trench is formed in a semiconductor layer 202 on a semiconductor device 201, and a trench 204 is formed by etching using the insulating mask pattern 203 as a mask. The semiconductor substrate 201 is an N-type high-concentration silicon substrate. The semiconductor layer 202 is an N-type low-concentration semiconductor layer laminated on the surface of the semiconductor substrate 201 by epitaxial growth. The insulator mask pattern 203 is a mask pattern for etching that opens in regions where trenches are to be formed on the surface of the semiconductor layer 202. Examples of insulating materials that form the insulator mask pattern 203 include silicon oxide, silicon nitride, and TEOS (tetraethyl orthosilicate). The insulator mask pattern 203 is laminated, for example, by chemical vapor deposition (CVD). The number of trenches 204 is arbitrary.

[0019] Next, a doping mask formation step for introducing P-type impurities under the trench 204 is performed, followed by a doping step. In the doping mask forming step, first, an insulator layer 205 is formed as shown in Fig. 9. The insulator layer 205 is laminated on the insulator mask pattern 203 in the above trench forming step. At the same time, the bottom and side surfaces of the trench 204 are covered with the insulator layer 205. Examples of insulating materials constituting the insulator layer 205 include silicon oxide, silicon nitride, and TEOS (tetraethyl orthosilicate). For example, chemical vapor deposition (CVD) is used as a method for laminating the insulator layer 205. Next, the entire surface is etched as shown in Fig. 10. Anisotropic etching is applied. For anisotropic etching, a reactive etching method is applied in which the etching speed in the vertical direction perpendicular to the surface is faster than the etching speed in the horizontal direction parallel to the surface. 10, it is possible to expose the central portion 204c of the bottom surface of the trench 204 while leaving the sidewall insulator 205S of the portion of the insulator layer 205 that covers the outer edge portion 204a and the side surface 204b of the bottom surface of the trench 204. This is because when the insulator on the central portion 204c of the bottom surface of the trench 204 is removed by vertical etching, the sidewall insulator 205S remains. Since the etching of the sidewall insulator 205S progresses more rapidly in a portion closer to the opening of the trench 204, the thickness increases from the opening of the trench 204 toward the bottom surface.

[0020] Moreover, on the surface of the semiconductor layer 202 around the trench 204, the insulator mask pattern 103 is covered with the insulator layer 205 in the stage before etching shown in Fig. 9. Therefore, when the insulator on the central portion 204c of the bottom surface of the trench 204 is removed by vertical etching, the insulator mask pattern 203 also remains. The insulating mask pattern 203 remaining after the above anisotropic etching and the sidewall insulator 205S are combined to form an insulating mask pattern 206. 10, the insulating mask pattern 206 is a pattern that covers the surface of the semiconductor layer 202 around the trench 204, as well as the outer edge 204a and side surface 204b of the bottom of the trench 204, and exposes the center 204c of the bottom. This insulating mask pattern 206 is used as a mask for the next doping.

[0021] Next, a doping step is carried out. 11, the doping process is performed by introducing impurities P of a second conductivity type (P type in this embodiment) into the semiconductor layer 202 from the center 204c of the bottom surface of the trench 204 using the insulator mask pattern 206 as a mask. A vapor phase diffusion method is applied as the impurity introduction method. Since the sidewall insulator 205S is present in the trench 204, the introduction surface of the impurity P into the semiconductor layer 202 is limited to the center 204c inside the sidewall insulator 205S. After the impurity introduction, annealing is performed to activate the P-type impurity and form the P-type region 202 P. This annealing causes the P-type impurity to diffuse more in the semiconductor layer 202 than when it was introduced, but the lateral direction is contained within the width of the trench 204, and the P-type region 202 P does not protrude outward from the trench 204.

[0022] 12, the insulator mask pattern 206 is removed, and insulating films (thermal oxide films) 207a and 207b are formed on the surface of the semiconductor layer 202 including inside the trench 204, as shown in Fig. 13, and then a conductor 208 is buried in the trench 204. The conductor 208 may be polysilicon or a metal material. 14, a Schottky metal film 209a is bonded to the surface 202a of the semiconductor layer 202 to form a Schottky barrier, and a surface electrode metal film 209b is formed to connect the Schottky metal film 209a and the conductor 208. Furthermore, a back electrode metal film 210 is formed.

[0023] (Semiconductor Device) For example, a semiconductor device 200 that can be manufactured by the above manufacturing method includes, as shown in FIG. 14 , a semiconductor substrate 201 of a first conductivity type and having a relatively high concentration, a semiconductor layer 202 of a first conductivity type and having a relatively low concentration stacked on the surface of the semiconductor substrate 201, a trench 204 formed on the surface of the semiconductor layer 202, an insulating film 207a covering the bottom and side surfaces of the trench 204, a conductor 208 filling the inside of the trench 204 covered with the insulating film 207, a second conductivity type region 202P formed in the semiconductor layer 202, and a Schottky metal film 209a electrically connected to the conductor 208 and forming a Schottky barrier with the surface 202a of the semiconductor layer 202. The second conductivity type region 202P is disposed below the trench 204, and is contained within the region of the trench 204 when the semiconductor substrate 201 is viewed in plan. Moreover, when the semiconductor substrate 201 is viewed from above, the second conductivity type region 202P is contained within the trench 204 at a distance from the outer edge thereof without contacting the outer edge of the trench 204. The second-conductivity type region 202P is contained within the width of the bottom of the trench 204, and the corners of the bottom of the trench 204 are not covered by the second-conductivity type region 202P. The corners of the bottom of the trench 204 may be rounded. This has the effect of alleviating localized concentration of an electric field when a reverse voltage is applied.

[0024] The region in the semiconductor layer 202, outside the region of the trench 204 when the semiconductor substrate 201 is viewed in plan, is occupied by a region of the first conductivity type (N type). Therefore, a large conductive region for forward current can be secured under the Schottky junction.

[0025] The second conductivity type region 202P is a region formed by vapor phase diffusion, and the impurity doped surface appearing at the bottom of the trench 204 corresponds to the central portion 204c in FIG. 11. When the semiconductor substrate 201 is viewed in plan, the impurity doped surface 202P is contained within the trench 204 without contacting the outer edge of the trench 204. The impurity doped surface 202b appearing at the bottom of the trench 204 is narrower than the final diffusion width of the second conductivity type region 202P in FIG. 14. The outline of the sidewall insulator 205S in FIG. 11 is also shown by a dashed line in FIG. 14. The inside of the dashed line corresponds to the impurity doped surface 202b.

[0026] The second-conductivity-type (P-type) impurity concentration distribution in the second-conductivity-type region 202P has a maximum value at the impurity introduction surface 202b. This is due to diffusion from the surface. The P-type impurities also diffuse laterally from the impurity introduction surface 202b, but are distributed at a lower concentration than the impurity introduction surface 202b.

[0027] The semiconductor device 200 can be applied to a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and the like in addition to a Schottky diode (SBD). When configuring a MOSFET, a P body, a gate, etc. are formed in the center, the front electrode metal film 209b becomes the source electrode, and the back electrode metal film 210 becomes the drain electrode. In the case of an IGBT, a P-type high-concentration substrate is further applied as the semiconductor substrate 201, the front electrode metal film 209b becomes the emitter electrode, and the back electrode metal film 210 becomes the collector electrode.

[0028] [Action and Effect] According to the embodiment described above, the second conductivity type region disposed under the trench reduces the electric field when a reverse voltage is applied, improving the breakdown voltage. In addition, a forward current conduction region under the Schottky junction is secured, thereby suppressing an increase in on-resistance.

[0029] [Characteristics comparison] 15 shows the VF-VRM characteristics for the comparative example and the example of the present invention. VF is the forward voltage when the forward current IF = 10 [A]. VRM is the breakdown voltage, which is the reverse voltage when the reverse leakage current IRM = 0.1 [mA]. In the graph of Fig. 15, point 13 appears, which indicates the characteristics of the SBD of the present invention according to the first embodiment. In the graph of Fig. 15, point 14 indicates the characteristics of the SBD of the comparative example in which the P-type region 102P protrudes outward from the trench 104. The other conditions were the same as those of the SBD of the present invention (point 13). 15, line 16 indicates the characteristics of a comparative SBD that does not have a P-type region 102P. Other conditions are the same as those of the SBD (point 13) of the invention example. Line 16 indicates the tendency for VF and VRM to increase linearly as the N-type impurity concentration of semiconductor layer 102 decreases.

[0030] In the SBD at point 14, among the SBDs of the comparative example in which the P-type region 102P protrudes outward from the trench 104, the withstand voltage VRM was improved compared to the SBD of the comparative example without the P-type region 102P. However, in exchange, the forward voltage VF increased. In the comparative SBD in which the P-type region 102P extends outward from the trench 104, the forward voltage VF increases as the withstand voltage VRM increases. This is because although an improvement in the withstand voltage is achieved, this is accompanied by an increase in the on-resistance. In contrast, in the SBD of the invention (point 13), the withstand voltage was improved while suppressing the increase in on-resistance, and a lower VF and a higher withstand voltage VRM were achieved compared to the comparative example.

[0031] Although an embodiment of the present disclosure has been described above, this embodiment is shown by way of example only, and the present disclosure can be embodied in various other forms, and components can be omitted, substituted, or modified without departing from the spirit of the invention. [Industrial Applicability]

[0032] The present disclosure can be utilized in a semiconductor device and a method for manufacturing a semiconductor device. [Explanation of symbols]

[0033] 100 Semiconductor device 101 Semiconductor substrate 102 Semiconductor layer (N-type) 102P 2nd conductivity type region (P type) 104 Trench 107a Insulating film (thermal oxide film) 108 Conductor 109a Schottky metal film 109b Surface electrode metal film 110 Back electrode metal film

Claims

1. A semiconductor substrate; a first conductive type semiconductor layer laminated on a surface of the semiconductor substrate; A trench formed in a surface of the semiconductor layer; an insulating film covering the bottom and side surfaces of the trench; a conductor filling the inside of the trench covered with the insulating film; a second conductivity type region formed in the semiconductor layer; a metal film electrically connected to the conductor and forming a Schottky barrier with a surface of the semiconductor layer; the second conductivity type region is disposed under the trench and is contained within the trench when the semiconductor substrate is viewed in a plan view; The second conductive type region is formed by introducing an impurity of the second conductive type by a vapor phase diffusion method.

2. 2 . The semiconductor device according to claim 1 , wherein, when the semiconductor substrate is viewed in plan, the second conductivity type region is contained within the trench region without contacting an outer edge of the trench region.

3. 3. The semiconductor device according to claim 1, wherein a region in the semiconductor layer outside the trench region when the semiconductor substrate is viewed in plan is occupied by a region of the first conductivity type.

4. 4. The semiconductor device according to claim 1, wherein the second conductivity type impurity concentration distribution in the second conductivity type region has a maximum value at a depth far from a bottom surface of the trench.

5. 5. The semiconductor device according to claim 1, wherein the insulating film is a thermal oxide film.

6. A semiconductor substrate; a first conductive type semiconductor layer laminated on a surface of the semiconductor substrate; A trench formed in a surface of the semiconductor layer; an insulating film covering the bottom and side surfaces of the trench; a conductor filling the inside of the trench covered with the insulating film; a second conductivity type region formed in the semiconductor layer; a metal film electrically connected to the conductor and forming a Schottky barrier with a surface of the semiconductor layer, the second conductivity type region being disposed under the trench, a doping mask forming step of providing an insulating mask pattern that covers the surface of the semiconductor layer around the trench and the outer edge and side of the bottom of the trench and exposes the center of the bottom; and a doping step of introducing a second conductivity type impurity into the semiconductor layer from the center of the bottom surface using the insulating mask pattern as a mask.

7. a trench forming step of forming an insulating mask pattern on a surface of the semiconductor layer, the insulating mask pattern being open in a region where the trench is to be formed, and etching the semiconductor layer using the insulating mask pattern as a mask to form the trench, before the doping mask forming step; 7. The method for manufacturing a semiconductor device according to claim 6, wherein in the doping mask formation process, an insulator layer is formed that is stacked on top of the insulator mask pattern in the trench formation process and covers the bottom and side surfaces of the trench, and the insulator layer is anisotropically etched to expose a central portion of the bottom surface of the trench while leaving behind a portion of the insulator layer that is an insulator covering the outer edge and side surfaces of the bottom surface of the trench.

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