Solar Cells and Photovoltaic Modules

Abstract

The present embodiments relate to the field of photovoltaics and provide solar cells and photovoltaic modules. [Solution] A solar cell includes a substrate, a doped semiconductor layer located on the substrate, a passivation layer covering a surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction, the doped semiconductor layer has a peripheral region, the peripheral region of the doped semiconductor layer has a first hole penetrating a thickness of the doped semiconductor layer, the passivation layer is filled in the first hole, and the electrode penetrates the passivation layer and is in electrical contact with the doped semiconductor layer. The solar cell and photovoltaic module provided in the embodiments of the present application can improve the photoelectric conversion efficiency of the solar cell.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present application relate to the field of photovoltaics, and in particular to solar cells and photovoltaic modules. [Background technology]

[0002] Currently, with the depletion of fossil energy, solar cells are being used more and more widely as a new alternative energy source. A solar cell is a device that converts the light energy of the sun into electrical energy. A solar cell uses the principle of photovoltaic power to generate carriers and extract them at electrodes, thereby contributing to the effective use of electrical energy.

[0003] TOPCon (Tunnel Oxide Passivated Contact) cells or TBC (TOPCon-BC) cells consisting of an IBC using TOPCon technology require the creation of a passivation contact structure on the silicon surface, such as an ultra-thin tunnel oxide layer and a highly doped polycrystalline silicon layer. By utilizing the chemical passivation of the tunnel oxide layer and the field passivation action of the polycrystalline silicon layer, the recombination rate of minority carriers on the silicon surface can be significantly reduced, while the highly doped polycrystalline layer significantly improves the conductive performance of majority carriers, contributing to improving the open circuit voltage and backing factor of the battery.

[0004] Chemical vapor deposition (LPCVD) is the main technology for fabricating the tunnel oxide layer and polysilicon layer, and low pressure chemical vapor deposition (LPCVD) is currently widely used due to its advantages of low cost, high yield, and high performance of the fabricated film. However, there are some issues that may affect the cell efficiency in the process of fabricating the back passivation contact structure. Summary of the Invention [Problem to be solved by the invention]

[0005] In the embodiments of the present application, a solar cell and a photovoltaic module are provided that are advantageous in improving at least the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0006] According to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell is provided, the solar cell including a substrate, a doped semiconductor layer located on the substrate, a passivation layer covering a surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction, the doped semiconductor layer having a peripheral region, the peripheral region of the doped semiconductor layer having a first hole penetrating a thickness of the doped semiconductor layer, the passivation layer being filled in the first hole, and the electrode penetrating the passivation layer and electrically contacting the doped semiconductor layer.

[0007] In some embodiments, the doped semiconductor layer is doped with a P-type doping element, and the width of the peripheral region along the first direction is less than or equal to 50 μm.

[0008] In some embodiments, the first hole has a range of one dimension less than 10 μm.

[0009] In some embodiments, the doped semiconductor layer is doped with an N-type doping element, and the width of the peripheral region along the first direction is less than or equal to 300 μm.

[0010] In some embodiments, the first hole has a first dimension of 30 μm or less.

[0011] In some embodiments, the substrate includes a trench, the trench communicates with the first hole, and the trench has a depth of less than 4 μm.

[0012] In some embodiments, a portion of the electrode is located within the first hole and in electrical contact with the substrate.

[0013] In some embodiments, the inner wall surface of the groove has a textured structure.

[0014] In some embodiments, the method further includes a dielectric layer located between the substrate and the doped semiconductor layer, the dielectric layer having a second hole corresponding to the first hole, and a surface of the substrate being exposed from a bottom of the second hole.

[0015] In some embodiments, the substrate comprises alternating P and N regions with spacing regions between the P and N regions, the doped semiconductor layer comprises a first doped semiconductor layer located in the P regions and a second doped semiconductor layer located in the N regions, the electrodes comprise a first electrode and a second electrode, the first electrode being in electrical contact with the first doped semiconductor layer and the second electrode being in electrical contact with the second doped semiconductor layer, the passivation layer covers a substrate surface in the spacing regions, the first doped semiconductor layer comprises a first peripheral region, the first peripheral region comprises a first sub-hole, and / or the second doped semiconductor layer comprises a second peripheral region, the second peripheral region comprises a second sub-hole.

[0016] In some embodiments, the first peripheral region comprises a first subhole and the second peripheral region comprises a second subhole, the first subhole having a smaller dimension than the second subhole.

[0017] In some embodiments, the ratio of the number of the first holes to the length of the peripheral region along a third direction is 20%*um. -1 is less than.

[0018] In some embodiments, the doped semiconductor layer comprises a boundary, and a number of the first holes close to the boundary is greater than a number of the first holes away from the boundary.

[0019] In some embodiments, the doped semiconductor layer comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0020] According to some embodiments of the present application, in another aspect of the embodiments of the present application, a photovoltaic module is further provided, the photovoltaic module including a cell string formed by connecting a plurality of solar cells described in any of the above embodiments, a sealing adhesive film for covering a surface of the cell string, and a cover plate for covering a surface of the sealing adhesive film remote from the cell string. Effect of the Invention

[0021] The technical solutions provided in the embodiments of the present application have at least the following advantages:

[0022] In the solar cell and photovoltaic module provided in this embodiment, the doped semiconductor layer has a peripheral region, and the peripheral region of the doped semiconductor layer has a first hole penetrating the thickness of the doped semiconductor layer. A passivation layer is filled into the first hole, so that the passivation layer can passivate the substrate exposed from the doped semiconductor layer and reduce surface defects, while the first hole can reduce the structural strength of the doped semiconductor layer and reduce the probability of breakage of the doped semiconductor layer at the edges. [Brief description of the drawings]

[0023] One or more embodiments are illustratively described in the figures in the corresponding accompanying drawings, but these illustrative descriptions are not intended to limit the embodiments, and unless otherwise specified, the figures in the accompanying drawings are not limited to scale. In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the drawings that need to be used in the embodiments are briefly introduced below, but obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative labor. [Figure 1] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Diagram 2] FIG. 2 is an enlarged view of part C in FIG. [Diagram 3] FIG. 3 is a diagram showing a cross-sectional structure taken along the line A1-A2 of FIG. [Figure 4] FIG. 4 is a diagram showing the structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. [Diagram 5] FIG. 5 is a diagram showing different structures of the first hole of the solar cell provided in one embodiment of the present application. [Figure 6] FIG. 6 is a diagram showing a surface structure of one of the doped semiconductor layers of the solar cell provided in one embodiment of the present application. [Figure 7] FIG. 7 is a diagram showing a cross-sectional structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. [Figure 8] FIG. 8 is a diagram showing another configuration of the first hole of the solar cell provided in one embodiment of the present application. [Figure 9] FIG. 9 is a diagram showing a first cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 10] FIG. 10 is a diagram showing a second cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 11] FIG. 11 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Figure 12] FIG. 12 is an enlarged view of part D in FIG. [Figure 13] FIG. 13 is a diagram showing a cross-sectional structure taken along line B1-B2 of FIG. [Figure 14] FIG. 14 is a diagram showing a structure of a solar cell corresponding to a step of providing a substrate in a method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 15] FIG. 15 is a diagram showing a structure of a solar cell corresponding to the step of removing the first borosilicate glass doped layer in the method for manufacturing a solar cell provided in one embodiment of the present application. [Figure 16]FIG. 16 is a diagram showing a structure of a solar cell corresponding to the step of forming a second borosilicate glass doped layer in the solar cell manufacturing method provided in one embodiment of the present application. [Figure 17] FIG. 17 is a diagram showing a structure of a solar cell corresponding to the step of removing the second borosilicate glass doped layer in the solar cell manufacturing method provided in one embodiment of the present application. [Figure 18] FIG. 18 is a diagram showing the structure of a stacked battery provided in one embodiment of the present application. [Figure 19] FIG. 19 is a diagram showing the structure of a photovoltaic module provided in one embodiment of the present application. [Figure 20] FIG. 20 is a diagram showing a cross-sectional structure taken along line M1-M2 of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0025] In the solar cell provided in this embodiment, the doping semiconductor layer is configured to have a peripheral region and is configured to have a first hole in the peripheral region, and a passivation layer is located in the first hole and passivates the substrate, so that the passivation layer can passivate the substrate exposed from the doping semiconductor layer, reduce the surface defects of the substrate, and reduce the recombination rate of the substrate. By having the peripheral region have the first holes, the structural strength of the doping semiconductor layer is reduced by the multiple first holes, and in the process of forming electrodes thereon and realizing the welding between the electrodes and the PV ribbons and the lamination process of the photovoltaic module, the doping semiconductor layer with the first holes can relieve the compressive stress suffered by the doping semiconductor layer, reduce the probability of damage to the doping semiconductor layer at the edge, and improve the yield of the solar cell.

[0026] Hereinafter, each embodiment of the present application will be described in detail in conjunction with the drawings. However, as will be understood by those skilled in the art, although many technical details are proposed in the embodiments of the present application in order to allow the reader to better understand the present application, the technical solution claimed for protection in the embodiments of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.

[0027] Fig. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. Fig. 2 is an enlarged view of part C in Fig. 1. Fig. 3 is a diagram showing a cross-sectional structure along A1-A2 in Fig. 2. Fig. 4 is a diagram showing the structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application.

[0028] According to some embodiments of the present application, as shown in FIGS. 1 to 4, in one aspect of the present embodiment, a solar cell is provided, the solar cell including a substrate 100, a doped semiconductor layer 112 located on the substrate 100, a passivation layer 113 covering a surface of the doped semiconductor layer 112, and a plurality of electrodes 114 arranged along a first direction X, the doped semiconductor layer 112 having a peripheral region 122, the peripheral region 122 of the doped semiconductor layer 112 having a first hole 1120 penetrating a thickness of the doped semiconductor layer 112, the passivation layer 113 being filled in the first hole 1120, and the electrode 114 penetrating the passivation layer 113 to be in electrical contact with the doped semiconductor layer 112.

[0029] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, and may be, for example, silicon or germanium. Here, the elemental semiconductor material may be in a monocrystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a monocrystalline state and an amorphous state is called a microcrystalline state), and for example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0030] In some embodiments, the material of the substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, materials such as silicon germanium, silicon carbide, gallium arsenide, indium gallide, perovskites, cadmium telluride, copper indium selenide, etc. The substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0031] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. In the N-type semiconductor substrate, an N-type doping element is doped, which may be any of the group V elements, such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In the P-type semiconductor substrate, an P-type doping element is doped, which may be any of the group III elements, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0032] In some embodiments, the substrate 100 has a first surface 11 and a second surface 12 disposed opposite to each other, and the first surface 11 of the substrate 100 may be the front surface and the second surface 12 may be the back surface, or the first surface of the substrate may be the back surface and the second surface of the substrate may be the front surface. The solar cell is a single-sided cell, and the front surface is used as the light receiving surface to receive incident light, and the back surface is the backlight surface. In some embodiments, the solar cell is a double-sided cell, that is, both the first surface and the second surface of the substrate can be used as the light receiving surface to receive incident light. Here, the backlight surface can also receive incident light, but the efficiency of receiving incident light is weaker than the efficiency of receiving incident light of the light receiving surface.

[0033] Here, in the solar cell shown in Figure 3, and Figures 9, 10, and 13 described below, the first surface of the substrate is the front surface, and the second surface of the substrate is the back surface. In the solar cell shown in Figure 3, and Figures 9, 10, and 13 described below, an improvement is made to the back surface of the solar cell, and a doped semiconductor layer 112 is located on the back surface of the substrate, improving the passivation performance of the back surface of the solar cell. In the solar cell shown in Figure 3, and Figures 9, 10, and 13 described below, the upward-facing side of the substrate is the light-receiving surface, and the downward-facing side of the substrate is the backlight surface.

[0034] In some embodiments, the doped semiconductor layer 112 may be located on the first surface. The doped semiconductor layer 112 may be located on the front surface, and this embodiment is not limited to the doped semiconductor layer 112 being located on the first surface or the second surface, but only the doped semiconductor layer 112 may be located on the front surface of the substrate.

[0035] In some embodiments, the solar cell further includes a dielectric layer 111 located between the substrate 100 and the doped semiconductor layer 112, the dielectric layer 111 having a second hole 1110 corresponding to the first hole 1120, and the surface of the substrate 100 being exposed from the bottom of the second hole 1110.

[0036] In addition, the dielectric layer 111 is generally set to be thin in order to ensure the tunneling function of carriers so that carriers can tunnel into the doped semiconductor layer 112 through the dielectric layer 111. Since the thickness of the dielectric layer 111 is less than 15 nm, in the process of forming the first hole 1120, the dielectric layer 111 exposed from the first hole 1120 may be removed, so the second hole 1110 is formed in the dielectric layer 111. In some embodiments, in the process of forming the first hole, the dielectric layer is not completely etched and damaged, so there is no second hole in the dielectric layer. This also falls within the scope of protection of the embodiments of the present application.

[0037] In some embodiments, a passivation contact structure is formed between the dielectric layer 111 and the doped semiconductor layer 112, and the doped semiconductor layer 112 can form a band bending at the surface of the substrate 100, and the dielectric layer 111 creates an asymmetric offset in the bands at the surface of the substrate 100, such that the potential barrier for majority carriers among the carriers is lower than the potential barrier for minority carriers among the carriers, so that majority carriers can easily tunnel through the dielectric layer 111 to perform quantum tunneling, but minority carriers have difficulty tunneling through the dielectric layer 111, thereby realizing selective transport of carriers.

[0038] In addition, the dielectric layer 111 exerts a chemical passivation effect. Specifically, since there are interface state defects at the interface between the substrate 100 and the dielectric layer 111, the interface state density at the front surface of the substrate 100 increases, and the increase in the interface state density promotes the recombination of photogenerated carriers, increases the backing factor, short circuit current, and open circuit voltage of the solar cell, and enhances the photoelectric conversion efficiency of the solar cell. By arranging the dielectric layer 111 so as to be located at the second surface 12 of the substrate 100, the dielectric layer 111 can exert a chemical passivation effect on the surface of the substrate 100. Specifically, by saturating the dangling bonds of the substrate 100, the defect state density of the substrate 100 is reduced, the recombination center of the substrate 100 is reduced, and the recombination speed of the carriers is reduced.

[0039] In some embodiments, the thickness of the dielectric layer 111 is 0.5 nm to 5 nm. The thickness range of the dielectric layer 111 is 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. When the dielectric layer 111 is within any of the above ranges, majority carriers can easily perform quantum tunneling through the dielectric layer 111 due to the thin thickness of the dielectric layer 111, but minority carriers have difficulty passing through the dielectric layer 111, and selective transport of carriers can be realized.

[0040] In some embodiments, the doped semiconductor layer 112 exhibits a field passivation effect, specifically, it forms an electrostatic field on the surface of the substrate 100 toward the inside of the substrate 100, which causes minority carriers to escape from the interface, reduces the concentration of minority carriers, reduces the carrier recombination rate at the interface of the substrate 100, increases the open circuit voltage, short circuit current and backing factor of the solar cell, and improves the photoelectric conversion efficiency of the solar cell.

[0041] The doped semiconductor layer 112 may be doped with the same type of doping element as the substrate 100, for example, the type of doping element of the substrate 100 is N-type, and the doped semiconductor layer 112 is doped with N-type doping element.

[0042] In some embodiments, the doped semiconductor layer 112 includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0043] In some embodiments, as shown in FIG. 4, the doping semiconductor layer 112 is doped with a P-type doping element, and the width w of the peripheral region 122 along the first direction is 50 μm or less. The width w of the peripheral region 122 is 45 μm or less, the width w of the peripheral region 122 is 39 μm or less, or the width w of the peripheral region 122 is 30 μm or less. In this way, if the width of the peripheral region 122 of the doping semiconductor layer 112 is within any of the above ranges, the area occupied by the first hole 1120 is smaller, so that the influence of the first hole 1120 on the entire doping semiconductor layer 112 is reduced, and the passivation effect of the doping semiconductor layer 112 on the substrate can be improved. If the width of the peripheral region 122 of the doping semiconductor layer 112 is within any of the above ranges, the doping semiconductor layer 112 can form a part of a tunnel channel for improving the probability that carriers in the substrate 100 tunnel from the first hole 1120 to the electrode 114 and are collected by the electrode 114. In some embodiments, the area of ​​the doped semiconductor layer 112 is generally set to be larger than the area of ​​the electrode 114, so as to ensure that the areas in contact with the electrode 114 are all highly doped areas and reduce the contact resistance between the electrode 114 and the doped semiconductor layer 112. In the present application, the area of ​​the peripheral region 122 is controlled to be small, thereby reducing the influence of the first hole 1120 on the electrode 114 and improving the photoelectric conversion efficiency of the cell. By configuring the peripheral region 122 to have the first hole 1120, recombination defects in the doped semiconductor layer 112 in the non-electrode region can be reduced.

[0044] In some embodiments, the range of the first dimension d of the first hole 1120 is 10 μm or less. The range of the first dimension d of the first hole 1120 is 8 μm or less, the range of the first dimension d of the first hole 1120 is 5.8 μm or less, and the range of the first dimension d of the first hole 1120 is 4.3 μm or less. If the range of the first dimension d of the first hole 1120 is within any of the above ranges, the diameter of the first hole 1120 is small, which reduces the effect of the first hole 1120 on the strength of the doped semiconductor layer 112 itself, and peeling between the doped semiconductor layer 112 and the substrate 100 can be avoided. If the range of the first dimension d of the first hole 1120 is within any of the above ranges, the first hole 1120 can be filled with the passivation layer 113 without forming a cavity, thereby improving the cell efficiency of the solar cell.

[0045] In some embodiments, when the first hole 1120 has a first dimension d within any of the above ranges, the number and first dimension d of the first holes 1120 may be used to provide space for thermal deformation of the doped semiconductor layer 112 and thermal deformation of the passivation layer 113, which can reduce the probability of curling of the solar cell.

[0046] In some embodiments, the doping semiconductor layer 112 is doped with an N-type doping element, and along the first direction, the width w of the peripheral region 122 is 300 μm or less, the width w of the peripheral region 122 is 280 μm or less, the width w of the peripheral region 122 is 250 μm or less, and the width w of the peripheral region 122 is 200 μm or less. Since the N-type doping element is an acceptor type, the growth of crystal grains for constructing the doping semiconductor layer 112 can be promoted by diffusion doping in the preparation of the doping semiconductor layer 112, and the surface morphology of the doping semiconductor layer 112 can be made denser and rougher. The doping semiconductor layer 112 has a dense and rough surface, which can reduce the influence of the external environment on the doping semiconductor layer 112 in the subsequent etching process, improve the passivation performance of the doping semiconductor layer 112 itself, and reduce the range and size of the first hole 1120 in the doping semiconductor layer 112.

[0047] Regarding the definition of the peripheral region 122, in the embodiment of the present application, the peripheral region 122 of the P-type doped semiconductor layer refers to a region surrounded by a region in the doped semiconductor layer 112 that is 50 μm or less in width away from the boundary of the doped semiconductor layer 112, and the other regions are the first region. The peripheral region 122 of the N-type doped semiconductor layer refers to a region surrounded by a region in the doped semiconductor layer 112 that is 300 μm or less in width away from the boundary of the doped semiconductor layer 112, and the other regions are the first region.

[0048] In some embodiments, the first hole 1120 has a first dimension d of 30 μm or less, a first dimension d of 28 μm or less, a first dimension d of 23 μm or less, or a first dimension d of 20 μm or less.

[0049] In some embodiments, an N-type doping element is doped in the doped semiconductor layer 112, and the crystal grains of the doped semiconductor layer 112 are unified by the N-type doping element, and the doped semiconductor layer 112 has a single crystal structure, and the grain size of the doped semiconductor layer 112 with the N-type doping element is small, the number of grain boundaries is large and uniform, and the one-dimensional dimension d of the formed first hole 1120 is large.

[0050] In some embodiments, a P-type doping element is doped in the doped semiconductor layer 112, and the compatibility between the P-type doping element and the dielectric layer 111 is good. For example, when the P-type doping element is B, B can form a B-O bond and a B-Si bond with silicon and oxygen, and the contact performance between the doped semiconductor layer 112 and the dielectric layer 111 and between the doped semiconductor layer 112 and the dielectric layer is good, the range of the peripheral region 122 is small, and the one-dimensional dimension d of the formed first hole 1120 is small.

[0051] In some embodiments, FIG. 5 is a diagram showing different structures of the first hole of the solar cell provided in one embodiment of the present application, and as shown in FIG. 5, the shape of the first hole 1120 may be circular, rectangular, elliptical or triangular as shown in FIG. 5.

[0052] In some embodiments, the first dimension d of the first hole 1120 may be the diameter of a circle, the length of a side of a rectangle or triangle, or the long side of an ellipse, and further, the first dimension d may be the line connecting the two corners.

[0053] 6 is a diagram showing a surface structure of a doped semiconductor layer of a solar cell provided in an embodiment of the present application; FIG. 7 is a diagram showing a cross-sectional structure of a doped semiconductor layer of a solar cell provided in an embodiment of the present application;

[0054] In some embodiments, as shown in Figures 4, 6 and 7, the doped semiconductor layer 112 includes a boundary 115, and the number of first holes 1120 close to the boundary 115 is greater than the number of first holes 1120 away from the boundary 115. Thus, a greater number of first holes 1120 close to the boundary 115 means that the number of first holes 1120 away from the boundary 115 is relatively smaller, and the number of electrodes located within the first holes 1120 is also reduced, allowing the collection area of ​​the electrodes 114 to be increased. The greater the number of first holes 1120 close to the boundary 115, the weaker the doped semiconductor layer 112 close to the boundary 115, and the probability of edge breakage is correspondingly reduced.

[0055] In some embodiments, the spacing between the first holes 1120 near the boundary 115 is discontinuous, as shown in Figure 7. This allows the first holes 1120 to have a small first dimension d, and also allows the doped semiconductor layer 112 to be present between the first holes 1120 as spacing, and also allows the peripheral region 122 of the substrate to have the doped semiconductor layer 112 for collecting carriers in the substrate and ultimately collecting them in the electrode.

[0056] In some embodiments, having more first holes 1120 closer to the boundary 115 can correspondingly reduce the total doping concentration of the doped semiconductor layer 112 in the peripheral region 122, thereby reducing the probability of edge leakage current.

[0057] In some embodiments, the ratio of the number of first holes 1120 to the length of the peripheral region along the third direction is 20%*um. -1 That is, the number of first holes 1120 per 100 μm of the length of the doped semiconductor layer 112 along the direction from the boundary of the doped semiconductor layer 112 toward the first region is less than 20, and further, the number of first holes 1120 is less than 18, 16, 13 or 10.

[0058] As long as the number of the first holes 1120 is within any of the above ranges, it can improve the passivation performance of the doped semiconductor layer 112, reduce damage to the tunneling performance of the dielectric layer 111, reduce damage to the edges of the doped semiconductor layer 112, and improve the deformation resistance of the solar cell to thermal radiation.

[0059] 9 is a diagram showing a first cross-sectional structure of a solar cell provided in an embodiment of the present application. In some embodiments, the substrate 100 includes a groove 1000, the groove 1000 and the first hole 1120 penetrate each other, and the depth h of the groove 1000 is less than 4 μm. The depth h of the groove 1000 is less than 3.6 μm, the depth h of the groove 1000 is less than 3.3 μm, or the depth h of the groove 1000 is less than 2.8 μm.

[0060] In some embodiments, the doped semiconductor layer 112 is doped with an N-type doping element and the depth h of the trench 1000 is less than 3 μm. In some embodiments, the doped semiconductor layer 112 is doped with a P-type doping element and the depth h of the trench 1000 is less than 4 μm.

[0061] In some embodiments, the depth h of the grooves 1000 within any of the above ranges can avoid breakdown of the substrate 100 due to the grooves 1000 penetrating through the substrate 100, and can also act as a light trapping structure to enhance internal reflection of the solar cell.

[0062] In some embodiments, Fig. 8 illustrates another configuration of the first hole of the solar cell provided in an embodiment of the present application. As shown in Figs. 8 and 9, the inner wall surface of the groove 1000 is provided with a textured structure 14. The textured structure 14 is formed on the surface of the substrate 100. The textured structure 14 and the groove 1000 form a light trapping structure, and the textured structure 14 can improve the internal reflection of solar light and improve the light absorptance of the peripheral region 122.

[0063] In some embodiments, the texture structure 14 may include a pyramid structure, a prism structure, or a protrusion structure. The pyramid structure includes an inverted pyramid and a pyramid. In FIG. 8, the texture structure 14 includes two pyramids 1001 as an example.

[0064] In some embodiments, one first hole 1120 can have 1 to 5 pyramids 1001, thus increasing the internal reflection of incident light and improving photoelectric conversion efficiency. If the number of pyramids 1001 in the first hole 1120 is within the above range, the size of the pyramids 1001 is relatively large, the defects on the surface of the substrate 100 are smaller, the recombination center of the substrate 100 is smaller, and the passivation layer 113 can form a good passivation for the substrate 100.

[0065] In some embodiments, the electrode 114 contacts the pyramid 1001, which can increase the contact area between the electrode 114 and the pyramid 1001 and improve the contact performance between the electrode 114 and the pyramid 1001 and the battery yield.

[0066] In some embodiments, in addition to the peripheral region 122, the remaining region of the doped semiconductor layer 112 is the first region 121. In the solar cell of FIG. 4, only a portion of the peripheral region 122 is shown, and the positional relationship between the peripheral region 122 and the first region 121 can be such that the peripheral region 122 surrounds a central region (e.g., the first region) or the peripheral region 122 is located at one end of the first region 121.

[0067] In some embodiments, the passivation layer 113 may be a single layer structure or a laminate structure, and the material of the passivation layer 113 may be one or more of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0068] In some embodiments, the solar cell further includes an anti-reflective layer located on the surface of the passivation layer, and an electrode passes through the anti-reflective layer and the passivation layer to electrically contact the doped semiconductor layer. The anti-reflective layer is used to reduce or eliminate light reflection on the surface of the solar cell, and can increase the light transmission on the surface of the solar cell and reduce or eliminate stray light in the system. Materials for the anti-reflective layer include silicon nitride and silicon oxynitride.

[0069] 10 is a diagram showing a second type of cross-sectional structure of a solar cell provided in an embodiment of the present application. In some embodiments, as shown in FIG. 10, some of the electrodes 114 are located in the first holes 1120 and are in electrical contact with the substrate. The electrodes 114 are in direct electrical contact with the substrate 100 through the first holes 1120, and can directly collect carriers generated in the substrate 100. The first holes 1120 can be used as extra conductive channels to increase the current collection efficiency of the peripheral region 122 and offset the low efficiency caused by the pinhole effect of the dielectric layer 111.

[0070] In some embodiments, the electrodes 114 may be partially located in the peripheral region 122. In some embodiments, the electrodes 114 may be completely located in the peripheral region 122.

[0071] As shown in FIG. 3, the solar cell further includes an emitter 101 located on the first surface 11, a first passivation layer 103 covering the surface of the emitter 101, and a fine grid 104 penetrating the first passivation layer 103 and making electrical contact with the emitter 101.

[0072] In some embodiments, the emitter 101 and the substrate 100 are made of the same material, and the emitter 101 and the substrate 100 can be formed after doping the same original substrate. The type of doping element in the emitter 101 is different from the type of doping element in the substrate 100. A part of the thickness of the original substrate is doped, and the doped part of the original substrate is the emitter, and the remaining original substrate is the substrate.

[0073] In some embodiments, the emitter 101 is a doped layer formed on a first surface of a substrate, which is a semiconductor layer doped with an N-type doping element or a P-type doping element formed by a deposition process, and the semiconductor layer may be silicon, germanium or polycrystalline silicon.

[0074] In some embodiments, the surface of the first surface 11 comprises a first textured structure 13 , the first textured structure 13 including a plurality of protruding structures 105 .

[0075] In some embodiments, the first passivation layer 103 may be a single layer structure or a laminate structure, and the material of the first passivation layer 103 may be one or more of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0076] In some embodiments, the material of the first passivation layer 103 is the same as the material of the passivation layer 113 , and the first passivation layer 103 is manufactured in the same manufacturing process as the passivation layer 113 .

[0077] In some embodiments, either the electrode 114 or the fine grid 104 may be sintered with a burn-through paste. The method of forming the electrode 114 includes employing a silk screen printing technique to print a metal paste on a portion of the surface of the passivation layer 113. The method of forming the fine grid 104 includes employing a silk screen printing technique to print a metal paste on a portion of the surface of the first passivation layer 103. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0078] In some embodiments, when the solar cell is a bifacial TOPCon cell structure, the solar cell further includes a tunnel dielectric layer located on the first surface, and a polysilicon doped layer located on the surface of the tunnel dielectric layer, and the type of doping element in the polysilicon doped layer is different from the type of doping element in the substrate, for example, an N-type doping element is doped in the substrate, and a P-type doping element is doped in the polysilicon doped layer.

[0079] In some embodiments, the dielectric layer and the doped semiconductor layer are located on a first surface of the substrate, and the tunnel dielectric layer and the polysilicon doped layer are located on a second surface of the substrate.

[0080] In some embodiments, the dielectric layer and the doped semiconductor layer are located on a first surface of the substrate, further comprising an intrinsic dielectric layer, an amorphous silicon doped layer, and a transparent conductive layer, wherein the intrinsic dielectric layer is located on a second surface of the substrate, the amorphous silicon doped layer is located on a surface of the intrinsic dielectric layer, the transparent conductive layer is located on a surface of the amorphous silicon doped layer, the electrode is in electrical contact with the doped semiconductor layer, and the fine grid is in electrical contact with the transparent conductive layer.

[0081] In the solar cell provided in this embodiment, the doped semiconductor layer 112 is configured to have a peripheral region and a first hole 1120 is configured in the peripheral region 122, and the passivation layer 113 is located in the first hole 1120 and passivates the substrate, so that the passivation layer 113 passivates the substrate 100 exposed from the doped semiconductor layer 112, reduces surface defects of the substrate 100, and reduces the recombination rate of the substrate 100. Because the peripheral region 122 has the first holes 1120, the structural strength of the doped semiconductor layer 112 is reduced by providing the doped semiconductor layer 112 with a plurality of first holes 1120. In the process of forming the electrode 214 thereon, welding between the electrode and the PV ribbon, and laminating the photovoltaic module, the doped semiconductor layer 112 with the first holes 1120 can relieve the compressive stress experienced by the doped semiconductor layer 112, reduce the probability of damage to the doped semiconductor layer 112 at the edges, and improve the yield of the solar cell.

[0082] In addition, another aspect of this embodiment further provides another solar cell. In the above embodiment, the electrode with a first polarity and the fine grid with a second polarity are located on the first surface and the second surface of the substrate, respectively, while in another embodiment, the first electrode with a first polarity and the second electrode with a second polarity are both located on the second surface of the substrate. The same or corresponding technical features as those in the above embodiment will not be described again here.

[0083] FIG. 11 is a diagram showing the structure of a solar cell provided in one embodiment of the present application, FIG. 12 is an enlarged view of portion D in FIG. 11, and FIG. 13 is a diagram showing the cross-sectional structure along the B1-B2 cross section of FIG. 12.

[0084] As shown in Figures 11 to 13, the solar cell includes a substrate 200, a doped semiconductor layer located on the substrate 200, a passivation layer 213 covering the surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction, where the doped semiconductor layer has a peripheral region, the peripheral region of the doped semiconductor layer has a first hole penetrating the thickness of the doped semiconductor layer, the passivation layer 213 is filled in the first hole, and the electrode penetrates the passivation layer 213 to be in electrical contact with the doped semiconductor layer.

[0085] In some embodiments, substrate 200 comprises alternating P and N regions with spaced apart regions gap between the P and N regions.

[0086] In some embodiments, the substrate 200 includes a first surface 21 and a second surface 22 opposite to each other, the surface of the first surface 21 includes a first textured structure 23, and the first textured structure 23 includes a plurality of protruding structures 205. The first surface 21 includes a front surface field (FSF) whose dopant ion conductivity type is the same as that of the dopant ion of the substrate 200, and the field passivation effect can be utilized to reduce the surface minority carrier concentration, lower the surface recombination velocity, reduce the series resistance, and increase the electron transport capability.

[0087] In some embodiments, as shown in FIG. 13, the gap region is flush with the P region and the N region, i.e., the substrate is not etched, and the P region and the N region are insulated from each other by some isolation film layers between them, and the isolation film layers may be passivation layers.

[0088] In some embodiments, the gap is lower than the P and N regions, and the gap comprises a trench extending from the second surface toward the first surface, where the trench is used to provide automatic isolation between regions of different conductivity types and prevent the heavily doped P and N regions in an IBC (Interdigitated Back Contact) cell from forming a PN junction that could cause leakage current and affect cell efficiency.

[0089] In some embodiments, the surface of the gap may be a polished surface structure and the surface of the gap may be a second textured structure, the roughness of the first textured structure being equal to or greater than the roughness of the second textured structure.

[0090] Here, "roughness" refers to the arithmetic mean of the absolute values ​​of the vertical deviations of the peaks and valleys within a sampled length from the average horizontal line, which is set at one sampled length (1 μm). Roughness can be measured by the comparative method, the light section method, the interference method, and the probe scanning method.

[0091] In some embodiments, the doped semiconductor layer includes a first doped semiconductor layer 244 located in a P region and a second doped semiconductor layer 254 located in an N region, the electrodes include a first electrode 2141 and a second electrode 2142, the first electrode 2141 being in electrical contact with the first doped semiconductor layer 244 and the second electrode 2142 being in electrical contact with the second doped semiconductor layer 254, the passivation layer 213 covering the substrate surface in the gap region, the first doped semiconductor layer 244 comprising a first peripheral region 242, the first peripheral region 242 comprising a first sub-hole 2121, and / or the second doped semiconductor layer 254 comprising a second peripheral region 252, the second peripheral region 252 comprising a second sub-hole 2122.

[0092] In some embodiments, the first peripheral region 242 comprises a first subhole 2121 and the second peripheral region 252 comprises a second subhole 2122, where one dimension of the first subhole 2121 is smaller than one dimension of the second subhole 2122.

[0093] In some embodiments, the first sub-area 241 is a region of the first doped semiconductor layer 244 excluding the first peripheral region 242. The second sub-area 251 is a region of the second doped semiconductor layer 254 excluding the second peripheral region 252.

[0094] In some embodiments, the dielectric layer includes a first dielectric layer 243 and a second dielectric layer 253, with the first doped semiconductor layer 244 located in the first dielectric layer 243 and the second doped semiconductor layer 254 located in the second dielectric layer 253.

[0095] In some embodiments, there is a second hole 2110 in the first dielectric layer and a second hole 2110 in the second dielectric layer.

[0096] In some embodiments, the first dielectric layer 243 and the second dielectric layer 253 may be the same as the dielectric layer 111 in the previous embodiment, i.e., the first dielectric layer 243 and the second dielectric layer 253 are tunnel dielectric layers. Similarly, the first doped semiconductor layer 244 and the second doped semiconductor layer 254 may be the doped semiconductor layer 112 in the previous embodiment. The difference is that the first doped semiconductor layer 244 is doped with a P-type doping element, and the second doped semiconductor layer 254 is doped with an N-type doping element.

[0097] In some embodiments, the first electrode 2141 and the second electrode 2142 may refer to the electrode 114 in the previous embodiments, the first texture structure 23, the protrusion structure 205 and the first passivation layer 203 of the first surface 21 may refer to the first texture structure 13, the protrusion structure 105 and the first passivation layer 103 in the previous embodiments, and the passivation layer 213 may refer to the passivation layer 113 in the previous embodiments, which will not be described again here.

[0098] FIG. 14 is a diagram showing a structure of a solar cell corresponding to a step of providing a substrate in the method for manufacturing a solar cell provided in an embodiment of the present application. FIG. 15 is a diagram showing a structure of a solar cell corresponding to a step of removing a first borosilicate glass doped layer in the method for manufacturing a solar cell provided in an embodiment of the present application. FIG. 16 is a diagram showing a structure of a solar cell corresponding to a step of forming a second borosilicate glass doped layer in the method for manufacturing a solar cell provided in an embodiment of the present application. FIG. 17 is a diagram showing a structure of a solar cell corresponding to a step of removing a second borosilicate glass doped layer in the method for manufacturing a solar cell provided in an embodiment of the present application. In this embodiment, the solar cell provided in another embodiment is taken as an example.

[0099] As shown in Figure 14, the manufacturing method includes providing a substrate 200. The substrate 200 has a first surface and a second surface 22, the second surface 22 facing the first surface.

[0100] In some embodiments, the substrate comprises P regions and N regions with a spacer region gap between adjacent P and N regions.

[0101] 14, the manufacturing method includes forming a first dielectric film 225 located on the second surface 22 of the substrate, and forming a first doped semiconductor film located on the surface of the first dielectric film 225. Here, while forming the first doped semiconductor film 226, a first borosilicate glass doped layer 227 is formed on the first surface of the substrate 200 and the surface of the first doped semiconductor film 226.

[0102] In some embodiments, a thermal oxidation method or a chemical deposition method is used to form the first dielectric film 225. The first dielectric film 225 is located in the P region, the N region, and the gap region.

[0103] In some embodiments, the manufacturing method for forming the first doped semiconductor film 226 includes a first deposition, a second deposition, and a high temperature oxidation step, where in the first deposition, the deposition gas includes silane, the flow rate is controlled between 100 sccm and 1,000 sccm, and the deposition temperature is controlled between 400° C. and 700° C. to form an intrinsic semiconductor film. In the second deposition, the deposition gas includes a doping source gas and an oxygen gas, the flow rate is controlled between 100 sccm and 3,000 sccm, and the deposition temperature is controlled between 700° C. and 1,000° C. to form a doped semiconductor film. In the high temperature oxidation step, the gas includes nitrogen gas and oxygen gas, in the process converting the doped semiconductor film into the first doped semiconductor film 226 and forming a first borosilicate glass doped layer 227 on the first surface of the substrate 200 and the surface of the first doped semiconductor film 226.

[0104] As shown in FIG. 15, the manufacturing method includes removing the first borosilicate glass doped layer 227 in the spacing region and the N region. Using the first borosilicate glass doped layer 227 on the first surface and in the P region as a doping source, a high-temperature diffusion process is performed to diffuse the P-type doping element in the first borosilicate glass doped layer 227 located in the P region into the first doped semiconductor film 226 located in the P region, and the P-type doping element in the first borosilicate glass doped layer 227 on the first surface is doped into a part of the substrate close to the first surface. After the high-temperature diffusion process, the first borosilicate glass doped layer 227 on the first surface and in the P region is removed.

[0105] In some embodiments, in the process of removing the first borosilicate glass doped layer 227, the etchant may etch the first doped semiconductor film 226 and the first dielectric film 225, thereby removing the first doped semiconductor film 226 and the first dielectric film 225.

[0106] As shown in FIG. 16, the manufacturing method includes forming a second dielectric film 228 and a second doped semiconductor film 229 on the surface of the N region and the surface of the first doped semiconductor film 226, where, simultaneously with forming the second doped semiconductor film 229, a second borosilicate glass doped layer 235 is formed on the first surface of the substrate 200 and the surface of the second doped semiconductor film 229.

[0107] As shown in FIG. 17, the manufacturing method includes removing the second borosilicate glass doped layer 235 at the first surface and the second borosilicate glass doped layer 235 in the P region, removing the second dielectric film 228 and the second doped semiconductor film 229 in the P region, and making the first dielectric film and the first doped semiconductor film in the P region into a first dielectric layer 243 and a first doped semiconductor layer 244, respectively, and making the second dielectric film and the second doped semiconductor film in the N region into a second dielectric layer 253 and a second doped semiconductor layer 254, respectively.

[0108] In some embodiments, the method of manufacture includes performing a texturing process on the first surface 21 such that the first surface 21 comprises a first textured structure 23. The first textured structure 23 comprises a plurality of protruding structures 205.

[0109] In some embodiments, the texture formation process may include chemical etching, for example, the substrate 200 may be cleaned with a mixed solution of potassium hydroxide and hydrogen peroxide solution, and the first texture structure having a desired shape may be formed by controlling the concentration ratio of the potassium hydroxide and hydrogen peroxide solutions. In some embodiments, the first texture structure may be formed by a method such as laser etching, a mechanical method, or a plasma etching method. In laser etching, the parameters of the laser process may be controlled to obtain a texture structure having a desired shape.

[0110] In some embodiments, the etching process of the etching solution is controlled to have first sub-holes 2121 in a portion of the first doped semiconductor layer 244 and second sub-holes 2122 in the second doped semiconductor layer 254 during the removal and texturing process of the first borosilicate glass doped layer 227 and the second borosilicate glass doped layer 235.

[0111] Here, the process parameters for removing the first borosilicate glass-doped layer 227 include removing the first borosilicate glass-doped layer using a mixture of hydrofluoric acid and hydrochloric acid with a reaction time of 300 seconds or less, whereby the first borosilicate glass-doped layer can be removed without etching and damaging the first doped semiconductor film if the reaction time is less than 60 seconds.

[0112] The process parameters for removing the second borosilicate glass-doped layer include removing the second borosilicate glass-doped layer using a mixture of hydrofluoric acid and hydrochloric acid with a reaction time of less than 350 seconds, whereby the second borosilicate glass-doped layer can be removed without etching and damaging the second doped semiconductor film when the reaction time is less than 70 seconds.

[0113] In some embodiments, the concentration of at least one of the hydrofluoric acid solution for removing the first borosilicate glass-doped layer or the hydrofluoric acid solution for removing the second borosilicate glass-doped layer is 20% to 50%. The concentration of at least one of the hydrochloric acid solution for removing the first borosilicate glass-doped layer or the hydrochloric acid solution for removing the second borosilicate glass-doped layer is 0% to 20%.

[0114] In some embodiments, the mixture of hydrofluoric acid solution and hydrochloric acid solution for removing the first borosilicate glass doped layer is the same as the mixture of hydrofluoric acid solution and hydrochloric acid solution for removing the second borosilicate glass doped layer.

[0115] In some embodiments, the process parameters for the texture formation process include a mixture of sodium hydroxide solution, additives and aqueous solution, a reaction temperature of 50°C-100°C, and a reaction time of 200s-1200s, where the concentration of the sodium hydroxide solution is 1%-5%, and the concentration of the additives is 0.01%-1%.

[0116] As shown in FIG. 13, the manufacturing method includes forming a passivation layer 213 covering the first sub-hole 2121, the second sub-hole 2122, the gap region gap, the first doped semiconductor layer 244 and the second doped semiconductor layer 254.

[0117] As shown in FIG. 13, the method includes forming a first passivation layer 203 overlying a first surface 21 of a substrate 200 .

[0118] In some embodiments, the passivation layer 213 and the first passivation layer 203 are formed in the same manufacturing process.

[0119] 13, the manufacturing method includes forming a first electrode 2141 and a second electrode 2142, where the first electrode 2141 penetrates the passivation layer 213 to electrically contact the first doped semiconductor layer 244, and the second electrode 2142 penetrates the passivation layer 213 to electrically contact the second doped semiconductor layer 254.

[0120] In some embodiments, the method of manufacturing the first electrode 2141 and the second electrode 2142 includes printing a metal paste on a portion of the surface of the passivation layer 213 using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, a sintering process is performed on the metal paste, and the metal paste includes a highly corrosive component such as glass powder, so that the corrosive component corrodes the passivation layer 213 during the sintering process, and the metal paste penetrates the passivation layer 213 to electrically contact the first doped semiconductor layer 244 to form the first electrode 2141, and electrically contact the second doped semiconductor layer 254 to form the second electrode 2142.

[0121] Accordingly, Fig. 18 is a diagram showing the structure of a tandem solar cell provided in one embodiment of the present application. As shown in Fig. 18, this embodiment provides a tandem solar cell including a bottom cell 350 and a top cell 360, in which the bottom cell 350 may be a solar cell as shown in one embodiment (Figs. 1 to 10), and the top cell 360 is located on the surface of an emitter or a surface of a doped semiconductor layer in the bottom cell 350.

[0122] In some embodiments, the stacked battery includes first grid lines 366 of a first polarity and second grid lines 367 of a second polarity, with the first grid lines 366 in electrical contact with the top cells 360 and the second grid lines 367 in electrical contact with the bottom cells 350.

[0123] In some embodiments, there is an interface layer 361 between the top cell and the bottom cell, and the interface layer 361 fills the first hole 1120 .

[0124] It should be noted that the stacked cell in the embodiment of the present application only shows a two-layer solar cell, and those skilled in the art can install a three-layer solar cell or a multi-layer solar cell with more than three layers according to actual needs.

[0125] In some embodiments, the top cell 360 may be a perovskite solar cell that includes stacked first transport layer 362, a perovskite substrate 363, a second transport layer 364, a transparent conductive layer 365, and an anti-reflective layer (not shown), where the first transport layer faces the bottom cell.

[0126] In some embodiments, the first transport layer can be one of an electron transport layer or a hole transport layer, and the second transport layer can be the other of an electron transport layer or a hole transport layer.

[0127] FIG. 19 is a diagram showing the structure of a photovoltaic module provided in one embodiment of the present application, and FIG. 20 is a diagram showing a cross-sectional structure along the M1-M2 cross section of FIG.

[0128] In some embodiments, as shown in Figures 19 and 20, another aspect of this embodiment further provides a photovoltaic module including a cell string formed by connecting a plurality of solar cells 40 of any of the above embodiments, a sealing adhesive film for covering a surface of the cell string, and a cover plate for covering a surface of the sealing adhesive film away from the cell string.

[0129] Specifically, in some embodiments, multiple battery cells may be electrically connected to each other by connection members 409, and the connection members 409 and the main grids 264 of the battery cells may be welded to each other.

[0130] In some embodiments, there is no space between the battery cells, i.e., the battery cells overlap each other.

[0131] In some embodiments, a weld is formed between the connection member and a sub-grid of the battery cell, the sub-grid including a first electrode 2141 and a second electrode 2142. In some embodiments, a weld is formed between the connection member and a main grid 264 of the battery cell, the main grid including a first main grid and a second main grid, the first main grid welded to the first electrode 2141 and the second main grid welded to the second electrode 2142.

[0132] In some embodiments, the sealing adhesive film includes a first sealing adhesive film and a second sealing adhesive film, the first sealing adhesive film covers one of the front and back surfaces of the solar cell, and the second sealing adhesive film covers the other of the front and back surfaces of the solar cell. Specifically, at least one of the first sealing adhesive film and the second sealing adhesive film may be an organic sealing adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0133] Before lamination processing, there is a boundary between the first sealing adhesive film and the second sealing adhesive film, and after lamination processing, when the photovoltaic module is formed, the concept of the first sealing adhesive film and the second sealing adhesive film no longer exists; in other words, the first sealing adhesive film and the second sealing adhesive film are integrated to form a sealing adhesive film 47.

[0134] In some embodiments, the cover plate 48 may be a cover plate with a light transmission function, such as a glass cover plate, a plastic cover plate, etc. Specifically, the surface of the cover plate 48 facing the sealing adhesive film 47 may be an uneven surface, which can improve the utilization rate of the incident light. The cover plate 48 includes a first cover plate and a second cover plate, the first cover plate facing the first sealing adhesive film and the second cover plate facing the second sealing adhesive film, or the first cover plate facing one side of the solar cell and the second cover plate facing the other side of the solar cell.

[0135] Those skilled in the art will understand that the above embodiments are specific examples for implementing the present application, but various changes in form and details are possible in practice without departing from the scope of the present application. Since any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, the scope of protection of the present application should be based on the scope limited by the claims.

Claims

1. The semiconductor device includes a substrate, a doped semiconductor layer disposed on the substrate, a passivation layer covering a surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction, the doped semiconductor layer comprises a peripheral region, the peripheral region of the doped semiconductor layer comprising a plurality of first holes interspersed therebetween, the first holes extending through a thickness of the doped semiconductor layer; The passivation layer is filled in the first hole; the electrode passes through the passivation layer and is in electrical contact with the doped semiconductor layer; A solar cell characterized by:

2. The doped semiconductor layer is doped with a P-type doping element, and the width of the peripheral region along the first direction is 50 μm or less. The solar cell according to claim 1 .

3. The range of a first dimension of the first hole is 10 μm or less; Here, the shape of the first hole is a circle, a rectangle, or a triangle, and the one-dimensional dimension of the first hole is a diameter of the circle, a side length of the rectangle, or a side length of the triangle. The solar cell according to claim 2 .

4. The doped semiconductor layer is doped with an N-type doping element, and the width of the peripheral region along the first direction is 300 μm or less. The solar cell according to claim 1 .

5. The range of a first dimension of the first hole is 30 μm or less; Here, the shape of the first hole is a circle, a rectangle, or a triangle, and the one-dimensional dimension of the first hole is a diameter of the circle, a side length of the rectangle, or a side length of the triangle. The solar cell according to claim 4 .

6. A groove is provided in the substrate, the groove and the first hole are connected to each other, and the depth of the groove is less than 4 μm. The solar cell according to claim 1 .

7. A portion of the electrode is located within the first hole and is in electrical contact with the substrate. The solar cell according to claim 6 .

8. The inner wall surface of the groove is provided with a textured structure. The solar cell according to claim 6 .

9. a dielectric layer located between the substrate and the doped semiconductor layer, the dielectric layer having a second hole corresponding to the first hole, and a surface of the substrate being exposed from a bottom of the second hole; The solar cell according to claim 1 .

10. the substrate comprises alternating P and N regions, with a spacing region between the P and N regions; the doped semiconductor layer comprises a first doped semiconductor layer located in the P region and a second doped semiconductor layer located in the N region; the electrode comprises a first electrode and a second electrode, the first electrode being in electrical contact with the first doped semiconductor layer and the second electrode being in electrical contact with the second doped semiconductor layer; the passivation layer covers a substrate surface in the spacing region; the first doped semiconductor layer comprises a first peripheral region, the first peripheral region comprising the first hole located in the first peripheral region, and / or the second doped semiconductor layer comprises a second peripheral region, the second peripheral region comprising the first hole located in the second peripheral region. The solar cell according to claim 1 .

11. the first peripheral region comprises the first hole located in the first peripheral region, the second peripheral region comprises the first hole located in the second peripheral region, a first dimension of the first hole located in the first peripheral region is smaller than a first dimension of the first hole located in the second peripheral region, and a shape of at least one of the first hole located in the first peripheral region or the first hole located in the second peripheral region is a circle, a rectangle, or a triangle, and at least one of the first dimensions of the first hole located in the first peripheral region or the first hole located in the second peripheral region is a diameter of a circle, a side length of a rectangle, or a side length of a triangle. The solar cell according to claim 10 .

12. The orthogonal projection pattern of the doped semiconductor layer on a reference plane includes at least one boundary, the number of the first holes close to the boundary is greater than the number of the first holes away from the boundary, and the reference plane is perpendicular to a thickness direction of the substrate. The solar cell according to claim 1 .

13. The doped semiconductor layer comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, or a silicon carbide doped layer; The solar cell according to claim 1 .

14. A cell string formed by connecting a plurality of solar cells according to any one of claims 1 to 13; a sealing adhesive film for covering a surface of the cell string; and a cover plate for covering a surface of the sealing adhesive film away from the cell string. A photovoltaic module comprising:

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