Semiconductor device and method for manufacturing the same

Abstract

The semiconductor device (1) comprises an electron transit layer (103), an electron supply layer (104) provided on the electron transit layer (103), a gate electrode (303) provided on the electron supply layer (104), contact layers (212) embedded in through recesses (211) penetrating the electron supply layer (104) at positions sandwiching the gate electrode (303), and a contact layer (212) provided in contact with the electron supply layer (104) and the contact layer (212) but not in contact with the gate electrode (303). the gate electrode (303) and the alloy layer (402) containing Si, the first insulating layer (201) being provided in contact with the gate electrode (303) but not in contact with the contact layer (212); and a source electrode (301) and / or a drain electrode (302) being provided on the contact layer (212) and the alloy layer (402).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a Group III nitride semiconductor device using a Group III nitride semiconductor and a manufacturing method thereof. [Background technology]

[0002] Group III nitride semiconductors, particularly Group III nitride semiconductor devices using gallium nitride (GaN) or aluminum gallium nitride (AlGaN), have high breakdown voltages due to the wide band gap of the material. Also, heterostructures such as AlGaN / GaN can be easily formed in Group III nitride semiconductor devices.

[0003] In the AlGaN / GaN heterostructure, a high concentration of electrons (two-dimensional electron gas) is generated on the GaN layer side of the interface between the AlGaN layer and the GaN layer due to the difference between the piezoelectric polarization caused by the lattice constant difference between the materials and the spontaneous polarization of AlGaN and GaN, forming a channel of the two-dimensional electron gas layer. III-nitride semiconductor devices using this channel by the two-dimensional electron gas have a relatively high electron saturation velocity, a relatively high insulation resistance, and a relatively high thermal conductivity, and therefore are applied to high-frequency power devices and the like.

[0004] In order to improve the characteristics of these III-nitride semiconductor devices, it is advisable to reduce as much as possible parasitic resistance components, such as the contact between the ohmic electrode and the two-dimensional electron gas layer in the III-nitride semiconductor device (hereinafter referred to as "ohmic contact") and the channel resistance due to the two-dimensional electron gas.

[0005] Conventionally, in a group III nitride semiconductor device using a channel by two-dimensional electron gas, a technique for reducing the ohmic contact resistance has been proposed. For example, Patent Document 1 discloses a technique for forming an ohmic electrode by forming a recess (hereinafter referred to as a "penetrating recess") penetrating an electron supply layer made of AlGaN in a portion where an ohmic electrode is to be formed in a group III nitride semiconductor device, in order to reduce the ohmic contact resistance. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2021 / 246227 Summary of the Invention [Problem to be solved by the invention]

[0007] However, when a through recess is formed in the electron supply layer as in the technology disclosed in Patent Document 1, it is unavoidable that the two-dimensional electron gas layer and the contact layer embedded in the through recess are essentially connected at a point. In addition, when a through recess is formed in the electron supply layer, not only do crystal defects occur at the interface between the two-dimensional electron gas layer (channel layer) made of GaN and the contact layer when the through recess is formed, but also a region where the carrier (electron) concentration is reduced occurs in the electron supply layer adjacent to the side surface of the through recess due to pollutants in the air and bond defects, resulting in a decrease in the maximum drain current.

[0008] The present disclosure has been made in consideration of such problems, and has an object to provide a semiconductor device capable of suppressing a decrease in maximum drain current, and a manufacturing method thereof. [Means for solving the problem]

[0009] In order to achieve the above object, one aspect of the semiconductor device according to the present disclosure includes an electron transit layer, an electron supply layer provided on the electron transit layer and having a band gap larger than that of the electron transit layer, a gate electrode provided on the electron supply layer, a source side contact layer and a drain side contact layer embedded in recesses penetrating the electron supply layer at positions on either side of the gate electrode, an n-type semiconductor layer made of an n-type semiconductor containing Si, provided in contact with the electron supply layer, in contact with the source side contact layer and / or the drain side contact layer but without in contact with the gate electrode, an alloy layer containing Si and having a thickness of 2 nm or less provided on the n-type semiconductor layer, an insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, in contact with the gate electrode but without in contact with the source side contact layer and / or the drain side contact layer, and a source electrode and / or a drain electrode provided on the source side contact layer and / or the drain side contact layer and on the alloy layer.

[0010] a step of forming an insulating layer containing Si on the electron supply layer without exposing the insulating layer to air; a step of thinning a portion of the insulating layer to form a thin portion in the insulating layer; a step of forming a through recess that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron transit layer while leaving a portion of the thin portion as an insulating layer remnant; a step of embedding a contact layer in the through recess; a step of forming a source electrode and / or a drain electrode across the insulating layer remnant and the contact layer;

[0011] Furthermore, one aspect of a second manufacturing method of a semiconductor device according to the present disclosure includes the steps of: forming an electron supply layer on an electron transit layer, the electron supply layer having a band gap larger than that of the electron transit layer; forming an insulating layer containing Si on the electron supply layer without exposing the insulating layer to air; thinning a portion of the insulating layer to form a thin portion in the insulating layer; forming a through recess that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron transit layer while leaving a portion of the thin portion as an insulating layer remnant; forming a source electrode and / or a drain electrode across the insulating layer remnant and the through recess; Effect of the Invention

[0012] According to the present disclosure, it is possible to obtain a semiconductor device capable of suppressing a decrease in the maximum drain current. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing a conduction band of the energy band of the semiconductor device according to the first embodiment. [Figure 3A] FIG. 3A is a cross-sectional view showing a step of forming a semiconductor stack, a first insulating layer, and a second insulating layer in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view showing a step of forming a thin portion in the first insulating layer in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3C] FIG. 3C is a cross-sectional view showing a step of forming a penetrating recess portion in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3D]FIG. 3D is a cross-sectional view showing a step of forming a contact layer in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3E] FIG. 3E is a cross-sectional view showing a step of forming a source electrode and a drain electrode in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3F] FIG. 3F is a cross-sectional view showing a heat treatment step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3G] FIG. 3G is a cross-sectional view showing a step of forming a gate electrode in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment. [Figure 5A] FIG. 5A is a cross-sectional view showing a step of forming a semiconductor stack, a first insulating layer, and a second insulating layer in a method for manufacturing a semiconductor device according to the second embodiment. [Figure 5B] FIG. 5B is a cross-sectional view showing a step of forming a thin portion in the first insulating layer in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 5C] FIG. 5C is a cross-sectional view showing a step of forming a penetrating recess portion in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 5D] FIG. 5D is a cross-sectional view showing a step of forming a source electrode and a drain electrode in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 5E] FIG. 5E is a cross-sectional view showing a heat treatment step in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 5F] FIG. 5F is a cross-sectional view showing a step of forming a gate electrode in the method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Each embodiment shown here shows a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangement and connection of the components, steps (processes) and the order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept of the present disclosure will be described as optional components.

[0015] In addition, each figure is a schematic diagram and is not necessarily precisely illustrated. Therefore, the scales and the like are not necessarily the same in each figure. In each figure, the same reference numerals are given to substantially the same configurations, and duplicated explanations are omitted or simplified.

[0016] In this specification, the terms "above" and "upper" and "below" and "lower" in the configuration of a semiconductor device do not refer to the upper direction (vertically above) and lower direction (vertically below) in absolute spatial recognition, but are terms defined by a relative positional relationship based on the stacking order in a stacked structure. In addition, the terms "above" and "lower" are applied not only to the case where two components are arranged with a gap between them and another component exists between the two components, but also to the case where two components are arranged closely together and are in contact with each other.

[0017] In this specification and the drawings, the x-axis, y-axis, and z-axis indicate the three axes of a three-dimensional Cartesian coordinate system. In each embodiment, the two axes parallel to the upper surface of the substrate of the semiconductor device are the x-axis and y-axis, and the direction perpendicular to this upper surface is the z-axis direction. In the embodiments described below, the positive direction of the z-axis may be described as "up" and the negative direction of the z-axis may be described as "down." In this specification, "planar view" refers to the substrate of the semiconductor device viewed from the positive direction of the z-axis.

[0018] (Embodiment 1) First, a semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the configuration of the semiconductor device 1 according to the first embodiment.

[0019] In this embodiment, a case will be described in which the semiconductor device 1 is a high electron mobility transistor (HEMT) having a Schottky junction gate structure.

[0020] As shown in FIG. 1, the semiconductor device 1 includes a substrate 101, a buffer layer 102, an electron transit layer 103, an electron supply layer 104, a first insulating layer 201, a second insulating layer 202, a source electrode 301, a drain electrode 302, a gate electrode 303, an electron supply assistance layer 401, and an alloy layer 402.

[0021] The substrate 101 is, for example, a silicon substrate made of Si. In this embodiment, the substrate 101 is, for example, a silicon substrate made of single crystal Si with a (111) principal surface. The substrate 101 is not limited to a silicon substrate, and may be a substrate made of sapphire, SiC, GaN, AlN, or the like, which serves as a base for forming a nitride semiconductor layer. The resistivity of the substrate 101 is, for example, 1 kΩ or more. The substrate 101 may have a resistivity of 20Ω or less.

[0022] The buffer layer 102 is provided on the substrate 101. The buffer layer 102 is, for example, a group III nitride semiconductor layer having a thickness of 2 μm and made of a multi-layer structure of AlN and AlGaN. In this case, 20 to 100 pairs of AlN and AlGaN may be laminated. 1-α Ga α The buffer layer 102 may have a structure in which multiple N (0≦α<0.8) layers are stacked, and may include a superlattice structure. Alternatively, the buffer layer 102 may be composed of a single layer or multiple layers of a group III nitride semiconductor such as InGaN or AlInGaN. The carbon concentration of the buffer layer 102 is preferably 1×10 19 atoms / cm 3As described above, the resistance of the buffer layer 102 may be increased.

[0023] The electron transit layer 103 is provided on the buffer layer 102. In this embodiment, the electron transit layer 103 is, for example, a GaN layer made of GaN with a thickness of 150 nm. The group III nitride semiconductor making up the electron transit layer 103 is not limited to GaN. The electron transit layer 103 may be made of a group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN. The electron transit layer 103 may contain n-type impurities.

[0024] The electron supply layer 104 is provided on the electron transit layer 103. The electron supply layer 104 has a larger band gap than the electron transit layer 103. In this embodiment, the electron supply layer 104 is, for example, an AlGaN layer having a thickness of 13 nm and made of AlGaN with an Al composition ratio of 30%. A high concentration of two-dimensional electron gas is generated on the electron transit layer 103 side of the heterointerface between the electron supply layer 104 and the electron transit layer 103, and a channel of the two-dimensional electron gas layer 105 is formed. Therefore, the semiconductor device 1 has the two-dimensional electron gas layer 105. The details will be described later, but the two-dimensional electron gas layer 105 is made up of a first two-dimensional electron gas layer 105A and a second two-dimensional electron gas layer 105B having different electron concentrations of the two-dimensional electron gas.

[0025] The Al composition ratio of the electron supply layer 104 made of AlGaN is not limited to 30%. The Al composition ratio of the electron supply layer 104 may be 20 to 100%. The group III nitride semiconductor constituting the electron supply layer 104 is not limited to AlGaN. The electron supply layer 104 may be composed of a group III nitride semiconductor containing In, such as AlInGaN. The electron supply layer 104 may contain n-type impurities.

[0026] A cap layer may be provided on the electron supply layer 104. The cap layer may be, for example, a GaN layer having a thickness of about 1 to 2 nm and made of GaN. A spacer layer may be provided between the electron transit layer 103 and the electron supply layer 104. The spacer layer may be, for example, an AlN layer having a thickness of about 1 nm and made of AlN.

[0027] The first insulating layer 201 is provided on the electron supply layer 104. The first insulating layer 201 is an insulating layer containing Si (silicon). In this embodiment, the first insulating layer 201 is a SiN layer made of SiN. Specifically, the first insulating layer 201 is a SiN layer made of in-situ SiN and has a thickness of 2 nm. Note that "in-situ" means that it is formed without exposure to the atmosphere. Therefore, the first insulating layer 201 made of in-situ SiN is a SiN layer formed without exposure to the atmosphere after the electron supply layer 104 is formed.

[0028] By forming the first insulating layer 201 from In-situ SiN in this way, it is possible to eliminate uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104. By eliminating uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104, the generation of interface states is suppressed. This makes it possible to avoid an increase in the potential at the interface and suppress a decrease in the electron concentration of the two-dimensional electron gas.

[0029] The thickness of the first insulating layer 201 is preferably 2 nm or more and 30 nm or less. By making the thickness of the first insulating layer 201 2 nm or more, it is possible to suppress uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 due to natural oxidation. On the other hand, if the thickness of the first insulating layer 201 exceeds 30 nm, the wafer will warp when the semiconductor device 1 is manufactured, and the quality of the semiconductor device 1 will deteriorate. For this reason, it is preferable that the thickness of the first insulating layer 201 is 30 nm or less. In other words, by making the thickness of the first insulating layer 201 30 nm or less, it is possible to suppress warping of the wafer.

[0030] Moreover, it is preferable that the first insulating layer 201 does not contain oxygen. If the first insulating layer 201 contains oxygen, the interface state at the interface between the first insulating layer 201 and the electron supply layer 104 increases, the potential at the interface between the first insulating layer 201 and the electron supply layer 104 increases, and the electron concentration of the two-dimensional electron gas decreases. If the first insulating layer 201 does not contain oxygen, it is possible to suppress a decrease in the electron concentration of the two-dimensional electron gas.

[0031] The second insulating layer 202 is provided on the first insulating layer 201. In the present embodiment, the second insulating layer 202 is in contact with the first insulating layer 201. The thickness of the second insulating layer 202 is thicker than the thickness of the first insulating layer 201, but is not limited to this. In other words, the thickness of the second insulating layer 202 may be thinner than the thickness of the first insulating layer 201. The second insulating layer 202 is made of, for example, SiO 2 The second insulating layer 202 is a silicon oxide layer having a thickness of 50 nm and is made of SiO 2 It may be made of SiN, SiON or the like.

[0032] An opening 201a is provided in the first insulating layer 201. The opening 201a is formed in the first insulating layer 201 in a region where the gate electrode 303 is to be provided. Therefore, the first insulating layer 201 is provided on a portion of the electron supply layer 104 where the gate electrode 303 is not provided.

[0033] Also, an opening 202a is provided in the second insulating layer 202. The opening 202a is formed in the second insulating layer 202 in a region where the gate electrode 303 is to be provided. Therefore, the second insulating layer 202 is provided on a portion of the first insulating layer 201 where the gate electrode 303 is not provided.

[0034] The first insulating layer 201 and the second insulating layer 202 are in contact with the gate electrode 303. Moreover, the first insulating layer 201 and the second insulating layer 202 are not in contact with the contact layer 212. In the present embodiment, the first insulating layer 201 and the second insulating layer 202 are not in contact with either the source side contact layer 212A or the drain side contact layer 212B, but this is not limited thereto. For example, the first insulating layer 201 may not be in contact with either the source side contact layer 212A or the drain side contact layer 212B, but may be in contact with the other. Moreover, the second insulating layer 202 may not be in contact with either the source side contact layer 212A or the drain side contact layer 212B, but may be in contact with the other.

[0035] The electron supply layer 104 is provided with a through recess 211. In the present embodiment, the through recess 211 is provided so as to penetrate through the first insulating layer 201 and the electron supply layer 104 and reach the electron transit layer 103. The through recess 211 reaches the inside of the electron transit layer 103, and a recess is provided in the electron transit layer 103.

[0036] The distance from the upper surface of the electron transit layer 103 to the bottommost part of the bottom surface of the through recess 211 is preferably 10 nm or less. As an example, the distance from the upper surface of the electron transit layer 103 to the bottommost part of the bottom surface of the through recess 211 is 5 nm. The elevation angle from the center to the side of the bottom surface of the through recess 211 is preferably 10 degrees or less, and more preferably 5 degrees or less. In this way, it is possible to reduce crystal defects on the side surface of the through recess 211 when the through recess 211 is formed by dry etching, and to suppress a decrease in the maximum drain current.

[0037] The penetrating recess portion 211 is provided in a region corresponding to the region where the source electrode 301 and the drain electrode 302 are provided. Specifically, the penetrating recess portion 211 is provided as a pair so as to face each other with the gate electrode 303 interposed therebetween.

[0038] A contact layer 212 is provided in the through recess 211. The contact layer 212 is provided so as to fill the through recess 211. The contact layer 212 provided in one of the pair of through recesses 211 is a source side contact layer 212A, and the contact layer 212 provided in the other of the pair of through recesses 211 is a drain side contact layer 212B. The source side contact layer 212A and the drain side contact layer 212B are provided at positions sandwiching the gate electrode 303 therebetween.

[0039] The through recess 211 is provided at a distance from the first insulating layer 201 and the second insulating layer 202. Therefore, the contact layer 212 embedded in the through recess 211 is also at a distance from the first insulating layer 201 and the second insulating layer 202, and the contact layer 212 is not in contact with the first insulating layer 201 and the second insulating layer 202.

[0040] The contact layer 212 is, for example, an n-GaN layer made of n-type GaN. The material constituting the contact layer 212 is not limited to n-type GaN, and may be a group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN containing a donor such as Si or Ge as an n-type impurity, or may be a multilayer electrode film having a laminated structure in which Ti and Al are laminated in this order. The material constituting the contact layer 212 may be Ti, Ta, Al, Au, Hf, Ru, and Cu.

[0041] A source electrode 301 or a drain electrode 302 is provided on the contact layer 212. Specifically, the source electrode 301 is provided on the source-side contact layer 212A, and the drain electrode 302 is provided on the drain-side contact layer 212B. The source electrode 301 and the drain electrode 302 are provided to face each other with a gate electrode 303 interposed therebetween.

[0042] In addition, the source electrode 301 and the drain electrode 302 are provided on the contact layer 212 and the alloy layer 402. In this embodiment, the source electrode 301 and the drain electrode 302 further cover a part of the second insulating layer 202. Specifically, the source electrode 301 is provided so as to cover the source side contact layer 212A, the alloy layer 402, and a part of the second insulating layer 202. In addition, the drain electrode 302 is provided so as to cover the drain side contact layer 212B, the alloy layer 402, and a part of the second insulating layer 202.

[0043] The source electrode 301 and the drain electrode 302 are formed of a multilayer electrode film having a laminated structure in which, for example, a Ti film having a thickness of 30 nm and an Al film having a thickness of 200 nm are laminated in this order, but are not limited to this. The source electrode 301 and the drain electrode 302 may also be formed using Ti, Ta, W, Al, Au, Hf, Ru, and Cu.

[0044] The gate electrode 303 is provided on the electron supply layer 104. Specifically, the gate electrode 303 is provided on the electron supply layer 104 via an opening 201a provided in the first insulating layer 201 and an opening 202a provided in the second insulating layer 202. Note that the opening width of the opening 201a in the first insulating layer 201 and the opening width of the opening 202a in the second insulating layer 202 are the same, but are not limited to this.

[0045] The gate electrode 303 is, for example, a multilayer electrode film having a laminated structure in which a TiN film and an Al film are laminated in order. The gate electrode 303 is not limited to a laminated structure of a TiN film and an Al film, and may be composed of a nitride and a carbide of a transition metal. Specifically, the gate electrode 303 may be composed of TiN, WN, TaN, or HfN. The gate electrode 303 may be composed of Ti, Ta, W, Al, Pd, Pt, Hf, Ru, and Cu, may be a compound containing these elements, or may be a multilayer electrode film having a laminated structure. Another insulating layer or a p-type nitride semiconductor layer may be provided between the electron supply layer 104 and the gate electrode 303.

[0046] The electron supply assistance layer 401 is an n-type semiconductor layer made of an n-type semiconductor containing Si. The thickness of the electron supply assistance layer 401 is preferably 2 nm or less, but is not limited to this. In this embodiment, the electron supply assistance layer 401 is an n-AlGaN layer made of n-type AlGaN containing Si and having a thickness of 1 nm.

[0047] The electron supply auxiliary layer 401 is not in contact with the gate electrode 303, but is in contact with the electron supply layer 104 and the contact layer 212. In a plan view, the electron supply auxiliary layer 401 is provided between the contact layer 212 and the first insulating layer 201. In a cross-sectional view, the electron supply auxiliary layer 401 is provided so as to be embedded in an end portion of the electron supply layer 104 on the contact layer 212 side. Specifically, in a cross-sectional view, the electron supply auxiliary layer 401 is provided so that its upper surface is flush with the upper surface of the electron supply layer 104 and its lower surface is located between the upper and lower surfaces of the electron supply layer 104.

[0048] In this embodiment, the electron supply auxiliary layer 401 is in contact with each of the source side contact layer 212A and the drain side contact layer 212B. Specifically, the electron supply auxiliary layer 401 is embedded in the end of the electron supply layer 104 on the source side contact layer 212A side and is embedded in the end of the electron supply layer 104 on the drain side contact layer 212B side. The electron supply auxiliary layer 401 may be in contact with only one of the source side contact layer 212A and the drain side contact layer 212B. The electron supply auxiliary layer 401 may be divided into a plurality of layers. In this case, the electron supply auxiliary layer 401 on the source electrode 301 side among the plurality of electron supply auxiliary layers 401 may be in contact with the source side contact layer 212A, and the electron supply auxiliary layer 401 on the drain electrode 302 side among the plurality of electron supply auxiliary layers 401 may be in contact with the drain side contact layer 212B.

[0049] The width of the electron supply assist layer 401 may be smaller than the distance L between the end of the electron supply assist layer 401 on the gate electrode 303 side and the gate electrode 303. As an example, the width of the electron supply assist layer 401 is 1 μm or less in a cross-sectional view. In this way, an increase in leakage current between the gate electrode 303 and the drain electrode 302 can be efficiently suppressed.

[0050] Alternatively, one of the electron supply assist layer 401 on the source electrode 301 side and the electron supply assist layer 401 on the drain electrode 302 side may not be in contact with the gate electrode 303, and the other may be in contact with the gate electrode 303. For example, when the width of the electron supply assist layer 401 on the drain electrode 302 side is within the range of the above-mentioned distance L, the electron supply assist layer 401 on the source electrode 301 side may be in contact with the gate electrode 303. In this way, the access resistance between the source electrode 301 and the gate electrode 303 can be reduced, and therefore the maximum drain current can be increased.

[0051] The alloy layer 402 is provided on the electron supply assistance layer 401, which is an n-type semiconductor layer. Specifically, the alloy layer 402 is provided directly on the electron supply assistance layer 401 and is in contact with the electron supply assistance layer 401.

[0052] The alloy layer 402 is a Si-based alloy layer containing Si. The alloy layer 402 is an alloy layer formed by reaction between an element constituting the first insulating layer 201 and an element constituting the source electrode 301 and / or the drain electrode 302. In this case, the Si constituting the alloy layer 402 is derived from the Si contained in the first insulating layer 201. In this embodiment, the first insulating layer 201 is a SiN layer, and the source electrode 301 and the drain electrode 302 are laminated films of a Ti film and an Al film, so that the alloy layer 402 is an alloy layer composed of Ti, Al, Si, and N. Specifically, the alloy layer 402 is a TiAlSiN alloy layer having a thickness of 1 nm composed of a TiAlSiN alloy. The thickness of the alloy layer 402 is not limited to 1 nm, but is preferably 2 nm or less. In this way, the concentration of Si diffusing into the electron supply layer 104 can be increased.

[0053] The alloy constituting the alloy layer 402 is not limited to a TiAlSiN alloy, and various combinations of alloys are possible depending on the types of elements constituting the first insulating layer 201 and the types of elements constituting the source electrode 301 and the drain electrode 302. Specifically, the alloy layer 402 may be made of an alloy containing Si and at least one of the elements Ti, Ta, Al, Au, Hf, Ru, and Cu.

[0054] Furthermore, the alloy layer 402 is not in contact with the gate electrode 303, but is in contact with the contact layer 212. In a plan view, the alloy layer 402 is provided between the contact layer 212 and the first insulating layer 201. In this embodiment, the alloy layer 402 is in contact not only with the contact layer 212, but also with the first insulating layer 201.

[0055] In this embodiment, the alloy layer 402 is in contact with each of the source side contact layer 212A and the drain side contact layer 212B. The alloy layer 402 may be in contact with only one of the source side contact layer 212A and the drain side contact layer 212B. The alloy layer 402 may be divided into a plurality of layers. In this case, the alloy layer 402 on the source electrode 301 side among the plurality of alloy layers 402 may be in contact with the source side contact layer 212A, and the alloy layer 402 on the drain electrode 302 side among the plurality of alloy layers 402 may be in contact with the drain side contact layer 212B.

[0056] By providing the semiconductor device 1 with such a structure, the electron concentration of the two-dimensional electron gas layer 105 can be made different between a portion where the electron supply auxiliary layer 401 and the alloy layer 402 are present and a portion where the electron supply auxiliary layer 401 and the alloy layer 402 are not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A that is not located under the electron supply auxiliary layer 401 and the alloy layer 402, and a second two-dimensional electron gas layer 105B that is located under the electron supply auxiliary layer 401 and the alloy layer 402, and the electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A. The contact layer 212 and the second two-dimensional electron gas layer 105B are electrically connected to each other through an ohmic connection.

[0057] Here, the mechanism by which the electron concentration of the second two-dimensional electron gas layer 105B becomes higher than the electron concentration of the first two-dimensional electron gas layer 105A will be described with reference to Fig. 2. Fig. 2 is a schematic diagram showing the conduction band of the energy band of the semiconductor device 1 according to the first embodiment.

[0058] In FIG. 2, the solid line A is a diagram of a portion corresponding to the dashed line A in FIG. 1, and the dashed line B is a diagram of a portion corresponding to the dashed line B in FIG. 1. That is, the solid line A in FIG. 2 is a diagram of a gate adjacent portion adjacent to the gate electrode 303 (i.e., a portion where the electron supply auxiliary layer 401 and the alloy layer 402 are not provided), and the names of the corresponding layers are indicated by a row of double-headed arrows (A) on the lower side. Also, the dashed line B in FIG. 2 is a diagram of a contact adjacent portion adjacent to the contact layer 212 (i.e., a portion where the electron supply auxiliary layer 401 and the alloy layer 402 are provided), and the names of the corresponding layers are indicated by a row of double-headed arrows (B) on the upper side. Note that the dashed line above the electron supply auxiliary layer 401 (left side in the figure) indicates that the Fermi level of the drain electrode 302, which is a metal, coincides with the conduction band.

[0059] As described above, in the semiconductor device 1 of the present embodiment, the electron supply auxiliary layer 401 made of an n-type semiconductor is provided inside the electron supply layer 104. As a result, the potential of the electron supply layer 104 is relatively lowered in the portion where the electron supply layer 104 is provided, and the potential at the interface between the electron supply layer 104 and the electron transit layer 103 is lowered. As a result, the electron concentration of the second two-dimensional electron gas layer 105B increases. That is, the electron concentration of the second two-dimensional electron gas layer 105B located below the electron supply auxiliary layer 401 becomes higher relative to the electron concentration of the first two-dimensional electron gas layer 105A not located below the electron supply auxiliary layer 401.

[0060] In this way, the electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A, so that the electron concentration of the side adjacent portion of the through recess portion 211 in the electron supply layer 104 can be prevented from decreasing. As a result, the maximum drain current can be prevented from decreasing. Moreover, since the electron concentration of the gate adjacent portion corresponding to the first two-dimensional electron gas layer 105A is maintained, the leakage current between the gate electrode 303 and the drain electrode 302 can also be reduced. In other words, the configuration of the semiconductor device 1 in this embodiment can achieve both the suppression of the decrease in the maximum drain current and the reduction of the leakage current between the gate and the drain. Moreover, since the current increases not only through the contact layer 212 but also through the electron supply auxiliary layer 401 and the alloy layer 402, the maximum drain current can be further prevented from decreasing.

[0061] In the semiconductor device 1 according to the present embodiment, the width of the electron supply assistance layer 401 is preferably 1 μm or less. This makes it possible to efficiently reduce the leakage current between the gate electrode 303 and the drain electrode 302.

[0062] In the semiconductor device 1 according to the present embodiment, the band gap of the electron supply layer 104 on the electron supply assist layer 401 side may be smaller than the band gap of the electron supply layer 104 on the electron transit layer 103 side below the electron supply layer 401. Specifically, when the electron supply layer 104 is made of AlGaN, the Al composition of the electron supply layer 104 on the electron supply assist layer 401 side may be smaller than the Al composition of the electron supply layer 104 on the electron transit layer 103 side. Since the electron affinity of AlGaN decreases as the Al composition increases, the barrier height decreases when the alloy layer 402 containing Si is brought into contact with the electron supply assist layer 401. Therefore, the ohmic contact resistance can be reduced by making the band gap of the electron supply layer 104 on the electron supply assist layer 401 side smaller than the band gap of the electron supply layer 104 on the electron transit layer 103 side. Moreover, the variation in the drain current can be reduced by reducing the ohmic contact resistance.

[0063] In the semiconductor device 1 according to the present embodiment, the first insulating layer 201 and the electron supply auxiliary layer 401 may contain halogen such as fluorine (F) or chlorine (Cl). The halogen concentration of the first insulating layer 201 and the electron supply auxiliary layer 401 is preferably 1×10 18 atoms / cm 3 The halogen concentration in the first insulating layer 201 is preferably 1×10 or less. This is because the halogen contained in the semiconductor layer or insulating layer has a high electronegativity and becomes a negative fixed charge. 18 atoms / cm 3 or less, it is possible to reduce the negative fixed charges in the first insulating layer 201. This makes it possible to prevent an increase in the potential at the interface between the electron supply layer 104 and the electron transit layer 103, and to prevent a decrease in the electron concentration in the second two-dimensional electron gas layer 105B due to the halogen.

[0064] In the semiconductor device 1 of the present embodiment, the thickness of the first insulating layer 201 may be greater than the thickness of the alloy layer 402. In this way, the leakage current between the gate electrode 303 and the drain electrode 302 can be further reduced.

[0065] Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. 3A to 3G. FIGS. 3A to 3G are cross-sectional views showing steps in the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. 3A shows a step of forming the semiconductor stacked structure 100, the first insulating layer 201, and the second insulating layer 202. FIG. 3B shows a step of forming the thin portion 201b in the first insulating layer 201. FIG. 3C shows a step of forming the through recess portion 211. FIG. 3D shows a step of forming the contact layer 212. FIG. 3E shows a step of forming the source electrode 301 and the drain electrode 302. FIG. 3F shows a step of performing a heat treatment. FIG. 3G shows a step of forming the gate electrode 303.

[0066] First, as shown in FIG. 3A, a semiconductor laminated structure 100 including a buffer layer 102, an electron transit layer 103, and an electron supply layer 104 is formed on a substrate 101 by metal organic chemical vapor deposition (MOCVD) (semiconductor laminated structure formation process).

[0067] In this embodiment, a buffer layer 102 having a layered structure of AlN and AlGaN with a layer thickness of 2 μm, an electron transit layer 103 having a layer thickness of 200 nm and made of GaN, and an electron supply layer 104 having a layer thickness of 20 nm and made of AlGaN with an Al composition ratio of 25% are formed on a substrate 101 made of Si in the +c plane direction ( <0001> The semiconductor laminated structure 100 is formed by epitaxial growth in the first direction (the first direction) and the second direction (the second direction).

[0068] Next, a first insulating layer 201 is formed on the semiconductor laminated structure 100 as an insulating layer containing Si (first insulating layer forming step). Specifically, after forming the semiconductor laminated structure 100, the first insulating layer 201 made of SiN and having a layer thickness of 2 nm is formed in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without exposure to the atmosphere. In this way, by forming the first insulating layer 201 directly on the electron supply layer 104 without exposure to the atmosphere, oxygen is not unevenly distributed between the electron supply layer 104 and the first insulating layer 201.

[0069] Next, the second insulating layer 202 is formed on the first insulating layer 201 (second insulating layer forming step). Specifically, after the first insulating layer 201 is formed, the semiconductor stacked structure 100 and the substrate 101 on which the first insulating layer 201 is formed are transferred to another device and SiO 2 The second insulating layer 202 has a thickness of 50 nm. In this structure, a high concentration of two-dimensional electron gas is generated on the electron transit layer 103 side of the heterointerface between the electron supply layer 104 and the electron transit layer 103, and a two-dimensional electron gas layer 105 is formed.

[0070] The film formation conditions for forming the first insulating layer 201 and the second insulating layer 202 are, for example, a growth temperature of 900 to 1150° C. and a source gas of SiH 4 and N.H. 3 In order to prevent halogen from being mixed as an impurity into the first insulating layer 201, it is better not to use halogen when dry cleaning the inside of the MOCVD furnace. Even if halogen is used during dry cleaning, N 2 or NH 3 It is advisable to remove halogens from inside the MOCVD furnace using methods such as the above.

[0071] Next, as shown in FIG. 3B, a part of the first insulating layer 201 is thinned to form a thin portion 201b in the first insulating layer 201 (thin portion forming step).

[0072] Specifically, a resist is applied onto the second insulating layer 202, and then the resist is patterned by lithography to form a mask (resist mask) on the second insulating layer 202 except for the regions where the contact layer 212, the electron supply assist layer 401, and the alloy layer 402 are to be formed. That is, openings are formed in the resist in the regions where the contact layer 212, the electron supply assist layer 401, and the alloy layer 402 are to be formed. Specifically, openings are formed in regions including the regions where the source side contact layer 212A and the drain side contact layer 212B are to be formed.

[0073] Then, etching is performed using a resist having an opening as a mask, thereby removing a part of the second insulating layer 202 and thinning a part of the first insulating layer 201. In this case, dry etching and wet etching are performed using a resist having an opening as a mask, thereby selectively removing the second insulating layer 202 from the first insulating layer 201. That is, by performing dry etching and wet etching, the second insulating layer 202 is removed and the first insulating layer 201 is thinned in the region where the contact layer 212, the electron supply auxiliary layer 401, and the alloy layer 402 are formed. As a result, as shown in FIG. 3B, a part of the first insulating layer 201 (the region where the contact layer 212, the electron supply auxiliary layer 401, and the alloy layer 402 are formed) is thinned, and the thin portion 201b can be formed in the first insulating layer 201 as a remaining film. Then, the mask (resist) and the polymer generated by the dry etching are removed.

[0074] When wet etching is performed on the first insulating layer 201 and the second insulating layer 202, the second insulating layer 202 can be selectively removed with respect to the first insulating layer 201 by using DHF or BHF. 2 When forming the second insulating layer 202 made of, the surface of the first insulating layer 201 may be oxidized to selectively remove only a portion of the first insulating layer 201.

[0075] Also, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is preferably 2 nm or less. In this case, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is preferably more than half the thickness of the first insulating layer 201 before thinning (i.e., more than half should be left), but is not limited to this. As an example, when the thickness of the first insulating layer 201 before thinning is 2 nm, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is 1.5 nm.

[0076] 3C, an end of the thin portion 201b of the first insulating layer 201 and a part of the semiconductor stack 100 are removed to form a through recess 211 (through recess forming step). Specifically, the through recess 211 is formed so as to penetrate through the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron transit layer 103 while leaving a part of the thin portion 201b of the first insulating layer 201 as the insulating layer remaining portion 201b1.

[0077] In this case, first, a resist is applied onto the second insulating layer 202 and onto a part of the thin portion 201b of the first insulating layer 201, and then the resist is patterned by lithography to form a mask (resist mask) in an area other than the area where the through recess 211 is to be formed. That is, the resist forms an opening in the area where the through recess 211 is to be formed. Specifically, the resist has an opening in each of the areas where the source side contact layer 212A and the drain side contact layer 212B are to be formed.

[0078] Next, dry etching is performed using the resist having the opening as a mask, thereby forming a through recess 211 that penetrates through the end of the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron transit layer 103 while leaving a part of the thin portion 201b of the first insulating layer 201 as the insulating layer remaining portion 201b1. Specifically, as shown in FIG. 3C, two through recesses 211 are formed corresponding to the regions where the source side contact layer 212A and the drain side contact layer 212B are formed. By forming the through recess 211, a part of the electron transit layer 103 is exposed. Thereafter, the mask (resist) and the polymer generated by the dry etching are removed.

[0079] In the present embodiment, the penetrating recess 211 is formed by dry etching, but the method is not limited to this. Specifically, the penetrating recess 211 may be formed by wet etching.

[0080] Alternatively, after the first insulating layer 201 is thinned and the through-hole recess 211 is formed by dry etching, the side surface of the electron supply layer 104 may be selectively wet-etched using SPM, APM, or KOH. This allows the side surface of the through-hole recess 211 to be an inclined surface. Specifically, the side surface of the through-hole recess 211 can be an inclined surface having an elevation angle of 5 degrees or less in the direction from the center of the bottom surface of the through-hole recess 211 to the side portion.

[0081] Next, as shown in FIG. 3D, the contact layer 212 is embedded in the penetrating recess portion 211 (contact layer forming step).

[0082] Specifically, the second insulating layer 202 and the insulating layer remaining portion 201b1 of the first insulating layer 201 are used as a mask to form a n-type insulating film by MOCVD so as to fill the two through recess portions 211. + As a result, n-GaN is grown in each of the two through recesses 211. + The contact layer 212 made of -GaN can be selectively embedded and formed. The contact layer 212 embedded in one of the two through-recess portions 211 is the source-side contact layer 212A, and the contact layer 212 embedded in the other of the two through-recess portions 211 is the drain-side contact layer 212B.

[0083] In this embodiment, Si is doped as an n-type impurity, and the n + The contact layer 212 was formed by growing -GaN. The Si doping concentration of the contact layer 212 was, for example, 2×10 19 / cm 3The contact layer 212 may be formed by sputtering instead of regrowth, or may be formed by ion implantation and plasma treatment without forming the penetrating recess portion 211.

[0084] Next, as shown in FIG. 3E, source electrode 301 and drain electrode 302 are formed across insulating layer remaining portion 201b1 of first insulating layer 201 and contact layer 212 (source electrode / drain electrode forming step).

[0085] Specifically, a 30 nm thick Ti film and a 200 nm thick Al film are deposited in this order by vapor deposition or sputtering to form a laminated film, and then unnecessary laminated film is removed by lift-off to form a source electrode 301 and a drain electrode 302 of a predetermined shape made of a laminated film of a Ti film and an Al film on the contact layer 212. In this embodiment, the source electrode 301 is formed on the source side contact layer 212A, and the drain electrode 302 is formed on the drain side contact layer 212B. Then, the resist mask and the polymer are removed.

[0086] In this embodiment, the source electrode 301 and the drain electrode 302 are formed by deposition and lift-off, but the present invention is not limited to this. For example, a Ti film and an Al film may be deposited in this order by sputtering to form a laminated film, and then the laminated film may be patterned by lithography and dry etching to form the source electrode 301 and the drain electrode 302 in a predetermined shape.

[0087] Next, as shown in FIG. 3F, a heat treatment is performed to form an electron supply auxiliary layer 401 and an alloy layer 402 on the insulating layer remaining portion 201b1 of the first insulating layer 201 and on the electron supply layer 104 (heat treatment step).

[0088] The temperature of this heat treatment is, for example, 400 to 600° C., and preferably 500 to 550° C. The heat treatment is preferably performed in an atmosphere that does not contain oxygen. 2 The material was subjected to a heat treatment at a temperature of 540° C. in an atmosphere.

[0089] By carrying out heat treatment in this manner, the elements constituting each of the insulating layer remaining portion 201b1 of the first insulating layer 201 and the electron supply layer 104 and the elements constituting each of the source electrode 301 and the drain electrode 302 are mutually diffused and alloyed by heat, forming the electron supply auxiliary layer 401 and the alloy layer 402.

[0090] Specifically, in this embodiment, the first insulating layer 201 is an insulating layer containing Si, and the electron supply layer 104 is an AlGaN layer, so that an upper layer portion of the electron supply layer 104 in contact with the insulating layer remaining portion 201b1 of the first insulating layer 201 becomes n-type due to the formation of nitrogen vacancies caused by the diffusion of Si constituting the first insulating layer 201, and an n-type AlGaN layer is formed as the electron supply auxiliary layer 401. That is, the electron supply auxiliary layer 401, which is an n-type semiconductor layer, is formed.

[0091] Moreover, in this embodiment, since the source electrode 301 and the drain electrode 302 contain Ti, the formation of nitrogen vacancies due to the diffusion of this Ti also causes the upper portion of the electron supply layer 104 to become n-type. That is, in this embodiment, the diffusion of Si and Ti due to the heat treatment causes the upper portion of the electron supply layer 104 to become n-type, and the electron supply assistance layer 401, which is an n-type semiconductor layer, is formed.

[0092] In this manner, the upper portion of the electron supply layer 104 becomes n-type to form the electron supply auxiliary layer 401, which is an n-type semiconductor layer, thereby generating the second two-dimensional electron gas layer 105B having a higher electron concentration than the first two-dimensional electron gas layer 105A. As a result, the second two-dimensional electron gas layer 105B is electrically connected to the source electrode 301 and the drain electrode 302 in an ohmic contact.

[0093] In order to facilitate diffusion of Si in the first insulating layer 201 to the electron supply layer 104 by heat treatment, it is preferable that the insulating layer remaining portion 201b1, which is a part of the thin portion 201b of the first insulating layer 201, is thin. In this case, as described above, it is preferable that the thickness of the thin portion 201b of the first insulating layer 201 is 2 nm or less. In this way, the Si content in the upper portion of the electron supply layer 104 can be increased, and the upper portion of the electron supply layer 104 can be made more n-type.

[0094] 3G, a portion of the first insulating layer 201 that is spaced apart from the source electrode 301 and the drain electrode 302 is removed to form a gate electrode 303 (gate electrode formation step). In this embodiment, since the second insulating layer 202 is formed on the first insulating layer 201, a portion of the first insulating layer 201 and the second insulating layer 202 that is spaced apart from the source electrode 301 and the drain electrode 302 is removed to form the gate electrode 303.

[0095] Specifically, after applying a resist onto the second insulating layer 202, a mask (resist mask) is formed by lithography except for the region where the gate electrode 303 is to be formed (region where the gate electrode is to be formed). Next, the second insulating layer 202 and the first insulating layer 201 are selectively removed by dry etching to form an opening 201a in the first insulating layer 201 so that the electron supply layer 104 is exposed, and an opening 202a in the second insulating layer 202 is also formed. Next, the mask (resist mask) and polymer generated by dry etching are removed. Thereafter, the gate electrode 303 is formed in the openings 201a and 202a. Specifically, a laminated film is formed by depositing a TiN film having a layer thickness of 50 nm and an Al film having a layer thickness of 450 nm in this order by sputtering, and then the laminated film is patterned by lithography and dry etching to form the gate electrode 303 having a predetermined shape as shown in FIG. 3F. Thereafter, the mask and polymer generated by dry etching are removed.

[0096] In this manner, through the series of steps shown in FIGS. 3A to 3G, the semiconductor device 1 having the structure shown in FIG. 1 is completed.

[0097] (Embodiment 2) Next, a semiconductor device 2 according to a second embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view showing the configuration of the semiconductor device 2 according to the second embodiment. Note that the following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0098] The semiconductor device 2 according to the present embodiment has a different configuration of the source electrode 301A and the drain electrode 302A compared to the semiconductor device 1 according to the above-mentioned embodiment 1. Specifically, the source electrode 301A and the drain electrode 302A in the present embodiment are the same as the source electrode 301 and the drain electrode 302 in the semiconductor device 1 according to the above-mentioned embodiment 1, but are integrated with the contact layer 212 and made of the same material.

[0099] More specifically, the source electrode 301A in this embodiment is the same as the source electrode 301 and the source side contact layer 212A in the above embodiment 1, which are made of the same material and integrated together. Also, the drain electrode 302A in this embodiment is the same as the drain electrode 302 and the drain side contact layer 212B in the above embodiment 1, which are made of the same material and integrated together. In other words, the semiconductor device 2 according to this embodiment does not have a contact layer made of a semiconductor material.

[0100] In this embodiment, the source electrode 301A and the drain electrode 302A are provided so as to fill the through recess portion 211. The source electrode 301A and the drain electrode 302A are provided so as to cover the alloy layer 402 and a part of the second insulating layer 202. The source electrode 301A and the drain electrode 302A are formed of a multilayer electrode film having a laminated structure in which, for example, a Ti film having a thickness of 30 nm and an Al film having a thickness of 200 nm are laminated in this order, but this is not limited thereto. The source electrode 301A and the drain electrode 302A do not contain Au, but this is not limited thereto. The material forming the source electrode 301A and the drain electrode 302A may be formed using Ti, Ta, Al, Hf, Ru, and Cu.

[0101] The source electrode 301A and the drain electrode 302A thus configured are electrically ohmic-connected to the second two-dimensional electron gas layer 105B.

[0102] The semiconductor device 2 according to the present embodiment can also provide the same effects as those of the above-described embodiment 1. Specifically, the present embodiment also includes the electron supply auxiliary layer 401, which is an n-type semiconductor layer, and the alloy layer 402, so that the electron concentration of the second two-dimensional electron gas layer 105B is greater than the electron concentration of the first two-dimensional electron gas layer 105A. This can prevent the electron concentration of the electron supply layer 104 at the side adjacent portion of the through recess portion 211 from decreasing, thereby preventing a decrease in the maximum drain current.

[0103] Furthermore, in the semiconductor device 2 according to the present embodiment, the source electrode 301A and the drain electrode 302A also function as contact layers, and no contact layer made of a semiconductor material is provided. This makes it possible to eliminate the process of forming the contact layer. Also, in the semiconductor device 2 according to the present embodiment, the source electrode 301A and the drain electrode 302A do not contain Au, making it possible to reduce manufacturing costs.

[0104] Next, a method for manufacturing the semiconductor device 2 according to the present embodiment will be described with reference to FIGS. 5A to 5F. FIGS. 5A to 5F are cross-sectional views showing steps in the method for manufacturing the semiconductor device 2 according to the second embodiment. FIG. 5A shows a step of forming the semiconductor stack 100, the first insulating layer 201, and the second insulating layer 202. FIG. 5B shows a step of forming the thin portion 201b in the first insulating layer 201. FIG. 5C shows a step of forming the through recess portion 211. FIG. 5D shows a step of forming the source electrode 301A and the drain electrode 302A. FIG. 5E shows a step of performing a heat treatment. FIG. 5F shows a step of forming the gate electrode 303.

[0105] First, as shown in Fig. 5A, a semiconductor laminated structure 100 including a buffer layer 102, an electron transit layer 103, and an electron supply layer 104 is formed on a substrate 101 by MOCVD (semiconductor laminated structure forming step). This step is the same as the step shown in Fig. 3A in the first embodiment.

[0106] 5B, a part of the first insulating layer 201 is thinned to form a thin portion 201b in the first insulating layer 201 (thin portion forming step). This step is the same as the step of FIG. 3B in the first embodiment.

[0107] Next, as shown in Fig. 5C, an end of the thin portion 201b of the first insulating layer 201 and a part of the semiconductor stack 100 are removed to form a through recess 211 (through recess forming step). Specifically, the through recess 211 is formed so as to penetrate through the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron transit layer 103 while leaving a part of the thin portion 201b of the first insulating layer 201 as the insulating layer remaining portion 201b1. This step is the same as the step shown in Fig. 3C in the first embodiment.

[0108] 5D, the source electrode 301A and the drain electrode 302A are embedded in the through-recess portion 211 (source electrode / drain electrode forming step). Specifically, the source electrode 301A and the drain electrode 302A are formed across the insulating layer remaining portion 201b1 of the first insulating layer 201 and the through-recess portion 211.

[0109] In this embodiment, the second insulating layer 202 and the first insulating layer 201 are used as masks, and a Ti film and an Al film are deposited in order by a sputtering method so as to fill the through recess 211 to form a laminated film, and then a mask is formed by a lithography method in the region where the source electrode 301A and the drain electrode 302A are to be formed. The region where this mask is formed is a region that straddles the through recess 211, the insulating layer remaining portion 201b1 of the first insulating layer 201, and the second insulating layer 202 in a plan view. Thereafter, the Al film and the Ti film other than the region where the mask is formed are removed by a dry etching method, so that the source electrode 301A and the drain electrode 302A are formed straddling the insulating layer remaining portion 201b1 of the first insulating layer 201 and the through recess 211. Then, the mask and the polymer are removed.

[0110] 5E, a heat treatment is performed to form an electron supply auxiliary layer 401 and an alloy layer 402 in the insulating layer remaining portion 201b1 of the first insulating layer 201 and the electron supply layer 104 (heat treatment step). This step is the same as the step in FIG. 3F in the first embodiment. That is, by performing the heat treatment, elements constituting the insulating layer remaining portion 201b1 of the first insulating layer 201 and the electron supply layer 104 and elements constituting the source electrode 301A and the drain electrode 302A are mutually diffused and alloyed by heat, and the electron supply auxiliary layer 401 and the alloy layer 402 are formed.

[0111] Next, as shown in Fig. 5F, a portion of the first insulating layer 201 that is spaced apart from the source electrode 301A and the drain electrode 302A is removed to form the gate electrode 303 (gate electrode formation step). In the present embodiment, the second insulating layer 202 is also formed on the first insulating layer 201, so that a portion of the first insulating layer 201 and the second insulating layer 202 that is spaced apart from the source electrode 301A and the drain electrode 302A is removed to form the gate electrode 303. This step is the same as the step of Fig. 3G in the first embodiment.

[0112] In this manner, through the series of steps shown in FIGS. 5A to 5F, the semiconductor device 2 having the structure shown in FIG. 4 is completed.

[0113] (Modification) Although the semiconductor device according to the present disclosure has been described based on the first and second embodiments, the present disclosure is not limited to the first and second embodiments.

[0114] For example, in the first and second embodiments, the electron transit layer 103 and the electron supply layer 104 are made of a group III nitride semiconductor, but this is not limiting. Specifically, the electron transit layer 103 and the electron supply layer 104 may be made of other semiconductor materials, such as a group III arsenide semiconductor.

[0115] In addition, the present disclosure also includes forms obtained by applying various modifications to the above-mentioned embodiments that a person skilled in the art may conceive, and forms realized by arbitrarily combining the components and functions of the embodiments within the scope of the present disclosure. In addition, the present disclosure also includes any combination of two or more claims from among the multiple claims described in the claims at the time of filing of the present application, within the scope of technical compatibility. For example, when a cited-form claim described in the claims at the time of filing of the present application is made into a multiple claim or multiple multiple claim so as to cite all of the higher claims within the scope of technical compatibility, the present disclosure also includes a combination of all claims included in the multiple claim or multiple multiple claim. [Industrial Applicability]

[0116] The technology disclosed herein can be used in semiconductor devices such as switching transistors used in communication devices and inverters that require high-speed operation, and power supply circuits, etc. Among these, the technology disclosed herein is particularly useful for high-frequency power devices that have a significant impact on heat generation due to ohmic contact resistance. [Explanation of symbols]

[0117] 1, 2 Semiconductor device 100 Semiconductor laminated structure 101 Substrate 102 Buffer Layer 103 Electron Transport Layer 104 Electron supply layer 105 Two-dimensional electron gas layer 105A First two-dimensional electron gas layer 105B Second two-dimensional electron gas layer 201 First insulating layer 201a opening 201b Thin section 201b1 Residual part of insulation layer 202 Second insulating layer 202a opening 211 Through recess 212 Contact layer 212A Source side contact layer 212B Drain side contact layer 301, 301A Source electrode 302, 302A Drain electrode 303 Gate electrode 401 Electron supply auxiliary layer 402 alloy layer

Claims

1. An electron transport layer; an electron supply layer provided on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate electrode provided on the electron supply layer; a source-side contact layer and a drain-side contact layer embedded in a recess that penetrates the electron supply layer at positions that sandwich the gate electrode; an n-type semiconductor layer made of an n-type semiconductor containing Si, which is in contact with the electron supply layer, in contact with the source side contact layer and / or the drain side contact layer, and not in contact with the gate electrode; an alloy layer provided on the n-type semiconductor layer, containing Si and having a thickness of 2 nm or less; an insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, the insulating layer being in contact with the gate electrode and not in contact with the source side contact layer and / or the drain side contact layer; a source electrode and / or a drain electrode provided on the source side contact layer and / or the drain side contact layer and on the alloy layer; Semiconductor device.

2. The thickness of the n-type semiconductor layer is 2 nm or less.

2. The semiconductor device according to claim 1 .

3. In a cross-sectional view, the width of the n-type semiconductor layer is 1 μm or less.

3. The semiconductor device according to claim 1 or 2.

4. a band gap of a portion of the electron supply layer on the n-type semiconductor layer side under the n-type semiconductor layer is smaller than a band gap of a portion of the electron supply layer on the electron transit layer side; 3. The semiconductor device according to claim 1 or 2.

5. the source electrode and the source-side contact layer are made of the same material and do not contain Au; The drain electrode and the drain-side contact layer are made of the same material and do not contain Au.

3. The semiconductor device according to claim 1 or 2.

6. The insulating layer has a halogen concentration of 1×10 １８ atoms / cm ３ Below is the 3. The semiconductor device according to claim 1 or 2.

7. The thickness of the insulating layer is greater than the thickness of the alloy layer.

3. The semiconductor device according to claim 1 or 2.

8. The thickness of the insulating layer is 2 nm or more and 30 nm or less. The semiconductor device according to claim 7.

9. There is no uneven distribution of oxygen between the insulating layer and the electron supply layer.

3. The semiconductor device according to claim 1 or 2.

10. the electron transit layer and the electron supply layer are made of a Group III nitride semiconductor; 3. The semiconductor device according to claim 1 or 2.

11. forming an electron supply layer on an electron transit layer, the electron supply layer having a band gap larger than that of the electron transit layer; forming an insulating layer containing Si on the electron supply layer without exposing it to air; thinning a portion of the insulating layer to form a thin portion in the insulating layer; forming a through recess portion penetrating the thin portion of the insulating layer and the electron supply layer to reach the electron transit layer while leaving a part of the thin portion as an insulating layer remnant; forming a contact layer by embedding the through recess portion; forming a source electrode and / or a drain electrode across the remaining portion of the insulating layer and the contact layer; a step of performing a heat treatment to form an alloy layer and an electron supply auxiliary layer in the remaining portion of the insulating layer and the electron supply layer; and removing the insulating layer from a portion of the insulating layer spaced from the source electrode and / or the drain electrode to form a gate electrode. A method for manufacturing a semiconductor device.

12. forming an electron supply layer on an electron transit layer, the electron supply layer having a band gap larger than that of the electron transit layer; forming an insulating layer containing Si on the electron supply layer without exposing it to air; thinning a portion of the insulating layer to form a thin portion in the insulating layer; forming a through recess portion penetrating the thin portion of the insulating layer and the electron supply layer to reach the electron transit layer while leaving a part of the thin portion as an insulating layer remnant; forming a source electrode and / or a drain electrode across the remaining portion of the insulating layer and the through-hole recess; a step of performing a heat treatment to form an alloy layer and an electron supply auxiliary layer in the remaining portion of the insulating layer and the electron supply layer; and removing the insulating layer from a portion of the insulating layer spaced from the source electrode and / or the drain electrode to form a gate electrode. A method for manufacturing a semiconductor device.

13. The insulating layer is made of SiN. The method for manufacturing a semiconductor device according to claim 11 or 12.

14. There is no uneven distribution of oxygen between the insulating layer and the electron supply layer. The method for manufacturing a semiconductor device according to claim 13.

15. In the step of forming a thin portion in the insulating layer, the thin portion has a thickness of 2 nm or less. The method for manufacturing a semiconductor device according to claim 11 or 12.

16. the electron transit layer and the electron supply layer are made of a Group III nitride semiconductor; The method for manufacturing a semiconductor device according to claim 11 or 12.

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