Semiconductor device simulation method, semiconductor device simulation device, semiconductor device simulation program, and data structure

Abstract

To provide a simulation method of a semiconductor device capable of improving accuracy.SOLUTION: Provided is a simulation method of a semiconductor device. The semiconductor device includes a first electrode, a second electrode, a semiconductor portion arranged between the first electrode and the second electrode, an insulation member arranged in the semiconductor portion, a third electrode arranged in the insulation member, and a fourth electrode arranged between the first electrode and the third electrode in the insulation member. The semiconductor portion includes a first conductivity type first semiconductor layer connected to the first electrode, a first conductivity type second semiconductor layer connected to the second electrode, and a second conductivity type third semiconductor layer brought into contact with the first semiconductor layer and the second semiconductor layer. A value of a first resistance connected between the second electrode and the fourth electrode is changed by a value of a first voltage between the first electrode and the second electrode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a method for simulating a semiconductor device, a simulation device for a semiconductor device, and a simulation program and data structure for a semiconductor device. [Background technology]

[0002] In recent years, FP-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have been developed as power control MOSFETs, in which the gate electrode is placed in a trench and a field plate electrode (FP) is provided below the gate electrode. FP-type MOSFETs are often developed while estimating their electrical characteristics through simulation. For this reason, there is a demand for improved simulation accuracy. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5069711 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device simulation method, a semiconductor device simulation device, a semiconductor device simulation program, and a data structure that enable improvement in accuracy. [Means for solving the problem]

[0005] The simulation method according to the embodiment is a simulation method for a semiconductor device. The semiconductor device includes a first electrode, a second electrode, a semiconductor portion disposed between the first electrode and the second electrode, an insulating member disposed in the semiconductor portion, a third electrode disposed in the insulating member, and a fourth electrode disposed in the insulating member between the first electrode and the third electrode. The semiconductor portion includes a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of the first conductivity type connected to the second electrode, and a third semiconductor layer of a second conductivity type in contact with the first semiconductor layer and the second semiconductor layer. A value of a first resistor connected between the second electrode and the fourth electrode is changed depending on a value of a first voltage between the first electrode and the second electrode. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a simulation device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing a semiconductor device that is a target of simulation in the first embodiment. [Diagram 3] FIG. 3 is a graph showing the operation of a semiconductor device, with the horizontal axis representing time and the vertical axis representing the drain-source voltage VDS and the drain-source current Id. [Figure 4] FIG. 4 is a diagram in which elements of an equivalent circuit are superimposed on the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a circuit diagram showing an equivalent circuit assumed in the simulation according to the first embodiment. [Figure 6] FIG. 6 is a graph showing the relationship between the voltage VDS and the resistance RDS(OFF) in the first embodiment, with the drain-source voltage VDS on the horizontal axis and the drain-source resistance RDS(OFF) on the vertical axis. [Figure 7] FIG. 7 is a diagram showing a simulation method according to the first embodiment. [Figure 8]FIG. 8 is a graph showing the relationship between the voltage VDS and the resistance RDS(OFF) in the second embodiment, with the horizontal axis representing the drain-source voltage VDS and the vertical axis representing the drain-source resistance RDS(OFF). [Figure 9] FIG. 9 is a diagram showing a simulation method according to the third embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a resistive load switching circuit used in the test example. [Figure 11] 11(a) to (c) are graphs showing the results of a test example, with the horizontal axis representing time and the vertical axis representing the drain-source voltage VDS and the drain-source current Id. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <First embodiment> The present embodiment relates to a simulation device, a simulation method, a simulation program, and a data structure used in the simulation, which estimate the operation of a semiconductor device. FIG. 1 is a block diagram showing a simulation device according to this embodiment.

[0008] As shown in FIG. 1, the simulation device 1 according to this embodiment includes a calculation unit 10, a storage unit 20, and an input / output unit 30. The calculation unit 10 includes, for example, a CPU (Central Processing Unit). The storage unit 20 includes, for example, an SSD (Solid State Drive) or an HDD (Hard Disk Drive). The input / output unit 30 includes, for example, interface means such as a keyboard and a display, and communication means with the outside such as various cable terminals and wireless devices. The calculation unit 10 is connected to the storage unit 20 and the input / output unit 30. A simulation program described later is stored in the storage unit 20.

[0009] Next, a semiconductor device that is a target of the simulation in this embodiment will be described. FIG. 2 is a cross-sectional view showing a semiconductor device that is a target of the simulation in this embodiment.

[0010] 2, the semiconductor device 100 to be simulated in this embodiment is a field plate MOSFET. The semiconductor device 100 includes a drain electrode 101 (first electrode), a source electrode 102 (second electrode), a gate electrode 103 (third electrode), a field plate (FP) electrode 104 (fourth electrode), a semiconductor portion 110, and an insulating member 120. Note that, although the following description will be given taking as an example a case where the semiconductor device 100 is an n-channel MOSFET (nMOS), the semiconductor device 100 may also be a p-channel MOSFET (pMOS).

[0011] 2, among the external terminals connected to the semiconductor device 100, the drain terminal connected to the drain electrode 101 is indicated as "Drain", the source terminal connected to the source electrode 102 is indicated as "Source", and the gate terminal connected to the gate electrode 103 is indicated as "Gate". The same applies to other figures described later.

[0012] The semiconductor portion 110 is disposed between the drain electrode 101 and the source electrode 102. The insulating member 120 is disposed within the semiconductor portion 110. The insulating member 120 does not reach the surface (lower surface) of the semiconductor portion 110 on the drain electrode 101 side, but reaches the surface (upper surface) on the source electrode 102 side. The gate electrode 103 is disposed within the insulating member 120. The FP electrode 104 is disposed within the insulating member 120, between the drain electrode 101 and the gate electrode 103.

[0013] The insulating member 120, the gate electrode 103, and the FP electrode 104 extend linearly in a direction perpendicular to the plane of the paper in Fig. 1 (hereinafter also referred to as the "trench direction"). The gate electrode 103 and the FP electrode 104 are insulated from each other and from the semiconductor portion 110 by the insulating member 120. The FP electrode 104 is drawn out onto the semiconductor portion 110 at a position in the depth direction or in the front direction of the paper in Fig. 1, and is connected to the source electrode 102. In this specification, "connection" means electrical connection.

[0014] In the semiconductor portion 110, a drift layer 111 (first semiconductor layer), a source layer 112 (second semiconductor layer), and a base layer 113 (third semiconductor layer) are provided. The drift layer 111 is connected to the drain electrode 101, and its conductivity type is n-type. - The source layer 112 is connected to the source electrode 102 and has a conductivity type of n + The carrier concentration of the source layer 112 is higher than that of the drift layer 111. The base layer 113 is disposed between the drift layer 111 and the source layer 112, and is in contact with the drift layer 111, the source layer 112, and the source electrode 102. The conductivity type of the base layer 113 is p - The drift layer 111 and the source layer 112 are separated from each other via a base layer 113. When the semiconductor device 100 is a pMOS, the above-mentioned n-type and p-type are reversed.

[0015] The basic operation of the semiconductor device 100 will now be described. In the semiconductor device 100, the drain electrode 101 is a positive electrode and the source electrode 102 is a negative electrode. DSis applied to the gate electrode 103. As a result, a depletion layer spreads from the pn interface between the drift layer 111 and the base layer 113. In this state, when a potential higher than the threshold is applied to the gate electrode 103, an n-type inversion layer is formed in the portion of the base layer 113 that contacts the insulating member 120. This puts the semiconductor device 100 into the "on state", and a current flows between the drain electrode 101 and the source electrode 102. On the other hand, when a potential lower than the threshold is applied to the gate electrode 103, the inversion layer disappears. This puts the semiconductor device 100 into the "off state", and the current between the drain electrode 101 and the source electrode 102 is cut off.

[0016] In Figure 3, the horizontal axis represents time and the vertical axis represents the drain-source voltage V DS 1 is a graph showing the operation of the semiconductor device 100, taking a drain-source current Id and a drain-source current Ic. As shown in FIG. 3, when the semiconductor device 100 is switched from an on state to an off state, the drain-source voltage V DS The voltage V increases and oscillates from zero. DS The oscillation attenuates over time and eventually converges to a constant value. When designing the semiconductor device 100, it is important to control this oscillation.

[0017] Next, an equivalent circuit of the semiconductor device 100 assumed in the simulation of this embodiment will be described. FIG. 4 is a diagram in which elements of an equivalent circuit are superimposed on the semiconductor device shown in FIG. FIG. 5 is a circuit diagram showing an equivalent circuit assumed in the simulation according to this embodiment.

[0018] As shown in FIG. 4, in this embodiment, the resistance between the source electrode 102 and the FP electrode 104 is a resistance R fp (First resistor). Resistance R fp is the resistance of the FP electrode 104 itself in the direction perpendicular to the paper surface of FIG. 1 (trench direction).

[0019] The capacitance between the drain electrode 101 and the source electrode 102 is C DS1The capacitance between the drain electrode 101 and the gate electrode 103 is defined as capacitance C GD The capacitance between the source electrode 102 and the gate electrode 103 is defined as capacitance C GS1 (third capacitance). The resistance of the gate electrode 103 itself in the trench direction is resistance R G (second resistor). The capacitance between the drain electrode 101 and the FP electrode 104 is capacitance C DS2 The capacitance between the gate electrode 103 and the FP electrode 104 is defined as capacitance C GS2 (5th volume).

[0020] When the voltage between the source electrode 102 and the FP electrode 104 oscillates, i.e., when it contains an AC component, a current flows not only through the wiring connecting the FP electrode 104 to the source electrode 102, but also through a current path I1 that runs from the FP electrode 104 to the source electrode 102 via the insulating member 120, the drift layer 111, and the base layer 113. The current path I1 is a path that appears when the semiconductor device 100 is in an off state, and does not pass through an inversion layer.

[0021] When the semiconductor device 100 is in an off state, the resistance of a current path I0 (not shown) from the drain electrode 101 to the source electrode 102 is a resistance R DS(OFF) Resistance R DS(OFF) is the resistance R fp and the surrounding parasitic capacitance C DS1 and capacity C DS2 The current path I0 includes a current path I1. The current path I1 passes through a depletion layer formed between the drift layer 111 and the base layer 113. The thickness of the depletion layer is determined by the voltage V between the drain electrode 101 and the source electrode 102. DS (first voltage), so resistor R DS(OFF) is the voltage V DS Specifically, it depends on the voltage V DS As the temperature rises, the depletion layer becomes thicker and the resistance R DS(OFF) Also, the capacitance C DS1 Since the voltage V DS Specifically, it depends on the voltage V DSAs the temperature rises, the depletion layer becomes thicker and the capacitance C DS1 becomes smaller.

[0022] 5, an equivalent circuit 200 of the semiconductor device 100 includes a drain terminal, a source terminal, and a gate terminal. fp , capacity C DS1 , capacity C GD , capacity C GS1 , resistance R G , capacity C DS2 , and capacity C GS2 As mentioned above, the resistor R fp , capacity C DS1 and capacity C GS2 From the above, the resistance R DS(OFF) (not shown) are synthesized.

[0023] Capacity C DS1 (First capacitance) is connected between the drain terminal and the source terminal. Capacitance C GD (second capacitance) is connected between the drain terminal and the gate terminal. Capacitance C GS1 The third capacitance is connected between the source terminal and the gate terminal. G (Second resistor) has a capacitance of C GD and capacity C GS1 The capacitance C is connected between the connection point N1 and the gate terminal. DS2 (Fourth capacitance) is connected to the drain terminal. Capacitance C GS2 (The fifth capacitor) is connected to the connection point N1. Resistor R fp (First resistor) has a capacitance of C DS2 and capacity C GS2 The connection point N2 corresponds to the FP electrode 104 and is connected between the source terminal and a connection point N2 with the FP electrode 104.

[0024] The inductances L1, L2, and L3 are elements that configure an equivalent circuit of a package in which the semiconductor device 100 is mounted. All of the inductances L1, L2, and L3 are outside the equivalent circuit 200.

[0025] As mentioned above, the resistor R fp is the voltage V DSDepends on the voltage V DS The higher the resistance R fp will be higher. In Fig. 6, the horizontal axis indicates the drain-source voltage V DS The vertical axis represents the drain-source resistance R DS(OFF) Taking the voltage V DS and resistor R DS(OFF) 4 is a graph showing the relationship between In FIG. 6, the actual measured values ​​are indicated by black circles (●) and the approximation equation is indicated by a curve. In Fig. 6, the following formula 1 is used as an approximation formula. The following formula 1 is a quadratic formula.

[0026]

number

[0027] In the above formula 1, "a", "b", and "c" are coefficients. For example, the coefficient a is -9×10 -5 , coefficient b is 0.0128, and coefficient c is −0.0135. Substituting these coefficients into the above formula 1 gives the following formula 2.

[0028]

number

[0029] Next, the operation of the simulation device according to this embodiment, that is, the simulation method according to this embodiment, will be described. FIG. 7 is a diagram showing a simulation method according to the present embodiment.

[0030] 7, the simulation method according to the present embodiment is a method for simulating the operation of a semiconductor device 100 (see FIG. 2). A storage unit 20 of the simulation device 1 (see FIG. 1) stores a simulation program assuming an equivalent circuit 200 (see FIG. 5) of the semiconductor device 100, and a voltage V DS and resistor R fp and the voltage V DS and capacity CDS1 The relationship is stored.

[0031] In this simulation, an AC power supply 201, a DC power supply 202, and an ammeter 203 are assumed to be external to the equivalent circuit 200 and are connected in series between the source electrode 102 and the drain electrode 101. A voltmeter 204 is also assumed to be connected in parallel to the circuit consisting of the AC power supply 201 and the DC power supply 202.

[0032] In the simulation method according to this embodiment, the voltage V DS Depending on the drain-source resistance R DS(OFF) Instead of resistor R fp As mentioned above, the resistance R fp is essentially constant, but in this simulation, the voltage V DS Resistance R according to DS(OFF) In order to reflect the fluctuation of the voltage V DS Depending on the resistance R fp Also, the voltage V DS Depending on the capacity C DS1 Since the capacitance C DS1 Also changes.

[0033] Voltage V DS and resistor R fp The relationship between is, for example, the function R fp =f(V DS ) format. Voltage V DS and capacity C DS1 For example, the relationship between DS1 =g(V DS ) format. Function R fp =f(V DS ) is, for example, R in the above formula 1 DS(OFF) R fp For example, in the above formula 2, R DS(OFF) R fp This is the formula in which it is replaced by

[0034] 5, in the simulation method according to the present embodiment, the potential of the gate electrode 103 is set to the ground potential GND, thereby simulating the case where the semiconductor device 100 is in the off state.

[0035] The calculation unit 10 reads out the simulation program from the storage unit 20 and executes it. The simulation program according to the present embodiment is, for example, a program based on SPICE (Simulation Program with Integrated Circuit Emphasis), and simulates the operation of the equivalent circuit 200. In this simulation program, DS is set as the output of the DC power supply 202. In addition, this simulation program uses the function R fp =f(V DS ) to calculate the voltage V DS Based on the value of resistor R fp Calculate the value of function C DS1 =g(V DS ) to calculate the voltage V DS Based on the value of capacitance C DS1 By repeating these calculations, the operation of the semiconductor device 100 is simulated.

[0036] Next, the effects of this embodiment will be described. In this embodiment, the resistance R between the source electrode 102 and the FP electrode 104 fp is the drain-source voltage V DS This is based on the calculation of the voltage V DS The resistance R due to the change DS(OFF) The change in voltage V can be calculated as shown in Figure 3. DS The vibration can be accurately reproduced.

[0037] In this embodiment, the capacitance C DS1 Voltage V DS This is based on the calculation of the voltage V DS The capacitance C due to the change DS1 The change in voltage V can be calculated as shown in Figure 3.DS This allows the vibration to be reproduced more accurately.

[0038] <Second embodiment> In this embodiment, compared to the first embodiment, the voltage V DS and resistor R DS(OFF) The formulas expressing the relationship are different.

[0039] In Fig. 8, the horizontal axis indicates the drain-source voltage V DS The vertical axis represents the drain-source resistance R DS(OFF) Taking the voltage V DS and resistor R DS(OFF) 4 is a graph showing the relationship between In FIG. 8, the actual measured values ​​are indicated by black circles (●) and the approximation equation is indicated by a curve. 8, the following formula 3 is used as an approximation formula. The following formula 3 is a function including an activation function tanh (hyperbolic tangent function).

[0040]

number

[0041] FIG. 8 and the above formula 3 show "V dsMAX " represents the breakdown voltage of the semiconductor device 100. fp@0.5VdsMAX " is the voltage V DS is the breakdown voltage (V dsMAX ) when the voltage is half that of the resistance R fp "d", "e", "f", "g", "h", and "i" are coefficients. For example, coefficient d is +1, coefficient e is 3 / 4, coefficient f is -1, coefficient g is +1, coefficient h is +20, and coefficient i is -1. Substituting these coefficients into the above formula 3 gives the following formula 4.

[0042]

number

[0043] Other than the above, the configuration, operation, and effects of this embodiment are the same as those of the first embodiment.

[0044] <Third embodiment> In this embodiment, compared to the first and second embodiments, the voltage V DS and resistor R fp and voltage V DS and capacity C DS1 The difference is that the relationship between is realized as a data structure. FIG. 9 is a diagram showing a simulation method according to the present embodiment.

[0045] 9, in this embodiment, an equivalent circuit 200 and a data structure 300 are stored in the storage unit 20 (see FIG. 1) of the simulation device 1. In the data structure 300, a voltage V DS and resistor R fp Multiple values ​​of and capacitance C DS1 In other words, the data structure 300 stores a plurality of values ​​of the voltage V DS and resistor R fp and voltage V DS and capacity C DS1 This shows the relationship between:

[0046] The calculation unit 10 of the simulation device 1 (see FIG. 1 ) calculates a voltage V DS When the value of V is obtained, the data structure 300 is referenced to determine the voltage V DS Resistor R corresponding to the value fp Value and capacity C DS1 The value of the resistance R fp Value and capacity C DS1 Using the values ​​of , a simulation of the equivalent circuit 200 is performed. By repeating this process, the operation of the semiconductor device 100 is simulated.

[0047] According to this embodiment, it is possible to perform a simulation of the semiconductor device 100 at higher speed by using the data structure 300. Other configurations, operations, and effects of this embodiment than those described above are similar to those of the first embodiment.

[0048] <Test Example> Next, a test example showing the effect of the first embodiment will be described. FIG. 10 is a circuit diagram showing a resistive load switching circuit used in this test example. In Fig. 11(a) to (c), the horizontal axis represents time and the vertical axis represents the drain-source voltage V DS 13 is a graph showing the results of this test example, taking the drain-source current Id and the drain-source current Ic.

[0049] 10, in the resistive load switching circuit 400 used in this test example, the source electrode 102 of the semiconductor device 100 is connected to the ground potential GND. In addition, a resistor R G and a signal output circuit 401 are connected in series. Furthermore, a resistive load R L and a DC power supply 402 are connected in series.

[0050] FIG. 11(a) shows the results of the measurement. The results shown in FIG. 11(a) were measured using the resistive load switching circuit 400 shown in FIG. 10. As shown in FIG. 11(a), when the semiconductor device is turned off, the drain-source voltage V DS It vibrated. FIG. 11(b) shows the simulation result of the comparative example. In the comparative example, the resistor R fp The value of is fixed. FIG. 11C shows the simulation results of the first embodiment. As described above, in the first embodiment, the resistor R fp The value of voltage V DS was varied depending on the value of

[0051] As shown in FIGS. 11(a) to (c), the simulation results of the first embodiment were closer to the actual measurement results than the comparative example.

[0052] According to the embodiments described above, it is possible to realize a semiconductor device simulation method, a semiconductor device simulation device, a semiconductor device simulation program, and a data structure that can improve accuracy.

[0053] In the above-described embodiments, the calculation unit 10 of the simulation device 1 executes the simulation program stored in the storage unit 20, but the present invention is not limited to this. For example, the simulation program may exist on a cloud and be executed by the calculation unit 10, or the program itself may be executed on the cloud.

[0054] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0055] 1: Simulation device 10: Arithmetic section 20: Storage part 30: Input / output section 100: Semiconductor device 101: Drain electrode 102: source electrode 103: Gate electrode 104: Field plate electrode (FP electrode) 110: Semiconductor part 111: Drift layer 112: Source layer 113: Base layer 120: Insulating material 200: Equivalent circuit 201: AC power supply 202:DC power supply 203:Ammeter 204:Voltmeter 300: Data Structures 400: Resistive load switching circuit 401: Signal output circuit 402: DC power supply C DS1 , C DS2 , C GD , C GS1 , C GS2 :capacity I1: Current path I d : Drain-source current L1, L2: Inductance N1, N2: Connection points R G , R fp :resistance R L : Resistive load V DS : Drain-source voltage

Claims

1. A method for simulating a semiconductor device including a first electrode, a second electrode, a semiconductor portion disposed between the first electrode and the second electrode, an insulating member disposed in the semiconductor portion, a third electrode disposed in the insulating member, and a fourth electrode disposed in the insulating member between the first electrode and the third electrode, the semiconductor portion including a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of the first conductivity type connected to the second electrode, and a third semiconductor layer of a second conductivity type in contact with the first semiconductor layer and the second semiconductor layer, A method for simulating a semiconductor device, comprising: changing a value of a first resistor connected between the second electrode and the fourth electrode according to a value of a first voltage between the first electrode and the second electrode.

2. 2. The method of simulating a semiconductor device according to claim 1, wherein the value of said first resistance is increased as the value of said first voltage increases.

3. 3. The method of simulating a semiconductor device according to claim 1, wherein the value of the first resistance is calculated by a mathematical expression including the first voltage.

4. 4. The method of simulating a semiconductor device according to claim 3, wherein the mathematical expression is a quadratic expression.

5. The method of simulating a semiconductor device according to claim 3 , wherein the mathematical expression includes an activation function.

6. 3. A semiconductor device simulation method according to claim 1, further comprising: obtaining the value of the first resistance corresponding to the value of the first voltage by referring to a data structure including a correspondence between the value of the first voltage and the value of the first resistance.

7. The method for simulating a semiconductor device according to any one of claims 1 to 6, which assumes an equivalent circuit including a first capacitance connected between the first electrode and the second electrode, a second capacitance connected between the first electrode and the third electrode, a third capacitance connected between the second electrode and the third electrode, a second resistance connected between a first connection point between the second capacitance and the third capacitance and the third electrode, a fourth capacitance connected to the first electrode, a fifth capacitance connected to the first connection point, and the first resistance connected between a second connection point between the fourth capacitance and the fifth capacitance and the second electrode.

8. 8. The method for simulating a semiconductor device according to claim 7, wherein the first capacitance decreases as the first voltage increases.

9. a simulation device for a semiconductor device including a first electrode, a second electrode, a semiconductor portion disposed between the first electrode and the second electrode, an insulating member disposed in the semiconductor portion, a third electrode disposed in the insulating member, and a fourth electrode disposed in the insulating member between the first electrode and the third electrode, the semiconductor portion including a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of the first conductivity type connected to the second electrode, and a third semiconductor layer of a second conductivity type in contact with the first semiconductor layer and the second semiconductor layer, A simulation device for a semiconductor device, the simulation device changing a value of a first resistor connected between the second electrode and the fourth electrode depending on a value of a first voltage between the first electrode and the second electrode.

10. a semiconductor device including a first electrode, a second electrode, a semiconductor portion disposed between the first electrode and the second electrode, an insulating member disposed in the semiconductor portion, a third electrode disposed in the insulating member, and a fourth electrode disposed in the insulating member between the first electrode and the third electrode, the semiconductor portion including a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of the first conductivity type connected to the second electrode, and a third semiconductor layer of a second conductivity type in contact with the first semiconductor layer and the second semiconductor layer, A simulation program for a semiconductor device that causes a computer to obtain a value of a first resistor connected between the second electrode and the fourth electrode based on a first voltage between the first electrode and the second electrode.

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