Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing a harmonic noise in a frequency band affecting a peripheral device.SOLUTION: In an active element part CL of a semiconductor device 100, a semiconductor substrate 110 comprises a low resistance semiconductor layer, a drift layer, a base region, and a semiconductor region of a first conductivity type. The active element part CL comprises a gate electrode 124 and a first electrode layer 128. In a gate pad part GP, the semiconductor substrate 110 comprises a low resistance semiconductor layer, a drift layer, and a semiconductor region 132 of a second conductivity type. The gate pad part GP comprises a conductor layer 136 and an electrode layer 138 for a gate pad. When viewed in a plan view, the conductor layer 136 comprises a high resistance region 135 arranged in a central part of the conductor layer 136 and a low resistance region 137 formed in a peripheral region of the high resistance region 135.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices are known that include an active element portion (MOSFET portion) and a gate pad portion defined on a semiconductor substrate (see, for example, Patent Document 1).

[0003] 16 is a diagram for explaining a semiconductor device 800 described in Patent Document 1. As shown in FIG. 16, the semiconductor device described in Patent Document 1 (hereinafter, referred to as the conventional semiconductor device 800) has n + Drain layer 51 and n - The semiconductor device includes a MOSFET portion CL and a gate pad portion GP defined on a semiconductor substrate on which a drift layer 52 is stacked.

[0004] In the MOSFET section CL, the semiconductor substrate is, as shown in FIG. + Drain layer 51 and n + The n-type semiconductor layer 51 is formed on the drain layer 51. - A drift layer 52 and n - A p-type base region 53 is formed on the surface of the drift layer 52, and a n - The n + and a source region 54. In addition, the MOSFET section CL is + Source region 54 and n - A gate electrode 57 is formed at a position facing the p-base region 53 sandwiched between the drift layer 52 and the gate insulating film 56, and the gate electrode 57 is arranged in a state insulated by an interlayer insulating layer 58. + The semiconductor device further includes a source electrode 61 electrically connected to the source region 54 and the p-base region 53 .

[0005] In the gate pad portion GP, ​​the semiconductor substrate is + Drain layer 51 and n +The n-type semiconductor layer 51 is formed on the drain layer 51. - A drift layer 52 and n - and ap region 71 formed on the surface of the drift layer 52. The p region 71 is formed on the entire surface of the drift layer 52 in the gate pad portion GP. The gate pad GP is - The semiconductor device has a conductor layer 73 formed on the drift layer 52 and the p region 71 with an interlayer insulating film 72 interposed therebetween, and a gate pad electrode 62 disposed on the conductor layer 73 and electrically connected to the conductor layer 73.

[0006] Incidentally, the gate oscillation phenomenon during switching has become a problem due to the recent increase in switching speed and miniaturization of cells. However, when trying to provide a structure (such as a snubber circuit) to suppress the gate oscillation phenomenon, it is generally necessary to attach resistors and capacitors externally, which increases the number of discrete components.

[0007] Therefore, the inventor of the present invention conducted intensive research into the gate oscillation phenomenon, and as a result, invented a semiconductor device (semiconductor device 900 according to the prior application, see Figures 7 and 8) that suppresses the gate oscillation phenomenon when the switch is turned off while preventing an increase in discrete components, etc., and filed a patent application for the same, which has already been granted (see Patent Document 2).

[0008] In the gate pad portion GP of the semiconductor device 900 according to the prior application, as shown in Fig. 7(c), the semiconductor substrate 910 has a low-resistance semiconductor layer 912, a drift layer 914 formed on the low-resistance semiconductor layer 912, and a p-type semiconductor region 932 formed on the surface of the drift layer 914. As shown in Figs. 7(b) and 7(c), the p-type semiconductor region 932 has a first region 932a arranged along the outer periphery of the gate pad portion GP and electrically connected to the source electrode layer 928, and a plurality of second regions 932b arranged at positions separated from the first region 932a in a region surrounded by the first region 932a, at predetermined intervals when viewed in a predetermined cross section (for example, cross section AA in Fig. 7(a)), and having a floating potential.

[0009] According to the semiconductor device 900 of the prior application, the p-type semiconductor region 932 includes a first region 932a arranged along the outer periphery of the gate pad portion GP and electrically connected to the source electrode layer 928, and a plurality of second regions 932b arranged at positions separated from the first region 932a in a region surrounded by the first region 932a, spaced apart at a predetermined interval when viewed in a predetermined cross section, and having a floating potential, so that a narrow region sandwiched between the adjacent second regions 932b on the surface of the drift layer 914 becomes a current path, and in this current path, a depletion layer spreads from the first region 932a and the second region 932b toward the drift layer side during switching, so that a resistor having a relatively large resistance value is formed in the narrow region. As a result, according to the semiconductor device 900 of the prior application, a large capacitance and resistance can be built in between the gate and the drain, so that there is no need to externally attach capacitance and resistance between the gate and the drain, and it is possible to suppress the gate oscillation phenomenon at the time of switch-off without increasing the number of discrete components. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2005-150348 A [Patent Document 2] Patent No. 5719976 Summary of the Invention [Problem to be solved by the invention]

[0011] However, when a semiconductor device is built into an electrical device (such as a DC-DC converter), there is a problem in that harmonic noise is generated due to surge ripples that are generated when the semiconductor device is turned on, and this may have an effect such as interfering with the surrounding electronic devices (for example, when the semiconductor device is built into a DC-DC converter of an automobile, the automobile's car stereo, and in some cases, keyless entry, immobilizer, GPS, etc.). For this reason, it is conceivable that harmonic noise can be suppressed by reducing the surge ripple, but since it is practically difficult to completely eliminate the surge ripple, there is a limit to how much harmonic noise can be reduced.

[0012] Therefore, the inventor of the present invention has conducted extensive research into harmonic noise caused by surge ripples and has found that it is possible to reduce harmonic noise in a frequency band that affects peripheral devices by shifting the frequency (period) of the surge ripple to a frequency (period) that avoids a frequency band that affects peripheral devices (for example, a few MHz band limited by standards).The inventor of the present invention has conducted further research into shifting the frequency (period) of the surge ripple to reduce harmonic noise in a frequency band that affects peripheral devices and has found that it is possible to adjust the period (frequency) of the surge ripple by adjusting the resistance value of a part of the conductive layer of the gate pad.

[0013] Therefore, the present invention has been made in consideration of the above circumstances and findings, and has an object to provide a semiconductor device capable of reducing harmonic noise in a frequency band that affects peripheral devices. [Means for solving the problem]

[0014] The semiconductor device of the present invention is a semiconductor device including an active element section and a gate pad section defined in a semiconductor substrate on which a low-resistance semiconductor layer of a first conductivity type or a second conductivity type and a drift layer of the first conductivity type are laminated, and in the active element section, the semiconductor substrate includes the low-resistance semiconductor layer, the drift layer formed on the low-resistance semiconductor layer, a base region of the second conductivity type formed on a surface of the drift layer, and a first conductivity type semiconductor region of the first conductivity type formed at a position spaced apart from the drift layer on the surface of the base region, and the active element section includes a gate electrode formed at a position facing the base region sandwiched between the first conductivity type semiconductor region and the drift layer via a gate insulating film, and a gate electrode insulated from the gate electrode via an interlayer insulating layer. and a first electrode layer arranged in a state where the first conductivity type semiconductor region and the base region are separated from each other and electrically connected to the first conductivity type semiconductor region and the base region, and in the gate pad portion, the semiconductor substrate has the low resistance semiconductor layer, the drift layer formed on the low resistance semiconductor layer, and a second conductivity type semiconductor region formed on a surface of the drift layer, and the gate pad portion has a conductor layer formed on the drift layer and the second conductivity type semiconductor region via a field insulating layer, and a gate pad electrode layer arranged on the conductor layer and electrically connected to the conductor layer, and the conductor layer has a high resistance region arranged in the center of the conductor layer in a plan view, and a low resistance region formed in a peripheral region of the high resistance region. Effect of the Invention

[0015] According to the semiconductor device of the present invention, the conductor layer has a high resistance region disposed in the center of the conductor layer in a plan view, so that it is possible to adjust the frequency (period) of the surge ripple in the source-drain voltage, as shown in Fig. 9. Therefore, the frequency (period) of the surge ripple can be set to a frequency (period) that avoids the frequency band of harmonic noise that affects peripheral devices, and harmonic noise in the frequency band that affects peripheral devices can be reduced.

[0016] Furthermore, according to the semiconductor device of the present invention, the conductive layer has a high resistance region disposed in the center of the conductive layer in a plan view, so that a relatively large resistance can be formed between the source and drain, thereby reducing surge voltage and surge ripple, and also reducing gate oscillation when the switch is turned off.

[0017] In addition, according to the semiconductor device of the present invention, since the gate pad portion, which is unlikely to affect the active element portion, has a high resistance region, even if the high resistance region is formed in the semiconductor device, the operation of the active element is unlikely to slow down, and malfunctions in the operation as a switching element are unlikely to occur. Furthermore, since the gate pad portion has a conductive layer, and the conductive layer has a high resistance region, there is no need to provide an external resistor, and the ground area of ​​the electronic device can be small, resulting in a semiconductor device with a built-in harmonic noise suppression mechanism. [Brief description of the drawings]

[0018] [Figure 1] 1A is a plan view of a semiconductor device 100 according to embodiment 1. Fig. 1(a) is a plan view of the semiconductor device 100, Fig. 1(b) is a plan view showing a conductor layer of the semiconductor device 100, and Fig. 1(c) is a plan view showing a p-type semiconductor region. [Diagram 2] 2A is a cross-sectional view of the semiconductor device 100 according to embodiment 1. Fig. 2A is a cross-sectional view taken along line AA in Fig. 1A, Fig. 2B is a cross-sectional view taken along line BB in Fig. 1B, and Fig. 2C is a cross-sectional view taken along line CC in Fig. 1B. [Diagram 3] 3A is a diagram for explaining the effect of the semiconductor device 100 according to the embodiment 1. Fig. 3A is a diagram in which parasitic resistance and parasitic capacitance are added to the cross-sectional view, and Fig. 3B is an enlarged cross-sectional view of a main part showing the internal resistance of the high-resistance region 135. [Figure 4] 4A and 4B are diagrams showing an equivalent circuit of the semiconductor device 100 according to the embodiment 1. Fig. 4A is a diagram showing an equivalent circuit of the semiconductor device 100, and Fig. 4B is a diagram showing an equivalent circuit of the semiconductor device 100 in consideration of changing the range of the high-resistance region. [Diagram 5]5A and 5B are diagrams for explaining a semiconductor device 800A according to Comparative Example 1. Fig. 5A is a plan view showing a conductor layer of the semiconductor device 800A, Fig. 5B is a plan view showing a p-type semiconductor region on a surface of a semiconductor substrate 810 of the semiconductor device 800A, and Fig. 5C is a cross-sectional view taken along line AA of Fig. 5A. [Figure 6] 6A and 6B are diagrams for explaining a semiconductor device 800A according to Comparative Example 1. Fig. 6A is a diagram in which parasitic resistance and parasitic capacitance are added to a cross-sectional view of the semiconductor device 800A, and Fig. 6B is a diagram showing an equivalent circuit of the semiconductor device 800A. [Figure 7] 7A and 7B are diagrams for explaining a semiconductor device 900 according to Comparative Example 2. Fig. 7A is a plan view showing a conductor layer of the semiconductor device 900, Fig. 7B is a plan view showing a p-type semiconductor region on a surface of a semiconductor substrate 910 of the semiconductor device 900, and Fig. 7C is a cross-sectional view taken along line AA of Fig. 7A. [Figure 8] 8A and 8B are diagrams for explaining a semiconductor device 900 according to a comparative example 2. Fig. 8A is a diagram in which parasitic resistance and parasitic capacitance are added to a cross-sectional view of the semiconductor device 900, and Fig. 8B is a diagram showing an equivalent circuit of the semiconductor device 900. [Figure 9] 9A and 9B are diagrams for explaining the waveform of the drain-source voltage VDS when the semiconductor device 100 according to embodiment 1 is switched. Fig. 9A is a schematic waveform diagram of the drain-source voltage VDS when the semiconductor device is used in a bridge circuit, Fig. 9B shows a waveform diagram of the drain-source voltage VDS when the semiconductor device 900 according to comparative example 2 is switched, and Fig. 9C shows a waveform diagram of the drain-source voltage VDS when the semiconductor device 100 according to embodiment 1 is switched. [Figure 10] 10A and 10B are diagrams showing a semiconductor device 200 according to an embodiment 2. Fig. 10A is a cross-sectional view of a MOSFET portion of the semiconductor device 200, and Fig. 10B is a cross-sectional view of a gate pad portion of the semiconductor device 200. [Figure 11] FIG. 1 is a diagram showing a semiconductor device 100a according to a first modified example. [Figure 12]12(a) is a plan view shown for explaining semiconductor device 100b to 100d according to modifications 2 to 4. Fig. 12(a) is a plan view shown for explaining semiconductor device 100b, Fig. 12(b) is a plan view shown for explaining semiconductor device 100c, and Fig. 12(c) is a plan view shown for explaining semiconductor device 100d. [Figure 13] 13A and 13B are plan views for explaining a semiconductor device 100e according to Modification 5 and a semiconductor device 100f according to Modification 6. Fig. 13A is a cross-sectional view for explaining the semiconductor device 100e, and Fig. 13B is a cross-sectional view for explaining the semiconductor device 100f. [Figure 14] 14A and 14B are plan views for explaining a semiconductor device 100g according to Modification 7 and a semiconductor device 100h according to Modification 8. Fig. 14A is a cross-sectional view for explaining the semiconductor device 100g, and Fig. 14B is a cross-sectional view for explaining the semiconductor device 100h. [Figure 15] 15A and 15B are plan views shown for explaining a semiconductor device 100i according to a modification 9 and a semiconductor device 100j according to a modification 10. Fig. 15A is a cross-sectional view shown for explaining the semiconductor device 100i, and Fig. 15B is a cross-sectional view shown for explaining the semiconductor device 100j. [Figure 16] 16A and 16B are diagrams for explaining a semiconductor device 800 described in Patent Document 1. Fig. 16A is an enlarged plan view of a main portion of the semiconductor device 800, and Fig. 16B is an enlarged cross-sectional view of a main portion of the semiconductor device 800. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The semiconductor device of the present invention will be described below based on the embodiments shown in the drawings. Note that each drawing is a schematic diagram and does not necessarily strictly reflect the actual dimensions. The embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0020] [Embodiment 1] 1. Configuration of the semiconductor device 100 according to the first embodiment Fig. 1 is a plan view of a semiconductor device 100 according to embodiment 1. Fig. 2 is a cross-sectional view of the semiconductor device 100 according to embodiment 1. 1(a), the semiconductor device 100 according to the first embodiment has a generally rectangular shape in plan view, which is composed of two long sides X1, X2 and two short sides X3, X4. The semiconductor device 100 includes a MOSFET portion CL (active element portion), a gate pad portion GP, ​​and a gate finger portion GF, which are defined in a semiconductor base 110 on which a low-resistance semiconductor layer 112 and a drift layer 114 are stacked.

[0021] The MOSFET portion CL is defined in the center of the semiconductor substrate 110. As shown in Figures 2(a) and 2(c), the MOSFET portion CL includes the semiconductor substrate 110, a gate insulating film 122, a gate electrode 124, an interlayer insulating film 126, a source electrode layer 128, and a drain electrode layer 130.

[0022] In the MOSFET section CL, as shown in FIG. 2(c), the semiconductor substrate 110 includes a low-resistance semiconductor layer 112, a drift layer 114 formed on the low-resistance semiconductor layer 112, a p-type base region 116 formed on the surface of the drift layer 114, a p-type protruding region 118 protruding in the depth direction at the bottom of the base region 116, and a n-type protruding region 118 formed on the surface of the base region 116 at a position separated from the drift layer 114. + The base region 116, the overhang region 118, and the source region 120 (first conductivity type semiconductor region) extend in a stripe shape at a predetermined interval from the long side X1 side to the long side X2 side of the semiconductor substrate 110 (only the overhang region 118 is shown in FIG. 1(c)).

[0023] The thickness of the low-resistance semiconductor layer 112 is 100 μm to 400 μm, and the impurity concentration of the low-resistance semiconductor layer 112 is 1×10 19 cm -3 ~1×10 20 cm -3 The drift layer 114 has a thickness of 5 μm to 50 μm and an impurity concentration of 1×10 14 cm-3 ~1×10 16 cm -3 The depth of the base region 116 is 2 μm to 2.5 μm, and the impurity concentration of the base region 116 is 5×10 16 cm -3 ~1×10 18 cm -3 The depth of the source region 120 is 0.2 μm to 0.4 μm, and the impurity concentration of the source region 120 is 5×10 19 cm -3 ~2×10 20 cm -3 The depth of the protruding region 118, the p-type semiconductor region 132 described later, and the second p-type semiconductor region 162 described later is 2.4 μm to 8.0 μm, and the impurity concentration is 1×10 17 cm -3 ~3×10 18 cm -3 The protruding region 118, the p-type semiconductor region 132, and the second p-type semiconductor region 162 are formed collectively.

[0024] 2(c), the gate electrode 124 is formed on the surface of the semiconductor substrate 110 at a position facing the base region 116 sandwiched between the source region 120 and the drift layer 114 via the gate insulating film 122. The gate electrode 124 (and the gate insulating film 122) also extends in a striped shape at predetermined intervals from the long side X1 toward the long side X2 (see FIG. 1(b)). The interlayer insulating film 126 is formed on the gate electrode 124 to insulate the gate electrode 124 from the source electrode layer 128 . 2, the source electrode layer 128 (first electrode layer) is disposed in a state insulated from the gate electrode 124 via an interlayer insulating film 126, and is electrically connected to the source region 120 and the base region 116 via contact holes formed in the interlayer insulating film 126. As shown in FIG. 1(a), the source electrode layer 128 is formed so as to cover the entire MOSFET portion CL of the semiconductor substrate 110, and is formed in a U-shape so as to surround the gate pad portion GP from three sides in a plan view. The drain electrode layer 130 is formed over the entire surface of the semiconductor substrate 110 opposite to the surface on which the source electrode layer 128 is formed (see FIG. 2).

[0025] The gate pad portion GP is a rectangular region formed to protrude toward the center from the short side X3 side of the semiconductor substrate 110 in a plan view. The gate pad portion GP includes the semiconductor substrate 110, a field insulating film 134, a conductive layer 136, an interlayer insulating film 126, and a gate pad electrode layer 138, as shown in FIG.

[0026] In the gate pad portion GP, ​​the semiconductor body 110 has a low resistance semiconductor layer 112 , a drift layer 114 formed on the low resistance semiconductor layer 112 , and a p-type semiconductor region 132 formed on the surface of the drift layer 114 .

[0027] 1(c) and 2(a), the p-type semiconductor region 132 has a first region 132a and a second region 132b. The p-type semiconductor region 132 is formed by ion-implanting a p-type impurity (e.g., boron) and then thermally diffusing the impurity.

[0028] The first region 132a is disposed along the outer periphery of the gate pad portion GP, ​​and is connected to the base region 116 (and the protruding region 118) of the MOSFET portion CL and a second p-type semiconductor region 162 of the gate finger portion, which will be described later. Therefore, the first region 132a is electrically connected to the source electrode layer 128 via the second p-type semiconductor region 162 and the base region 116.

[0029] The second region 132b is disposed at a position separated from the first region 132a in a region surrounded by the first region 132a. The second region 132b has a shape in which a plurality of slits (four in the first embodiment) are formed from the long side X1 side toward the long side X2 side in a plan view, and has a shape in which a plurality of slits are arranged at a predetermined interval when viewed in a predetermined cross section (for example, a cross section passing through the center of the gate pad portion GP and parallel to the long side X1). The second region 132b is separated from the first region 132a and is surrounded by the drift layer 114, so that the potential of the second region 132b is a floating potential. In this specification, the region between the first region 132a and the second region 132b where the p-type impurity is not introduced is referred to as the third region 133a, and the region between adjacent second regions 132b where the p-type impurity is not introduced (the portion of the slit where the p-type impurity is not introduced and surrounded by the second region 132b in a plan view) is referred to as the fourth region 133b.

[0030] The field insulating film 134 is formed in the gate pad portion GP and the gate finger portion GF on the surface of the semiconductor substrate 110. The field insulating film 134 is thicker than the gate insulating film 122 (see FIG. 2(b)).

[0031] 1(b) and 2(a), the conductive layer 136 is formed on the entire gate pad portion GP on the drift layer 114 and the p-type semiconductor region 132 via the field insulating film 134. The conductive layer 136 is formed by introducing an n-type impurity into a polysilicon layer, and has a high resistance region 135 and a low resistance region 137 formed by adjusting the impurity concentration of the n-type impurity.

[0032] The high resistance region 135 is disposed in the center of the conductive layer 136 in a plan view. The high resistance region 135 has a lower impurity concentration of n-type impurities than the low resistance region 137. The high resistance region 135 is connected to the gate pad electrode layer 138 via the low resistance region 137. That is, the high resistance region 135 does not have a portion directly connected to the gate pad electrode layer 138. The high resistance region 135 is formed in a region overlapping with the second region 132b and a region overlapping with the fourth region 133b between the second regions 132b.

[0033] The low resistance region 137 is formed in a peripheral region of the high resistance region 135 in a plan view, and is connected to a gate pad electrode layer 138. The low resistance region 137 is connected to the gate electrode 124 of the MOSFET portion CL via an extraction wiring 139 of the gate finger portion GF (see FIG. 1(b)).

[0034] The interlayer insulating film 126 is formed on the conductive layer 136. The gate pad electrode layer 138 is disposed on the conductive layer 136 via the interlayer insulating film 126, and is electrically connected to a low resistance region 137 of the conductive layer 136 via an opening 140 formed in the interlayer insulating film 126. The gate pad electrode layer 138 is connected to a gate finger wiring 142, which will be described later.

[0035] As shown in Fig. 1(a), the gate finger portion GF is connected to the gate pad portion GP, ​​and the gate finger portion GF and the gate pad portion GP are formed to surround the periphery of the MOSFET portion CL. As shown in Fig. 2(b), the gate finger portion GF has a semiconductor substrate 110, a field insulating film 134, a lead-out wiring 139, an interlayer insulating film 126, and a gate finger wiring 142.

[0036] In the gate finger portion GF, the semiconductor body 110 has a second p-type semiconductor region 162 formed on the surface of the drift layer 114. The second p-type semiconductor region 162 is formed over the entire gate finger portion GF.

[0037] The lead-out wiring 139 is disposed on the surface of the semiconductor substrate 110 via a field insulating film 134. The lead-out wiring 139 is formed by introducing an n-type impurity into a polysilicon layer. As shown in FIG. 1(b), the lead-out wiring 139 is formed along the outer periphery of the semiconductor substrate 110 and is connected to the gate electrode 124 of the MOSFET portion CL and the conductive layer 136 of the gate pad portion GP. The gate finger wiring 142 is disposed on the lead-out wiring 139 via an interlayer insulating film 126. The gate finger wiring 142 is disposed apart from the source electrode layer 128 and is connected to the gate pad electrode layer 138.

[0038] The gate electrode 124, the conductive layer 136, and the lead-out wiring 139 are formed collectively. The gate electrode 124, the conductive layer 136, and the lead-out wiring 139 are formed by introducing an n-type impurity by ion implantation into a polysilicon layer formed by CVD. Specifically, after forming a polysilicon layer at a predetermined location, the n-type impurity is introduced into the entire polysilicon layer, and then a mask is formed in a region that is to become the high resistance region 135, and an n-type impurity (e.g., phosphorus) is further introduced into a region of the polysilicon layer other than the region that is to become the high resistance region 135. In this way, the gate electrode 124, the conductive layer 136, and the lead-out wiring 139 can be formed. The impurity concentration of the n-type impurity introduced into the entire polysilicon layer is, for example, 4×10 15 cm -3 ~8×10 15 cm -3の The impurity concentration of the n-type impurity introduced into the polysilicon layer after masking the high resistance region 135 is within the range of, for example, 3×10 15 cm -3 ~8×10 15 cm -3 The thickness of the gate electrode 124, the conductive layer 136 and the lead-out wiring 139 is, for example, 500 nm.

[0039] The source electrode layer 128, the gate pad electrode layer 138, and the gate finger wiring 142 are made of an Al film or an Al alloy film (e.g., an AlSi film), and the source electrode layer 128 has a thickness of 1 μm to 10 μm (e.g., 3 μm). The source electrode layer 128, the gate pad electrode layer 138, and the gate finger wiring 142 are formed collectively. The drain electrode layer 130 is formed of a multilayer metal film such as Ti-Ni-Au (or Ag), and the drain electrode layer 130 has a thickness of 0.2 μm to 1.5 μm (e.g., 1 μm).

[0040] 2. Parasitic Capacitance and Parasitic Resistance in the Semiconductor Device 100 of the First Embodiment Next, a description will be given of the parasitic capacitance and parasitic resistance in the semiconductor device 100 according to the embodiment 1. To this end, first, the structures, parasitic resistance, parasitic capacitance, and equivalent circuits of the semiconductor device 800A according to the comparative example 1 and the semiconductor device 900 according to the comparative example 2 will be described, and then the structure, parasitic resistance, parasitic capacitance, and equivalent circuit of the semiconductor device 100 according to the embodiment 1 will be described.

[0041] (1) Regarding the semiconductor device 800A according to Comparative Example 1 5 and 6 are diagrams shown for explaining a semiconductor device 800A according to a first comparative example. The semiconductor device 800A according to Comparative Example 1 basically has the same configuration as the conventional semiconductor device 800, but differs from the conventional semiconductor device 800 in that an interlayer insulating film 826 is provided between a conductive layer 836 and a gate pad electrode 838. In the semiconductor device 800A according to Comparative Example 1, the conductive layer 836 is entirely made up of a low resistance region as shown in Fig. 5(a), and a p-type semiconductor region 860 is formed on the surface of the semiconductor substrate 810 over the entire gate pad portion GP as shown in Fig. 5(b) and Fig. 5(c).

[0042] Next, the parasitic capacitance and parasitic resistance of the semiconductor device 800A in accordance with the first comparative example will be described. As shown in FIG. 6(a), the MOSFET section CL of the semiconductor device 800A according to the first comparative example has a parasitic capacitance C0 and a parasitic resistance R0 between the gate and the drain. In addition, a parasitic capacitance C1 and a parasitic resistance R1 are added to the gate pad section GP. The parasitic capacitance C1 is a capacitance having the conductor layer 836 as one electrode, the drift layer 814 as the other electrode, and the field insulating film 834 and the second p-type semiconductor region 860 as dielectrics, and the parasitic resistance R1 is an internal resistance of the drift layer 814. In the first comparative example, the conductor layer 836 has a low resistance, so that the internal resistance can be ignored. In addition, the second p-type semiconductor region 860 has a substantially uniform depth, so that the parasitic capacitance C1 and the parasitic resistance R1 are constant values ​​regardless of location.

[0043] Because of the above-mentioned configuration, when the semiconductor device 800A of Comparative Example 1 is represented by an equivalent circuit, as shown in FIG. 6(b), a configuration in which a capacitance C0 and a resistance R0 are connected in series between the gate and drain, and a configuration in which a capacitance C1 and a resistance R1 are connected in series are connected in parallel.

[0044] (2) Regarding the semiconductor device 900 according to the comparative example 2 7 and 8 are diagrams shown for explaining a semiconductor device 900 according to a second comparative example. The semiconductor device 900 according to Comparative Example 2 has a configuration similar to that of the semiconductor device 900 according to the prior application. In the semiconductor device 900 according to Comparative Example 2, the conductive layer 936 is entirely made of a low resistance region as shown in Fig. 7(a), and a p-type semiconductor region 932 is formed on the surface of the semiconductor substrate 910 as shown in Fig. 7(b) and Fig. 7(c). The p-type semiconductor region 932 has a first region 932a that is disposed along the outer periphery of the gate pad portion GP and electrically connected to the source electrode layer 928, and a second region 932b that is disposed in a region surrounded by the first region 932a and spaced apart from each other at a predetermined interval when viewed from a predetermined cross section, and has a floating potential.

[0045] Next, the parasitic capacitance and parasitic resistance of the semiconductor device 900 according to the second comparative example will be described. 8(a), in the MOSFET section CL of the semiconductor device 900 according to Comparative Example 2, a parasitic capacitance C0 and a parasitic resistance R0 are present between the gate and drain, similarly to the semiconductor device 800A according to Comparative Example 1. In addition, parasitic capacitances C2 and C3 and parasitic resistances R2 and R3 are added to the gate pad section GP of the semiconductor device 900 according to Comparative Example 2. The parasitic capacitance C2 is a capacitance having the conductor layer 936 as one electrode, the drift layer 914 as the other electrode, and the field insulating film 934 and the p-type semiconductor region 932 as a dielectric. The parasitic capacitance C3 is a capacitance having the conductor layer 936 as one electrode, the drift layer 914 as the other electrode, and the field insulating film 934 as a dielectric. The resistance R2 is the internal resistance of the low-resistance semiconductor layer 912 and the drift layer 914 from the lower end position of the p-type semiconductor region 932 to the drain electrode layer 930. The resistance R3 is the internal resistance of the drift layer 914 to the same depth position as the lower end position of the p-type semiconductor region 932. In Comparative Example 2, the conductor layer 936 has a low resistance, so the internal resistance can be ignored. In addition, in the region where the p-type semiconductor region 932 is formed, the capacitance C2 and the resistance R2 are connected in series, and in the region where the p-type semiconductor region 932 is not formed, the capacitance C3, the resistance R3, and the resistance R2 are connected in series.

[0046] When the semiconductor device 900 of Comparative Example 2 is represented by an equivalent circuit, as shown in FIG. 8(b), a configuration in which a capacitance C0 and a resistance R0 are connected in series between the gate and drain, a configuration in which a capacitance C2 and a resistance R2 are connected in series, and a configuration in which a capacitance C3, a resistance R3, and a resistance R2 are connected in series are connected in parallel.

[0047] Due to the above-mentioned configuration, in the semiconductor device 900 according to Comparative Example 2, a narrow region sandwiched between adjacent second regions 932b on the surface of the drift layer becomes a current path, and when the switch is turned off, a depletion layer spreads from the first region 932a and the second region 932b toward the drift layer side, and a resistor having a relatively large resistance value is formed in the narrow region described above. As a result, a large capacitance and resistance can be built in between the gate and drain, so that there is no need to externally attach capacitance and resistance between the gate and drain, and it is possible to suppress the gate oscillation phenomenon when the switch is turned off without increasing the number of discrete components.

[0048] (3) Regarding the semiconductor device 100 according to the first embodiment Fig. 3 is a diagram shown for explaining the effects of the semiconductor device 100 according to embodiment 1. Fig. 4 is a diagram showing an equivalent circuit of the semiconductor device 100 according to embodiment 1. In the MOSFET section CL, the parasitic resistance and parasitic capacitance between the gate and drain are the same as those in the semiconductor device 900 according to the comparative example 2, except for the resistance component of the high resistance region 135, as shown in FIG. 3(a). That is, in the MOSFET section CL, a parasitic capacitance C0 and a parasitic resistance R0 are present between the gate and drain. In addition, parasitic capacitances C2 and C3 and parasitic resistances R2 and R3 are added to the gate pad section GP. The parasitic capacitance C2 is a capacitance having the conductor layer 136 as one electrode, the drift layer 114 as the other electrode, and the field insulating film 134 and the p-type semiconductor region 132 as a dielectric. In addition, the parasitic capacitance C3 is a capacitance having the conductor layer 136 as one electrode, the drift layer 114 as the other electrode, and the field insulating film 134 as a dielectric. The resistance R2 is an internal resistance of the low resistance semiconductor layer 112 and the drift layer 114 from the lower end position of the p-type semiconductor region 132 to the drain electrode layer 130. Resistor R3 is an internal resistance of drift layer 114 up to the same depth as the lower end position of p-type semiconductor region 132. In the region where p-type semiconductor region 132 is formed, capacitor C2 and resistor R2 are connected in series, while in the region where p-type semiconductor region 132 is not formed, capacitor C3, resistor R3 and resistor R2 are connected in series.

[0049] In the semiconductor device 100 according to the first embodiment, a high resistance region 135 and a low resistance region 137 are provided in a conductive layer 136. The low resistance region 137 has a negligible internal resistance, as in the semiconductor devices according to the first and second comparative examples, but an internal resistance exists in the high resistance region 135. Therefore, the resistance value increases in proportion to the length from the boundary between the high resistance region 135 and the low resistance region 137. For example, the internal resistance value of the high resistance region 135 up to the second region 132b-1 closest to the boundary between the high resistance region 135 and the low resistance region 137 in FIG. 3(b) is a resistance R 4-1 The internal resistance value of the high resistance region 135 up to the fourth region 133b-1 closest to the boundary is defined as resistance R 4-2 The internal resistance value of the high resistance region 135 up to the second region 132b-2 that is second closest to the boundary is defined as resistance R 4-3The internal resistance value of the high resistance region 135 up to the fourth region 133b-2, which is the second closest to the boundary, is defined as resistance R 4-4 By repeating this process, the resistance R 4-1 <Resistance R 4-2 <Resistance R 4-3 <Resistance R 4-4 <...<Resistance R 4-n and (n: natural number) < ···. Therefore, in the region where the p-type semiconductor region 132 (second region 132b) is formed in the current path passing through the high resistance region 135 between the gate and the drain, a capacitance C2, a resistance R2, and a resistance R 4-n In the region where the p-type semiconductor region 132 (second region 132b) is not formed, a capacitance C3, a resistance R3, a resistance R2, and a resistance R 4-n (n: even number) are connected in series. In a region where the p-type semiconductor region 132 (first region 132a) is formed in a current path that does not pass through the high resistance region 135, a capacitance C2 and a resistance R2 are connected in series, and in a region where the p-type semiconductor region 132 (first region 132a) is not formed, a capacitance C3, a resistance R3, and a resistance R2 are connected in series.

[0050] With the above-described configuration, the semiconductor device 100 according to the first embodiment can be expressed as an equivalent circuit as shown in FIG. 4(a), which includes a configuration in which a capacitance C0 and a resistance R0 are connected in series between the gate and the drain, a configuration in which a capacitance C2 and a resistance R2 are connected in series, a configuration in which a capacitance C3, a resistance R3 and a resistance R2 are connected in series, and a configuration in which a capacitance C4, a resistance R5 and a resistance R6 are connected in series between the gate and the drain. 4-1 , R 4-3 ,R 4-5 A configuration in which a capacitance C2 and a resistance R2 are connected in series, and a resistance R 4-2 ,R 4-4 ,R 4-6 . . and a configuration in which capacitance C3, resistance R3, and resistance R2 are connected in series are connected in parallel. The formation range of the high resistance region 135 can be freely designed, so that the above-mentioned resistance R 4-1 ,R 4-2 ,R 4-3 ···R4-n (n is a natural number) can be freely changed, and can also be thought of as providing a virtual variable resistor R4, as shown in FIG. 4(b).

[0051] 3. About the test example The test example is a test to confirm whether the surge ripple period is changed by forming the high-resistance region 135 in the conductive layer 136. Fig. 9 is a diagram for explaining the waveform of the drain-source voltage VDS when the semiconductor device 100 according to the first embodiment is switched.

[0052] (1) Examples and Comparative Examples The example is the semiconductor device 100 according to embodiment 1. The comparative example has a configuration basically similar to that of the semiconductor device 100 according to embodiment 1, but differs in that the high resistance region 135 is not formed in the conductive layer 136 (the conductive layer 136 is entirely composed of the low resistance region 137). In other words, the comparative example has the same configuration as the semiconductor device 900 according to comparative example 2 shown in FIGS. 7 and 8.

[0053] (2) Test method Four semiconductor devices according to the embodiment and four semiconductor devices according to the comparative example were prepared, and a bridge circuit was formed for each. A voltage of 240 V was applied to the bridge circuit, and the time change in the source-drain voltage when one semiconductor device on the high side was turned on was plotted.

[0054] (3) Test results In the comparative example, as shown in FIG. 9(b), the surge ripple period generated after the surge voltage subsided was 95 nsec. In contrast, in the example, as shown in FIG. 9(c), the surge ripple period generated after the surge voltage subsided was 12 nsec. From this, it was found that the surge ripple period in the example was significantly different from that in the comparative example. From this, it was confirmed that the surge ripple period (frequency) changes by forming the high resistance region 135 in the conductive layer 136. Note that the surge voltage was 23 V in both the semiconductor device according to the example and the semiconductor device according to the comparative example, and it was found that both maintained the effect of reducing the surge voltage (for example, when a similar test was performed on the semiconductor device 800A according to the comparative example 2, the surge voltage was 44 V).

[0055] The reason why the surge ripple period changes by forming the high resistance region 135 in the conductive layer 136 has not yet been elucidated, but it is believed to be due to the following reason. That is, harmonic noise is composed of noises of various frequencies mixed together. On the other hand, the formation of the high resistance region 135 generates internal resistance, and further, the lengths from the boundary between the high resistance region 135 and the low resistance region 137 to each second region 132b of the p-type semiconductor region 132 and each fourth region 133b between adjacent second regions are different, so that the resistance values ​​are different. Therefore, it is possible to reduce some of the noises of various frequencies that constitute the harmonic noise, and as a result, it is believed that the frequency of the harmonic noise changes.

[0056] 4. Effects of the semiconductor device 100 according to the first embodiment According to the semiconductor device 100 of the first embodiment, the conductor layer 136 has a high resistance region 135 arranged in the center of the conductor layer 136 in a plan view and a low resistance region 137 formed in a peripheral region of the high resistance region 135, so that it is possible to change (adjust) the frequency (period) of the surge ripple in the source-drain voltage as shown in Fig. 9. Therefore, the frequency (period) of the surge ripple can be set to a frequency (period) that avoids the frequency band of harmonic noise that affects peripheral devices, and harmonic noise in the frequency band that affects peripheral devices can be reduced.

[0057] Furthermore, according to the semiconductor device 100 of embodiment 1, the conductor layer 136 has the high resistance region 135 disposed in the center of the conductor layer 136 in a plan view, so that a relatively large resistance can be created between the source and drain, and gate oscillation and surge ripple can be reduced.

[0058] Moreover, according to the semiconductor device 100 of the first embodiment, since the gate pad portion GP, ​​which is unlikely to affect the MOSFET portion CL, has the high resistance region 135, the operation of the active element (MOS operation) is unlikely to be slowed down even if the high resistance region 135 is formed in the semiconductor device, and the operation as a switching element is unlikely to be defective. Furthermore, since the gate pad portion GP has the conductive layer 136, and the conductive layer 136 has the high resistance region 135, there is no need to provide an external resistor, and the ground area of ​​the electronic device can be small, resulting in a semiconductor device with a built-in harmonic noise countermeasure mechanism.

[0059] Furthermore, in the semiconductor device 100 according to the first embodiment, the conductor layer 136 is formed by introducing an n-type impurity into a polysilicon layer, and the high resistance region 135 has a lower impurity concentration of the n-type impurity than the low resistance region 137. With this configuration, the high resistance region 135 and the low resistance region 137 can be easily formed simply by adjusting the impurity concentration of the n-type impurity, and further, the resistance value of the high resistance region 135 can also be easily changed.

[0060] According to the semiconductor device 100 of the first embodiment, the p-type semiconductor region 132 includes the first region 132a arranged along the outer periphery of the gate pad portion GP and electrically connected to the source electrode layer 128, and the second region 132b arranged at a position separated from the first region 132a in a region surrounded by the first region 132a, at a predetermined interval when viewed from a predetermined cross section, and having a floating potential. Therefore, a narrow region sandwiched between the adjacent second regions 132b on the surface of the drift layer becomes a current path, and when the switch is turned off, a depletion layer spreads from the first region 132a and the second region 132b to the drift layer 114 side, and a resistor having a relatively large resistance value is formed in the narrow region. As a result, according to the semiconductor device 100 of the first embodiment, a large capacitance and resistance can be built in between the gate and the drain, so that it is not necessary to externally attach capacitance and resistance between the gate and the drain, and it is possible to suppress the gate oscillation phenomenon when the switch is turned off without increasing the number of discrete components.

[0061] Since the second region 132b is in a floating state, it is generally considered that a depletion layer does not spread from the second region 132b to the drift layer 114 side during reverse bias. However, in the semiconductor device 100 according to the first embodiment, during reverse bias, the depletion layer comes into contact with the second region 132b in the process of spreading from the first region 132a electrically connected to the source electrode layer 128 to the drift layer 114 side. When this happens, the potential of the second region 132b becomes the same as that of the first region 132a, and the depletion layer spreads from the second region 132b to the drift layer 114 side.

[0062] Furthermore, when reverse bias is applied, the depletion layers extend laterally and come into contact with each other while extending toward the low-resistance semiconductor layer 112 over the entire surface of the gate pad portion GP, ​​making it possible to configure a high-voltage semiconductor device, as in the case of the conventional semiconductor device 800.

[0063] According to the semiconductor device 100 of the first embodiment, the p-type semiconductor region 132 has a first region 132a that is disposed along the outer periphery of the gate pad portion GP and electrically connected to the source electrode layer 128, and a second region 132b that is disposed at a position separated from the first region 132a in a region surrounded by the first region 132a, separated from each other at a predetermined interval when viewed from a predetermined cross section, and has a floating potential. Therefore, the pn junction area is small, the amount of carriers injected at the time of switch-off is small, the reverse recovery period trr is shortened, and the reverse recovery peak current IRP is reduced. According to the semiconductor device 100 of the first embodiment, the second region 132b of the gate pad portion GP is in a floating state, so that the area acting as a body diode is smaller and the amount of carriers injected at the time of switch-off is smaller than when the second region 132b of the gate pad portion GP is not in a floating state. As a result, the reverse recovery period trr is further shortened, and the di / dt resistance can be increased.

[0064] In addition, according to the semiconductor device 100 of the first embodiment, the high-resistance region 135 is formed in a region overlapping with the second region 132b and a region overlapping with the fourth region 133b between the second regions 132b. Therefore, various values ​​of resistance (resistance R 4-1 ,R 4-2 , . . .) can be added. As a result, it is possible to reduce noise of various periods that constitute the surge ripple, and it becomes easier to change the period of the surge ripple.

[0065] Furthermore, according to the semiconductor device 100 of embodiment 1, the high resistance region 135 does not have any portion that is connected to the gate finger wiring 142 or the lead-out wiring 139 without going through the low resistance region 137, so there is no high resistance region between the gate electrode 124 and the external terminal connected to the gate pad portion GP, ​​and the MOS operation does not become slow.

[0066] [Embodiment 2] The semiconductor device 200 according to the second embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but the configuration of the MOSFET part is different from that of the semiconductor device 100 according to the first embodiment. That is, the semiconductor device 200 according to the second embodiment is a trench gate type semiconductor device, not a planar gate type semiconductor device like the semiconductor device 100 according to the first embodiment (see FIG. 10).

[0067] In the semiconductor device 200 according to the second embodiment, the MOSFET section CL further has a plurality of trenches 217 each formed by opening the base region 216 and reaching the drift layer 214, a gate insulating film 222 is formed on the inner circumferential surface of the trench 217, a gate electrode 224 is embedded in the trench 217 via the gate insulating film 222, and a source region 220 is formed with at least a portion thereof exposed on the inner circumferential surface of the trench 217.

[0068] As described above, the semiconductor device 200 according to the second embodiment has a different configuration of the MOSFET portion from that of the semiconductor device 100 according to the first embodiment, but like the semiconductor device 100 according to the first embodiment, the conductive layer 236 has a high resistance region 235 arranged in the center of the conductive layer 236 in a plan view and a low resistance region 237 formed in the peripheral region of the high resistance region 235, so that the frequency (period) of the surge ripple in the source-drain voltage can be adjusted as shown in Fig. 9. Therefore, the frequency (period) of the surge ripple can be set to a frequency (period) that avoids the frequency band of harmonic noise that affects peripheral devices, and harmonic noise in the frequency band that affects peripheral devices can be reduced.

[0069] The semiconductor device 200 of embodiment 2 has a configuration similar to that of the semiconductor device 100 of embodiment 1 except for the configuration of the MOSFET section, and therefore has the corresponding effects among the effects of the semiconductor device 100 of embodiment 1.

[0070] Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment. The present invention can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0071] (1) The numbers, shapes, positions, sizes, etc. of the components described in the above embodiments are merely examples and may be changed without impairing the effects of the present invention. In addition, in the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but they may be reversed.

[0072] (2) In each of the above embodiments, the p-type semiconductor region is divided into the first region and the second region, but the present invention is not limited to this. The p-type semiconductor region may constitute a single p-type semiconductor region (semiconductor device 100a according to Modification 1. See FIG. 11). Even in this case, the period of the surge ripple can be adjusted to reduce noise in peripheral devices.

[0073] (3) In each of the above embodiments, the high resistance region 135 is configured as one, but the present invention is not limited to this. The high resistance region may be configured as two or more (see FIG. 12). In this case, the shape of the high resistance region 135 may be two rectangular shapes (see the semiconductor device 100b according to the second modification, FIG. 12(a)), a rectangular shape and a ring shape may be combined (see the semiconductor device 100c according to the third modification, FIG. 12(b)), or a plurality of linear high resistance regions 135 may be arranged in a stripe shape (see the semiconductor device 100d according to the fourth modification, FIG. 12(c)).

[0074] (4) In each of the above embodiments, the high resistance region 135 is formed in a region overlapping the second region 132b and the fourth region 133b, but the present invention is not limited to this. The high resistance region may be formed in a region overlapping the fourth region 133b (not overlapping the outermost second region 132b in the semiconductor device 100e according to the fifth modification, FIG. 13(a)), or may be formed in a region overlapping the second region 132b, the third region 133a, and the fourth region 133b (see the semiconductor device 100f according to the sixth modification, FIG. 13(b)).

[0075] (5) In each of the above embodiments, the p-type semiconductor region is formed in an island shape, and a plurality of linear slits extending from the long side X1 to the long side X2 are arranged in a stripe shape, but the present invention is not limited to this. The high resistance region may be formed in an island shape, and a plurality of linear slits extending from the short side X3 to the short side X4 may be arranged in a stripe shape (semiconductor device 100g according to modified example 7, see FIG. 14(a)), the p-type semiconductor region may be arranged in a lattice shape (semiconductor device 100h according to modified example 8, see FIG. 14(b)), the second region may be arranged in a stripe shape (semiconductor device 100i according to modified example 9, see FIG. 15(a)), or the p-type semiconductor region may be arranged in a plurality of islands (semiconductor device 100j according to modified example 10, see FIG. 15(b)).

[0076] (6) In each of the above embodiments, the low-resistance semiconductor layer is an n-type (n + In the above embodiment, the low resistance semiconductor layer is a p-type (p + The semiconductor layer may be of the same type. [Explanation of symbols]

[0077] 100, 100a to 100j, 200... semiconductor device, 110, 210... semiconductor substrate, 112, 212... low-resistance semiconductor layer, 114, 214... drift layer, 116, 216... base region, 118... protruding region, 120, 220... source region, 122, 222... gate insulating film, 124, 224... gate electrode, 126, 226... interlayer insulating film, 128, 228... source electrode layer, 130, 230... drain electrode layer, 132, 232... p-type semiconductor region, 132a... First region, 132b... second region, 133a... third region, 133b... fourth region, 134, 234... field insulating film, 135, 235... high resistance region, 136, 236... conductive layer, 137, 237... low resistance region, 138, 238... electrode layer for gate pad, 139... lead wiring, 140, 240... opening, 142... wiring for gate finger, 160, 162... second p-type semiconductor region, CL... MOSFET portion, GF... gate finger portion, GP... gate pad portion

Claims

1. A semiconductor device including an active element section and a gate pad section defined in a semiconductor substrate in which a low-resistance semiconductor layer of a first conductivity type or a second conductivity type and a drift layer of the first conductivity type are stacked, In the active element section, the semiconductor substrate includes the low-resistance semiconductor layer, the drift layer formed on the low-resistance semiconductor layer, a base region of a second conductivity type formed on a surface of the drift layer, and a first-conductivity-type semiconductor region of a first conductivity type formed on the surface of the base region at a position separated from the drift layer, The active element section includes: a gate electrode formed at a position facing the base region sandwiched between the first conductive type semiconductor region and the drift layer via a gate insulating film; a first electrode layer that is disposed in a state insulated from the gate electrode via an interlayer insulating layer and is electrically connected to the first conductive type semiconductor region and the base region; In the gate pad portion, the semiconductor substrate has the low resistance semiconductor layer, the drift layer formed on the low resistance semiconductor layer, and a second conductive type semiconductor region formed on a surface of the drift layer, The gate pad portion is a conductive layer formed on the drift layer and the second conductive type semiconductor region via a field insulating layer; a gate pad electrode layer disposed on the conductive layer and electrically connected to the conductive layer; A semiconductor device characterized in that the conductive layer has a high resistance region disposed in a central portion of the conductive layer when viewed in a plan view, and a low resistance region formed in a peripheral region of the high resistance region.

2. the conductive layer is formed by doping a first conductive type impurity into a polysilicon layer; 2. The semiconductor device according to claim 1, wherein the high resistance region has a lower impurity concentration of the first conductivity type impurity than the low resistance region.

3. The second conductive type semiconductor region is a first region disposed along an outer periphery of the gate pad portion and electrically connected to the first electrode layer; 3. The semiconductor device according to claim 1, further comprising: a second region, the second region being arranged at a position separated from the first region in a region surrounded by the first region and spaced apart from each other at a predetermined interval when viewed in a predetermined cross section, and the second region having a floating potential.

4. 4. The semiconductor device according to claim 3, wherein the high resistance region is formed at least in a region overlapping with the third region between the second regions.

5. 4. The semiconductor device according to claim 3, wherein the high resistance region is formed at least in a region overlapping the second region and a region overlapping a third region between the second regions.

6. 4. The semiconductor device according to claim 3, wherein the high resistance region is formed at least in a region overlapping with the second region, a region overlapping with a third region between the second regions, and a region overlapping with a fourth region between the first region and the second region.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that the high resistance region does not have a portion that is connected to a gate finger that connects the gate pad electrode layer and the gate electrode without going through the low resistance region.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that in the active element portion, the gate electrode is formed via the gate insulating film on the base region sandwiched between the first conductive type semiconductor region and the drift layer.

9. the active element section further includes a plurality of trenches each formed to open the base region and reach the drift layer, the gate insulating film is formed on an inner circumferential surface of the trench, the gate electrode is embedded in the trench via the gate insulating film, 8. The semiconductor device according to claim 1, wherein the first conductive type semiconductor region is formed with at least a portion thereof exposed on an inner periphery of the trench.

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