Semiconductor device and method for manufacturing the same

Abstract

To fill a gap between columnar semiconductors while suppressing void and surface roughness under a low-temperature condition that thermal damage to an active layer is reduced.SOLUTION: An embedded layer forming step includes three steps of a facet structure forming step, a c-plane forming step and a flattening step. In the facet structure forming step, an embedded layer 140 is grown so as to form a cyclic facet structure matched with an array pattern of columnar semiconductors 130. In the c-plane forming step, the embedded layer 140 is grown so as to form a {0001} plane (top face 140a) in a region corresponding to upper parts of the columnar semiconductors 130 in the embedded layer 140. In the flattening step, a surface of the embedded layer 140 is flattened by promoting the lateral growth of the embedded layer 140 and widening the c-plane formed in the c-plane forming step.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The technical field of the present specification relates to semiconductor devices and methods for their manufacture. [Background technology]

[0002] A semiconductor light-emitting element emits light by the recombination of holes and electrons in the active layer. Conventionally, a flat sheet-like structure has been used as the active layer. In recent years, active layers with three-dimensional structures such as columnar structures have been researched.

[0003] For example, as shown in Patent Documents 1-3, semiconductor light-emitting devices are known that have a core-shell structure (multi-quantum shell; MQS) in which the semiconductor layer is a hexagonal nanowire (NW) and the active layer is formed to cover the hexagonal column. In MQS, the main surface of the active layer can be an m-plane. When the active layer is an m-plane, no polarization occurs and there is no quantum confined Stark effect, so an improvement in internal quantum efficiency can be expected. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-77817 A [Patent Document 2] JP 2019-12744 A [Patent Document 3] JP 2019-169735 A Summary of the Invention [Problem to be solved by the invention]

[0005] In semiconductor devices with nanowire structures, it is necessary to fill the gaps between the nanowires with semiconductor to achieve a flat surface. Although it is possible to fill the gaps evenly by growing the semiconductor at high temperatures, this creates the problem of thermal damage to the active layer. On the other hand, if the growth temperature is lowered to avoid thermal damage, this can result in the formation of voids (spaces) in the filling layer or large pits on the surface, resulting in a very rough surface.

[0006] Therefore, the problem that the technology of this specification aims to solve is to provide a manufacturing method for a semiconductor element having a plurality of periodically arranged columnar semiconductors and a buried layer filling the spaces between the columnar semiconductors, which can suppress thermal damage to the columnar semiconductors and suppress voids and surface roughness in the buried layer. [Means for solving the problem]

[0007] The method for manufacturing a semiconductor device according to the present disclosure is a method for manufacturing a semiconductor device having a plurality of periodically arranged columnar semiconductors and a buried layer that fills the spaces between the columnar semiconductors. The buried layer forming step includes a facet structure forming step of growing a buried layer having a periodic facet structure that matches the arrangement pattern of the columnar semiconductors, and a planarizing step of growing the buried layer at a higher temperature than in the facet structure forming step to grow the buried layer laterally and planarize the buried layer. During the transition from the facet structure formation process to the flattening process, the temperature is increased stepwise.

[0008] In the method for manufacturing a semiconductor element of the present disclosure, the growth temperature of the buried layer in the facet structure forming step may be 900 to 950°C, and the growth temperature of the buried layer in the planarizing step may be 1000 to 1100°C.

[0009] The manufacturing method for a semiconductor element according to the present disclosure may further include, after the facet structure forming step and before the planarizing step, a c-plane forming step of growing a buried layer at a higher temperature than in the facet structure forming step and at a lower temperature than in the planarizing step, thereby forming a {0001} plane in a region of the buried layer corresponding to the upper part of the columnar semiconductor.

[0010] In the method for manufacturing a semiconductor element according to the present disclosure, the growth temperature of the buried layer in the c-plane formation step may be 950 to 1050°C.

[0011] In the method for manufacturing a semiconductor device of the present disclosure, the facet structure may have a ratio of the area of ​​the {0001} plane of the buried layer to the total area of ​​the buried layer surface when the buried layer surface is projected onto the {0001} plane of 30% or less.

[0012] In the method for manufacturing a semiconductor device of the present disclosure, in the step of forming the buried layer, the growth pressure of the buried layer may be 10 kPa to 100 kPa, V / III may be 1000 to 5000, and the growth rate may be 5 to 50 nm / min.

[0013] In the manufacturing method of a semiconductor element according to the present disclosure, the columnar semiconductors are arranged in a square lattice or a regular triangular lattice, and H and L may be set so as to satisfy 1.06×H-0.25≦L≦1.06×H+2, where H is the height of the columnar semiconductor and L is the distance between the columnar semiconductors 130.

[0014] The semiconductor element of the present disclosure includes a plurality of periodically arranged columnar semiconductors and a buried layer filling the spaces between the columnar semiconductors. Threading dislocations are distributed on the surface of the buried layer with the same periodicity as the arrangement of the columnar semiconductors, and the dislocation density in the upper region of the columnar semiconductors is different from the dislocation density in other regions. Effect of the Invention

[0015] This specification provides a method for manufacturing a semiconductor element that can suppress voids and surface roughness in a buried layer while suppressing thermal damage to a pillar-shaped semiconductor. [Brief description of the drawings]

[0016] [Figure 1] 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a semiconductor light emitting device 100 according to a first embodiment. [Diagram 3] FIG. 2 is a schematic diagram of a pillar-shaped semiconductor 130. [Figure 4] FIG. 4 is a cross-sectional view showing a cross section taken along line IV-IV in FIG. [Diagram 5] FIG. 2 is a diagram showing an arrangement of pillar-shaped semiconductors 130. [Figure 6] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 7] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 8] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 9] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 10] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 11] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 12] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 13] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 14] SEM image of buried layer 140. [Figure 15] SEM image of buried layer 140. [Figure 16] CL image of the surface of the buried layer 140. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Specific embodiments will be described below with reference to the drawings, taking a semiconductor light-emitting device as an example. However, the technology of this specification is not limited to these embodiments. In addition, the stacked structure and electrode structure of each layer of the semiconductor light-emitting device described below are examples. There are cases where a stacked structure different from the embodiment may be used. Furthermore, the thickness ratio of each layer in each figure is shown conceptually, and does not show the actual thickness ratio.

[0018] (First embodiment) 1. Semiconductor light emitting element Fig. 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 of the first embodiment. Fig. 2 is a view showing a cross section of the semiconductor light emitting device 100. As shown in Figs. 1 and 2, the semiconductor light emitting device 100 has a substrate 110, a mask 120, a columnar semiconductor 130, an embedded layer 140, a cathode electrode N1, and an anode electrode P1. Fig. 3 is a view showing the configuration of the columnar semiconductor 130.

[0019] The substrate 110 is a growth substrate, and serves to support the mask 120, the columnar semiconductor 130, and the embedded layer 140. The substrate 110 has a conductive substrate 111 and an n-type semiconductor layer 112. The conductive substrate 111 is, for example, an n-type GaN substrate having a c-plane as the main surface, or Si or SiC. The n-type semiconductor layer 112 is, for example, an n-type GaN layer. These are merely examples, and structures other than those described above may also be used.

[0020] The mask 120 is made of a material that inhibits the growth of semiconductor on the surface. As will be described later, the mask 120 has through holes. The mask 120 is preferably a transparent insulating film. In this case, the mask 120 hardly absorbs light. The current flows suitably to the pillar-shaped semiconductor 130 without passing through the mask 120. The mask 120 is made of, for example, SiO 2 , SiN x , Al 2 O 3 Examples include:

[0021] As shown in FIGS. 1 and 2, the columnar semiconductor 130 is a columnar Group III nitride semiconductor. The columnar semiconductor 130 is formed on the substrate 110. More specifically, the columnar semiconductor 130 is a semiconductor selectively grown from the surface of the substrate 110 exposed in the opening 120a of the mask 120. The columnar semiconductor 130 has a hexagonal columnar shape. The cross section perpendicular to the central axis direction of the columnar semiconductor 130 is a regular hexagon or a flattened hexagon. The columnar semiconductors 130 are arranged in a square lattice. Other than the square lattice, the periodic arrangement may be a parallelepiped lattice, a rectangular lattice, a diagonal lattice, a regular triangular lattice, a honeycomb lattice, or the like.

[0022] The columnar semiconductors 130 are preferably arranged along the crystal orientation of the n-type semiconductor layer 112. For example, when the columnar semiconductors 130 are arranged in a triangular lattice on the {0001} plane of a group III nitride semiconductor having a wurtzite structure, it is preferable that the triangular lattice overlaps with any crystal orientation of the group III nitride semiconductor or is rotated by 30°. On the other hand, when the columnar semiconductors 130 are arranged in a square lattice, the arrangement has two-fold symmetry, which is different from the symmetry of the {0001} plane of the group III nitride semiconductor. In that case, it is preferable to align one side of the square lattice with any crystal orientation of the group III nitride semiconductor. By aligning the arrangement of the columnar semiconductors 130 with the crystal orientation of the n-type semiconductor layer 112 in this way, the growth mode of the buried layer 140 tends to be stable, and the buried layer tends to be easily buried. Of course, the arrangement of the columnar semiconductors 130 may be misaligned with the crystal orientation of the n-type semiconductor layer, or may be completely different.

[0023] The embedding layer 140 is a layer for embedding the gap between the pillar-shaped semiconductors 130. The embedding layer 140 covers the pillar-shaped semiconductors 130. The surface of the embedding layer 140 is flat. The material of the embedding layer 140 is, for example, Si-doped n-GaN. The embedding layer 140 is provided to improve the light extraction efficiency.

[0024] The cathode electrode N1 is formed on the rear surface of the substrate 110 (the surface opposite to the surface on which the mask 120 is provided).

[0025] The anode electrode P1 is formed on the buried layer 140.

[0026] 2. Columnar semiconductor 3, the pillar-shaped semiconductor 130 includes a pillar-shaped n-type semiconductor 131, an active layer 132, a cylindrical p-type semiconductor 133, and a tunnel junction layer 134. The side surface of the pillar-shaped n-type semiconductor 131 is an m-plane or a plane close to the m-plane. The m-plane is a non-polar plane. Therefore, in the active layer 132, there is almost no decrease in luminous efficiency due to piezoelectric polarization.

[0027] 2-1. Structure of pillar-shaped semiconductor The pillar-shaped n-type semiconductor 131 is a semiconductor layer selectively grown in a pillar shape starting from the substrate 110 exposed in the opening 120a of the mask 120. The pillar-shaped n-type semiconductor 131 has a hexagonal pillar shape. A cross section perpendicular to the axial direction of this hexagonal pillar is a regular hexagon or a flattened hexagon. The pillar-shaped n-type semiconductor 131 actually grows slightly in the lateral direction as well. Therefore, the thickness of the pillar-shaped n-type semiconductor 131 is slightly larger than the opening width of the opening 120a of the mask 120. The pillar-shaped n-type semiconductor 131 is, for example, an n-type GaN layer.

[0028] The height of the pillar-shaped n-type semiconductor 131 is, for example, 0.25 μm or more and 5 μm or less. The diameter of the pillar-shaped n-type semiconductor 131 is, for example, 50 nm or more and 500 nm or less. Here, the diameter refers to the diameter of a circumscribing circle of the hexagon of the pillar-shaped n-type semiconductor 131. The interval between the pillar-shaped n-type semiconductors 131 (the distance between the centers of adjacent pillar-shaped semiconductors 130) is, for example, 0.27 μm or more and 5 μm or less. These numerical values ​​are merely examples, and other numerical values ​​may be used.

[0029] The active layer 132 is formed along the outer periphery of the columnar n-type semiconductor 131 having a hexagonal columnar shape. Therefore, the active layer 132 has a hexagonal cylindrical shape. The active layer 132 has, for example, one to five well layers and barrier layers sandwiching the well layers. The well layers of the active layer 132 are approximately perpendicular to the plate surface of the substrate 110. However, the top of the active layer 132 may cover the top of the columnar n-type semiconductor 131. The top of the active layer 132 may be approximately parallel to the plate surface of the substrate 110. For example, the well layers are InGaN layers, and the barrier layers are AlGaInN layers.

[0030] The cylindrical p-type semiconductor 133 is formed along the outer periphery of the active layer 132 having a hexagonal cylindrical shape. Therefore, the cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is in direct contact with the active layer 132, but may not be in direct contact with the columnar n-type semiconductor 131. The cylindrical p-type semiconductor 133 is, for example, a p-type GaN layer. An electron barrier layer may be provided between the active layer 132 and the cylindrical p-type semiconductor 133. The electron barrier layer is a p-type semiconductor having a larger band gap than the cylindrical p-type semiconductor 133. For example, it is p-AlGaInN. By providing the electron barrier layer, electrons can be efficiently injected into the active layer 132, and the light emission efficiency can be improved.

[0031] The tunnel junction layer 134 is formed along the outer periphery of the cylindrical p-type semiconductor 133. Therefore, the tunnel junction layer 134 has a hexagonal cylindrical shape. The tunnel junction layer 134 has a p+ layer 135 and an n+ layer 136. The p+ layer 135 is located between the cylindrical p-type semiconductor 133 and the n+ layer 136. The p+ layer 135 is a layer having a high p-type impurity concentration, and is, for example, p-GaN. The Mg concentration of the p+ layer 135 is, for example, 2×10 20 cm -3 The n+ layer 136 is a layer having a high n-type impurity concentration, and is, for example, n-GaN. The Si concentration of the n+ layer 136 is, for example, 4×10 20 cm -3 The tunnel junction layer 134 is provided and the buried layer 140 is made of n-GaN, thereby making it possible to obtain electrical conduction.

[0032] It is also possible to omit the tunnel junction layer 134 and use p-GaN for the buried layer 140. However, if n-GaN is used as in the first embodiment, the electrical conductivity can be improved compared to the case of using p-GaN.

[0033] 2-2.Cross-sectional shape Fig. 4 is a first cross-sectional view showing a cross section taken along line IV-IV in Fig. 3. Fig. 4 shows a cross section of the pillar-shaped semiconductor 130 parallel to the plate surface of the substrate 110. As shown in Fig. 4, the shape of the cross section perpendicular to the axial direction of the pillar-shaped semiconductor 130 is a regular hexagon. From the inside of the hexagonal pillar-shaped pillar-shaped semiconductor 130, a pillar-shaped n-type semiconductor 131, an active layer 132, a cylindrical p-type semiconductor 133, and a tunnel junction layer 134 are arranged. Note that the shape of the cross section perpendicular to the axial direction of the pillar-shaped semiconductor 130 does not need to be a regular hexagon, and may be a flat hexagon. 3. Dislocation density in the buried layer The dislocation density on the surface of the buried layer 140 is not uniform but has a distribution. On the surface of the buried layer, threading dislocations are distributed with the same periodicity as the arrangement of the pillar-shaped semiconductors 130, and the dislocation density in the region above the pillar-shaped semiconductors 130 (hereinafter referred to as region A) is different from the dislocation density in other regions (hereinafter referred to as region B) (see FIG. 5). The dislocation density in region A is about 2 to 2000 times higher than the dislocation density in region B. The dislocation density in region A is, for example, 1×10 9 ~2×10 10 cm -2 The dislocation density in region B is, for example, 1×10 7 ~5×10 8 cm -2 It is.

[0034] The reason why the dislocation density on the surface of the buried layer 140 has such a distribution is as follows. The active layer 132 formed on the top of the pillar-shaped semiconductor 130 (the region corresponding to the c-plane GaN) tends to have a low crystal quality. Therefore, threading dislocations are formed at a higher density than the top of the pillar-shaped semiconductor 130. On the other hand, the threading dislocations in region B are formed when the buried layer 140 grown from the adjacent pillar-shaped semiconductor 130 is combined, or are caused by threading dislocations generated in the active layer 132 formed on the m-plane of the pillar-shaped semiconductor 130. In the process in which the buried layer 140 grows laterally and becomes flat, the dislocations generated in the active layer 132 on the m-plane also propagate laterally, and there is a high possibility that the dislocations annihilate each other. Alternatively, there may be originally few dislocations generated by lattice mismatch or dislocations propagating laterally. Therefore, the threading dislocation density in region B is lower than that in region A.

[0035] 4. Manufacturing method of semiconductor light emitting element 4-1. Board preparation process 6, a growth substrate 111 is prepared. Then, an n-type semiconductor layer 112 is laminated by MOCVD on the growth substrate 111. In the following, the MOCVD method is used for forming all the semiconductor layers.

[0036] 4-2. Mask formation process As shown in Fig. 7, a mask 120 is formed on the n-type semiconductor layer 112. Note that Fig. 7 shows openings 120a that will be formed in an opening formation step, which will be described later.

[0037] 4-3. Opening formation process As shown in FIG. 7, a plurality of openings 120a that expose the n-type semiconductor layer 112 are formed in the mask 120. The mask 120 is patterned by, for example, nanoimprinting. The diameter of the openings 120a is, for example, 100 to 500 nm. FIG. 8 is a diagram showing the arrangement of the openings 120a in the mask 120. FIG. 8 is a diagram showing the substrate 110 as viewed from a direction perpendicular to the surface of the substrate 110. For reference, the shape of the columnar semiconductor 130 is drawn by a dashed line in FIG. 8. As shown in FIG. 8, the openings 120a in the mask 120 are circular and arranged in a square lattice pattern.

[0038] The shape of the pillar-shaped semiconductor 130 can be controlled by changing the shape of the opening 120a of the mask 120. When the shape of the opening 120a is circular, the pillar-shaped semiconductor 130 having a cross-sectional shape close to a regular hexagon can be formed. When the shape of the opening 120a is oval, the pillar-shaped semiconductor 130 having a cross-sectional shape close to a flat shape can be formed.

[0039] 4-4. Columnar semiconductor formation process 9, a hexagonal columnar n-type semiconductor 131 is selectively grown starting from the n-type semiconductor layer 112 exposed under the opening 120a of the mask 120. For this purpose, a known selective growth technique may be used. When the semiconductor layer is selectively grown in this manner, the m-plane is likely to be exposed as a facet.

[0040] As described above, since the openings 120a of the mask 120 are circular, the columnar n-type semiconductor 131 grows in the shape of a hexagonal column whose cross section is close to a regular hexagon.

[0041] Next, the active layer 132 is formed around the pillar-shaped n-type semiconductor 131. The active layer 132 is formed on the side surface of the pillar-shaped n-type semiconductor 131, whose cross section is shaped like a regular hexagon. The active layer 132 is also formed on the top of the pillar-shaped n-type semiconductor 131.

[0042] Next, a cylindrical p-type semiconductor 133 is formed on the active layer 132 to cover the outer periphery of the active layer 132. The cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is formed on the side surface of the active layer 132. The cylindrical p-type semiconductor 133 is also formed on the top of the active layer 132.

[0043] Next, a p+ layer 135 is formed on the cylindrical p-type semiconductor 133 to cover the cylindrical p-type semiconductor 133, and an n+ layer 136 is further formed to cover the p+ layer 135. This forms a tunnel junction layer 134. The tunnel junction layer 134 is formed on the side surface of the cylindrical p-type semiconductor 133. The tunnel junction layer 134 is also formed on the top of the cylindrical p-type semiconductor 133. In this manner, the columnar semiconductor 130 is formed.

[0044] 4-5. Buried layer formation process Next, the gaps between the pillar-shaped semiconductors 130 are filled with the buried layer 140. The buried layer forming process includes three steps: a facet structure forming process, a c-plane forming process, and a planarizing process.

[0045] First, as shown in FIG. 10, in the facet structure forming step, the buried layer 140 is grown so that a periodic facet structure that matches the arrangement pattern of the columnar semiconductors 130 is formed. In other words, the buried layer 140 is grown so that the surface of the buried layer 140 is dominated by the inclined plane 140a, and planes parallel to or perpendicular to the substrate 110 are minimized. The shape of the buried layer 140 at this stage is, for example, a pyramidal shape that is continuously connected in the same pattern as the arrangement of the columnar semiconductors 130, and the columnar semiconductors 130 are contained within the pyramids. The inclined plane 140a is a {10-1x} plane (where x is a natural number equal to or greater than 1) that is an inclined plane of the {10-10} plane (m-plane), and is mainly a {10-11} plane.

[0046] Such a facet structure can be formed by controlling the growth conditions. For example, a facet structure that conforms to a periodic structure can be formed by controlling the growth temperature to 900 to 950°C, the growth pressure to 10 k to 100 kPa, the V / III ratio to 1000 to 5000, and the growth rate to 5 to 50 nm / min.

[0047] The facet structure is a structure in which, for example, when the surface of the buried layer 140 is projected onto the {0001} plane, the ratio of the area of ​​the {0001} plane of the buried layer 140 to the total area of ​​the surface of the buried layer 140 is 30% or less. The {0001} plane is the (0001) plane (+c plane) or the (000-1) plane (-c plane).

[0048] In the facet structure forming process, if the height H of the columnar semiconductors 130 is large or the distance L between the columnar semiconductors 130 (the distance between the center of one columnar semiconductor 130 and the center of the other adjacent columnar semiconductor 130) is short, the source gas may not reach the lower part sufficiently as the embedded layer 140 grows, and voids 160 may occur in that region in the embedded layer 140. In particular, immediately after the formation of the facet structures, when the inclined surface 140a of one facet structure intersects with the inclined surface of the other adjacent facet structure above the mask 120, voids 160 are likely to occur at the intersection (see FIG. 11). Therefore, it is preferable to set the height H and the distance L to satisfy the following formula. 1.06×H-0.25≦L≦1.06×H+2 If the height H and the distance L are set to satisfy this formula, as shown in FIG. 10, immediately after the formation of the facet structures, the inclined surface of one facet structure and the inclined surface of the adjacent facet structure do not intersect above the mask 120 or intersect near the surface, so that the generation of voids 160 can be suppressed. This formula was derived by calculating the case where the above condition is satisfied based on the angle of about 62° between the {10-11} plane, which is the inclined plane that is mainly formed, and the (0001) plane (c-plane). The lower limit in the formula takes into consideration a range in which the voids 160 are small enough to be tolerated even if they are formed. The upper limit takes into consideration the ease of filling between the columnar semiconductors 130. In other words, if the distance between the columnar semiconductors 130 is large, the volume to be filled increases, making flattening difficult, so the distance between the columnar semiconductors 130 that makes flattening easy is taken into consideration. More preferably, the following formula is satisfied: 1.06×H-0.15≦L≦1.06×H+1.5 More preferably, the following formula is satisfied: 1.06×H≦L≦1.06×H+1

[0049] When the adjacent facet structures start to contact each other, the process proceeds to the next c-plane forming process. In the c-plane forming process, as shown in FIG. 12, the embedded layer 140 is grown so that the {0001} plane (upper surface 140b) is formed in the region of the embedded layer 140 that corresponds to the upper part of the columnar semiconductor 130. The shape of the embedded layer 140 at this stage is, for example, a shape in the form of a truncated pyramid shape that is continuously connected in the same pattern as the arrangement of the columnar semiconductor 130, and the columnar semiconductor 130 is contained within the truncated pyramid. Since the embedded layer 140 grows while maintaining the periodic structure having the inclined surface 140a formed in the facet structure forming process, it is possible to fill the spaces between the columnar semiconductors 130 without generating voids in the embedded layer 140 and without gaps. If the filling proceeds randomly in the plane without maintaining the periodic structure, voids will be generated and the surface will have severe unevenness. If the growth mode is not uniform in the plane, such a periodic structure cannot be maintained.

[0050] The formation of such a {0001} plane is possible by controlling the growth conditions. For example, the c-plane can be formed by setting the growth temperature at 950 to 1050°C, the growth pressure at 10k to 100kPa, the V / III at 1000 to 5000, and the growth rate at 5 to 50nm / min. Only the growth temperature may be changed to move from the facet structure formation process to the c-plane formation process. In addition, when moving from the facet structure formation process to the c-plane formation process, it is preferable to increase the growth temperature stepwise rather than continuously. By changing the growth mode stepwise, the growth proceeds while maintaining the periodic structure, and voids can be suppressed more, filling becomes easier, and flatness is improved.

[0051] The transition from the facet structure formation process to the c-plane formation process may be performed, for example, when the ratio of the area of ​​the {0001} plane of buried layer 140 to the total area of ​​the surface of buried layer 140 when the surface of buried layer 140 is projected onto the {0001} plane becomes greater than 30%.

[0052] When the area of ​​the {0001} plane becomes sufficiently large, the process proceeds to the next planarization step. In the planarization step, as shown in FIG. 13, the lateral growth of the buried layer 140 is promoted, and the c-plane formed in the c-plane formation step is widened, thereby planarizing the surface of the buried layer 140. The buried layer 140 is grown so that the facet structures are simultaneously combined while maintaining the periodic structure, and fill the spaces between the columnar semiconductors 130. Since the buried layer 140 grows while maintaining the periodic structure having the inclined planes, it is possible to fill the spaces between the columnar semiconductors 130 without generating voids in the buried layer 140. In addition, since the facet structures are simultaneously combined, the surface of the buried layer 140 can be uniformly planarized.

[0053] The transition from the c-plane formation process to the planarization process may be made, for example, when the ratio of the area of ​​the {0001} plane of buried layer 140 to the total area of ​​the surface of buried layer 140 when the surface of buried layer 140 is projected onto the {0001} plane becomes 70% or more.

[0054] The lattice mismatch may occur due to the merging of adjacent facet structures. In addition, dislocations also propagate laterally as the buried layer 140 grows laterally and is flattened, and there is a high probability that the dislocations will annihilate each other. Alternatively, there may be originally few dislocations caused by lattice mismatch or dislocations propagating laterally. Therefore, the dislocation density on the surface of the buried layer 140 is lower in the other region B than in the region A at the top of the pillar-shaped semiconductor 130.

[0055] Since the embedded layer 140 grows laterally toward the face center (the center of the square lattice) of the square lattice arrangement of the pillar-shaped semiconductors 130, the threading dislocations also propagate toward the face center, and the threading dislocations that do not annihilate and remain gather at the face center. Therefore, the threading dislocations on the surface of the embedded layer 140 tend to be distributed at the face center of the square lattice. The same is true for the triangular lattice arrangement, and threading dislocations tend to be distributed at the face center of the triangular lattice.

[0056] The thickness (thickest part) of the buried layer 140 required to flatten the buried layer 140 depends on the height H of the pillar-shaped semiconductor 130, but is, for example, 1 to 5 μm. The buried layer 140 is formed in the manner described above.

[0057] Such flattening of the buried layer 140 is possible by controlling the growth conditions. For example, the c-plane can be formed by setting the growth temperature to 1000-1100°C, the growth pressure to 10k-100kPa, the V / III to 1000-5000, and the growth rate to 5-50nm / min. Only the growth temperature may be changed to move from the c-plane formation process to the flattening process. When moving from the c-plane formation process to the flattening process, it is preferable to increase the growth temperature stepwise rather than continuously. By changing the growth mode stepwise, the growth proceeds while maintaining the periodic structure, which makes it possible to suppress voids more effectively, makes filling easier, and improves flatness.

[0058] It is also possible to omit the c-plane formation step and move directly from the facet structure formation step to the planarization step.

[0059] Voids 160 may be formed in the buried layer 140, but the height of the voids 160 formed between the columnar semiconductors 130 is preferably 30% or less, more preferably 20% or less, of the height of the columnar semiconductors 130 from the surface of the mask 120. In the case of a laser diode, even if the above-mentioned voids 160 are formed, there is little adverse effect on the formation of standing waves. In an LED, it is also possible to control the light extraction efficiency by uniformly controlling the formation of the voids 160.

[0060] Thus, in the first embodiment, even at a temperature of 1100° C. or less, which is lower than the conventional temperature, it is possible to fill the spaces between the columnar semiconductors 130 without generating voids, and to form the buried layer 140 with a flat surface. Furthermore, in the conventional method, the buried layer 140 is formed at a temperature higher than 1100° C. in order to flatten the surface without generating voids, and the active layer 132 is thermally damaged. However, in the first embodiment, the growth temperature is increased stepwise at a low temperature of 1100° C. or less, so that the thermal damage to the active layer 132 can be suppressed on average more than in the conventional method.

[0061] 4-6. Electrode formation process Next, a cathode electrode N1 is formed on the back surface of the substrate 110. Also, an anode electrode P1 is formed on the embedded layer 140. In this manner, the semiconductor light emitting device 100 of the first embodiment shown in FIGS.

[0062] 4-7.Other processes A heat treatment step, a step of forming a passivation film or the like on the surface of the semiconductor layer, or other steps may be performed.

[0063] 5. Effects of the First Embodiment In the first embodiment, the spaces between the pillar-shaped semiconductors 130 can be filled flatly with the filling layer 140 without leaving any gaps, and thermal damage to the active layer 132 can also be suppressed.

[0064] 6. Variations 6-1. Structure of semiconductor light emitting device In this embodiment, a vertical structure is used in which the cathode electrode N1 is provided on the back surface of the substrate 110 and conducts electricity perpendicular to the main surface of the substrate 110, but a flip-chip type or face-up type element structure in which the cathode electrode N1 is provided on the same side as the anode electrode P1 may also be used. In that case, the n-type semiconductor layer 112 is exposed by etching from the upper surface side of the embedded layer 140, and the cathode electrode N1 is formed on the exposed n-type semiconductor layer 112.

[0065] 6-2. Composition of columnar semiconductor In this embodiment, the columnar n-type semiconductor 131 is an n-type GaN layer, the well layer is an InGaN layer, the barrier layer is an AlGaInN layer, and the cylindrical p-type semiconductor 133 is a p-type GaN layer. These are merely examples, and other Group III nitride semiconductors may be used. Also, other semiconductors may be used.

[0066] 6-3.Surface layer A plurality of protrusions may be provided on the surface of the embedding layer 140 for light extraction. A surface layer may be provided on the embedding layer 140, and a plurality of protrusions may be provided on the surface layer. The surface layer may be, for example, an n-GaN layer having a different doping amount from that of the embedding layer 140. The material of the surface layer may be a transparent conductive oxide such as ITO or IZO. The arrangement of the protrusions may be, for example, a honeycomb or square lattice pattern. Recesses may be provided instead of the protrusions.

[0067] 6-4. Composition of buried layer In this embodiment, the material of the burying layer 140 is an n-GaN layer. However, an n-AlGaN layer can be used as the burying layer 140 instead of the n-GaN layer. n-GaN and n-AlGaN may be combined. In the case of a laser diode, forming n-AlGaN on n-GaN makes it possible to enhance light confinement due to the refractive index difference.

[0068] 6-5. Buried layer dopants In this embodiment, Si is used as the n-type dopant of the buried layer 140, but it is not limited to Si. However, this embodiment is more effective when the buried layer 140 is Si-doped n-type. Si acts as a surfactant to promote vertical growth, and if the vertical growth is strong, voids are likely to occur in the buried layer 140 and the surface is likely to become rough. Therefore, as in this embodiment, if the growth mode is controlled in three stages, namely, the facet structure formation process, the c-face formation process, and the flattening process, it is possible to stably obtain the buried layer 140 with suppressed voids and less surface roughness even in the case of Si doping. In addition, when Mg is used as a dopant, lateral growth is promoted, so that a flatter buried layer 140 is more likely to be obtained.

[0069] 6-6. Current blocking layer of pillar-shaped semiconductor It is preferable to promote current injection from the side surface of the pillar-shaped semiconductor 130. For example, a transparent insulating film is provided on the top of the pillar-shaped semiconductor 130. This blocks current flowing to the top of the pillar-shaped semiconductor 130, and allows current injection from the side surface of the pillar-shaped semiconductor 130 to be performed satisfactorily.

[0070] 6-7.Irregularized substrate When used as an LED, the growth substrate 111 of the substrate 110 may be textured. In other words, the growth substrate 111 has a textured portion with periodic projections and recesses on the surface on the semiconductor layer side. Examples of the textured shape include a cone shape and a hemisphere shape. These convex shapes may be arranged, for example, in a square lattice or honeycomb shape. This further improves the light extraction efficiency.

[0071] 6-8. Application to other semiconductor elements Although the first embodiment is a semiconductor light emitting device, the present invention can be applied to devices other than light emitting devices as long as it has a structure including a plurality of periodically arranged columnar semiconductors and a buried layer that fills the spaces between the columnar semiconductors. For example, the present invention can be applied to light receiving devices such as solar cells.

[0072] Combinations The above modifications may be freely combined.

[0073] 7. Experimental Results Various experimental results regarding the semiconductor light emitting device 100 of the first embodiment will be described.

[0074] Figure 14 shows SEM images of the shape of the buried layer 140 taken during the process of forming the buried layer 140. Figure 14(a) is a planar SEM image taken at the stage of the facet structure formation process, and Figure 14(b) is a cross-sectional SEM image. Figure 14(c) is a planar SEM image taken at the stage of the c-plane formation process, and Figure 14(d) is a cross-sectional SEM image. Figure 14(e) is a planar SEM image taken after the planarization process, and Figure 14(f) is a cross-sectional SEM image.

[0075] As shown in Figures 14(a) and (b), in the facet structure formation step, the facet structures are formed periodically in the same arrangement pattern as the square lattice arrangement of the pillar-shaped semiconductor 130. Also, as shown in Figures 14(c) and (d), in the c-plane formation step, the c-plane region in the upper part of the pillar-shaped semiconductor 130 is expanded. Also, as shown in Figures 14(e) and (f), although there are a small number of regions that are not planarized, it is understood that most of the region is planarized, and it is understood that the generation of voids in the buried layer 140 is suppressed.

[0076] Fig. 15 shows SEM images of the shape of the buried layer 140 when the arrangement pattern of the columnar semiconductors 130 is changed from a square lattice to a regular triangular lattice. Fig. 15(a) is a planar SEM image taken at the stage of the facet structure formation process, and Fig. 15(b) is a cross-sectional SEM image. Fig. 15(c) is a planar SEM image taken at the stage of the c-plane formation process, and Fig. 15(d) is a cross-sectional SEM image. Fig. 15(e) is a planar SEM image taken after the planarization process, and Fig. 15(f) is a cross-sectional SEM image.

[0077] As shown in Figures 15(a) and (b), in the facet structure formation step, it can be seen that the facet structures are formed periodically in the same arrangement pattern as the regular triangular lattice arrangement of the pillar-shaped semiconductor 130. Also, as shown in Figures 15(c) and (d), it can be seen that in the c-plane formation step, the c-plane region in the upper part of the pillar-shaped semiconductor 130 is expanded. Also, as shown in Figures 15(e) and (f), it can be seen that although there are a small number of regions that have not been flattened, the majority of the surface has been flattened, and it can be seen that the generation of voids in the buried layer 140 has been suppressed.

[0078] Fig. 16 is a CL image taken of the surface of the buried layer 140 after the formation of the buried layer 140. In Fig. 16, the region indicated by a circle is the upper region of the opening 120a of the mask 120, and is the upper region of the columnar semiconductor 130. The dark spots in Fig. 16 are threading dislocations.

[0079] As shown in FIG. 16, it can be seen that the region of the buried layer 140 where the pillar-shaped semiconductor 130 is located has a higher dislocation density than the other regions. [Industrial Applicability]

[0080] The semiconductor device of this specification can be used as a light emitting element such as a laser diode or an LED, or a light receiving element such as a solar cell. [Explanation of symbols]

[0081] 100...Semiconductor light emitting device 110...Substrate 111...Conductive substrate 112...n-type semiconductor layer 120…Mask 120a…Opening 130...Columnar semiconductor 131...Columnar n-type semiconductor 132...Active layer 133...Cylindrical p-type semiconductor 134...Tunnel junction layer 140…Buried layer N1: Cathode electrode P1…Anode electrode

Claims

1. A method for manufacturing a semiconductor device having a plurality of periodically arranged pillar-shaped semiconductors and a buried layer made of a semiconductor that fills spaces between the pillar-shaped semiconductors, comprising: The step of forming the buried layer includes: a facet structure forming step of growing the buried layer having a periodic facet structure that coincides with the arrangement pattern of the pillar-shaped semiconductors; a planarization step of growing the buried layer at a temperature higher than that of the facet structure formation step to cause the buried layer to grow laterally and planarize the buried layer, When transitioning from the facet structure forming step to the flattening step, the temperature is increased stepwise. A method for manufacturing a semiconductor device comprising the steps of:

2. The growth temperature of the buried layer in the facet structure forming step is 900 to 950° C., The growth temperature of the buried layer in the planarization step is 1000 to 1100° C.; 2. The method for manufacturing a semiconductor device according to claim 1.

3. The method further includes, after the facet structure forming step and before the planarizing step, a c-plane forming step of growing the buried layer at a temperature higher than that of the facet structure forming step and lower than that of the planarizing step to form a {0001} plane in a region of the buried layer corresponding to an upper portion of the pillar-shaped semiconductor.

3. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the growth temperature of the buried layer in the c-plane formation step is 950 to 1050.degree.

5. the facet structure has a ratio of an area of ​​the {0001} plane of the buried layer to a total area of ​​the buried layer surface when the buried layer surface is projected onto a {0001} plane of 30% or less; 5. The method for manufacturing a semiconductor device according to claim 1, wherein the first and second electrodes are formed on the substrate.

6. 6. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the buried layer, a growth pressure of the buried layer is 10 kPa to 100 kPa, a V / III is 1000 to 5000, and a growth rate is 5 to 50 nm / min.

7. 7. The method for manufacturing a semiconductor element according to claim 1, wherein the pillar-shaped semiconductors are arranged in a square lattice pattern or a regular triangular lattice pattern, and H and L are set so as to satisfy 1.06×H-0.25≦L≦1.06×H+2, where H is a height of the pillar-shaped semiconductors and L is a distance between the pillar-shaped semiconductors.

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