Semiconductor device and method for manufacturing the same

Abstract

To suppress a current leak between a semiconductor layer on a reverse side of a mask and a buried layer on a top side of the mask, and improve the efficiency of injection of a carrier into an active layer and reduce a drive voltage to improve light emission efficiency.SOLUTION: A semiconductor light emitting element 100 has a substrate 110, a mask 120, a columnar semiconductor 130, a buried layer 140, a cathode electrode N1, and an anode electrode P1. The substrate 110 has a conductive substrate 111, an n-type semiconductor layer 112 located on the conductive substrate 111, and a p-type semiconductor layer 113 located on the n-type semiconductor layer 112. The p-type semiconductor layer 113 has high resistance, and thereby can improve insulation between the n-type semiconductor layer 112 and buried layer 140.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The technical field of the present specification relates to semiconductor devices and methods of manufacturing semiconductor devices. [Background technology]

[0002] A semiconductor light-emitting element emits light by the recombination of holes and electrons in the active layer. Conventionally, a flat sheet-like structure has been used as the active layer. In recent years, active layers with three-dimensional structures such as columnar structures have been researched.

[0003] For example, as shown in Patent Document 1, a semiconductor light-emitting device is known that has a core-shell structure (multi-quantum shell; MQS) in which the semiconductor layer is a hexagonal nanowire (NW) and the active layer is formed to cover the hexagonal column. In MQS, the main surface of the active layer can be an m-plane. When the active layer is an m-plane, no polarization occurs and there is no quantum confined Stark effect, so an improvement in internal quantum efficiency can be expected.

[0004] Nanowires are formed by forming an n-layer on a substrate, forming a dielectric mask with openings (nanoholes) with diameters on the nanometer order, and selectively growing a semiconductor from the n-layer exposed to the openings.

[0005] Patent Document 1 also describes a structure in which the gaps between nanowires are filled with a buried layer made of a semiconductor. It also describes a structure in which a tunnel junction layer is provided on the side of the nanowire and the buried layer is made of n-type. Since n-type semiconductors have low resistance, the driving voltage can be reduced more than when the buried layer is made of p-type. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2020-77817 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, the inventors have found through their investigations that a structure in which a buried layer is located above a mask, as in Patent Document 1, has the following problems.

[0008] It is difficult to make the mask thick in manufacturing. Since the mask is thin, if there is a slight crack in the mask or damage to the crystal, the insulation of that part will be weak and become a current leak point. In the case of Patent Document 1, current may leak between the n-layer under the mask and the buried layer above the mask. The higher the current density, the greater the risk of mask destruction, which is a particular problem.

[0009] Therefore, the problem to be solved by the technique of this specification is to suppress current leakage between a semiconductor layer under a mask and a buried layer above the mask. [Means for solving the problem]

[0010] The first aspect includes a first semiconductor layer made of a semiconductor, and a second semiconductor layer provided on the first semiconductor layer and having a thickness larger than the first semiconductor layer. 100 times more A second semiconductor layer made of a semiconductor having a high resistivity and a 、 From the dielectric The thickness is 2 nm to 50 nm. a mask; and a plurality of holes provided on the mask, the holes having a depth reaching a first semiconductor layer. The diameter of the hole is 100 nm or more and 500 nm or less. an opening, a plurality of pillar-shaped semiconductors provided on the first semiconductor layer in the opening, and a buried layer made of a semiconductor and burying the spaces between the pillar-shaped semiconductors; of It is a semiconductor element having such a structure.

[0011] In the first embodiment, the second semiconductor layer may be a semiconductor having a conductivity type different from that of the first semiconductor layer, or may be a non-doped semiconductor.

[0012] In the first embodiment, the buried layer may be a semiconductor of the same conductivity type as the first semiconductor layer.

[0013] In the first embodiment, the mask may have a thickness of 2 to 50 nm.

[0014] The second aspect is a semiconductor element having a first semiconductor layer made of an n-type semiconductor, a tunnel junction layer provided on the first semiconductor layer, a second semiconductor layer provided on the tunnel junction layer and made of a p-type semiconductor, a mask made of a dielectric provided on the second semiconductor layer, a plurality of openings provided on the mask, which are holes having a depth reaching the second semiconductor layer, and a plurality of columnar semiconductors made of a p-type semiconductor provided on the second semiconductor layer in the openings.

[0015] In the second embodiment, a mesa may be further provided, and the tunnel junction layer and the second semiconductor layer may be exposed on a side surface of the mesa, or the columnar semiconductor may be exposed on a side surface of the mesa.

[0016] A third aspect is a method for manufacturing a semiconductor device, comprising: a first step of stacking a first semiconductor layer made of an n-type semiconductor, a tunnel junction layer, and a second semiconductor layer made of a p-type semiconductor in that order on a growth substrate; a second step of performing activation annealing on the tunnel junction layer and the second semiconductor layer after the first step; a third step of forming a mask made of a dielectric and having a plurality of openings on the second semiconductor layer after the second step; a fourth step of selectively growing columnar semiconductors made of a p-type semiconductor in the openings after the third step; a fifth step of forming a mesa so that the tunnel junction layer and the second semiconductor layer are exposed on the side surfaces after the fourth step; and a sixth step of performing activation annealing on the tunnel junction layer, the second semiconductor layer, and the columnar semiconductor after the fifth step. Effect of the Invention

[0017] The present specification provides a semiconductor device capable of suppressing current leakage between a semiconductor layer under a mask and a buried layer above the mask. [Brief description of the drawings]

[0018] [Figure 1] 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 according to a first embodiment. [Diagram 2]1 is a cross-sectional view of a semiconductor light emitting device 100 according to a first embodiment. [Diagram 3] FIG. 2 is a schematic diagram of a pillar-shaped semiconductor 130. [Figure 4] FIG. 4 is a cross-sectional view showing a cross section taken along line IV-IV in FIG. [Diagram 5] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 6] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 7] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 8] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 9] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 10] 2A to 2C are diagrams for explaining a manufacturing method of the semiconductor light emitting device according to the first embodiment. [Figure 11] FIG. 4 is a cross-sectional view of a semiconductor light emitting device according to a second embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a VV cross section of FIG. [Figure 13] 5A to 5C are diagrams for explaining a manufacturing method of a semiconductor light emitting device according to the second embodiment. [Figure 14] 5A to 5C are diagrams for explaining a manufacturing method of a semiconductor light emitting device according to the second embodiment. [Figure 15] 5A to 5C are diagrams for explaining a manufacturing method of a semiconductor light emitting device according to the second embodiment. [Figure 16] 5A to 5C are diagrams for explaining a manufacturing method of a semiconductor light emitting device according to the second embodiment. [Figure 17] A diagram showing the lines on the side of the mesa. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Specific embodiments will be described below with reference to the drawings, taking a semiconductor light-emitting device as an example. However, the technology of this specification is not limited to these embodiments. In addition, the stacked structure and electrode structure of each layer of the semiconductor light-emitting device described below are examples. There are cases where a stacked structure different from the embodiment may be used. Furthermore, the thickness ratio of each layer in each figure is shown conceptually, and does not show the actual thickness ratio.

[0020] (First embodiment) 1. Semiconductor light emitting element Fig. 1 is a perspective view showing a schematic configuration of a semiconductor light emitting device 100 of the first embodiment. Fig. 2 is a view showing a cross section of the semiconductor light emitting device 100. As shown in Figs. 1 and 2, the semiconductor light emitting device 100 has a substrate 110, a mask 120, a columnar semiconductor 130, a buried layer 140, a cathode electrode N1, and an anode electrode P1.

[0021] The substrate 110 is a growth substrate for growing the pillar-shaped semiconductor 130, and also serves to support the mask 120, the pillar-shaped semiconductor 130, and the embedded layer 140. The substrate 110 has a conductive substrate 111, an n-type semiconductor layer (first semiconductor layer) 112 located on the conductive substrate 111, and a p-type semiconductor layer (second semiconductor layer) 113 located on the n-type semiconductor layer 112.

[0022] The conductive substrate 111 is, for example, an n-type GaN substrate having a c-plane as its principal surface, or Si or SiC.

[0023] The n-type semiconductor layer 112 is, for example, a Si-doped n-type GaN layer. The thickness of the n-type semiconductor layer 112 is, for example, 1 to 5 μm.

[0024] The p-type semiconductor layer 113 is provided to improve the insulation between the n-type semiconductor layer 112 and the buried layer 140, which is insufficient when only the mask 120 is used. The p-type semiconductor layer 113 is, for example, a Mg-doped p-type GaN layer. Since the p-type semiconductor layer 113 has high resistance, it can improve the insulation between the n-type semiconductor layer 112 and the buried layer 140. In the p-type semiconductor layer 113, a through hole is formed in the region of the opening 120a described below, and the n-type semiconductor layer 112 is exposed at the bottom surface of the through hole.

[0025] The thickness of the p-type semiconductor layer 113 is, for example, 2 to 100 nm. In this range, the insulating properties can be sufficiently improved. The Mg concentration of the p-type semiconductor layer 113 is, for example, 1×10 18 ~1×10 21 cm -3 Within this range, the resistance of the p-type semiconductor layer 113 can be made sufficiently high.

[0026] Since it is preferable that the p-type semiconductor layer 113 has a high resistance, it is not necessary to fully activate Mg. For example, it is preferable that the activation rate of Mg is 0.5% or less.

[0027] Instead of the p-type semiconductor layer 113, a non-doped semiconductor layer, for example, a non-doped GaN layer, may be used. Also, instead of GaN, a material having a larger band gap than the n-type semiconductor layer 112, such as AlGaN, may be used. In short, a semiconductor layer having a higher resistance than the n-type semiconductor layer 112 may be provided on the n-type semiconductor layer 112. For example, a layer having a resistivity 100 times or more higher than that of the n-type semiconductor layer 112 may be provided.

[0028] The mask 120 is a material that inhibits the growth of a semiconductor on the surface, and is a dielectric. As described below, the mask 120 has a through hole (opening 120a). The p-type semiconductor layer 113 in this opening 120a is removed, and the n-type semiconductor layer 112 is exposed in the opening 120a. The mask 120 is preferably a transparent insulating film. In this case, the mask 120 hardly absorbs light. Examples of the material of the mask 120 include SiO 2 , SiN x, Al 2 O 3 Examples include:

[0029] The thickness of the mask 120 is, for example, 2 to 50 nm. Since it is necessary to provide the openings 120a of a fine pattern in the mask 120 with high precision and at low cost, the openings 120a are formed by using nanoimprinting as described below. As a result, the mask 120 needs to be very thin. Since the mask 120 is very thin, if the mask 120 has a small crack or pinhole or if the crystal is damaged, there is a high possibility that a weak part in insulation will be generated. Then, the weak part becomes a leakage point of current, and conduction occurs between the n-type semiconductor layer 112 and the buried layer 140. Therefore, by providing the above-mentioned p-type semiconductor layer 113, insulation that cannot be sufficiently ensured by the mask 120 alone is ensured.

[0030] As shown in FIGS. 1 and 2, the columnar semiconductor 130 is a columnar Group III nitride semiconductor. The columnar semiconductor 130 is formed on the substrate 110. More specifically, the columnar semiconductor 130 is a semiconductor selectively grown from the surface of the substrate 110 (the surface of the n-type semiconductor layer 112) exposed in the opening 120a of the mask 120. The columnar semiconductor 130 has a hexagonal columnar shape. The cross section perpendicular to the central axis direction of the columnar semiconductor 130 is a regular hexagon or a flattened hexagon. The columnar semiconductors 130 are arranged in a square lattice. Other than the square lattice, the periodic arrangement may be a parallelepiped lattice, a rectangular lattice, a diagonal lattice, a regular triangular lattice, a honeycomb lattice, or the like.

[0031] The columnar semiconductors 130 are preferably arranged along the crystal orientation of the n-type semiconductor layer 112. For example, when the columnar semiconductors 130 are arranged in a triangular lattice on the {0001} plane of a group III nitride semiconductor having a wurtzite structure, it is preferable that the triangular lattice overlaps with any crystal orientation of the group III nitride semiconductor or is rotated by 30°. On the other hand, when the columnar semiconductors 130 are arranged in a square lattice, the arrangement has two-fold symmetry, which is different from the symmetry of the {0001} plane of the group III nitride semiconductor. In that case, it is preferable to align one side of the square lattice with any crystal orientation of the group III nitride semiconductor. By aligning the arrangement of the columnar semiconductors 130 with the crystal orientation of the n-type semiconductor layer 112 in this way, the growth mode of the buried layer 140 tends to be stable, and the buried layer tends to be easily buried. Of course, the arrangement of the columnar semiconductors 130 may be misaligned with the crystal orientation of the n-type semiconductor layer, or may be completely different.

[0032] The embedding layer 140 is a layer for embedding the gap between the pillar-shaped semiconductors 130. The embedding layer 140 covers the pillar-shaped semiconductors 130. The surface of the embedding layer 140 is flat. The material of the embedding layer 140 is, for example, Si-doped n-GaN. The embedding layer 140 is provided to improve the light extraction efficiency.

[0033] The cathode electrode N1 is formed on the rear surface of the substrate 110 (the surface opposite to the surface on which the mask 120 is provided).

[0034] The anode electrode P1 is formed on the buried layer 140.

[0035] 2. Columnar semiconductor 3 is a diagram showing the configuration of the pillar-shaped semiconductor 130. As shown in FIG. 3, the pillar-shaped semiconductor 130 has a pillar-shaped n-type semiconductor 131, an active layer 132, a cylindrical p-type semiconductor 133, and a tunnel junction layer 134. The side surface of the pillar-shaped n-type semiconductor 131 is an m-plane, or a plane close to the m-plane. The m-plane is a non-polar plane. Therefore, in the active layer 132, there is almost no decrease in luminous efficiency due to piezoelectric polarization.

[0036] 2-1. Structure of pillar-shaped semiconductor The pillar-shaped n-type semiconductor 131 is a semiconductor layer selectively grown in a pillar shape starting from the surface of the n-type semiconductor layer 112 exposed in the opening 120a of the mask 120. The pillar-shaped n-type semiconductor 131 has a hexagonal pillar shape. A cross section perpendicular to the axial direction of this hexagonal pillar is a regular hexagon or a flattened hexagon. The pillar-shaped n-type semiconductor 131 actually grows slightly in the lateral direction as well. Therefore, the thickness of the pillar-shaped n-type semiconductor 131 is slightly larger than the opening width of the opening 120a of the mask 120. The pillar-shaped n-type semiconductor 131 is, for example, an n-type GaN layer.

[0037] The height of the pillar-shaped n-type semiconductor 131 is, for example, 0.25 μm or more and 5 μm or less. The diameter of the pillar-shaped n-type semiconductor 131 is, for example, 50 nm or more and 500 nm or less. Here, the diameter refers to the diameter of a circumscribing circle of the hexagon of the pillar-shaped n-type semiconductor 131. The interval between the pillar-shaped n-type semiconductors 131 (the distance between the centers of adjacent pillar-shaped semiconductors 130) is, for example, 0.27 μm or more and 5 μm or less. These numerical values ​​are merely examples, and other numerical values ​​may be used.

[0038] The active layer 132 is formed along the outer periphery of the columnar n-type semiconductor 131 having a hexagonal columnar shape. Therefore, the active layer 132 has a hexagonal cylindrical shape. The active layer 132 has, for example, one to five well layers and barrier layers sandwiching the well layers. The well layers of the active layer 132 are approximately perpendicular to the plate surface of the substrate 110. However, the top of the active layer 132 may cover the top of the columnar n-type semiconductor 131. The top of the active layer 132 may be approximately parallel to the plate surface of the substrate 110. For example, the well layers are InGaN layers, and the barrier layers are AlGaInN layers.

[0039] The cylindrical p-type semiconductor 133 is formed along the outer periphery of the active layer 132 having a hexagonal cylindrical shape. Therefore, the cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is in direct contact with the active layer 132, but may not be in direct contact with the columnar n-type semiconductor 131. The cylindrical p-type semiconductor 133 is, for example, a p-type GaN layer. An electron barrier layer may be provided between the active layer 132 and the cylindrical p-type semiconductor 133. The electron barrier layer is a p-type semiconductor having a larger band gap than the cylindrical p-type semiconductor 133. For example, it is p-AlGaInN. By providing the electron barrier layer, electrons can be efficiently injected into the active layer 132, and the light emission efficiency can be improved.

[0040] The tunnel junction layer 134 is formed along the outer periphery of the cylindrical p-type semiconductor 133. Therefore, the tunnel junction layer 134 has a hexagonal cylindrical shape. The tunnel junction layer 134 has a p+ layer 135 and an n+ layer 136. The p+ layer 135 is located between the cylindrical p-type semiconductor 133 and the n+ layer 136. The p+ layer 135 is a layer having a high p-type impurity concentration, and is, for example, p-GaN. The Mg concentration of the p+ layer 135 is, for example, 2×10 20 cm -3 The n+ layer 136 is a layer having a high n-type impurity concentration, for example, n-GaN. 136 The Si concentration is, for example, 4×10 20 cm -3 The tunnel junction layer 134 is provided and the buried layer 140 is made of n-GaN, thereby making it possible to obtain electrical conduction.

[0041] The tunnel junction layer 134 may be omitted and the buried layer 140 may be made of p-GaN. However, if the buried layer 140 is made of n-GaN as in the first embodiment, the electrical conductivity can be improved compared to the case of p-GaN. Furthermore, the effect of providing the p-type semiconductor layer 113 as in the first embodiment is greater when the buried layer 140 is of the same n-type as the n-type semiconductor layer 112. This is because when both the n-type semiconductor layer 112 and the buried layer 140 are of n-type, the barrier to electrical conduction is smaller than when the buried layer 140 is of p-type, and therefore insulation between the n-type semiconductor layer 112 and the buried layer 140 is more necessary.

[0042] 2-2.Cross-sectional shape Fig. 4 is a cross-sectional view showing a cross section taken along line IV-IV in Fig. 3. Fig. 4 shows a cross section of the pillar-shaped semiconductor 130 parallel to the plate surface of the substrate 110. As shown in Fig. 4, the shape of the cross section perpendicular to the axial direction of the pillar-shaped semiconductor 130 is a regular hexagon. From the inside of the hexagonal pillar-shaped pillar-shaped semiconductor 130, a pillar-shaped n-type semiconductor 131, an active layer 132, a cylindrical p-type semiconductor 133, and a tunnel junction layer 134 are arranged. Note that the shape of the cross section perpendicular to the axial direction of the pillar-shaped semiconductor 130 does not need to be a regular hexagon, and may be a flat hexagon.

[0043] 3. Manufacturing method of semiconductor light emitting element 3-1. Board preparation process 5, a growth substrate 111 is prepared. Then, an n-type semiconductor layer 112 and a p-type semiconductor layer 113 are laminated in this order on the growth substrate 111 by MOCVD. The following semiconductor layers are all formed by MOCVD.

[0044] 3-2. Mask formation process As shown in Fig. 6, a mask 120 is formed on the n-type semiconductor layer 112. Note that Fig. 6 shows openings 120a that will be formed in an opening formation step, which will be described later.

[0045] 3-3. Opening formation process As shown in FIG. 6, a plurality of openings 120a that expose the n-type semiconductor layer 112 are formed in the mask 120. The mask 120 is patterned by, for example, nanoimprinting. The diameter of the openings 120a is, for example, 100 to 500 nm. FIG. 7 is a diagram showing the arrangement of the openings 120a in the mask 120. FIG. 7 is a diagram showing the substrate 110 as viewed from a direction perpendicular to the surface of the substrate 110. For reference, the shape of the columnar semiconductor 130 is drawn by a dashed line in FIG. 7. As shown in FIG. 7, the openings 120a in the mask 120 are circular and arranged in a square lattice pattern.

[0046] The shape of the pillar-shaped semiconductor 130 can be controlled by changing the shape of the opening 120a of the mask 120. When the shape of the opening 120a is circular, the pillar-shaped semiconductor 130 having a cross-sectional shape close to a regular hexagon can be formed. When the shape of the opening 120a is oval, the pillar-shaped semiconductor 130 having a cross-sectional shape close to a flat shape can be formed.

[0047] 3-4. P-type semiconductor layer 113 removal process 8, the p-type semiconductor layer 113 exposed in the opening 120a is removed by etching to expose the n-type semiconductor layer 112. Thermal etching or the like is used for the etching.

[0048] Alternatively, when forming the opening 120a by nanoimprinting in the previous process, rather than stopping the etching at the stage when the p-type semiconductor layer 113 is exposed by the etching to form the opening 120a, the etching may be allowed to proceed further to etch the p-type semiconductor layer 113 and expose the n-type semiconductor layer 112.

[0049] 3-5. Columnar semiconductor formation process As shown in Fig. 9, a pillar-shaped semiconductor 130 is formed. First, starting from the n-type semiconductor layer 112 exposed under the opening 120a of the mask 120, a hexagonal pillar-shaped n-type semiconductor 131 is selectively grown. For this purpose, a known selective growth technique may be used. When the semiconductor layer is selectively grown in this manner, the m-plane is likely to be exposed as a facet.

[0050] As described above, since the openings 120a of the mask 120 are circular, the columnar n-type semiconductor 131 grows in the shape of a hexagonal column whose cross section is close to a regular hexagon.

[0051] Next, the active layer 132 is formed around the pillar-shaped n-type semiconductor 131. The active layer 132 is formed on the side surface of the pillar-shaped n-type semiconductor 131, whose cross section is shaped like a regular hexagon. The active layer 132 is also formed on the top of the pillar-shaped n-type semiconductor 131.

[0052] Next, a cylindrical p-type semiconductor 133 is formed on the active layer 132 to cover the outer periphery of the active layer 132. The cylindrical p-type semiconductor 133 has a hexagonal cylindrical shape. The cylindrical p-type semiconductor 133 is formed on the side surface of the active layer 132. The cylindrical p-type semiconductor 133 is also formed on the top of the active layer 132.

[0053] Next, a p+ layer 135 is formed on the cylindrical p-type semiconductor 133 to cover the cylindrical p-type semiconductor 133, and an n+ layer 136 is further formed to cover the p+ layer 135. This forms a tunnel junction layer 134. The tunnel junction layer 134 is formed on the side surface of the cylindrical p-type semiconductor 133. The tunnel junction layer 134 is also formed on the top of the cylindrical p-type semiconductor 133. In this manner, the columnar semiconductor 130 is formed.

[0054] 3-6. Buried layer formation process Next, as shown in FIG. 10, the gaps between the pillar-shaped semiconductors 130 are filled with a buried layer 140.

[0055] 3-7. Electrode formation process Next, a cathode electrode N1 is formed on the back surface of the substrate 110. Also, an anode electrode P1 is formed on the embedded layer 140. In this manner, the semiconductor light emitting device 100 of the first embodiment shown in FIGS.

[0056] 3-8.Other processes A heat treatment step, a step of forming a passivation film or the like on the surface of the semiconductor layer, or other steps may be performed.

[0057] 4. Effects of the First Embodiment In the first embodiment, a p-type semiconductor layer 113 is provided on an n-type semiconductor layer 112. This can improve the insulation between the n-type semiconductor layer 112 of the substrate 110 and the buried layer 140 on the mask 120. Furthermore, the efficiency of carrier injection into the active layer 132 can be improved, so that the driving voltage can be reduced and the light emission efficiency can be improved.

[0058] 5. Variations 5-1. Structure of semiconductor light emitting device In this embodiment, a vertical structure is used in which the cathode electrode N1 is provided on the back surface of the substrate 110 and conducts electricity perpendicular to the main surface of the substrate 110, but a flip-chip type or face-up type element structure in which the cathode electrode N1 is provided on the same side as the anode electrode P1 may also be used. In that case, the n-type semiconductor layer 112 is exposed by etching from the upper surface side of the embedded layer 140, and the cathode electrode N1 is formed on the exposed n-type semiconductor layer 112.

[0059] 5-2. Composition of columnar semiconductor In this embodiment, the columnar n-type semiconductor 131 is an n-type GaN layer, the well layer is an InGaN layer, the barrier layer is an AlGaInN layer, and the cylindrical p-type semiconductor 133 is a p-type GaN layer. These are merely examples, and other Group III nitride semiconductors may be used. Also, other semiconductors may be used.

[0060] 5-3.Surface layer A plurality of protrusions may be provided on the surface of the embedding layer 140 for light extraction. A surface layer may be provided on the embedding layer 140, and a plurality of protrusions may be provided on the surface layer. The surface layer may be, for example, an n-GaN layer having a different doping amount from that of the embedding layer 140. The material of the surface layer may be a transparent conductive oxide such as ITO or IZO. The arrangement of the protrusions may be, for example, a honeycomb or square lattice pattern. Recesses may be provided instead of the protrusions.

[0061] 5-4. Composition of the buried layer In this embodiment, the material of the burying layer 140 is an n-GaN layer. However, an n-AlGaN layer can be used as the burying layer 140 instead of the n-GaN layer. n-GaN and n-AlGaN may be combined. In the case of a laser diode, forming n-AlGaN on n-GaN makes it possible to enhance light confinement due to the refractive index difference.

[0062] 5-5. Current blocking layer of pillar-shaped semiconductor It is preferable to promote current injection from the side surface of the pillar-shaped semiconductor 130. For example, a transparent insulating film is provided on the top of the pillar-shaped semiconductor 130. This blocks current flowing to the top of the pillar-shaped semiconductor 130, and allows current injection from the side surface of the pillar-shaped semiconductor 130 to be performed satisfactorily.

[0063] 5-6.Irregularized substrate When used as an LED, the growth substrate 111 of the substrate 110 may be textured. In other words, the growth substrate 111 has a textured portion with periodic projections and recesses on the surface on the semiconductor layer side. Examples of the textured shape include a cone shape and a hemisphere shape. These convex shapes may be arranged, for example, in a square lattice or honeycomb shape. This further improves the light extraction efficiency.

[0064] 5-7. Application to other semiconductor devices Although the first embodiment is directed to a semiconductor light emitting device, the present invention can be applied to devices other than light emitting devices, such as photodetectors such as solar cells.

[0065] Combinations The above modifications may be freely combined.

[0066] Second Embodiment 1. Semiconductor light emitting element 11 is a cross-sectional view showing the periphery of the pillar-shaped semiconductor 230 of the semiconductor light emitting device 200 of the second embodiment. As shown in FIG. 11, the semiconductor light emitting device 200 includes a substrate 210, a mask 120, a pillar-shaped semiconductor 230, and a buried layer. 2 40, a cathode electrode N1, and an anode electrode P1.

[0067] The substrate 210 is a growth substrate for growing the columnar semiconductor 230, and also serves to support the mask 120, the columnar semiconductor 230, and the buried layer 240. The substrate 210 has a conductive substrate 111, an n-type semiconductor layer 112 located on the conductive substrate 111, a tunnel junction layer 213 located on the n-type semiconductor layer 112, and a p-type semiconductor layer 214 located on the tunnel junction layer 213. The conductive substrate 111 and the n-type semiconductor layer 112 are the same as those in the first embodiment.

[0068] The tunnel junction layer 213 is configured by laminating an n+ layer 215 and a p+ layer 216 in this order from the n-type semiconductor layer 112 side. The n+ layer 215 is a layer having a high n-type impurity concentration, for example, n-GaN. The p+ layer 216 is a layer having a high p-type impurity concentration, for example, p-GaN. The thicknesses and impurity concentrations of the n+ layer 215 and the p+ layer 216 depend on the thickness of the n-type semiconductor layer 112 when compared to the thickness of the p-type semiconductor layer. 2 14.

[0069] The p-type semiconductor layer 214 is, for example, a Mg-doped p-type GaN layer. The thickness of the p-type semiconductor layer 214 is, for example, 50 to 500 nm. The Mg concentration of the p-type semiconductor layer 214 is, for example, 5×10 18 ~5×10 20 cm -3 It is.

[0070] The mask 120 is similar to that in the first embodiment, except that it is provided on the p-type semiconductor layer 214 .

[0071] The pillar-shaped semiconductor 230 is a pillar-shaped Group III nitride semiconductor. The pillar-shaped semiconductor 230 is a semiconductor selectively grown from the surface of the substrate 110 (the surface of the p-type semiconductor layer 114) exposed in the opening 120a of the mask 120. The shape and arrangement of the pillar-shaped semiconductor 230 are similar to those of the pillar-shaped semiconductor 130 of the first embodiment.

[0072] The buried layer 140 is similar to that in the first embodiment.

[0073] The anode electrode P1 is formed on the back surface of the substrate 110 (the surface opposite to the surface on which the mask 120 is provided).

[0074] Cathode Electrode N 1 is the buried layer 2 It is formed above 40.

[0075] 2. Columnar semiconductor 11, the pillar-shaped semiconductor 230 includes a pillar-shaped p-type semiconductor 231, an active layer 232, and a non-doped semiconductor 233. The side surface of the pillar-shaped p-type semiconductor 231 is an m-plane or a surface close to the m-plane. 2 In the case of 32, there is almost no decrease in luminous efficiency due to piezoelectric polarization.

[0076] 2-1. Structure of pillar-shaped semiconductor The pillar-shaped p-type semiconductor 231 is a semiconductor layer selectively grown in a pillar shape starting from the surface of the p-type semiconductor layer 214 exposed in the opening 120a of the mask 120. The pillar-shaped p-type semiconductor 231 is, for example, a p-type GaN layer. The shape of the pillar-shaped p-type semiconductor 231 is similar to that of the pillar-shaped n-type semiconductor 131 of the first embodiment.

[0077] The non-doped semiconductor 233 is located at the tip of the columnar p-type semiconductor 231. The non-doped semiconductor 233 is, for example, an non-doped GaN layer. By providing the non-doped semiconductor 233, current flow to the tip of the columnar semiconductor 230 is suppressed, and current injection to the side surface of the columnar semiconductor 230 is promoted. The non-doped semiconductor may be a layer that is made highly resistive by co-doping with Mg and Si.

[0078] The active layer 232 is formed along the outer periphery of the hexagonal columnar p-type semiconductor 231 and the non-doped semiconductor 233. The other configurations are similar to those of the active layer 132 of the first embodiment.

[0079] An electron barrier layer may be provided between the pillar-shaped p-type semiconductor 231 and the active layer 232. The electron barrier layer is a p-type semiconductor having a larger band gap than the pillar-shaped p-type semiconductor 231. For example, it is p-AlGaInN. By providing the electron barrier layer, electrons can be efficiently injected into the active layer 232, and the light emission efficiency can be improved.

[0080] 2-2.Cross-sectional shape Fig. 12 is a cross-sectional view showing a VV cross section of Fig. 11. Fig. 12 shows a cross section of the columnar semiconductor 230 parallel to the plate surface of the substrate 210. As shown in Fig. 12, the shape of the cross section perpendicular to the axial direction of the columnar semiconductor 230 is a regular hexagon. Then, a columnar p-type semiconductor 231 and an active layer 232 are arranged from the inside of the hexagonal columnar semiconductor 230. Note that the shape of the cross section perpendicular to the axial direction of the columnar semiconductor 230 does not need to be a regular hexagon, and may be a flat hexagon. 3. Manufacturing method of semiconductor light emitting element 3-1. Board preparation process As shown in FIG. 13, a growth substrate 111 is prepared. Then, an n-type semiconductor layer 112, a tunnel junction layer 213, and a p-type semiconductor layer 214 are laminated in this order on the growth substrate 111 by MOCVD. The following semiconductor layers are all formed by MOCVD. Then, annealing is performed to activate the p+ layer 216 and the p-type semiconductor layer 214 in the tunnel junction layer 213. Since this is performed before the active layer 232 is formed, this can be performed without considering thermal damage. In this manner, a substrate 210 for growing a columnar semiconductor 230 is formed.

[0081] 3-2. Mask forming process and opening forming process 14, in the same manner as in the first embodiment, a mask 120 is formed on the p-type semiconductor layer 214, and a plurality of openings 120a that expose the p-type semiconductor layer 214 are formed in the mask 120. After the formation of the mask 120, activation annealing may be performed.

[0082] 3-3. Columnar semiconductor formation process As shown in FIG. 15, a columnar semiconductor 230 is formed. First, a columnar p-type semiconductor 231 having a hexagonal columnar shape is selectively grown starting from the p-type semiconductor layer 214 exposed under the opening 120a of the mask 120. Then, the supply of Mg dopant gas is stopped to form a non-doped semiconductor 233 at the tip of the columnar semiconductor 230. For this purpose, a known selective growth technique may be used. When a semiconductor layer is selectively grown in this manner, the m-plane is likely to be exposed as a facet.

[0083] As described above, since the opening 120a of the mask 120 is circular, the columnar p-type semiconductor 231 grows in the shape of a hexagonal column whose cross section is close to a regular hexagon.

[0084] Next, the active layer 232 is formed around the pillar-shaped p-type semiconductor 231 and the non-doped semiconductor 233. The active layer 232 is formed on the side surface of the pillar-shaped p-type semiconductor 231, whose cross section is shaped like a regular hexagon. The active layer 232 is also formed on the top surface and side surface of the non-doped semiconductor 233. In this manner, the pillar-shaped semiconductor 230 is formed.

[0085] 3-4. Buried layer formation process 16, the spaces between the pillar-shaped semiconductors 230 are filled with a buried layer 240. The buried layer 240 is grown until its surface becomes flat.

[0086] 3-5.Mesa formation process Next, a mesa for element isolation is formed. The tunnel junction layer 213 and the p-type semiconductor layer 214 are exposed on the side of the mesa. Then, activation annealing is performed. Since the tunnel junction layer 213 and the p-type semiconductor layer 214 are exposed on the side of the mesa, hydrogen desorption is promoted, and the p-type can be efficiently changed. If the semiconductor light emitting element 200 is an LED, the line L1 on the side of the mesa may be arranged along the square lattice arrangement of the columnar semiconductor 230 and may pass through the columnar semiconductor 230 (see FIG. 17). Since the columnar p-type semiconductor 231 of the columnar semiconductor 230 is exposed on the side of the mesa, the columnar p-type semiconductor 231 can be efficiently changed to a p-type. If the semiconductor light emitting element 200 is a laser diode, the line L2 on the side of the mesa may be arranged along the square lattice arrangement of the columnar semiconductor 230 and may not pass through the columnar semiconductor 230 so as not to affect the resonance of the laser light. For example, it may be arranged to pass through the face center of the square lattice.

[0087] 3-6. Electrode formation process Next, an anode electrode P1 is formed on the back surface of the substrate 210. In addition, a cathode electrode N1 is formed on the embedded layer 240. In this manner, the semiconductor light emitting device 200 of the second embodiment shown in FIG.

[0088] 3-7.Other processes A heat treatment step, a step of forming a passivation film or the like on the surface of the semiconductor layer, or other steps may be performed. 4. Effects of the Second Embodiment In a structure in which the main trunk of the pillar-shaped semiconductor is n-type and the pillar-shaped semiconductor is buried with a p-type semiconductor, the buried layer is thick and the p-type semiconductor has high resistance, resulting in a high driving voltage. For this reason, a structure has been developed in which a tunnel junction layer is provided on the side of the pillar-shaped semiconductor and the buried layer is made of an n-type semiconductor, as in the first embodiment. Since the n-type semiconductor has low resistance, the driving voltage can be reduced compared to when the buried layer is made of a p-type semiconductor.

[0089] However, because the p-type semiconductor of the pillar-shaped semiconductor and the tunnel junction layer is surrounded by the buried layer, it is difficult to activate the p-type semiconductor, which results in a decrease in injection efficiency.

[0090] The semiconductor light emitting device 200 of the second embodiment solves such problems. In the second embodiment, since the tunnel junction layer 213 is provided on the substrate 210 side, activation annealing can be performed at a stage before the active layer 232 is formed, and the p+ layer 216 and the p-type semiconductor layer 214 in the tunnel junction layer 213 can be efficiently activated. In addition, activation annealing after the active layer 232 is formed can be efficiently performed by forming a mesa. Since activation annealing can be distributed between before and after the active layer 232 is formed, the annealing time after the active layer 232 is formed can be shortened, and thermal damage to the active layer 232 can be suppressed.

[0091] As described above, in the semiconductor light emitting device 200 of the second embodiment, the p-type semiconductor can be efficiently activated, so that the injection efficiency can be improved. In addition, since the buried layer 240 is not p-type, the p-type semiconductor can be made as thin as possible, so that the driving voltage can be improved. In addition, the thermal damage to the active layer 232 can be suppressed by dispersing the activation annealing.

[0092] Furthermore, the semiconductor light emitting device 200 of the second embodiment has the advantage that the tunnel junction layer 213 can be easily set. When forming a tunnel junction layer on the side surface of a columnar semiconductor, it was necessary to change the thickness and impurity concentration of the tunnel junction layer depending on the diameter and height of the columnar semiconductor. On the other hand, in the semiconductor light emitting device 200 of the second embodiment, since the tunnel junction layer 213 is provided on the substrate 210 side, the thickness and impurity concentration of the tunnel junction layer 213 can be set regardless of the diameter and height of the columnar semiconductor 230. [Industrial Applicability]

[0093] The semiconductor device of this specification can be used as a light emitting element such as a laser diode or an LED, or a light receiving element such as a solar cell. [Explanation of symbols]

[0094] 100, 200...Semiconductor light emitting device 110, 210...Substrate 111...Conductive substrate 112...n-type semiconductor layer 113, 214...p-type semiconductor layer 120…Mask 120a…Opening 130, 230...Columnar semiconductor 131...Columnar n-type semiconductor 132, 232...active layer 133...Cylindrical p-type semiconductor 134, 213...Tunnel junction layer 140, 240...buried layer 231...Columnar p-type semiconductor 233...Non-doped semiconductor N1: Cathode electrode P1…Anode electrode

Claims

1. A first semiconductor layer made of a semiconductor; a second semiconductor layer provided on the first semiconductor layer and made of a semiconductor having a resistivity 100 times or more higher than that of the first semiconductor layer; a mask provided on the second semiconductor layer, the mask being made of a dielectric material and having a thickness of 2 nm to 50 nm; a plurality of openings provided on the mask, the openings having a depth reaching the first semiconductor layer, the openings having a diameter of 100 nm or more and 500 nm or less; a plurality of pillar-shaped semiconductors provided on the first semiconductor layer in the opening; a buried layer made of a semiconductor and burying the spaces between the pillar-shaped semiconductors; A semiconductor element having

2. The semiconductor device according to claim 1 , wherein the second semiconductor layer is made of a semiconductor having a conductivity type different from that of the first semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the second semiconductor layer is made of a non-doped semiconductor.

4. 4. The semiconductor device according to claim 1, wherein the buried layer is made of a semiconductor of the same conductivity type as that of the first semiconductor layer.

5. A first semiconductor layer made of an n-type semiconductor; a tunnel junction layer provided on the first semiconductor layer; a second semiconductor layer formed on the tunnel junction layer and made of a p-type semiconductor; a mask made of a dielectric material provided on the second semiconductor layer; a plurality of openings provided on the mask, the openings being holes each having a depth reaching the second semiconductor layer; a plurality of pillar-shaped semiconductors formed of a p-type semiconductor and provided on the second semiconductor layer in the opening; A semiconductor element having

6. The semiconductor device according to claim 5 , further comprising a mesa, the tunnel junction layer and the second semiconductor layer being exposed on a side surface of the mesa.

7. The semiconductor device according to claim 6 , wherein the pillar-shaped semiconductor is exposed on a side surface of the mesa.

8. a first step of stacking a first semiconductor layer made of an n-type semiconductor, a tunnel junction layer, and a second semiconductor layer made of a p-type semiconductor on a growth substrate in this order; a second step of performing activation annealing on the tunnel junction layer and the second semiconductor layer after the first step; a third step of forming a mask made of a dielectric material and having a plurality of openings on the second semiconductor layer after the second step; a fourth step of selectively growing a pillar-shaped semiconductor made of a p-type semiconductor in the opening after the third step; a fifth step of forming a mesa such that the tunnel junction layer and the second semiconductor layer are exposed on a side surface of the mesa after the fourth step; a sixth step of performing activation annealing on the tunnel junction layer, the second semiconductor layer, and the pillar-shaped semiconductor after the fifth step; 2. A method for manufacturing a semiconductor device comprising the steps of:

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