Method for manufacturing an optoelectronic device - Patents.com

Abstract

The present disclosure relates to a method for manufacturing an optoelectronic device (5) comprising an assembly of light emitting diodes (LEDs) including first and second assembly(ies), and a first block (32) formed of a first photoluminescent material each overlying one of the first assembly(ies), the method comprising forming a layer overlying the first and second assembly(ies), defining first openings in the layer to expose the first assembly(ies), filling the first openings with a first material, and chemical-mechanical polishing to define the first block(s).

Description

[Technical field]

[0001] The present invention generally relates to an optoelectronic device comprising a nanometer- or micrometer-sized semiconductor element, in particular a microwire- or nanowire- or pyramidal-shaped structure, forming a light-emitting diode, and a photoluminescent block covering the light-emitting diode. [Background technology]

[0002] The term "optoelectronic device" is used to denote a device capable of converting an electrical signal into electromagnetic radiation or vice versa, in particular a device for the detection, measurement or emission of electromagnetic radiation. An electronic device comprising a three-dimensional semiconductor element may comprise a light emitting diode covered with a photoluminescent block. Summary of the Invention [Problem to be solved by the invention]

[0003] A method of making such an optoelectronic device includes forming light emitting diodes on a substrate and forming a photoluminescent block overlying the light emitting diodes. The photoluminescent block may be formed by depositing a photoluminescent layer over the collection of light emitting diodes and etching the photoluminescent layer to define the photoluminescent block.

[0004] The photoluminescent blocks may be defined in the photoluminescent layer by depositing a resin layer over the photoluminescent layer and defining portions of the photoluminescent layer at desired locations in the photoluminescent blocks by photolithographic techniques, which typically use detection of visible alignment marks on the substrate to accurately position a mask used to expose the resin layer relative to the light emitting diodes.

[0005] A disadvantage of such an approach is that the photoluminescent layer may be partially opaque to visible light, making it difficult to perform lithographic processes using detection of the alignment marks.

[0006] It is therefore an object of the embodiments to at least partially overcome the disadvantages of the above mentioned methods for manufacturing an optoelectronic device comprising a light emitting diode and a photoluminescent block.

[0007] Another object of the embodiment is that the material forming the photoluminescent block does not have to be a photosensitive material adapted for use in a photolithography process.

[0008] Another object of an embodiment is to allow for a large height to width ratio for the glittering blocks.

[0009] Another object of embodiments is that optoelectronic devices may be formed on an industrial scale and at low cost. [Means for solving the problem]

[0010] An embodiment provides a method for manufacturing an optoelectronic device comprising an assembly of light emitting diodes including a first assembly and a second assembly, and a first block formed of a first photoluminescent material covering each of the first assemblies, the method including forming a layer covering the first assembly and the second assembly, defining a first opening in the layer to expose the first assembly, filling the first opening with the first photoluminescent material, and performing chemical mechanical polishing to define the first block.

[0011] According to an embodiment, the optoelectronic device further includes second blocks formed of a second photoluminescent material different from the first photoluminescent material and each covering one of the second aggregates, and the method includes defining second openings in the layer to expose the second aggregates, filling the second openings with the second photoluminescent material, and performing chemical mechanical polishing to define the second blocks.

[0012] According to an embodiment, the optoelectronic device further comprises a third group of light-emitting diodes and a third block formed of a third photoluminescent material different from the first photoluminescent material and the second photoluminescent material, each covering one of the third groups, and the method includes defining a third opening in the layer to expose the third group, filling the third opening with the third photoluminescent material, and performing chemical mechanical polishing to define the third block.

[0013] According to an embodiment, the optoelectronic device further comprises a fourth set of light emitting diodes, and the method includes defining fourth blocks in the layer, each fourth block covering one of the fourth set of light emitting diodes.

[0014] According to an embodiment, said layer is at least partially transparent to radiation emitted by light emitting diodes of said fourth set of light emitting diodes.

[0015] According to an embodiment, the method includes defining a fourth opening in the layer between the aggregates and forming a wall in the fourth opening having reflective sides.

[0016] According to an embodiment, the method includes depositing a reflective coating in the fourth opening and filling the remainder of the fourth opening with a fifth material.

[0017] According to an embodiment, the wall is formed after the first block.

[0018] According to an embodiment, the method further comprises forming a barrier layer extending into the fourth opening and covering the first block before forming the wall.

[0019] According to an embodiment, after the first block and the second block, the wall is formed.

[0020] According to an embodiment, the wall is formed before the first block and the second block.

[0021] According to an embodiment, the method includes forming a barrier layer extending into the fourth opening and covering the first block, the second block and the third block before etching the layer between the first block, the second block and the third block and forming the wall in the space between the first block, the second block and the third block. [Brief description of the drawings]

[0022] The above and other features and advantages are explained in more detail in the following particular embodiments, given as non-limiting illustrations of the invention with reference to the accompanying drawings, in which: FIG.

[0023] [Figure 1] 1 is a partial cross-sectional schematic diagram illustrating an embodiment of an optoelectronic device comprising a light emitting diode and a photoluminescent block. [Diagram 2] 1 is a schematic partial cross-sectional view illustrating an embodiment of a light emitting diode. [Diagram 3] 2A to 2C are cross-sectional views illustrating structures obtained at steps of an embodiment of a method for manufacturing the optoelectronic device of FIG. [Figure 4] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 5] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 6] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 7] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 8] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 9] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 10] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 11] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 12]5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 13] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 14] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 15] 2A-2C are cross-sectional views illustrating structures obtained at steps of another embodiment of a method for manufacturing the optoelectronic device of FIG. [Figure 16] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 17] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 18] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 19] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 20] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 21] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 22] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 23] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 24] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 25] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 26] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 27] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 28] 2A-2C are cross-sectional views illustrating structures obtained at steps of another embodiment of a method for manufacturing the optoelectronic device of FIG. [Figure 29] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 30] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 31] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 32] 2A-2C are cross-sectional views illustrating structures obtained at steps of another embodiment of a method for manufacturing the optoelectronic device of FIG. [Diagram 33] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 34] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 35] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 36] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 37] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 38] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 39] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 40] 2A-2C are cross-sectional views illustrating structures obtained at steps of another embodiment of a method for manufacturing the optoelectronic device of FIG. [Diagram 41] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 42] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 43] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 44] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 45] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Diagram 46] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 47] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 48] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 49]5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 50] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 51] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; [Figure 52] 5A-5C are cross-sectional views illustrating the structure obtained at different steps of the method; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Similar features are indicated by similar reference numerals in the various figures. In particular, structural and / or functional features common to various embodiments may have the same reference numerals and may have the same structural, dimensional and material characteristics. For clarity, only those steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0025] In the following description, when referring to terms defining absolute positions such as "front", "back", "top", "bottom", "left", "right" or relative positions such as "up", "down", "upper", "lower" or orientations such as "horizontal" and "vertical", the terms refer to the optoelectronic device in its orientation in the drawing or in its normal position of use. Unless otherwise specified, the terms "about", "approximately", "substantially" and "to the extent" mean within 10% of the relevant value, preferably within 5%. When the terms "about", "approximately", "substantially" and "to the extent" are used in relation to orientation, these terms mean within 10% of the relevant value, preferably within 5%. Further, in this specification, the terms "insulating" and "conducting" are deemed to mean "electrically insulating" and "electrically conducting", respectively.

[0026] The transmittance of a layer corresponds to the ratio of the intensity of the radiation leaving the layer at the output face to the intensity of the radiation entering the layer at the input face opposite the output face. In the following description, a layer or a film is said to be opaque to radiation if the transmittance of the radiation through the layer or film is less than 10%. In the following description, a layer or a film is said to be transparent to radiation if the transmittance of the radiation through the layer or film is more than 10%. In the following description, "visible light" refers to electromagnetic radiation having a wavelength in the range of 400 nm to 700 nm.

[0027] In the following description, the permeability of a film or layer to oxygen at 40° C. is 1.10 -1 cm 3 / (m 2 The membrane or layer is said to be oxygen-tight when its permeability to oxygen is less than 1.10 ·day·atm. The permeability to oxygen may be measured according to ASTM D3985, "Standard Test Method for Oxygen Gas Transmission Rate Through Plastic Film and Sheeting Using a Coulometric Sensor." In the following description, a membrane or layer is considered to have an oxygen-tight permeability to water of 1.10 at 40°C. -1 g / (m 2 The film or layer is deemed watertight when the vapor transmission rate is less than 100% (days). The water permeability may be measured according to ASTM F1249, "Standard Test Method for Water Vapor Transmission Rate Through Plastic Film and Sheeting Using a Modulated Infrared Sensor".

[0028] The invention relates to the production of three-dimensional elements of nanometer or micrometer size, in particular optoelectronic devices comprising light-emitting diodes formed on the basis of microwires, nanowires or pyramids.

[0029] The term "microwire" or "nanowire" refers to a three-dimensional structure having an elongated shape in a desired direction, with at least two dimensions, referred to as minor dimensions, in the range of 5 nm to 5 μm, preferably in the range of 100 nm to 2 μm, more preferably in the range of 200 nm to 1.5 μm, and a third dimension, referred to as major dimension or height, that is equal to or greater than the maximum of the minor dimensions, preferably equal to or greater than three times the maximum, more preferably equal to or greater than five times the maximum. In an embodiment, the height of each microwire or nanowire may be equal to or greater than 500 nm, preferably in the range of 1 μm to 50 μm. In the following description, the term "wire" is used to mean "microwire" or "nanowire".

[0030] The cross-sectional shape of the wire may be different and may be, for example, elliptical, circular or polygonal, in particular triangular, rectangular, square or hexagonal. The term "average diameter" used in connection with the cross-section of a wire denotes a quantity related to the surface area of ​​the wire in this cross-section, which corresponds for example to the diameter of a disk having the same surface area as the cross-section of the wire.

[0031] In the following description, the term pyramid refers to a three-dimensional structure, some of which have a pyramidal or elongated pyramidal shape. The pyramidal structure may be truncated, i.e. the pyramidal tip is missing and replaced by a flat area. The base of the pyramid is inscribed within a square with side dimensions of 100 nm to 10 μm, preferably 0.2 μm to 2 μm. The polygon forming the base of the pyramid may be a hexagon. The height of the pyramid between the base of the pyramid and the apex or flat part of the apex is in the range of 100 nm to 20 μm, preferably in the range of 200 nm to 2 μm.

[0032] In the following description, embodiments are described for optoelectronic devices with light emitting diodes having microwires or nanowires, however, it should be clear that these embodiments may also relate to optoelectronic devices with light emitting diodes that include micrometer- or nanometer-sized pyramids.

[0033] The wire preferably comprises primarily at least 60% by weight, more preferably at least 80% by weight, of at least one semiconductor material, which may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, or a combination of at least two of these compounds.

[0034] Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds include GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements, such as phosphorus or arsenic, may also be used. In general, the elements in a III-V compound may be combined in different mole fractions. Examples of group II elements include group IIA elements, particularly beryllium (Be) and magnesium (Mg), and group IIB elements, particularly zinc (Zn), cadmium (Cd) and mercury (Hg). Examples of group VI elements include group VIA elements, particularly oxygen (O) and tellurium (Te). Examples of II-VI compounds include ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe or HgTe. In general, the elements in the II-VI compounds may be combined in different mole fractions. The semiconductor material of the wire may contain dopants, for example silicon to ensure N-type doping of III-N compounds, or magnesium to ensure P-type doping of III-N compounds.

[0035] FIG. 1 is a schematic partial cross-sectional view showing an embodiment of an optoelectronic device 5 comprising microwires or nanowires. The optoelectronic device 5 is shown in FIG. 1 from bottom to top as follows: a substrate 10 having an opposing surface 12 (the upper surface 12 is preferably flat at least at the level of the light emitting diodes) and a surface 14; a seed layer 16 arranged on the surface 12 and made of a material that promotes wire growth; an insulating layer 18 covering the seed layer 16 and having an opening 20 exposing a portion of the seed layer 16; - light emitting diodes LED (six light emitting diodes are shown) each in contact with the seed layer 16 through one of the openings 20; an insulating layer 24 extending laterally on the lower part of the light-emitting diode and on the insulating layer 18 between the light-emitting diodes LED; an electrode layer 26 forming an electrode covering each light emitting diode LED and further extending onto the insulating layer 24 between the light emitting diodes LED; a reflective conductive layer 28 extending on the electrode layer 26 between the light-emitting diodes LED (the conductive layer 28 may alternatively be arranged between the electrode layer 26 and the insulating layer 24 between the light-emitting diodes LED); a dielectric protective layer 30 extending over the electrode layer 26 and the conductive layer 28; - a photoluminescent block 32, 33 covering a particular group of light-emitting diodes; a block 34 (the transparent block 34 may be omitted) that covers the other clusters of light-emitting diodes through the light emitted by the light-emitting diodes; an insulating layer 36 covering the upper surface of each block 32, 33, 34 or only a part of the upper surface of each block 32, 33, 34 (the insulating layer 36 may be omitted); a protective layer 37 covering the insulating layer 36, the sides of the blocks 32, 33, 34 and the electrode layer 26 between the blocks 32, 34; - walls 38 between the blocks 32, 33, 34, each having a core 40 surrounded by a reflective coating 42; - one, two or three color filters 44 covering at least a part of the photoluminescent blocks 32, 33, for example one yellow filter, two filters (the first filter being a yellow filter and the second filter being a red filter), three filters (the first filter being a red filter, the second filter being a green filter and the third filter being a blue filter) (one filter 44 covering two blocks is shown as an example), - A transparent protective layer 46 covering the entire structure; It is equipped with:

[0036] 2 shows an embodiment of a light emitting diode LED. According to an embodiment, each light emitting diode LED has a wire 21 contacting the seed layer 16 through one of the openings 20 and a shell 22 including a stack of semiconductor layers covering the sidewalls and top of the wire 21. The assembly formed by each wire 21 and the associated shell 22 forms a light emitting diode LED.

[0037] The shell 22 may include a stack of layers including, inter alia, an active layer 23 and a bonding layer 25. The active layer 23 is the layer from which the majority of the light emitted by the light emitting diode LED is emitted. By way of example, the active layer 23 may include a confinement means such as multiple quantum wells. The bonding layer 25 may include a stack of semiconductor layers of the same III-V material as the wires 21, but of the opposite conductivity type to that of the wires 21.

[0038] The substrate 10 may represent a monoblock structure or a layer covering a support made of another material. The substrate 10 is preferably a semiconductor substrate, for example a substrate made of silicon, germanium, silicon carbide, a III-V compound such as GaN or GaAs, or a ZnO substrate. The substrate 10 is preferably a monocrystalline silicon substrate. The substrate is preferably a semiconductor substrate compatible with the manufacturing methods implemented in microelectronics. The substrate 10 may represent a multilayer structure of the silicon-on-insulator type, also called SOI.

[0039] The cross-section of the openings 20 may correspond to the desired cross-section of the wire 21 or may differ from the resulting cross-section of the wire 21. The average diameter of the wire 21 may be equal to or greater than the average diameter of the openings 20.

[0040] The seed layer 16 is formed of a material that favors wire growth. By way of example, the material forming the seed layer 16 may be a nitride, carbide or boride of a transition metal from columns IV, V or VI of the periodic table of the elements, or a combination of these compounds. By way of example, the seed layer 16 may be formed of aluminum nitride (AlN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium boride (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), tantalum carbonitride (TaCN), Mg x N y (where x is about 3 and y is about 2, e.g. magnesium nitride in the form of Mg3N2), magnesium gallium nitride (MgGaN), tungsten (W), tungsten nitride (WN), or combinations thereof. The seed layer 16 may have a monolayer structure or may correspond to a stack of at least two layers, each formed, for example, of one of the aforementioned materials.

[0041] According to an embodiment, the seed layer 16 may not be provided. According to an alternative embodiment, the seed layer 16 may be replaced by a seed pad, for example formed at the bottom of the opening 20.

[0042] Each of the insulating layers 18, 24, 30, 36, 37, 46 and the filling material 40 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si x N y , where x is about 3 and y is about 4, e.g., Si3N4), (particularly of the general formula SiO x N yThe insulating layers 18, 24, 30, 36, 37, 46 may be made of silicon oxynitride (e.g., Si2ON2), aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium dioxide (TiO2) or diamond. The insulating layers 18, 24, 30, 36, 37, 46 may have a single-layer structure or may correspond to a stack of two or more layers. If the insulating layer 18 corresponds to a stack of at least two layers, the upper layer of the stack has insulating properties and is made, for example, of a dielectric material.

[0043] The conductive layer 28 or coating 42 preferably corresponds to a metal layer, for example of aluminum, silver, copper, gold or zinc. The thickness of the conductive layer 28 or coating 42 may be in the range of 0.01 μm to 1,000 μm. Alternatively, the coating 42 may not be provided. In this case, the filling material 40 may be a metallic material, for example of aluminum, silver, copper or zinc.

[0044] The electrode layer 26 is transparent to the electromagnetic radiation emitted by the light emitting diode. The material forming the electrode layer 26 may be a transparent conductive material such as indium tin oxide (ITO), zinc aluminum oxide, zinc gallium oxide or graphene. The thickness of the electrode layer 26 may be in the range of 0.01 μm to 10 μm.

[0045] According to an embodiment, each photoluminescent block 32, 33 is arranged opposite one of the light emitting diodes or a group of light emitting diodes. Each photoluminescent block 32, 33 has a luminophore which, when excited by the light emitted by the associated light emitting diode LED, can emit light at a wavelength different from the wavelength of the light emitted by the associated light emitting diode LED. According to an embodiment, the optoelectronic device 5 comprises at least two types of photoluminescent blocks 32, 33. Each photoluminescent block 32 of a first type is capable of converting the light emitted by the light emitting diode LED into a first emitted light of a first wavelength, and each photoluminescent block 33 of a second type is capable of converting the light emitted by the light emitting diode it covers into a second emitted light of a second wavelength. According to an embodiment, the optoelectronic device 5 comprises at least three types of photoluminescent blocks 32, 33, and each photoluminescent block of a third type is capable of converting the light emitted by the light emitting diode LED into a third emitted light of a third wavelength. The first, second and third wavelengths may be different.

[0046] According to an embodiment, the light emitting diode can emit blue light, i.e. radiation light having a wavelength in the range of 430 nm to 480 nm. According to an embodiment, the first wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to an embodiment, the second wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0047] According to another embodiment, the light emitting diode LED can emit, for example, ultraviolet light. According to an embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 480 nm. According to an embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0048] The aspect ratio of the blocks 32, 33, ie the ratio of the height of the block to the maximum width, may be in the range of 0.01-10, preferably in the range of 0.05-2.

[0049] According to an embodiment, each photoluminescent block 32, 33 includes particles of at least one photoluminescent material, for example in a transparent matrix. Examples of photoluminescent materials include YAG:Ce or YAG:Ce. 3+ Also called yttrium aluminum garnet (YAG), which is activated by trivalent cerium ions. The average particle size of conventional photoluminescent materials is generally greater than 5 μm.

[0050] According to an embodiment, each photoluminescent block 32, 33 comprises a matrix in which nanometer-sized, single-crystalline particles of semiconductor material, hereinafter also referred to as semiconductor nanocrystals or nanoluminophore particles, are dispersed. int The internal quantum efficiency, QY, of semiconductor nanocrystals is equal to the ratio of the number of emitted photons to the number of photons absorbed by the photoluminescent material. int is greater than 5%, preferably greater than 10%, and more preferably greater than 20%.

[0051] According to an embodiment, the average size of the semiconductor nanocrystals is in the range of 0.5 nm to 1,000 nm, preferably 0.5 nm to 500 nm, more preferably 1 nm to 100 nm, in particular 2 nm to 30 nm. At sizes smaller than 50 nm, the light conversion properties of the semiconductor nanocrystals are essentially determined by the quantum confinement phenomenon. Therefore, the semiconductor nanocrystals correspond to quantum dots.

[0052] According to an embodiment, the semiconductor material of the semiconductor crystal is selected from the group comprising cadmium selenide (CdSe), indium phosphide (InP), cadmium sulfide (CdS), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium telluride (CdTe), zinc telluride (ZnTe), cadmium oxide (CdO), cadmium zinc oxide (ZnCdO), cadmium zinc sulfide (CdZnS), cadmium zinc selenide (CdZnSe), silver indium sulfide (AgInS2), perovskites of the PbScX3 type (where X is a halogen atom, in particular iodine (I), bromine (Br) or chlorine (Cl)) and mixtures of at least two of these compounds. According to an embodiment, the semiconductor material of the semiconductor nanocrystals is selected from the materials described in the publication by Le Blevenec et al., Physica Status Solidi (RRL) - Rapid Research Letters Volume 8, No. 4, p. 349-352, April 2014.

[0053] According to an embodiment, the size of the semiconductor nanocrystals is selected according to the desired wavelength of the radiation emitted by the semiconductor nanocrystals. As an example, CdSe nanocrystals with an average size of about 3.6 nm can convert blue light to red light, and CdSe nanocrystals with an average size of about 1.3 nm can convert blue light to green light. According to another embodiment, the composition of the semiconductor nanocrystals is selected according to the desired wavelength of the radiation emitted by the semiconductor nanocrystals.

[0054] The matrix is ​​at least partially transparent, preferably more than 80%, of the radiation emitted by the photoluminescent particles and / or the light-emitting diodes LED. The matrix is ​​for example made of silica. The matrix is ​​for example made of any at least partially transparent polymer, in particular silicone, epoxy resin, acrylic resin of the polymethylmethacrylate (PMMA) type or polylactic acid (PLA). The matrix may in particular be made of an at least partially transparent polymer used with three-dimensional printers. The matrix may correspond to a photosensitive or non-photosensitive glass (SOG, spin-on glass) deposited by centrifugation. According to an embodiment, the matrix comprises 2 to 90% by weight, preferably 10 to 60% by weight, of nanocrystals, for example about 30% by weight of nanocrystals.

[0055] The thickness of the photoluminescent blocks 32, 33 is dependent on the concentration of nanocrystals and the type of nanocrystals used. The height of the photoluminescent blocks 32, 33 is preferably greater than the height of the wires 21 and less than or equal to the height of the walls 38. In plan view, each photoluminescent block 32, 33 may correspond to a square, a rectangle, an "L" shaped polygon, etc., having an area that may be equal to the area of ​​a square with side lengths between 1 μm and 100 μm, preferably between 3 μm and 15 μm.

[0056] The walls 38 are at least partially made of at least one reflective material, which may be a metallic material, in particular iron, copper, aluminum, tungsten, silver, titanium, hafnium, zirconium, or a combination of at least two of these compounds. The walls 38 are preferably made of a material that is compatible with manufacturing methods implemented in microelectronics. The walls 38 are preferably made of aluminum or silver.

[0057] The height of the wall 38 measured in a direction perpendicular to the surface 12 is in the range of 300 nm to 200 μm, preferably in the range of 3 μm to 15 μm. The thickness of the wall 38 measured in a direction parallel to the surface 12 is in the range of 100 nm to 50 μm, preferably in the range of 0.5 μm to 10 μm.

[0058] Depending on the embodiment, the wall 38 may be formed of a reflective material or may be covered with a coating that reflects the wavelengths of radiation emitted by the photoluminescent blocks 32, 33 and / or the light emitting diodes.

[0059] Wall 38 preferably surrounds photoluminescent blocks 32, 33. Thus, wall 38 reduces crosstalk between adjacent photoluminescent blocks 32, 33.

[0060] The encapsulation layer 46 is at least partially transparent to the radiation emitted by the photoluminescent particles and / or the light emitting diode LED. The encapsulation layer may be formed of an inorganic material that is at least partially transparent to the radiation emitted by the photoluminescent particles and / or the light emitting diode LED. For example, the inorganic material may be SiO. x (where x is a real number between 1 and 2) type silicon oxide or SiO y N z (where y and z are real numbers between 0 and 1), titanium oxide, aluminum oxide, e.g. Al2O3, and mixtures of these compounds. The encapsulation layer may be formed of an at least partially transparent organic material. By way of example, the encapsulation layer is a silicone polymer, an epoxide polymer, an acrylic polymer, or a polycarbonate. The encapsulation layer 46 may have a single layer structure or a multi-layer structure, and may for example comprise a stack of organic and / or inorganic layers.

[0061] 3 to 14 show structures obtained at successive steps of an embodiment of a method for manufacturing the optoelectronic device 5 shown in FIG.

[0062] 3 shows the structure obtained after forming a seed layer 16 on the surface 12 of the substrate 10, forming an insulating layer 18 on the seed layer 16, etching openings 20 in the insulating layer 18, forming light emitting diodes LED, i.e. growing wires in the openings 20, for example by metal organic chemical vapor deposition (MOCVD) or any other suitable method, forming a shell covering the wires, forming an insulating layer 24 on the feet of each light emitting diode LED, forming an electrode layer 26, forming a conductive layer 28, forming a dielectric layer 30, and depositing a layer 50 of a material transparent to visible light, in particular a dielectric material, to fill the spaces between the wires 21 and to form a substantially flat top surface 52 on top of the dielectric layer 30. The layer 50 may be formed of a mineral material transparent in the visible range, SiO2, SiN, Al2O3. The layer 50 may also be formed of a resin, in particular a resist. The layer 50 may also be deposited by spin coating, slot die coating, blade coating, flexographic printing or silk screen.

[0063] FIG. 4 shows the structure obtained after depositing a layer 54 used as an etching mask on the transparent layer 50, etching openings 56 in the layer 54 at the desired locations of each of the first type of photoluminescent blocks 32, and etching openings 58 in the transparent layer 50 throughout its thickness, which openings 58 communicate with the openings 56. The layer 54 may be made of one of the materials mentioned above for the insulating layers 18, 24, 30, 36, 37, 46. The etching of the insulating layer 54 may be a dry etching, for example of the ion plasma type, or a wet etching, preferably selective with respect to the material of the transparent layer 50. If the layer 50 is made of SiO2, the layer 54 may be a resist and may be removed after the formation of the openings 58. The etching of the transparent layer 50 may be a dry etching, for example of the ion plasma type, preferably selective with respect to the protective layer 30.

[0064] 5 shows the resulting structure after the openings 56, 58 have been completely filled with the material that will form the first type of photoluminescent block 32. The filling method may be spin coating or slot die coating. The filling process forms a layer 60 of the material that will form the photoluminescent block 32 on the insulating layer 54.

[0065] FIG. 6 shows the structure obtained after a step of removing layer 60 and insulating layer 54 by etching, in particular chemical mechanical polishing, also called CMP, in order to expose the top surface 52 of transparent layer 50. The chemical mechanical polishing step may comprise simultaneous or successive mechanical polishing and chemical etching steps. According to an embodiment, layer 60 may be removed by CMP, so that layer 54 is used as an etch stop layer. Layer 54 may then be removed, for example by dry etching, in particular plasma etching or wet etching. In this way, the photoluminescent block 32 is defined. As a variant, layer 54 may not be removed.

[0066] 7 shows the structure obtained after depositing a layer 62 used as an etching mask on the transparent layer 50, etching openings 64 in the layer 62 at the desired locations of each of the second type of photoluminescent blocks 33, and etching openings 66 in the transparent layer 50 throughout its thickness, connecting with the openings 64. The layer 62 may be made of one of the materials mentioned above for the insulating layers 18, 24, 30, 36, 37, 46, 56.

[0067] 8 shows the resulting structure after completely filling the openings 64, 66 with the material that will form the second type of photoluminescent block 33. The filling method may be spin coating or slot die coating. The filling process forms a layer 67 of the material that will form the photoluminescent block 33 on top of the transparent layer 50.

[0068] 9 shows the structure obtained after a CMP step has been carried out to remove layer 67 and insulating layer 62 in order to expose the upper surface 52 of transparent layer 50. In this way, the photoluminescent block 33 is defined. Alternatively, layer 67 may be removed by CMP, so that layer 62 serves as an etch stop layer. Layer 62 may then be removed, for example by dry etching, in particular plasma etching, or by wet etching. Alternatively, layer 62 may not be removed.

[0069] FIG. 10 shows the structure obtained after depositing a layer 68 used as an etching mask on the transparent layer 50 and the photoluminescent blocks 32, 33 and etching openings 70 in the layer 68 at the desired locations on each of the walls 38.

[0070] 11 shows the structure obtained after etching openings 72 in transparent layer 50 for each opening 70, connecting them throughout the thickness of transparent layer 50. Layer 68 may or may not be retained. The remaining parts of transparent layer 50 form transparent block 34. If layer 50 is made of SiO2, layer 68 may be a resist layer and may be removed after the formation of openings 72.

[0071] Figure 12 shows the structure obtained after depositing an insulating layer 37 over the structure shown in figure 11. The insulating layer 37 may be deposited by a conformal deposition method, in particular by an atomic layer deposition (ALD) method. The insulating layer 37 may be a layer that is particularly tight against moisture and / or air and may perform the function of a protective layer for the photoluminescent blocks 32, 33. It is advantageous to deposit the insulating layer 37 immediately after the formation of the photoluminescent blocks 32, 33.

[0072] FIG. 13 shows the resulting structure after depositing a layer 76 of material forming the cladding 42 of wall 38 over the structure shown in FIG. 12, filling openings 72 with material forming core 40 of wall 38, and forming a layer 78 of filler material over blocks 32, 33, 34.

[0073] 14 shows the structure obtained after an etching step has been performed to remove parts of layer 78 and parts of layer 76 of filler material outside opening 72 to expose parts of insulating layer 37 covering part of insulating layer 68, thereby defining wall 38, and in particular core 40 and cladding 42. By way of example, the parts of layer 78 outside opening 72 may be removed by dry etching, and the parts of layer 76 outside opening 72 may be removed by wet or dry etching.

[0074] The method includes the additional steps of forming a color filter 44 and a protective layer 46 .

[0075] 15 to 27 show structures obtained in successive steps of another embodiment of a method for manufacturing an optoelectronic device 5 .

[0076] FIG. 15 shows the resulting structure after steps identical to those previously described in connection with FIGS. 3, 4, 5 and 6, except that the CMP step does not remove insulating layer 54.

[0077] FIG. 16 shows the resulting structure after depositing layer 62 used as an etching mask over the entire structure, etching openings 64 in layer 62 at the desired locations of each of the second type of photoluminescent blocks 33, etching openings 79 in layer 54 that connect with openings 64, and etching openings 66 in transparent layer 50 through the entire thickness of transparent layer 50 that connect with openings 64.

[0078] Figure 17 shows the structure obtained after a process similar to that described above in relation to figure 8, i.e. after completely filling the openings 64, 79, 66 with the material forming the second type of photoluminescent block 33. The filling method may be spin coating. The filling process forms a layer 67 of the material forming the photoluminescent block 33 on the insulating layer 62.

[0079] 18 shows the structure obtained after a CMP step has been carried out to remove layer 67, in order to reach the non-removable insulating layer 62. In this way, the photoluminescent block 33 is defined.

[0080] 19 and 20 illustrate a process similar to that previously described in connection with FIGS. 10 and 11, and show the structure obtained after depositing a layer 68 used as an etching mask over the entire structure, etching openings 70 in layer 68 at the desired locations in each of walls 38, optionally etching openings 80 in layer 62 which communicate with openings 70, etching openings 81 in layer 54 which communicate with openings 70, and etching openings 72 in transparent layer 50 which communicate with openings 70 throughout the thickness of transparent layer 50.

[0081] 21 shows the resulting structure after a CMP step has been performed to remove insulating layers 54, 62, 68. This step may be omitted.

[0082] FIG. 22 shows the structure obtained after a process similar to that previously described in connection with FIG. 13, which is to deposit over the structure shown in FIG. 21 an insulating layer 76 of the material forming the covering 42 of the wall 38, to fill the openings 72 with the material forming the core 40 of the wall 38, and to form a layer 78 of filling material over the blocks 32, 33, 34.

[0083] FIG. 23 shows the resulting structure after a CMP or dry etching process has been performed to remove the portions of layer 78 and layer 76 of fill material that are outside opening 72 and expose the portions of insulating layer 37 that cover insulating layer 36, thereby defining wall 38.

[0084] FIG. 24 shows the resulting structure after depositing a layer 82, which is used as an etching mask, over the entire structure and etching openings 83 in layer 82 at the desired locations of each of the third type of photoluminescent blocks.

[0085] FIG. 25 shows the resulting structure after removing layer 82 and etching an opening 84 in transparent layer 50 through its entire thickness, linking opening 83 .

[0086] 26 shows the resulting structure after the openings 84 are completely filled with the material forming the third type of photoluminescent block. The filling method may be spin coating. The filling process forms a layer 88 of the material forming the photoluminescent block on the remainder of the structure outside the openings 84.

[0087] 27 shows the structure obtained after performing a CMP step to remove layer 88. In this way, a third type of photoluminescent block 90 is defined. As mentioned before, in the absence of a transparent block 34 covering the light emitting diode LED, there is no need to form layer 50 from a highly transparent material, since at the end of the manufacturing method there is no further part of layer 50 covering the light emitting diode.

[0088] The method includes the additional steps of forming a color filter 44 and a protective layer 46 .

[0089] 28 to 31 show structures obtained in successive steps of another embodiment of a method for manufacturing an optoelectronic device 5.

[0090] The initial steps of the method include all of the steps previously described with reference to Figures 3-18.

[0091] FIG. 28 shows the resulting structure after depositing layer 82 used as an etching mask over the entire structure, etching openings 83 in layer 82 at the desired locations of each of the third type photoluminescent blocks 90, etching openings 92 in layer 62 that connect with openings 83, etching openings 94 in layer 54 that connect with openings 83, and etching openings 84 in transparent layer 50 that connect with openings 83 throughout the thickness of transparent layer 50.

[0092] 29 shows the resulting structure after opening 84 has been completely filled with material forming a third type of photoluminescent block 90. ​​The filling method may be spin coating. The filling process forms a layer 88 of material forming photoluminescent block 90 on the remainder of the structure outside opening 84.

[0093] 30 shows the resulting structure after a CMP step has been performed to remove layer 88. In this way, a third type of photoluminescent block 90 is defined.

[0094] In the embodiment described above, forming the openings 58, 66, 84 in layer 50 involves the use of an etch mask. According to another embodiment, if layer 50 is formed from resist, etching the openings in layer 50 may be performed directly by a photolithography process.

[0095] FIG. 31 shows the resulting structure after a selective etching step has been performed to remove mask layers 54, 62, 82 and the portions of transparent layer 50 remaining between photoluminescent blocks 32, 33, 90.

[0096] Therefore, the method may include the steps described above in connection with FIGS. 13 and 14, particularly for forming the walls 38 in the openings between the photoluminescent blocks 32, 33, 90.

[0097] 32 to 39 show structures obtained in successive steps of another embodiment of a method for manufacturing an optoelectronic device 5.

[0098] The first step of the method includes all of the steps previously described in connection with FIG.

[0099] FIG. 32 shows the structure obtained after depositing a layer 68 used as an etching mask on the transparent layer 50 and etching openings 70 in the layer 68 at the desired locations of each of the walls 38.

[0100] FIG. 33 shows the resulting structure after etching openings 72 in the transparent layer 50 throughout its thickness, linking each opening 70 .

[0101] FIG. 34 shows the resulting structure after steps similar to those previously described in connection with FIG. 13, including depositing an insulating layer 76 of material forming the coating 42 of wall 38 over the structure shown in FIG. 33, filling openings 72 with material forming core 40 of wall 38, and forming a layer 78 of filler material over transparent layer 50.

[0102] 35 shows the resulting structure after an etching step has been performed to define walls 38 by removing the portions of layer 76 and layer 78 of fill material that are outside opening 72. As previously mentioned, the portions of layer 78 outside opening 72 may be removed by dry etching or CMP, and the portions of layer 76 outside opening 72 may be removed by wet etching or dry etching.

[0103] Figures 36-39 show the structure obtained by the steps previously described in relation to Figures 24-27, respectively, and illustrate the formation of a first type of photoluminescent block 32. These steps are repeated once to form a second type of photoluminescent block 33, and optionally once to form a third type of photoluminescent block 90.

[0104] 40 to 52 show structures obtained in successive steps of another embodiment of a method for manufacturing an optoelectronic device 5 .

[0105] The first step of the method includes all of the steps previously described in connection with FIG.

[0106] 40 shows the resulting structure after depositing a layer 100, used as an etch mask and covering the transparent layer 50, and a resist layer 102 covering the layer 100. The layer 100 may be formed of one of the materials previously mentioned for the insulating layers 18, 24, 30, 36, 37, 46.

[0107] FIG. 41 shows the resulting structure after etching openings 104 in layer 102 at the desired locations of each of the first type of photoluminescent blocks 32 and etching openings 106 in layer 100 that communicate with openings 104.

[0108] 42 shows the resulting structure after removing resist layer 102 and depositing an insulating layer 106 over the entire structure. Insulating layer 106 may be formed from one of the materials previously described for insulating layers 18, 24, 30, 36, 37, and 46.

[0109] 43 shows the structure obtained after etching the insulating layer 106 to form portions 108 of the insulating layer 106, called spacers, on the sides of each opening 104 while removing the insulating layer 106 on the other side. The etching may be a dry etching.

[0110] FIG. 44 shows the resulting structure after etching openings 110 in transparent layer 50 through the entire thickness of transparent layer 50, openings 110 being defined by the mask formed by layer 100 and spacers 108.

[0111] 45 shows the resulting structure after the opening 110 has been completely filled with the material that will form the first type of photoluminescent block 32. The filling method may be spin coating. The filling process forms a layer 88 of the material that will form the photoluminescent block 32 on the remainder of the structure outside the opening 110.

[0112] 46 shows the structure obtained after a CMP step has been carried out to remove layer 88. In this way, a first type of photoluminescent block 32 is defined.

[0113] FIG. 47 shows the structure obtained after repeating the steps described above in relation to FIGS. 40-45 to define a second type of photoluminescent block 33. FIG.

[0114] Figure 48 shows the structure obtained after removing the spacers 108, for example by etching selective to the material forming the photoluminescent blocks 32, 33, the material forming the transparent layer 50 and the material forming the insulating layer 100. The etching may be a dry or wet etch.

[0115] FIG. 49 shows the resulting structure after etching openings 112 through the entire thickness of transparent layer 50 in line with the openings formed by the removal of spacers 108.

[0116] FIG. 50 shows the resulting structure after deposition of an insulating layer 37 over the structure shown in FIG.

[0117] FIG. 51 shows the resulting structure after the material forming the core 40 of the wall 38 has been filled into the openings 112 to form a layer 78 of filler material over the blocks 32, 33, 34.

[0118] FIG. 52 shows the resulting structure after a CMP step has been performed to remove portions of layer 78 and layer 76 of fill material outside opening 112 and expose portions of insulating layer 37 covering the top surfaces of blocks 32, 33, and 34, thereby defining walls 38.

[0119] Various embodiments and variants have been described. The skilled artisan will understand that certain features of these various embodiments and variants can be combined, and other variants will occur to the skilled artisan. In particular, the method for manufacturing an optoelectronic device may comprise additional steps not described, for example a step of transferring the structure to an intermediate support, also called a handle, to allow handling of the structure. Finally, the actual implementation of the embodiments and variants described herein is within the skill of the skilled artisan based on the functional representations given above.

[0120] This patent application claims priority to French Patent Application No. 19 / 11133, which is incorporated herein by reference.

Claims

1. 1. A method of manufacturing an optoelectronic device comprising a collection of light emitting diodes including a first collection and a second collection, and a first block formed of a first photoluminescent material respectively covering one of the first collections, the method comprising: forming a layer that is transparent to visible light and covers the first assembly and the second assembly; defining a first opening in the layer to expose the first mass; Filling the first opening with the first photoluminescent material; performing chemical mechanical polishing to define the first block; The method, wherein the first photoluminescent material is a material capable of emitting radiation at a first wavelength that is different than the wavelength of radiation emitted by the light emitting diodes of the first collection.

2. the optoelectronic device further comprises second blocks formed of a second photoluminescent material different from the first photoluminescent material, the second blocks covering one of the second aggregates respectively; defining a second opening in the layer to expose the second mass; Filling the second opening with the second photoluminescent material; performing chemical mechanical polishing to define the second block; 10. The method of claim 1, wherein the second photoluminescent material is a material capable of emitting radiation at a second wavelength that is different than the wavelength of radiation emitted by the light emitting diodes of the second collection.

3. the optoelectronic device further comprises third groups of light emitting diodes and third blocks formed of a third photoluminescent material different from the first photoluminescent material and the second photoluminescent material, each covering one of the third groups; defining a third opening in the layer to expose the third mass; Filling the third opening with the third photoluminescent material; performing chemical mechanical polishing to define the third block; 3. The method of claim 2, wherein the third photoluminescent material is a material capable of emitting radiation at a third wavelength that is different than the wavelength of radiation emitted by the light emitting diodes of the third collection.

4. the optoelectronic device further comprises a fourth collection of light emitting diodes; The method according to any one of claims 1 to 3, further comprising defining fourth blocks in the layer, each covering a fourth group of the light emitting diodes.

5. The method of claim 4 , wherein the layer is at least partially transparent to radiation emitted by light emitting diodes of the fourth collection of light emitting diodes.

6. defining a fourth opening in the layer between the assemblies; The method according to any one of claims 1 to 5, further comprising forming a wall at the fourth opening with reflective sides.

7. depositing a reflective coating on the fourth opening; 7. The method of claim 6, further comprising filling the remaining portion of said fourth opening with a fifth material forming a core of said wall.

8. The method of claim 6 , further comprising forming the wall after the first block.

9. forming a barrier layer extending into the fourth opening and covering the first block prior to forming the wall; The method of claim 8 , wherein the barrier layer is an insulating layer that serves to protect the first block.

10. The method according to claim 7, which is dependent on claim 2, further comprising forming the wall after the first block and the second block.

11. The method according to claim 6, wherein the wall is formed before the first block and the second block.

12. Etching the layer between the first block, the second block, and the third block; forming a barrier layer extending into the fourth opening and covering the first block, the second block, and the third block before forming the wall; forming the wall in a space between the first block, the second block, and the third block; The method according to claim 6, which is dependent on claim 3, wherein the barrier layer is an insulating layer serving to protect the first block, the second block and the third block.

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