Light receiving element, imaging element, and imaging device

Abstract

This light receiving element comprises a sensor board (102) and a circuit board (101). The sensor board (102) is provided with a light receiving region (103), a pair of voltage impression electrodes, and an incidence surface electrode (104). The light receiving region (103) photoelectrically converts incident light into a signal charge. The pair of voltage impression electrodes are alternately impressed with a voltage so as to generate, in the light receiving region (103), an electrical field in which the signal charge is time-divided and distributed to a pair of charge accumulation electrodes. The incidence surface electrode (104) is disposed on a light incidence surface of the light receiving region and is impressed with a voltage at or below ground potential. The circuit board (101) is disposed on a surface of the sensor board (102) opposing the light incidence surface. The circuit board (101) is provided with a pixel transistor that processes the signal charge accumulated by the charge accumulation electrodes.

Description

[Technical field]

[0001] The present disclosure relates to a light receiving element, an imaging element, and an imaging device. [Background technology]

[0002] A light receiving element used in a distance measuring system using an indirect ToF (Time of Flight) method has a pixel array in which a plurality of light receiving pixels are arranged in a matrix. Each light receiving pixel has a light receiving region that photoelectrically converts incident light into a signal charge, and a pair of electrodes to which a voltage is alternately applied to generate an electric field in the light receiving region that time-divides the signal charge and distributes it to a pair of charge storage electrodes (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-86904 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, as the size of the light-receiving pixels becomes smaller, the charge collection efficiency decreases.

[0005] In view of this, the present disclosure proposes a light receiving element, an imaging element, and an imaging device that can increase the charge collection efficiency. [Means for solving the problem]

[0006] According to the present disclosure, a light receiving element is provided. The light receiving element has a sensor substrate and a circuit substrate. The sensor substrate is provided with a light receiving region, a pair of voltage application electrodes, and an incident surface electrode. The light receiving region photoelectrically converts incident light into signal charges. The pair of voltage application electrodes alternately apply voltages that generate an electric field in the light receiving region that time-divides the signal charges and distributes them to a pair of charge storage electrodes. The incident surface electrode is provided on a light incident surface of the light receiving region, and a voltage equal to or lower than ground potential is applied to the incident surface electrode. The circuit substrate is provided on a surface of the sensor substrate opposite to the light incident surface. The circuit substrate is provided with pixel transistors that process the signal charges stored in the charge storage electrodes. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating an example of the configuration of a solid-state imaging element, which is an example of a light receiving element according to the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating an example of a pixel configuration according to the present disclosure. [Diagram 3] FIG. 2 is a diagram showing a configuration example of a portion of a signal extraction section of a pixel according to the present disclosure. [Figure 4] FIG. 2 is a diagram showing an example of a circuit configuration of a pixel according to the present disclosure. [Diagram 5] 1A and 1B are diagrams illustrating a connection state between a circuit board and a sensor board according to the present disclosure. [Figure 6] 4A and 4B are explanatory diagrams of an incident surface electrode and a pixel isolation region according to the present disclosure. [Figure 7A] 1 is a diagram showing a configuration example of a pixel isolation region according to the present disclosure; [Figure 7B] 1 is a diagram showing a configuration example of a pixel isolation region according to the present disclosure; [Figure 7C] 1 is a diagram showing a configuration example of a pixel isolation region according to the present disclosure; [Figure 8] FIG. 11 is an explanatory diagram of a pixel isolation region according to Modification 1 of the present disclosure. [Figure 9] 11 is an explanatory diagram of a pixel isolation region according to Modification 2 of the present disclosure. FIG. [Figure 10] 1A and 1B are diagrams illustrating an example of an arrangement of pixel isolation regions according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0009] [1. Example of the configuration of a solid-state imaging device] The present technology can be applied to, for example, a solid-state imaging element constituting a distance measuring system that performs distance measurement by an indirect ToF (Time of Flight) method, and an imaging device having such a solid-state imaging element.

[0010] For example, the ranging system can be applied to an in-vehicle system that is installed in a vehicle and measures the distance to an object outside the vehicle, or a gesture recognition system that measures the distance to an object such as a user's hand and recognizes the user's gestures based on the measurement results. In this case, the result of the gesture recognition can be used for operating a car navigation system, for example.

[0011] Fig. 1 is a diagram showing a configuration example of a solid-state imaging element which is an example of a light receiving element according to the present disclosure. The solid-state imaging element 11 shown in Fig. 1 is a back-illuminated CAPD (Current Assisted Photonic Demodulator) sensor, and is provided in an imaging device having a distance measuring function.

[0012] The solid-state imaging element 11 includes a circuit board 101 and a sensor board 102 laminated on the circuit board 101. The sensor board 102 is provided with a pixel array section 21 in which a plurality of light-receiving pixels (hereinafter simply referred to as "pixels") are arranged in a matrix.

[0013] Peripheral circuits are provided on the circuit board 101. The peripheral circuit section includes, for example, a vertical drive section 22, a column processing section 23, a horizontal drive section 24, and a system control section 25. The vertical drive section 22 includes, for example, a pixel transistor that processes signal charges photoelectrically converted in each pixel. Note that, in this example, in order to facilitate understanding of the connection relationship between the components of the circuit board 101 and the components of the sensor board 102, the components are illustrated on the same plane.

[0014] In this way, the solid-state imaging device 11 has pixels of the pixel array unit 21 provided on the sensor substrate 102 and pixel transistors provided on the circuit substrate 101, thereby enabling improvement in charge collection efficiency and reduction in power consumption. This will be described later with reference to FIG.

[0015] The solid-state imaging element 11 is further provided with a signal processing unit 26 and a data storage unit 27. The signal processing unit 26 and the data storage unit 27 may be mounted on the same substrate as the solid-state imaging element 11, or may be disposed on a substrate separate from the solid-state imaging element 11 in the imaging device.

[0016] The pixel array section 21 has pixels arranged two-dimensionally in rows and columns, that is, in a matrix, that generate electric charges according to the amount of received light and output signals according to the electric charges. That is, the pixel array section 21 has a plurality of pixels that perform photoelectric conversion of incident light and output signals according to the electric charges obtained as a result.

[0017] Here, the row direction refers to the direction in which pixels in a pixel row are arranged (i.e., the horizontal direction), and the column direction refers to the direction in which pixels in a pixel column are arranged (i.e., the vertical direction). In other words, the row direction is the horizontal direction in the figure, and the column direction is the vertical direction in the figure.

[0018] In the pixel array unit 21, a pixel drive line 28 is wired in the row direction for each pixel row in the matrix-like pixel arrangement, and two vertical signal lines 29 are wired in the column direction for each pixel column. For example, the pixel drive line 28 transmits a drive signal for driving when reading out a signal from the pixel. Note that, although FIG. 1 shows the pixel drive line 28 as a single wire, the number of lines is not limited to one. One end of the pixel drive line 28 is connected to an output terminal of the vertical drive unit 22 corresponding to each row.

[0019] The vertical driving unit 22 is composed of a shift register, an address decoder, etc., and drives each pixel of the pixel array unit 21 simultaneously for all pixels or on a row-by-row basis, etc. In other words, the vertical driving unit 22, together with a system control unit 25 that controls the vertical driving unit 22, constitutes a driving unit that controls the operation of each pixel of the pixel array unit 21.

[0020] Signals output from each pixel in a pixel row in response to drive control by the vertical drive unit 22 are input to the column processing unit 23 through vertical signal lines 29. The column processing unit 23 performs predetermined signal processing on the signals output from each pixel through the vertical signal lines 29, and temporarily holds the pixel signals after signal processing.

[0021] Specifically, the column processing unit 23 performs signal processing such as noise removal processing and AD (Analog to Digital) conversion processing.

[0022] The horizontal driving unit 24 is composed of a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 23. Through selective scanning by the horizontal driving unit 24, pixel signals that have been signal-processed for each unit circuit in the column processing unit 23 are sequentially output.

[0023] The system control unit 25 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 22, the column processing unit 23, and the horizontal driving unit 24, etc. based on the various timing signals generated by the timing generator.

[0024] The signal processing unit 26 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing based on the pixel signals output from the column processing unit 23. The data storage unit 27 temporarily stores data necessary for the signal processing in the signal processing unit 26.

[0025] [2. Example of pixel configuration] Next, a description will be given of an example of the configuration of the pixels provided in the pixel array section 21. The pixels provided in the pixel array section 21 are configured, for example, as shown in FIG.

[0026] FIG. 2 shows a cross section of one pixel 51 provided in the pixel array section 21. This pixel 51 receives light, particularly infrared light, that is incident on the light receiving region 103 from the outside, performs photoelectric conversion, and outputs a signal corresponding to the resulting charge.

[0027] The pixel 51 has a sensor substrate 102 including, for example, a silicon substrate, that is, a P-type semiconductor substrate made of a P-type semiconductor region, and an on-chip lens 62 which is an example of an imaging optical system formed on the sensor substrate 102. The sensor substrate 102 is stacked on the circuit substrate 101.

[0028] Pixel transistors such as a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor, which will be described later, are provided on the circuit board 101. An example of the circuit configuration of the circuit board 101 will be described later with reference to FIG.

[0029] In the figure of the sensor substrate 102, an on-chip lens 62 is formed on the upper surface, i.e., the surface of the light receiving area 103 on which light from the outside is incident (hereinafter also referred to as the incident surface), which collects the light incident from the outside and causes it to enter the light receiving area 103.

[0030] Furthermore, in the pixel 51, an inter-pixel light shielding portion 63-1 and an inter-pixel light shielding portion 63-2 are formed at the end portions of the pixel 51 on the incident surface of the light receiving region 103 in order to prevent color mixing between adjacent pixels.

[0031] Furthermore, the sensor substrate 102 has an incident surface electrode 104 to which a voltage equal to or lower than the ground potential is applied, on the light incident surface of the light receiving region 103, thereby enabling an improvement in the charge collection efficiency. This point will be described later with reference to FIG.

[0032] An oxide film 64 and signal extracting portions 65-1 and 65-2 called Taps are formed on the inner surface of the light receiving region 103 opposite the incident surface, i.e., the inner surface of the lower surface in the figure.

[0033] In this example, an oxide film 64 is formed in the center of the pixel 51 near the surface opposite the incident surface of the light receiving region 103, and a signal extraction portion 65-1 and a signal extraction portion 65-2 are formed on both ends of the oxide film 64, respectively.

[0034] Here, the signal extracting section 65-1 has an N+ semiconductor region 71-1 and an N- semiconductor region 72-1 which are N-type semiconductor regions, and a P+ semiconductor region 73-1 and a P- semiconductor region 74-1 which are P-type semiconductor regions.

[0035] That is, N+ semiconductor region 71-1 is formed at a position adjacent to the right side of oxide film 64 in the figure, in the inner surface portion of the surface opposite the incident surface of light receiving region 103. In addition, N- semiconductor region 72-1 is formed on the upper side of N+ semiconductor region 71-1 in the figure so as to cover (surround) N+ semiconductor region 71-1.

[0036] Furthermore, a P+ semiconductor region 73-1 is formed at a position adjacent to the right side of the N+ semiconductor region 71-1 in the figure, in the inner surface portion of the surface opposite the incident surface of the light receiving region 103. Also, a P- semiconductor region 74-1 is formed on the upper side of the P+ semiconductor region 73-1 in the figure so as to cover (surround) the P+ semiconductor region 73-1.

[0037] Although not shown here, in more detail, when the light receiving region 103 is viewed from a direction perpendicular to the surface of the sensor substrate 102, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 are formed so as to surround the P+ semiconductor region 73-1 and the P- semiconductor region 74-1, respectively, with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 at the center.

[0038] Similarly, the signal extraction unit 65-2 has an N-semiconductor region 72-2 having a lower donor impurity concentration than the N+ semiconductor region 71-2 and the N- semiconductor region 72-2, which are N-type semiconductor regions, and a P-semiconductor region 74-2 having a lower acceptor impurity concentration than the P+ semiconductor region 73-2 and the P- semiconductor region 74-2, which are P-type semiconductor regions. Here, the donor impurity may be, for example, an element belonging to Group 5 of the periodic table of elements such as phosphorus (P) or arsenic (As) for Si. The acceptor impurity may be, for example, an element belonging to Group 3 of the periodic table of elements such as boron (B) for Si.

[0039] That is, N+ semiconductor region 71-2 is formed at a position adjacent to the left side of oxide film 64 in the figure, in the inner surface portion of the surface opposite the incident surface of light receiving region 103. In addition, N- semiconductor region 72-2 is formed on the upper side of N+ semiconductor region 71-2 in the figure so as to cover (surround) N+ semiconductor region 71-2.

[0040] Furthermore, a P+ semiconductor region 73-2 is formed at a position adjacent to the left side of the N+ semiconductor region 71-2 in the figure, in the inner surface portion of the surface opposite the incident surface of the light receiving region 103. Also, a P- semiconductor region 74-2 is formed on the upper side of the P+ semiconductor region 73-2 in the figure so as to cover (surround) the P+ semiconductor region 73-2.

[0041] Although not shown here, in more detail, when the light receiving region 103 is viewed from a direction perpendicular to the surface of the sensor substrate 102, the N+ semiconductor region 71-2 and the N- semiconductor region 72-2 are formed so as to surround the P+ semiconductor region 73-2 and the P- semiconductor region 74-2, respectively, with the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 at the center.

[0042] Hereinafter, when there is no need to particularly distinguish between the signal extracting unit 65-1 and the signal extracting unit 65-2, they will also be referred to simply as the signal extracting unit 65.

[0043] In the following, when there is no need to particularly distinguish between N+ semiconductor region 71-1 and N+ semiconductor region 71-2, they will be simply referred to as N+ semiconductor region 71, and when there is no need to particularly distinguish between N- semiconductor region 72-1 and N- semiconductor region 72-2, they will be simply referred to as N- semiconductor region 72.

[0044] Furthermore, hereinafter, when there is no need to particularly distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, they will be simply referred to as the P+ semiconductor region 73, and when there is no need to particularly distinguish between the P- semiconductor region 74-1 and the P- semiconductor region 74-2, they will be simply referred to as the P- semiconductor region 74.

[0045] In the light receiving region 103, between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1, an isolation portion 75-1 is formed of an oxide film or the like to isolate these regions. Similarly, between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2, an isolation portion 75-2 is formed of an oxide film or the like to isolate these regions. Hereinafter, when there is no need to particularly distinguish between the isolation portion 75-1 and the isolation portion 75-2, they will also be referred to simply as isolation portion 75.

[0046] The N+ semiconductor region 71 provided in the light-receiving region 103 functions as a detection unit for detecting the amount of light incident on the pixel 51 from the outside, that is, the amount of signal carriers generated by photoelectric conversion in the light-receiving region 103. The P+ semiconductor region 73 functions as an injection contact for injecting majority carrier current into the light-receiving region 103, that is, for applying a voltage directly to the light-receiving region 103 to generate an electric field within the light-receiving region 103.

[0047] In pixel 51, an FD (Floating Diffusion) section (hereinafter also referred to as FD section A), which is a floating diffusion region not shown, is directly connected to the N+ semiconductor region 71-1, and the FD section A is further connected to a vertical signal line 29 via an amplification transistor or the like not shown.

[0048] Similarly, another FD part (hereinafter also referred to as FD part B) different from the FD part A is directly connected to the N+ semiconductor region 71-2, and the FD part B is further connected to the vertical signal line 29 via an amplification transistor or the like (not shown). Here, the FD part A and the FD part B are connected to different vertical signal lines 29.

[0049] For example, when measuring the distance to an object using the indirect ToF method, infrared light is emitted toward the object from an imaging device provided with a solid-state imaging element 11. When the infrared light is reflected by the object and returns to the imaging device as reflected light, the light receiving region 103 of the solid-state imaging element 11 receives the incident reflected light (infrared light) and performs photoelectric conversion.

[0050] At this time, the vertical drive unit 22 drives the pixel 51, and distributes a signal corresponding to the charge obtained by photoelectric conversion to the FD unit A and the FD unit B. As described above, the pixel 51 may be driven not by the vertical drive unit 22 but by a separately provided drive unit or the horizontal drive unit 24 via the vertical signal line 29 or another vertically long control line.

[0051] For example, at a certain timing, the vertical drive unit 22 applies a voltage to two P+ semiconductor regions 73 via contacts etc. Specifically, for example, the vertical drive unit 22 applies a voltage of 1.5 V to the P+ semiconductor region 73-1 and a voltage of 0 V to the P+ semiconductor region 73-2.

[0052] Then, an electric field is generated between the two P+ semiconductor regions 73 in the light receiving region 103, and a current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the light receiving region 103 move toward the P+ semiconductor region 73-2, and electrons move toward the P+ semiconductor region 73-1.

[0053] Therefore, in this state, when infrared light (reflected light) from the outside enters the light-receiving region 103 through the on-chip lens 62 and the infrared light is photoelectrically converted in the light-receiving region 103 into pairs of electrons and holes, the resulting electrons are guided by the electric field between the P+ semiconductor regions 73 toward the P+ semiconductor region 73-1 and move into the N+ semiconductor region 71-1.

[0054] In this case, electrons generated by photoelectric conversion are used as signal carriers for detecting the amount of infrared light incident on pixel 51, that is, a signal corresponding to the amount of received infrared light.

[0055] As a result, an electric charge corresponding to the electrons that have moved into the N+ semiconductor region 71-1 is accumulated in the N+ semiconductor region 71-1, and this electric charge is detected in the column processing unit 23 via the FD section A, the amplifying transistor, the vertical signal line 29, etc.

[0056] That is, the charges stored in the N+ semiconductor region 71-1 are transferred to the FD unit A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charges transferred to the FD unit A is read out by the column processing unit 23 via the amplification transistor and the vertical signal line 29. Then, the read-out signal is subjected to processing such as AD conversion processing in the column processing unit 23, and the resulting pixel signal is supplied to the signal processing unit 26.

[0057] This pixel signal is a signal indicating the amount of charge corresponding to the electrons detected by the N+ semiconductor region 71-1, that is, the amount of charge accumulated in the FD portion A. In other words, the pixel signal can be said to be a signal indicating the amount of infrared light received by the pixel 51.

[0058] Furthermore, at the next timing, voltages are applied to the two P+ semiconductor regions 73 via contacts or the like by the vertical drive unit 22 so as to generate an electric field in the opposite direction to the electric field that has been generated in the light receiving region 103 up until that point. Specifically, for example, a voltage of 1.5 V is applied to the P+ semiconductor region 73-2, and a voltage of 0 V is applied to the P+ semiconductor region 73-1.

[0059] As a result, an electric field is generated between the two P+ semiconductor regions 73 in the light receiving region 103, and a current flows from the P+ semiconductor region 73-2 to the P+ semiconductor region 73-1.

[0060] In this state, when infrared light (reflected light) from the outside enters the light-receiving region 103 through the on-chip lens 62 and the infrared light is photoelectrically converted in the light-receiving region 103 into pairs of electrons and holes, the resulting electrons are guided toward the P+ semiconductor region 73-2 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-2.

[0061] As a result, an electric charge corresponding to the electrons that have moved into the N+ semiconductor region 71-2 is accumulated in the N+ semiconductor region 71-2, and this electric charge is detected in the column processing unit 23 via the FD section B, the amplifying transistor, the vertical signal line 29, etc.

[0062] That is, the charges stored in the N+ semiconductor region 71-2 are transferred to the FD unit B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charges transferred to the FD unit B is read out by the column processing unit 23 via the amplification transistor and the vertical signal line 29. Then, the read-out signal is subjected to processing such as AD conversion processing in the column processing unit 23, and the resulting pixel signal is supplied to the signal processing unit 26.

[0063] In this way, when pixel signals are obtained from photoelectric conversion of different periods at the same pixel 51, the signal processing unit 26 calculates distance information indicating the distance to the object based on those pixel signals and outputs it to a subsequent stage.

[0064] This method of distributing signal carriers to different N+ semiconductor regions 71 and calculating distance information based on signals corresponding to those signal carriers is called an indirect ToF method.

[0065] 2, that is, in a direction perpendicular to the surface of the light receiving region 103, the signal extraction portion 65 in the pixel 51 has a structure in which the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71, as shown in Fig. 3. In Fig. 3, the same reference numerals are used to designate parts corresponding to those in Fig. 2, and descriptions thereof will be omitted as appropriate.

[0066] 3, an oxide film 64 (not shown) is formed in the center of the pixel 51, and a signal extraction portion 65 is formed slightly toward the edge from the center of the pixel 51. In particular, two signal extraction portions 65 are formed in the pixel 51.

[0067] In each signal extraction portion 65, a rectangular P+ semiconductor region 73 is formed at the center thereof, and the P+ semiconductor region 73 is surrounded by a rectangular, more specifically, rectangular frame-shaped N+ semiconductor region 71 with the P+ semiconductor region 73 at the center.

[0068] Furthermore, in pixel 51, on-chip lens 62 is formed so that infrared light incident from the outside is focused on the center portion of pixel 51, i.e., the portion indicated by arrow A11. In other words, infrared light incident on on-chip lens 62 from the outside is focused by on-chip lens 62 at the position indicated by arrow A11, i.e., the upper position of oxide film 64 in FIG. 2.

[0069] In general pixels used in indirect ToF distance measurement, the signal extraction unit 65 and the pixel transistor are provided in the same layer of the sensor substrate 102. For this reason, as pixels become more miniaturized, the distance between the signal extraction unit 65 and the pixel transistor becomes shorter, causing current leakage from the signal extraction unit 65 to the pixel transistor side, reducing the charge collection efficiency.

[0070] Specifically, as described above, the pixel alternately applies a predetermined voltage to a pair of P+ semiconductor regions 73, sequentially passing a bidirectional current between P+ semiconductor region 73-1 and P+ semiconductor region 73-2, and distributes the charge obtained by photoelectric conversion to FD section A and FD section B.

[0071] However, as pixels become smaller and the distance between the signal extraction portion 65 and the pixel transistor becomes shorter, part of the current that should flow between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2 leaks into the Pwell region of the pixel transistor.

[0072] This not only increases the power consumption of the pixel, but also weakens the electric field strength generated in the light receiving region to guide the charge to the signal extraction section 65, resulting in a decrease in the charge captured by the N+ semiconductor region 71, thereby reducing the charge collection efficiency.

[0073] Therefore, in the pixel 51 according to the present disclosure, the pixel transistor is provided on the circuit board 101 , and the light receiving region 103 including the signal extraction portion 65 is provided on the sensor substrate 102 laminated on the circuit board 101 .

[0074] In this way, in pixel 51, the signal extraction section 65 and the pixel transistor are provided on different substrates that are stacked together, so even if pixel 51 is miniaturized in the planar direction, the distance between the signal extraction section 65 and the pixel transistor does not become shorter.

[0075] Therefore, when the pixel 51 is miniaturized, the power consumption can be reduced and the charge collection efficiency can be improved by preventing current leakage from the signal extraction section 65 to the pixel transistor.

[0076] [3. Example of pixel path configuration] Next, an example of a circuit configuration of a pixel according to the present disclosure will be described with reference to Fig. 4. Fig. 4 is a diagram showing an example of a circuit configuration of a pixel according to the present disclosure.

[0077] 4, in the pixel 51, a signal extraction section 65-1 including an N+ semiconductor region 71-1 and a P+ semiconductor region 73-1, etc. is provided on the sensor substrate 102. On the circuit substrate 101, a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplifier transistor 724A, and a selection transistor 725A are provided as pixel transistors corresponding to the signal extraction section 65-1.

[0078] In addition, in the pixel 51, a signal extraction unit 65-2 including an N+ semiconductor region 71-2 and a P+ semiconductor region 73-2, etc. is provided on the sensor substrate 102. On the circuit substrate 101, a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplification transistor 724B, and a selection transistor 725B are provided as pixel transistors corresponding to the signal extraction unit 65-2.

[0079] The vertical drive unit 22 applies a predetermined voltage MIX0 to the P+ semiconductor region 73-1, and applies a predetermined voltage MIX1 to the P+ semiconductor region 73-2. In the above example, one of the voltages MIX0 and MIX1 is 1.5 V, and the other is 0 V. The P+ semiconductor regions 73-1 and 73-2 are voltage application electrodes to which a predetermined voltage is applied.

[0080] The N+ semiconductor regions 71-1 and 71-2 are charge storage electrodes that detect and store charges generated by photoelectric conversion of light incident on the light receiving region 103.

[0081] When the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721A becomes conductive in response to this, thereby transferring the charge stored in the N+ semiconductor region 71-1 to the FD722A. When the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721B becomes conductive in response to this, thereby transferring the charge stored in the N+ semiconductor region 71-2 to the FD722B.

[0082] The FD722A temporarily holds the charge supplied from the N+ semiconductor region 71-1. The FD722B temporarily holds the charge supplied from the N+ semiconductor region 71-2. The FD722A corresponds to the FD unit A described with reference to FIG. 2, and the FD722B corresponds to the FD unit B.

[0083] The reset transistor 723A becomes conductive in response to the drive signal RST supplied to its gate electrode becoming active, thereby resetting the potential of the FD722A to a predetermined level (reset voltage VDD). The reset transistor 723B becomes conductive in response to the drive signal RST supplied to its gate electrode becoming active, thereby resetting the potential of the FD722B to a predetermined level (reset voltage VDD). When the reset transistors 723A and 723B are activated, the transfer transistors 721A and 721B are also activated at the same time.

[0084] The amplifier transistor 724A has a source electrode connected to the vertical signal line 29A via the selection transistor 725A, and thereby constitutes a source follower circuit together with a load MOS of a constant current source circuit unit 726A connected to one end of the vertical signal line 29A. The amplifier transistor 724B has a source electrode connected to the vertical signal line 29B via the selection transistor 725B, and thereby constitutes a source follower circuit together with a load MOS of a constant current source circuit unit 726B connected to one end of the vertical signal line 29B.

[0085] The selection transistor 725A is connected between the source electrode of the amplification transistor 724A and the vertical signal line 29A. When a selection signal SEL supplied to a gate electrode of the selection transistor 725A becomes active, the selection transistor 725A becomes conductive in response to the selection signal SEL, and outputs a pixel signal output from the amplification transistor 724A to the vertical signal line 29A.

[0086] The selection transistor 725B is connected between the source electrode of the amplification transistor 724B and the vertical signal line 29B. When a selection signal SEL supplied to a gate electrode of the selection transistor 725B becomes active, the selection transistor 725B becomes conductive in response to the selection signal SEL, and outputs a pixel signal output from the amplification transistor 724B to the vertical signal line 29B.

[0087] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled by the vertical drive unit 22, for example.

[0088] In this manner, in the pixel 51, the signal extraction section 65 is provided on the sensor substrate 102, and the pixel transistor is provided on the circuit substrate 101. Therefore, by preventing current leakage from the signal extraction section 65 to the pixel transistor, the charge collection efficiency can be improved.

[0089] In addition, the pixel 51 has a light receiving region 103 including a signal extraction portion 65 formed of a III-V group semiconductor such as GaAs or InGaAs. This allows the pixel 51 to have an improved quantum efficiency and improved sensitivity due to a direct transition band structure, and a thinner sensor due to a thinner substrate.

[0090] Furthermore, the light receiving region 103 including the signal extraction portion 65 may be formed of, for example, Ge, GaSb, etc. In this case, the pixel 51 can improve the electron collection efficiency due to high electron mobility and reduce power consumption due to low hole mobility.

[0091] [4. Connection between the circuit board and the sensor board] Next, a connection mode between the circuit board and the sensor board will be described with reference to Fig. 5. Fig. 5 is a diagram showing a connection mode between the circuit board and the sensor board according to the present disclosure.

[0092] 5, a Cu-Cu joint MIX that connects the wiring on the sensor substrate 102 side that applies a predetermined voltage to the P+ semiconductor region 73 of the light receiving region 103 to the wiring on the circuit substrate 101 side is indicated by a white circle. Also, a Cu-Cu joint DET that connects the wiring on the sensor substrate 102 side that is connected to the N+ semiconductor region 71 of the light receiving region 103 to the wiring on the circuit substrate 101 side is indicated by a black circle.

[0093] As shown in FIG. 5, the pixel 51 has two Cu-Cu joints MIX provided outside the pixel array 21. Also, two Cu-Cu joints DET are provided for each pixel 51. This makes it easier to miniaturize the pixel 51 by reducing the number of Cu-Cu joints MIX compared to when a Cu-Cu joint MIX is provided for each pixel. Note that the Cu-Cu joints MIX may be formed by a TCV (Through Chip Via). Also, the Cu-Cu joints MIX, DET may be formed by a bump.

[0094] [5. Incident surface electrode and pixel separation area] Next, the incident surface electrode and pixel separation region according to the present disclosure will be described with reference to Fig. 6. Fig. 6 is an explanatory diagram of the incident surface electrode and pixel separation region according to the present disclosure. As shown in Fig. 6, in pixel 51, for example, when a current flows from signal extraction section 65-1 to signal extraction section 65-2 in light receiving region 103, the photoelectrically converted charge is induced from signal extraction section 65-2 to signal extraction section 65-1 as shown by the arrow by the electric field generated by the current.

[0095] Here, as pixel 51 becomes finer in the planar direction of the light incident surface, the distance between signal extraction section 65-1 and signal extraction section 65-2 is reduced, but the length of light receiving region 103 in the thickness (depth) direction is not reduced.

[0096] For this reason, when the pixel 51 is miniaturized, even if a current flows from the signal extraction section 65-1 to the signal extraction section 65-2, the electric field cannot be sufficiently spread to the vicinity of the light incident surface in the light receiving region 103. As a result, the pixel 51 cannot efficiently guide the charge photoelectrically converted in the vicinity of the light incident surface in the light receiving region 103 to the signal extraction section 65-2, and the charge collection efficiency decreases.

[0097] Therefore, in the pixel 51, an incident surface electrode 104 is provided on the light incident surface in the light receiving region 103. The incident surface electrode is connected to, for example, a ground wiring or a negative voltage generating circuit provided on the circuit board 101, and 0 V or a negative voltage is applied to it.

[0098] For this reason, when the pixel 51 passes a current from the signal extraction portion 65-1 to the signal extraction portion 65-2, a current also passes from the signal extraction portion 65-1 to the incident surface electrode 104. As a result, the pixel 51 can efficiently induce charges photoelectrically converted near the light incident surface to the signal extraction portion 65-2, as indicated by the arrow, by an electric field generated by the current flowing from the signal extraction portion 65-1 to the incident surface electrode 104.

[0099] In this way, pixel 51 has incident surface electrode 104 to which a voltage equal to or lower than the ground potential is applied to the light incident surface, so that even when miniaturized, the charge collection efficiency can be improved by guiding the charge photoelectrically converted near the light incident surface to signal extraction section 65-1.

[0100] Since the incident surface electrode 104 needs to transmit incident light, a transparent electrode is used. For example, the incident surface electrode 104 is a hole accumulation layer formed on the light incident surface of the light receiving region 103 by a negative fixed charge film laminated on the light incident surface.

[0101] The incident surface electrode 104 may also be a P-type conductive layer doped with P-type impurities on the light incident surface of the light-receiving region 103. The incident surface electrode 104 may also be an inorganic electrode film such as an ITO (Indium Tin Oxide) film laminated on the light incident surface of the light-receiving region 103. The incident surface electrode 104 may also be a metal film such as a W film having a thickness (for example, 50 nm or less) and having light transparency laminated on the light incident surface of the light-receiving region 103.

[0102] Regardless of which of the above-mentioned incident surface electrodes 104 are provided in the pixel 51, the electric field generated by the current flowing from the signal extraction section 65 to the incident surface electrode 104 can efficiently induce the charge photoelectrically converted near the light incident surface to the signal extraction section 65.

[0103] Moreover, the pixel 51 includes a pixel isolation region 105 between the light receiving region 103 and the light receiving region 103 of an adjacent pixel 51, which electrically isolates the adjacent light receiving regions. The pixel isolation region 105 is, for example, a deep trench isolation (DTI) formed between each pixel 51.

[0104] The pixel isolation region 105 reaches halfway from the light incident surface of the light receiving region 103 to a surface opposite to the light incident surface of the light receiving region 103. The pixel isolation region 105 is provided so as to divide the pixel array 21, in which a plurality of light receiving regions 103 provided for each pixel 51 are arranged in a matrix, into light receiving regions 103.

[0105] As a result, each pixel 51 can confine photoelectrically converted charges within the light receiving region 103 by the pixel isolation region 105, thereby suppressing electrical color mixing caused by charge leakage to adjacent pixels 51. Next, a configuration example of such a pixel isolation region 103 will be described.

[0106] [6. Example of pixel isolation region configuration] 7A to 7C are diagrams showing configuration examples of pixel isolation regions according to the present disclosure. As shown in FIG. 7A, the pixel isolation region 105A is made of an insulator 106 such as SiO2. As a result, the pixels 51 can suppress electrical color mixing between the pixels 51 by the pixel isolation region 105A, as described above. Furthermore, the pixel isolation region 105 can reflect light incident on the light receiving region 103, thereby suppressing optical color mixing caused by the incident light leaking to an adjacent pixel 51.

[0107] 7B, pixel isolation region 105B may be made of metal 108 having insulating film 107 such as SiO2 provided on its surface. According to pixel isolation region 105B, metal 108 functions as a light shielding film, so that optical color mixing caused by incident light leaking to adjacent pixels 51 can be suppressed.

[0108] 7C, the pixel isolation region 105C may be made of an insulator 106 such as SiO2 having a negative fixed charge film 109 on its surface. According to the pixel isolation region 105C, the negative high and low charge film 109 can maintain the electric field distribution in the light receiving region 103, while suppressing dark current and white spots generated on the surface of the pixel isolation region 105C.

[0109] 7A to 7C can be placed in an electrically floating state. In this case, the current flowing from the signal extraction section 65 to the incident surface electrode 104 flows more uniformly in the light receiving region 103, so that the necessary electric field can be formed up to the vicinity of the incident surface electrode 104 even if the pixel 51 is miniaturized.

[0110] Furthermore, a voltage equal to or lower than the ground potential may be applied to the metal 108 in the pixel isolation region 105B and the negative fixed charge film 109 in the pixel isolation region 105C. In this case, in the pixel 51, Si in the light receiving region 103 near the pixel isolation regions 105B and 105C is pinned to P type, so that dark current and white spots generated on the surfaces of the pixel isolation regions 105B and 105C can be suppressed.

[0111] As described above, pixel 51 can improve the resolution of a luminance image and a distance image because pixel isolation regions 105A, 105B, and 105C suppress optical color mixing and electrical color mixing, and can reduce noise caused by dark current, etc. Furthermore, when background light is strong, pixel 51 can also reduce sensitivity by bringing the voltage applied to incident surface electrode 104 closer to 0 V.

[0112] [7. Modifications of pixel isolation region] Next, modified examples and arrangement examples of the pixel isolation region will be described with reference to Fig. 8 to Fig. 10. Fig. 8 is an explanatory diagram of a pixel isolation region according to Modification 1 of the present disclosure. Fig. 9 is an explanatory diagram of a pixel isolation region according to Modification 2 of the present disclosure. Fig. 10 is a diagram showing an arrangement example of the pixel isolation region according to the present disclosure.

[0113] 8, the pixel 51A according to the first modification includes a pixel isolation region 110 that extends from the light incident surface of the light receiving region 103 to a surface of the sensor substrate 102 that faces the light incident surface. The pixel isolation region 110 is made of an insulator such as SiO2. The pixel isolation region 110 is provided so as to penetrate the front and back of the sensor substrate 102, and therefore optical color mixing and electrical color mixing occurring between adjacent pixels 51A can be more reliably suppressed.

[0114] 8. As shown in FIG. 9, a pixel isolation region 110A included in a pixel 51B according to the second modification is provided so as to penetrate the sensor substrate 102 from the front to the back, but has a different configuration from the pixel isolation region 110 shown in FIG.

[0115] The pixel isolation region 110A is made of a metal 108 having an insulating film 107 such as SiO2 provided on its surface. The pixel isolation region 110A is provided at the corners of a plurality of light receiving regions 103 each having a rectangular shape in plan view and arranged in a matrix, as shown in Fig. 10, for example, and connects the incident surface electrode 104 to a ground wiring or a negative voltage generating circuit.

[0116] In the pixel isolation region 110A, for example, a ground terminal of the sensor substrate 102 and each incident surface electrode 104 can be connected by low resistance wiring on the surface side facing the light incident surface in the light receiving region 103, or by low resistance wiring on the circuit substrate 101. This suppresses voltage drop in the incident surface electrode 104 due to wiring resistance.

[0117] Furthermore, when the pixel isolation region 110A is provided at a corner of the light receiving region 103 which is rectangular in plan view, for example, the pixel isolation region 105 shown in FIG. 6 is provided on the outer periphery of the light receiving region 103 other than the corners in plan view.

[0118] Therefore, most of the outer periphery of each light receiving region 103 in a plan view, excluding the corners, is surrounded by a pixel isolation region 105 that extends from the light incident surface of the light receiving region 103 to the middle in the depth direction.

[0119] As a result, most of the current flowing from the signal extraction section 65 to the incident surface electrode 104 flows uniformly within the light receiving area 103, so that the necessary electric field can be formed up to the vicinity of the incident surface electrode 104 even if the pixels 51 are miniaturized.

[0120] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0121] The present technology can also be configured as follows. (1) a light receiving region for photoelectrically converting incident light into a signal charge; a pair of voltage application electrodes to which a voltage is alternately applied to generate an electric field in the light receiving region for time-divisionally distributing the signal charges to a pair of charge storage electrodes; an incident surface electrode provided on a light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; a sensor substrate on which the a pixel transistor that is provided on a surface of the sensor substrate opposite to the light incidence surface and processes the signal charge stored in the charge storage electrode; A circuit board on which the A light receiving element having the same. (2) The incident surface electrode is A hole accumulation layer is formed on the light incident surface by a negative fixed charge film laminated on the light incident surface. The light receiving element according to (1) above. (3) The incident surface electrode is The light incident surface is a P-type conductive layer doped with P-type impurities. The light receiving element according to (1) above. (4) The incident surface electrode is An inorganic electrode film is laminated on the light incident surface. The light receiving element according to (1) above. (5) The incident surface electrode is A metal film having a thickness and transparency is laminated on the light incident surface. A photodetector as described in (1). (6) A pixel isolation region is provided between the light receiving regions arranged in a matrix, and electrically isolates the adjacent light receiving regions. The light-receiving element according to any one of (1) to (6), comprising: (7) The pixel isolation region is The light receiving region extends from the light incident surface to a midway point toward a surface facing the light incident surface. The light receiving element according to (6) above. (8) The pixel isolation region is A pixel array in which a plurality of the light receiving regions are arranged in a matrix is ​​partitioned into individual light receiving regions, which are electrically floating. The light receiving element according to (7) above. (9) The pixel isolation region is The light reaches from the incident surface to a surface of the sensor substrate opposite to the incident surface. The light receiving element according to (6) above. (10) The pixel isolation region is A plurality of light receiving regions each having a rectangular shape in plan view and arranged in a matrix are provided at the corners of the light receiving region, and the light receiving region connects the incident surface electrode to a ground wiring or a negative voltage generating circuit. The light receiving element according to (9) above. (11) The pixel isolation region is Consists of an insulator The light-receiving element according to any one of (6) to (10) above. (12) The pixel isolation region is It is made of a metal with an insulating film on its surface. The light-receiving element according to any one of (6) to (10) above. (13) The pixel isolation region is It is composed of an insulator with a negative fixed charge film on its surface. The light-receiving element according to any one of (6) to (10) above. (14) a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix; a pair of voltage application electrodes to which a voltage is alternately applied for each of the light receiving regions to generate an electric field in the light receiving region for time-divisionally distributing the signal charges to a pair of charge storage electrodes; an incident surface electrode provided on a light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; a sensor substrate on which the a pixel transistor that is provided on a surface of the sensor substrate opposite to the light incidence surface and processes the signal charge stored in the charge storage electrode; A circuit board on which the An imaging element having (15) An imaging optical system; a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix; a pair of voltage application electrodes to which a voltage is alternately applied for each of the light receiving regions to generate an electric field in the light receiving region for time-divisionally distributing the signal charges to a pair of charge storage electrodes; an incident surface electrode provided on a light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; a sensor substrate on which the a pixel transistor that is provided on a surface of the sensor substrate opposite to the light incidence surface and processes the signal charge stored in the charge storage electrode; A circuit board on which the An imaging device having the above configuration. [Explanation of symbols]

[0122] 11 solid-state imaging element, 21 pixel array section, 22 vertical drive section, 51 pixel, 61 substrate, 62 on-chip lens, 71-1, 71-2, 71 N+ semiconductor region, 73-1, 73-2, 73 P+ semiconductor region, 441-1, 441-2, 441 separation region, 471-1, 471-2, 471 separation region, 631 reflective member, 721 transfer transistor, 722 FD, 723 reset transistor, 724 amplification transistor, 725 selection transistor

Claims

1. a light receiving region for photoelectrically converting incident light into a signal charge; a pair of voltage application electrodes to which a voltage is alternately applied to generate an electric field in the light receiving region for time-divisionally distributing the signal charges to a pair of charge storage electrodes; an incident surface electrode provided on a light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; a sensor substrate on which the a pixel transistor that is provided on a surface of the sensor substrate opposite to the light incidence surface and processes the signal charge stored in the charge storage electrode; a circuit board on which the a pixel isolation region provided between the light receiving regions arranged in a matrix and electrically isolating adjacent light receiving regions; having the pixel separation regions provided at corners of the light receiving regions each having a rectangular shape in a plan view and arranged in a matrix form extend from the light incident surface to a surface of the sensor substrate opposite to the light incident surface, and are connected to the light incident surface electrode and a ground wiring or a negative voltage generating circuit; The pixel separation region provided on the outer periphery of the light receiving region other than the corners extends from the light incident surface to a midway point toward a surface of the light receiving region opposite to the light incident surface. Photodetector.

2. The incident surface electrode is A hole accumulation layer is formed on the light incident surface by a negative fixed charge film laminated on the light incident surface. The light receiving element according to claim 1 .

3. The incident surface electrode is The light incident surface is a P-type conductive layer doped with P-type impurities. The light receiving element according to claim 1 .

4. The incident surface electrode is An inorganic electrode film is laminated on the light incident surface. The light receiving element according to claim 1 .

5. The incident surface electrode is A metal film having a thickness and transparency is laminated on the light incident surface. The light receiving element according to claim 1 .

6. The pixel isolation region provided on the outer periphery other than the corner portions is A pixel array in which a plurality of the light receiving regions are arranged in a matrix is ​​partitioned into individual light receiving regions, which are electrically floating. The light receiving element according to claim 1 .

7. The pixel isolation region provided on the outer periphery other than the corner portions is Consists of an insulator The light receiving element according to claim 1 .

8. The pixel isolation region provided at the corner portion is It is made of a metal with an insulating film on its surface. The light receiving element according to claim 1 .

9. a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix; a pair of voltage application electrodes to which a voltage is alternately applied for each of the light receiving regions to generate an electric field in the light receiving region for time-divisionally distributing the signal charges to a pair of charge storage electrodes; an incident surface electrode provided on a light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; a sensor substrate on which the a pixel transistor that is provided on a surface of the sensor substrate opposite to the light incidence surface and processes the signal charge stored in the charge storage electrode; a circuit board on which the a pixel isolation region provided between the light receiving regions arranged in a matrix and electrically isolating adjacent light receiving regions; having the pixel separation regions provided at corners of the light receiving regions each having a rectangular shape in a plan view and arranged in a matrix form extend from the light incident surface to a surface of the sensor substrate opposite to the light incident surface, and are connected to the light incident surface electrode and a ground wiring or a negative voltage generating circuit; The pixel separation region provided on the outer periphery of the light receiving region other than the corners extends from the light incident surface to a midway point toward a surface of the light receiving region opposite to the light incident surface. Image sensor.

10. An imaging optical system; a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix; a pair of voltage application electrodes to which a voltage is alternately applied for each of the light receiving regions to generate an electric field in the light receiving region for time-divisionally distributing the signal charges to a pair of charge storage electrodes; an incident surface electrode provided on a light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; a sensor substrate on which the a pixel transistor that is provided on a surface of the sensor substrate opposite to the light incidence surface and processes the signal charge stored in the charge storage electrode; a circuit board on which the a pixel isolation region provided between the light receiving regions arranged in a matrix and electrically isolating adjacent light receiving regions; having the pixel separation regions provided at corners of the light receiving regions each having a rectangular shape in a plan view and arranged in a matrix form extend from the light incident surface to a surface of the sensor substrate opposite to the light incident surface, and are connected to the light incident surface electrode and a ground wiring or a negative voltage generating circuit; The pixel separation region provided on the outer periphery of the light receiving region other than the corners extends from the light incident surface to a midway point toward a surface of the light receiving region opposite to the light incident surface. Imaging device.

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