Imaging device

Abstract

The present disclosure relates to an imaging device provided with: a plurality of pixel circuits each of which generates a pixel signal including a pixel voltage corresponding to an amount of received light, and performs AD conversion by comparing the pixel signal with a reference signal; and a reference signal generating unit comprising a signal generating circuit for generating a voltage signal having a ramp waveform, and a voltage follower circuit for generating a reference signal by performing a voltage follower operation on the basis of the voltage signal, and supplying the reference signal to the plurality of pixel circuits.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device that captures an image of a subject. [Background technology]

[0002] In general, in an imaging device, pixels including photodiodes are arranged in a matrix, and each pixel generates a pixel voltage according to the amount of light received. Then, for example, an AD conversion circuit (Analog to Digital Converter) converts the pixel voltage (analog signal) into a digital signal. For example, Patent Document 1 discloses an imaging device that performs AD conversion by comparing a signal including the pixel voltage with a reference signal having a ramp waveform. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-278135 A Summary of the Invention

[0004] Incidentally, in imaging devices, it is desired that the image quality of the captured image is high, and further improvement in image quality is expected.

[0005] It is desirable to provide an imaging device that can improve the quality of captured images.

[0006] An imaging device according to an embodiment of the present disclosure includes a plurality of pixel circuits and a reference signal generating unit. Each of the plurality of pixel circuits is configured to generate a pixel signal including a pixel voltage corresponding to an amount of received light, and to perform AD conversion by comparing the pixel signal with a reference signal. The reference signal generating unit includes a signal generating circuit that generates a voltage signal having a ramp waveform, and a voltage follower circuit that generates a reference signal by performing a voltage follower operation based on the voltage signal and supplies the reference signal to the plurality of pixel circuits. The voltage follower circuit has an amplifier having a positive input terminal to which a voltage signal is supplied, a negative input terminal, an output terminal connected to the negative input terminal and outputting a reference signal, and an output circuit connected to the output terminal. The output circuit has a first transistor of a first conductivity type having a source connected to a first power supply node, a drain connected to the output terminal, and a gate, and a second transistor of a second conductivity type having a source connected to a second power supply node, a drain connected to the output terminal, and a gate. The amplifier includes a first differential transistor pair connected to the positive input terminal and the negative input terminal, generating a differential current including a first current and a second current; a third transistor of a first conductivity type provided in a first current path connecting a first power supply node and a second power supply node, the third transistor having a source connected to the first power supply node, a gate, and a drain; a fourth transistor of a second conductivity type provided in the first current path, the fourth transistor having a source connected to the second power supply node, a gate, and a drain; a fifth transistor of the first conductivity type provided between the third transistor and the fourth transistor in the first current path, the fifth transistor having a source connected to a first node on the first current path, a drain connected to a second node on the first current path, and a gate supplied with a first bias voltage; and a sixth transistor of the second conductivity type provided between the third transistor and the fourth transistor in the first current path, the sixth transistor having a drain connected to the first node, a source connected to the second node, and a gate supplied with a second bias voltage. The amplifier controls a current flowing between a first node and a second node in the first current path based on the first current and the second current. A gate of the first transistor is connected to the first node. A gate of the second transistor is connected to the second node.

[0007] In an imaging device according to an embodiment of the present disclosure, a voltage signal having a ramp waveform is generated in each of the pixel circuits, and a reference signal is generated by performing a voltage follower operation based on the voltage signal. Then, a pixel signal including a pixel voltage according to the amount of received light is generated in each of the pixel circuits, and AD conversion is performed by comparing the pixel signal with the reference signal. The generated reference signal is supplied to the pixel circuits. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating an example configuration of an imaging device according to an embodiment of the present disclosure. [Diagram 2] 2 is a schematic diagram illustrating an example of an implementation of the imaging device illustrated in FIG. 1. [Diagram 3] 2 is a circuit diagram illustrating an example of the configuration of a pixel circuit included in the pixel illustrated in FIG. 1. [Figure 4] 2 is a circuit diagram illustrating an example of the configuration of a reference signal generating unit illustrated in FIG. 1. [Diagram 5] 5 is a block diagram illustrating an example of the configuration of the amplifier illustrated in FIG. 4. [Figure 6] 5 is a circuit diagram illustrating an example of the configuration of the amplifier illustrated in FIG. 4. [Figure 7] 2 is a timing waveform diagram illustrating an example of an operation of the imaging device shown in FIG. [Figure 8] 7 is an explanatory diagram illustrating an example of an operation of the amplifier illustrated in FIG. 6. [Figure 9] 5 is an explanatory diagram illustrating an example of a characteristic of the voltage follower circuit shown in FIG. [Figure 10] FIG. 11 is a circuit diagram illustrating a configuration example of a reference signal generating unit according to a comparative example. [Figure 11] FIG. 13 is a circuit diagram illustrating a configuration example of an amplifier according to a modified example. [Figure 12] FIG. 13 is a circuit diagram illustrating an example of a configuration of an amplifier according to another modified example. [Figure 13] FIG. 13 is a circuit diagram illustrating an example of a configuration of an amplifier according to another modified example. [Figure 14]FIG. 1 is an explanatory diagram illustrating an example of use of an imaging device. [Figure 15] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 16] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. Embodiment 2. Examples of use of imaging devices 3. Application examples for mobile objects

[0010] <Embodiment Mode> [Configuration example] 1 shows an example of the configuration of an imaging device (imaging device 1) according to an embodiment. The imaging device 1 includes a pixel array 11, a reference signal generator 12, a pixel driver 13, a vertical driver 14, a signal processor 15, and a timing generator 16.

[0011] The pixel array 11 has a plurality of pixels P arranged in a matrix. Each pixel P has a photodiode PD, generates a pixel signal SIG including a pixel voltage Vpix according to the amount of received light, and performs AD conversion based on the pixel signal SIG. The pixels P are arranged across two semiconductor substrates.

[0012] 2 shows an example of an implementation of the imaging device 1. In this example, the imaging device 1 is formed on two semiconductor substrates 101 and 102. The semiconductor substrate 101 is disposed on the imaging surface side of the imaging device 1, and the semiconductor substrate 102 is disposed on the opposite side of the imaging surface side of the imaging device 1. The semiconductor substrates 101 and 102 are overlapped with each other. The wiring of the semiconductor substrate 101 and the wiring of the semiconductor substrate 102 are connected by wiring 103. For the wiring 103, for example, a metallic bond such as Cu-Cu can be used. The pixel P is disposed across these two semiconductor substrates 101 and 102.

[0013] 3 shows an example of the configuration of a pixel P. The pixel P has a pixel circuit 20. The pixel circuit 20 has a light receiving circuit 21, a comparison circuit 22, and a latch 23.

[0014] The light receiving circuit 21 is configured to generate a pixel voltage Vpix according to the amount of received light. The light receiving circuit 21 is disposed on a semiconductor substrate 101. The light receiving circuit 21 has a photodiode PD, a discharge transistor MN1, a transfer transistor MN2, a floating diffusion FD, and a reset transistor MN3. The discharge transistor MN1, the transfer transistor MN2, and the reset transistor MN3 are N-type MOS (Metal Oxide Semiconductor) transistors.

[0015] The photodiode PD is a photoelectric conversion element that generates and accumulates an electric charge in an amount corresponding to the amount of light received. The anode of the photodiode PD is grounded, and the cathode is connected to the source of the drain transistor MN1 and the source of the transfer transistor MN2.

[0016] The discharge transistor MN1 has a gate supplied with a control signal OFG from the pixel drive unit 13 (FIG. 1), a drain supplied with a voltage VOFG, and a source connected to the cathode of the photodiode PD and the source of the transfer transistor MN2.

[0017] The gate of the transfer transistor MN2 is supplied with a control signal TX from the pixel driving unit 13 (Figure 1), the source is connected to the cathode of the photodiode PD and the source of the discharge transistor MN1, and the drain is connected to the floating diffusion FD, the source of the reset transistor MN3, and the gate of a transistor MN4 (described later) in the comparison circuit 22.

[0018] The floating diffusion FD is configured to accumulate the charge transferred from the photodiode PD. The floating diffusion FD is configured, for example, using a diffusion layer formed on the surface of the semiconductor substrate 101. In Fig. 3, the floating diffusion FD is shown using a symbol of a capacitive element.

[0019] A control signal RST is supplied to the gate of the reset transistor MN3, the drain is connected to the drain of a transistor MN4 (described later) of the comparison circuit 22, and the source is connected to the floating diffusion FD, the drain of the transfer transistor MN2, and the gate of a transistor MN4 (described later) of the comparison circuit 22.

[0020] With this configuration, in the light receiving circuit 21, the discharge transistor MN1 is turned on based on the control signal OFG, and the charge accumulated in the photodiode PD is discharged. Then, the discharge transistor MN1 is turned off, and an exposure period is started, and an amount of charge according to the amount of received light is accumulated in the photodiode PD. Then, after the exposure period is ended, the light receiving circuit 21 supplies the pixel signal SIG including the reset voltage Vreset and the pixel voltage Vpix to the comparison circuit 22. Specifically, as described later, in a P-phase (Pre-charge phase) period TP after the voltage of the floating diffusion FD is reset, the light receiving circuit 21 supplies the voltage of the floating diffusion FD at that time as the reset voltage Vreset to the comparison circuit 22. Also, in a D-phase (Data phase) period TD after the charge is transferred from the photodiode PD to the floating diffusion FD, the light receiving circuit 21 supplies the voltage of the floating diffusion FD at that time as the pixel voltage Vpix to the comparison circuit 22.

[0021] The comparison circuit 22 is configured to generate a signal CMP by comparing a reference signal REF with the pixel signal SIG. The comparison circuit 22 sets the signal CMP to a high level when the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG, and sets the signal CMP to a low level when the voltage of the reference signal REF is lower than the voltage of the pixel signal SIG. The comparison circuit 22 has transistors MN4 to MN6 and transistors MP1 and MP2. The transistors MN4 to MN6 are N-type MOS transistors, and the transistors MP1 and MP2 are P-type MOS transistors. The comparison circuit 22 is disposed across two semiconductor substrates 101 and 102. Specifically, the transistors MN4 to MN6 are disposed on the semiconductor substrate 101, and the transistors MP1 and MP2 are disposed on the semiconductor substrate 102.

[0022] The pixel signal SIG is supplied to the gate of the transistor MN4, the drain of which is connected to the drain of the reset transistor MN3 in the light receiving circuit 21, and is also connected to the drain of the transistor MP1 and the input terminal of the amplifier AMP via the wiring 103 between the semiconductor substrates 101 and 102, and the source of which is connected to the source of the transistor MN5 and the drain of the transistor MN6. The reference signal REF is supplied to the gate of the transistor MN5 from the reference signal generating unit 12 via the wiring 103 between the semiconductor substrates 101 and 102, the drain of which is connected to the drain of the transistor MP2 and the gates of the transistors MP1 and MP2 via the wiring 103 between the semiconductor substrates 101 and 102, and the source of which is connected to the source of the transistor MN4 and the drain of the transistor MN6. The reference signal REF is a signal having a so-called ramp waveform whose voltage level gradually changes over time in the P-phase period TP and the D-phase period TD, as will be described in detail later. The bias voltage Vb is supplied to the gate of the transistor MN6, the drain of which is connected to the sources of the transistors MN4 and MN5, and the source of which is grounded. The transistors MN4 and MN5 form a differential pair, and the transistor MN6 forms a constant current source.

[0023] The gate of transistor MP1 is connected to the gate and drain of transistor MP2 and is also connected to the drain of transistor MN5 via wiring 103 between semiconductor substrates 101 and 102, the source is supplied with power supply voltage VDD, and the drain is connected to the input terminal of amplifier AMP and is also connected to the drain of transistor MN4 and the drain of reset transistor MN3 in light receiving circuit 21 via wiring 103 between semiconductor substrates 101 and 102. The gate of transistor MP2 is connected to the gate of transistor MP1 and the drain of transistor MP2 and is also connected to the drain of transistor MN5 via wiring 103 between semiconductor substrates 101 and 102, the source is supplied with power supply voltage VDD, and the drain is connected to the gates of transistors MP1 and MP2 and is also connected to the drain of transistor MN5 via wiring 103 between semiconductor substrates 101 and 102. Transistors MP1 and MP2 constitute active loads for transistors MN4 and MN5.

[0024] An input terminal of the amplifier AMP is connected to the drain of the transistor MP1 and is also connected to the drain of the reset transistor MN3 and the drain of the reset transistor MN3 in the light receiving circuit 21 via a wiring 103 between the semiconductor substrates 101 and 102, and an output terminal is connected to the latch 23. The comparator circuit 22 outputs a signal CMP from the output terminal of the amplifier AMP.

[0025] The latch 23 is configured to latch the time code CODE, which changes with time and is supplied from the pixel driving unit 13 (FIG. 1), based on the signal CMP supplied from the comparison circuit 22. The time code CODE can be, for example, a gray code. As described below, the latch 23 latches the time code CODE at the transition timing of the signal CMP in the P phase period TP to acquire the time (code value CODE1) from the start of the P phase period TP to the transition of the signal CMP. Also, the latch 23 latches the time code CODE at the transition timing of the signal CMP in the D phase period TD to acquire the time (code value CODE2) from the start of the D phase period TD to the transition of the signal CMP. The difference between these two code values ​​(CODE2-CODE1) corresponds to a pixel value according to the amount of received light. The latch 23 supplies the two code values ​​CODE1 and CODE2 to the signal processing unit 15 based on a control signal supplied from the vertical driving unit 14.

[0026] In this way, the pixel circuit 20 generates a pixel signal SIG including a pixel voltage Vpix according to the amount of received light, and performs AD conversion based on this pixel signal SIG to generate code values ​​CODE1 and CODE2.

[0027] The reference signal generating unit 12 is configured to generate a reference signal REF. The reference signal REF has a so-called ramp waveform in which the voltage level gradually changes over time during a P-phase period TP and a D-phase period TD. The reference signal generating unit 12 supplies the generated reference signal REF to a plurality of pixel circuits 20 in the pixel array 11 (FIG. 1). The reference signal generating unit 12 is disposed on a semiconductor substrate 102 as shown in FIG. 3.

[0028] The pixel driving unit 13 (FIG. 1) is configured to control the operation of a plurality of pixel circuits 20 in the pixel array 11. Specifically, the pixel driving unit 13 generates control signals OFG, TX, and RST and supplies these control signals OFG, TX, and RST to a light receiving circuit 21, and also generates a time code CODE and supplies this time code CODE to a latch 23, thereby controlling the operation of the pixel circuits 20. The pixel driving unit 13 is disposed on, for example, a semiconductor substrate 102.

[0029] The vertical driving unit 14 is configured to supply the code values ​​CODE1 and CODE2 generated by each of the multiple pixel circuits 20 in the pixel array 11 to the signal processing unit 15 in a predetermined order. The vertical driving unit 14 is disposed on the semiconductor substrate 102, for example.

[0030] The signal processing unit 15 is configured to generate an image signal Spic by performing a predetermined image processing based on the code values ​​CODE1 and CODE2 generated by each of the pixel circuits 20. The predetermined image processing includes, for example, a process of generating pixel values ​​based on the two code values ​​CODE1 and CODE2 generated by the pixel circuits 20 using the principle of correlated double sampling (CDS) and a black level correction process of correcting a black level. The signal processing unit 15 is disposed on, for example, the semiconductor substrate 102.

[0031] The timing generation unit 16 is configured to generate various timing signals and supply the generated various timing signals to the reference signal generation unit 12, the pixel drive unit 13, the vertical drive unit 14, and the signal processing unit 15, thereby controlling the operation of the imaging device 1. The timing generation unit 16 is disposed on the semiconductor substrate 102, for example.

[0032] (Reference signal generation unit 12) Fig. 4 shows an example of the configuration of the reference signal generation unit 12. Fig. 4 also shows a plurality of pixel circuits 20 to which a reference signal REF generated by the reference signal generation unit 12 is supplied. The reference signal generation unit 12 has a signal generation circuit 31 and a voltage follower circuit 34.

[0033] The signal generating circuit 31 is configured to generate a signal REF0 having a ramp waveform similar to that of the reference signal REF. The signal generating circuit 31 has a current source 32 and a resistive element 33. The current source 32 is a variable current source capable of changing the current it supplies, with one end being supplied with a power supply voltage VDD and the other end being connected to one end of the resistive element 33 and an input terminal of a voltage follower circuit 34. One end of the resistive element 33 is connected to the other end of the current source 32 and an input terminal of the voltage follower circuit 34, and the other end is grounded. With this configuration, the signal generating circuit 31 is configured to generate a signal REF0 having a ramp waveform by switching the current value of the current supplied by the current source 32.

[0034] The voltage follower circuit 34 is configured to generate a reference signal REF by performing a voltage follower operation based on the signal REF0. The voltage follower circuit 34 has an amplifier 35. The amplifier 35 has a positive input terminal InP, a negative input terminal InN, and an output terminal OUT. The signal REF0 is supplied to the positive input terminal InP of the amplifier 35, and the negative input terminal InN is connected to the output terminal OUT of the amplifier 35. The amplifier 35 outputs a reference signal REF from the output terminal OUT. The voltage follower circuit 34 supplies the reference signal REF output by the amplifier 35 from the output terminal OUT to the negative input terminal InN of the amplifier 35. The voltage follower circuit 34 performs a voltage follower operation by performing a negative feedback operation in this manner.

[0035] In this manner, in the reference signal generating unit 12, the signal generating circuit 31 generates the signal REF0 having a ramp waveform, and the voltage follower circuit 34 performs a voltage follower operation based on this signal REF0 to generate the reference signal REF. Then, the reference signal generating unit 12 supplies the generated reference signal REF to a plurality of pixel circuits 20 in the pixel array 11 (FIG. 1).

[0036] FIG. 5 shows an example of the configuration of the amplifier 35. The amplifier 35 has a differential input circuit 91, a bias circuit 92, and an output circuit 93. The differential input circuit 91 is configured to output a differential signal corresponding to the voltage difference between the voltage of the positive input terminal InP and the voltage of the negative input terminal InN. The bias circuit 92 is configured to set an operating point of the output circuit 93 based on the differential signal supplied from the differential input circuit 91. The bias circuit 92 is a circuit that utilizes the translinear principle. The output circuit 93 is an output circuit that is capable of rail-to-rail operation. Such an amplifier 35 is also called, for example, a cross-coupled feedforward class AB amplifier.

[0037] 6 shows an example of a specific circuit configuration of the amplifier 35. The amplifier 35 has a constant current source IS, transistors MP11-MP22, MN31-MN40, resistance elements R1, R2, and capacitance elements C1, C2. The transistors MP11-MP22 are P-type MOS transistors, and the transistors MN31-MN40 are N-type MOS transistors.

[0038] One end of the constant current source IS is connected to the gate and drain of the transistor MP11 and to the gates of the transistors MP12, MP13, and MP19, and the other end is connected to a ground node NVSS. The gate of the transistor MP11 is connected to the drain of the transistor MP11 and one end of the constant current source IS and to the gates of the transistors MP12, MP13, and MP19, the source is connected to a power supply node NVDD, and the drain is connected to the gate of the transistor MP11 and one end of the constant current source IS and to the gates of the transistors MP12, MP13, and MP19. The transistors MP11, MP12, MP13, and MP19 form a current mirror circuit.

[0039] The gate of transistor MP12 is connected to the gate and drain of transistor MP11 and to one end of constant current source IS and to the gates of transistors MP13 and MP19, its source is connected to power supply node NVDD, its drain is connected to the gate and drain of transistor MN31 and to the gate of transistor MN39. The gate of transistor MN31 is connected to the drains of transistors MN31 and MP12 and to the gate of transistor MN39, its drain is connected to the gate of transistor MN31 and the drain of transistor MP12 and to the gate of transistor MN39, and its source is connected to ground node NVSS. Transistors MN31 and MN39 form a current mirror circuit.

[0040] The gate of the transistor MP13 is connected to the gate and drain of the transistor MP11 and to one end of the constant current source IS and to the gates of the transistors MP12 and MP19, the source is connected to the power supply node NVDD, and the drain is connected to the sources of the transistors MP14 and MP15. The gate of the transistor MP14 is connected to the negative input terminal InN of the amplifier 35, the source is connected to the source of the transistor MP15 and to the drain of the transistor MP13, the drain is connected to the gate and drain of the transistor MN32 and to the gate of the transistor MN35. The gate of the transistor MP15 is connected to the positive input terminal InP of the amplifier 35, the source is connected to the source of the transistor MP14 and to the drain of the transistor MP13, the drain is connected to the gate and drain of the transistor MN33 and to the gate of the transistor MN34. The gate of the transistor MN32 is connected to the drains of the transistors MN32 and MP14 and to the gate of the transistor MN35, the drain is connected to the gate of the transistor MN32 and the drain of the transistor MP14 and to the gate of the transistor MN35, and the source is connected to the ground node NVSS. The gate of transistor MN33 is connected to the drains of transistors MN33 and MP15 and to the gate of transistor MN34, its drain is connected to the gate of transistor MN33 and the drain of transistor MP15 and to the gate of transistor MN34, and its source is connected to the ground node NVSS. Transistors MP14 and MP15 form a differential pair, transistors MN32 and MN35 form a current mirror circuit, and transistors MN33 and MN34 form a current mirror circuit.

[0041] The transistors MP13 to MP15, MN32, and MN33 correspond to the differential input circuit 91 shown in FIG.

[0042] The gate of transistor MN34 is connected to the gate and drain of transistor MN33 and to the drain of transistor MP15, the drain is connected to the gate and drain of transistor MP16 and to the gate of transistor MP17, and the source is connected to the ground node NVSS. The gate of transistor MP16 is connected to the drains of transistors MP16,MN34 and to the gate of transistor MP17, the source is connected to the power supply node NVDD, and the drain is connected to the gate of transistor MP16 and the drain of transistor MN34 and to the gate of transistor MP17. Transistors MP16 and MP17 form a current mirror circuit.

[0043] The gate of transistor MP17 is connected to the gate and drain of transistor MP16 and to the drain of transistor MN34, its source is connected to power supply node NVDD, and its drain is connected to node N1. The gate of transistor MP18 is connected to the gate and drain of transistor MP21 and to the drain of transistor MN39, its source is connected to node N1, and its drain is connected to node N2. The gate of transistor MN36 is connected to the gate and drain of transistor MN38 and to the drain of transistor MP19, its drain is connected to node N1, and its source is connected to node N2. The gate of transistor MN35 is connected to the gate and drain of transistor MN32 and to the drain of transistor MP14, its drain is connected to node N2, and its source is connected to ground node NVSS.

[0044] The gate of transistor MP19 is connected to the gate and drain of transistor MP11 and to one end of constant current source IS and to the gates of transistors MP12 and MP13, its source is connected to power supply node NVDD, its drain is connected to the gate and drain of transistor MN38 and to the gate of transistor MN36. The gate of transistor MN38 is connected to the drain of transistor MN38 and the drain of transistor MP19 and to the gate of transistor MN36, its drain is connected to the gate of transistor MN38 and the drain of transistor MP19 and to the gate of transistor MN36, its source is connected to the gate and drain of transistor MN37. The gate of transistor MN37 is connected to the drain of transistor MN37 and the source of transistor MN38, its drain is connected to the gate of transistor MN37 and the source of transistor MN38, and its source is connected to ground node NVSS. Transistors MP19, MN38, and MN37 form a bias circuit that generates a bias voltage supplied to the gate of transistor MN36.

[0045] The gate of transistor MP20 is connected to the drain of transistor MP20 and the source of transistor MP21, the source is connected to the power supply node NVDD, and the drain is connected to the gate of transistor MP20 and the source of transistor MP21. The gate of transistor MP21 is connected to the drains of transistors MP21 and MN39 and to the gate of transistor MP18, the source is connected to the gate and drain of transistor MP20, the drain is connected to the gate of transistor MP21 and the drain of transistor MN39 and to the gate of transistor MP18. The gate of transistor MN39 is connected to the gate and drain of transistor MN31 and to the drain of transistor MP12, the drain is connected to the gate and drain of transistor MP21 and to the gate of transistor MP18, and the source is connected to the ground node NVSS. Transistors MP20, MP21, and MN39 form a bias circuit that generates a bias voltage supplied to the gate of transistor MP18.

[0046] The transistors MP16 to MP21 and MN34 to MN39 correspond to the bias circuit 92 shown in FIG.

[0047] The gate of the transistor MP22 is connected to the node N1, the source is connected to the power supply node NVDD, and the drain is connected to the output terminal OUT of the amplifier 35. The gate of the transistor MN40 is connected to the node N2, the drain is connected to the output terminal OUT of the amplifier 35, and the source is connected to the ground node NVSS. One end of the capacitance element C1 is connected to the node N1, and the other end is connected to one end of the resistance element R1. One end of the resistance element R1 is connected to the other end of the capacitance element C1, and the other end is connected to the output terminal OUT. One end of the capacitance element C2 is connected to the node N2, and the other end is connected to one end of the resistance element R2. One end of the resistance element R2 is connected to the other end of the capacitance element C2, and the other end is connected to the output terminal OUT. The capacitance elements C1 and C2 and the resistance elements R1 and R2 form a phase compensation circuit.

[0048] The transistors MP22 and MN40, the capacitive elements C1 and C2, and the resistive elements R1 and R2 correspond to the output circuit 93 shown in FIG.

[0049] With this configuration, the imaging device 1 is able to stably supply the reference signal REF to the pixel circuits 20 of the multiple pixels P in the pixel array 11, as will be described later.

[0050] Here, the pixel circuit 20 corresponds to a specific example of a "pixel circuit" in the present disclosure. The reference signal generating unit 12 corresponds to a specific example of a "reference signal generating unit" in the present disclosure. The signal generating circuit 31 corresponds to a specific example of a "signal generating circuit" in the present disclosure. The voltage follower circuit 34 corresponds to a specific example of a "voltage follower circuit" in the present disclosure. The pixel signal SIG corresponds to a specific example of a "pixel signal" in the present disclosure. The reference signal REF corresponds to a specific example of a "reference signal" in the present disclosure. The amplifier 35 corresponds to a specific example of an "amplifier" in the present disclosure. The output circuit 93 corresponds to a specific example of an "output circuit" in the present disclosure.

[0051] The power supply node NVDD corresponds to a specific example of a "first power supply node" in this disclosure. The ground node NVSS corresponds to a specific example of a "second power supply node" in this disclosure. The transistor MP22 corresponds to a specific example of a "first transistor" in this disclosure. The transistor MN40 corresponds to a specific example of a "second transistor" in this disclosure. The pair of transistors MP14 and MP15 corresponds to a specific example of a "first differential transistor pair" in this disclosure. The transistor MP17 corresponds to a specific example of a "third transistor" in this disclosure. The transistor MN35 corresponds to a specific example of a "fourth transistor" in this disclosure. The transistor MP18 corresponds to a specific example of a "fifth transistor" in this disclosure. The transistor MN36 corresponds to a specific example of a "sixth transistor" in this disclosure. The node N1 corresponds to a specific example of a "first node" in this disclosure. The node N2 corresponds to a specific example of a "second node" in this disclosure. The transistor MN33 corresponds to a specific example of a "seventh transistor" in this disclosure. The transistor MN32 corresponds to a specific example of an "eighth transistor" in this disclosure. The transistor MN34 corresponds to a specific example of a "ninth transistor" in this disclosure. The transistor MP16 corresponds to a specific example of a "tenth transistor" in this disclosure.

[0052] [Actions and Actions] Next, the operation and function of the imaging device 1 of the present embodiment will be described.

[0053] (Overview of overall operation) First, an overview of the overall operation of the imaging device 1 will be described with reference to Figs. 1 and 3. The reference signal generating unit 12 generates a reference signal REF. Each of the pixel circuits 20 in the pixel array 11 generates a pixel signal SIG including a pixel voltage Vpix according to the amount of received light, and generates code values ​​CODE1 and CODE2 by performing AD conversion based on the pixel signal SIG. The pixel driving unit 13 controls the operation of the pixel circuits 20 in the pixel array 11. The vertical driving unit 14 supplies the code values ​​CODE1 and CODE2 generated by each of the pixel circuits 20 in the pixel array 11 to the signal processing unit 15 in a predetermined order. The signal processing unit 15 generates an image signal Spic by performing predetermined image processing based on the code values ​​CODE1 and CODE2 generated by each of the pixel circuits 20. The timing generating unit 16 generates various timing signals and controls the operation of the imaging device 1 by supplying the generated various timing signals to the reference signal generating unit 12, the pixel driving unit 13, the vertical driving unit 14, and the signal processing unit 15.

[0054] (Details of operation) In each of the pixel circuits 20 (FIG. 3) in the pixel array 11, the discharge transistor MN1 is turned on based on the control signal OFG, and the charge accumulated in the photodiode PD is discharged. Then, the discharge transistor MN1 is turned off, and an exposure period begins, and an amount of charge according to the amount of received light is accumulated in the photodiode PD. Then, after the exposure period ends, the pixel circuit 20 performs AD conversion based on the pixel signal SIG including the reset voltage Vreset and the pixel voltage Vpix. This AD conversion will be described in detail below.

[0055] FIG. 7 shows an example of the operation of AD conversion in a particular pixel circuit 20, where (A) shows the waveform of the control signal RST, (B) shows the waveform of the control signal TX, (C) shows the waveform of the reference signal REF, (D) shows the waveform of the pixel signal SIG, and (E) shows the waveform of the signal CMP.

[0056] First, at timing t11, the reference signal generation unit 12 changes the voltage of the reference signal REF to a reset voltage Vreset (FIG. 7(C)). Also at this timing t11, the pixel drive unit 13 changes the control signal RST from low level to high level (FIG. 7(A)). As a result, in the pixel circuit 20, the reset transistor MN3 is turned on, the floating diffusion FD is reset, and the voltage of the pixel signal SIG becomes the reset voltage Vreset (FIG. 7(D)). Then, after a predetermined time has elapsed from timing t11, the pixel drive unit 13 changes the control signal RST from high level to low level (FIG. 7(A)). As a result, the reset transistor MN3 is turned off.

[0057] Next, at timing t12, the reference signal generating unit 12 changes the voltage of the reference signal REF from the reset voltage Vreset to the voltage V1 (FIG. 7(C)). As a result, the voltage of the reference signal REF becomes higher than the voltage of the pixel signal SIG, so that the comparator circuit 22 sets the signal CMP to a high level (FIG. 7(E)).

[0058] Next, during the period from timing t13 to t15 (P-phase period TP), the pixel circuit 20 performs AD conversion based on the voltage of this pixel signal SIG (reset voltage Vreset). Specifically, at timing t13, the reference signal generation unit 12 starts decreasing the voltage of the reference signal REF from voltage V1 at a predetermined rate of change (FIG. 7(C)). Also, at this timing t13, the pixel drive unit 13 starts an increment operation of the time code CODE.

[0059] Then, at timing t14, the voltage of the reference signal REF falls below the voltage of the pixel signal SIG (reset voltage Vreset) (Figures 7(C) and (D)). In response to this, the comparator circuit 22 changes the signal CMP from high to low (Figure 7(E)). The latch 23 latches the time code CODE based on this transition of the signal CMP. The code value of the time code CODE latched in the latch 23 at this timing t14 is CODE1. This code value CODE1 is a code value that corresponds to the length of time from timing t13 to t14 and also corresponds to the reset voltage Vreset.

[0060] Then, at timing t15, with the end of the P-phase period TP, the reference signal generation unit 12 changes the voltage of the reference signal REF to voltage V2 (FIG. 7(C)). During the period from timing t15 to t16, the vertical drive unit 14 supplies the code value CODE1 generated by the pixel circuit 20 to the signal processing unit 15.

[0061] Next, at timing t16, the reference signal generating unit 12 changes the voltage of the reference signal REF from voltage V2 to voltage V1 (FIG. 7(C)). As a result, the voltage of the reference signal REF becomes higher than the voltage of the pixel signal SIG, so the comparator circuit 22 changes the signal CMP from low level to high level (FIG. 7(E)).

[0062] Next, at timing t17, the pixel driving unit 13 changes the control signal TX from low level to high level (FIG. 7(B)). As a result, in the pixel circuit 20, the transfer transistor MN2 is turned on, the charge generated in the photodiode PD is transferred to the floating diffusion FD, and the voltage of the pixel signal SIG becomes the pixel voltage Vpix (FIG. 7(D)). Then, after a predetermined time has elapsed from timing t17, the pixel driving unit 13 changes the control signal TX from high level to low level (FIG. 7(B)). As a result, the transfer transistor MN2 is turned off.

[0063] Next, in the period from timing t18 to t20 (D-phase period TD), the pixel circuit 20 performs AD conversion based on the voltage of this pixel signal SIG (pixel voltage Vpix). Specifically, at timing t18, the reference signal generation unit 12 starts decreasing the voltage of the reference signal REF from the voltage V1 at a predetermined rate of change (FIG. 7(C)). Also, at this timing t18, the pixel drive unit 13 starts an increment operation of the time code CODE.

[0064] Then, at timing t19, the voltage of the reference signal REF falls below the voltage of the pixel signal SIG (pixel voltage Vpix) (Figures 7(C) and (D)). In response to this, the comparator circuit 22 changes the signal CMP from high to low (Figure 7(E)). The latch 23 latches the time code CODE based on this transition of the signal CMP. The code value of the time code CODE latched in the latch 23 at this timing t19 is CODE2. This code value CODE2 is a code value that corresponds to the length of time from timing t18 to t19 and also corresponds to the pixel voltage Vpix.

[0065] Then, at timing t20, with the end of the D-phase period TD, the reference signal generation unit 12 changes the voltage of the reference signal REF to voltage V2 (FIG. 7(C)). During the period from timing t20 to t21, the vertical drive unit 14 supplies the code value CODE2 generated by the pixel circuit 20 to the signal processing unit 15.

[0066] The signal processing unit 15 performs a predetermined image processing based on the code values ​​CODE1 and CODE2 generated by each of the pixel circuits 20. For example, the signal processing unit 15 generates pixel values ​​based on the two code values ​​CODE1 and CODE2 by utilizing the principle of correlated double sampling. The signal processing unit 15 also performs black level correction processing to correct the black level. In this manner, the signal processing unit 15 generates the image signal Spic.

[0067] (Regarding the voltage follower circuit 34) Next, a description will be given of the operation of the voltage follower circuit 34. The voltage follower circuit 34 performs a negative feedback operation to generate a reference signal REF according to the signal REF0 supplied from the signal generation circuit 31, and supplies the generated reference signal REF to the multiple pixel circuits 20 in the pixel array 11.

[0068] First, the operation of the bias circuit 92 in the amplifier 35 will be described.

[0069] 8 shows an example of the operation of the amplifier 35. In the amplifier 35, for example, transistors MN36, MN38, MN37, and MN40 form one loop. In this loop, the following equation holds due to the translinear principle. Vgs(MN36)+Vgs(MN40)=Vgs(MN38)+Vgs(MN37) …(EQ1) Here, Vgs(MN36) is the gate-source voltage of transistor MN36, Vgs(MN40) is the gate-source voltage of transistor MN40, Vgs(MN38) is the gate-source voltage of transistor MN38, and Vgs(MN37) is the gate-source voltage of transistor MN37. If the sizes (gate width W and gate length L) of these four transistors MN36, MN38, MN37, and MN40 are equal to one another, then the following equations EQ2 and EQ3 can be obtained from equation EQ1. I36 = I38 ... (EQ2) I37 = I40 …(EQ3) Here, I36 is the current flowing through transistor MN36, I38 ​​is the current flowing through transistor MN38, I37 is the current flowing through transistor MN37, and I40 is the current flowing through transistor MN40. Here, currents I37 and I38 are set by the current value of constant current source IS and the current mirror ratio of transistors MP11 and MP19. These currents I37 and I38 are equal to each other. In this way, currents I37 and I38 in equations EQ2 and EQ3 are set, and as a result, currents I36 and I40 in equations EQ2 and EQ3 are also set.

[0070] Similarly, for example, transistors MP18, MP21, MP20, and MP22 form one loop in the amplifier 35. In this loop, the following equation holds due to the translinear principle. Vgs(MP18)+Vgs(MP22)=Vgs(MP21)+Vgs(MP20) …(EQ4) Here, Vgs(MP18) is the gate-source voltage of transistor MP18, Vgs(MP22) is the gate-source voltage of transistor MP22, Vgs(MP21) is the gate-source voltage of transistor MP21, and Vgs(MP20) is the gate-source voltage of transistor MP20. If the sizes (gate width W and gate length L) of these four transistors MP18, MP21, MP20, and MP22 are equal to one another, the following equations EQ5 and EQ6 can be obtained from equation EQ4. I18 = I21 ... (EQ5) I20 = I22 …(EQ6) Here, I18 is the current flowing through transistor MP18, I21 is the current flowing through transistor MP21, I20 is the current flowing through transistor MP20, and I22 is the current flowing through transistor MP22. Here, the currents I20 and I21 are set by the current value of the constant current source IS, the current mirror ratio of transistors MP11 and MP12, and the current mirror ratio of transistors MN31 and MN39. These currents I20 and I21 are equal to each other. In this way, the currents I20 and I21 in the equations EQ5 and EQ6 are set, and as a result, the currents I18 and I20 in the equations EQ5 and EQ6 are also set.

[0071] In the above, an example has been described in which the sizes of the four transistors MN36, MN38, MN37, and MN40 are equal to each other, and the sizes of the four transistors MP18, MP21, MP20, and MP22 are equal to each other. In reality, for example, the currents I36 and I40 can be set by adjusting the sizes of MN36 and MN40, and similarly, the currents I18 and I20 can be set by adjusting the sizes of MP18 and MP22.

[0072] Next, attention will be paid to the current paths of the transistors MP17, MP18, MN36, and MN35. In a steady state where the voltage at the positive input terminal InP and the voltage at the negative input terminal InN are equal to each other, the amplifier 35 is designed, for example, so that the following formula holds. I17 = I35 = I18 + I36 …(EQ7) Here, I17 is the current flowing through transistor MP17, and I35 is the current flowing through transistor MN35. In the steady state, as shown in equation EQ7, the current I17 flowing through transistor MP17 and the current I35 flowing through transistor MN35 are equal to each other.

[0073] For example, when the voltage at the positive input terminal InP of the amplifier 35 rises, the current flowing through the transistor MP14 increases and the current flowing through the transistor MP15 decreases transiently, so that the current I35 flowing through the transistor MN35 increases and the current I17 flowing through the transistor MP17 decreases. In this case, the voltages at the nodes N1 and N2 decrease. As the voltage at the node N1 decreases, the absolute value of the gate-source voltage Vgs(MP18) of the transistor MP18 decreases, so that the current I18 flowing through the transistor MP18 decreases. As the absolute value of the gate-source voltage Vgs(MP18) of the transistor MP18 decreases in this way, as is clear from the equation EQ4, the absolute value of the gate-source voltage Vgs(MP22) of the transistor MP22 increases, so that the current I22 flowing through the transistor MP22 increases. Also, as the voltage at the node N2 decreases, the gate-source voltage Vgs(MN36) of the transistor MN36 increases, so that the current I36 flowing through the transistor MN36 increases. In this way, as the gate-source voltage Vgs(MN36) of transistor MN36 increases, as is clear from equation EQ1, the gate-source voltage Vgs(MN40) of transistor MN40 decreases, and the current I40 flowing through transistor MN40 decreases. In this way, in the output circuit 93, the current I22 flowing through transistor MP22 increases and the current I40 flowing through transistor MN40 decreases, and the voltage at the output terminal OUT of amplifier 35 increases. In the voltage follower circuit 34, the output terminal OUT of amplifier 35 is connected to the negative input terminal InN, and therefore the voltage at the negative input terminal InN of amplifier 35 increases. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the steady state (equation EQ7) is restored.

[0074] Similarly, for example, when the voltage at the positive input terminal InP of the amplifier 35 drops, the current flowing through the transistor MP15 increases and the current flowing through the transistor MP14 decreases transiently, so that the current I17 flowing through the transistor MP17 increases and the current I35 flowing through the transistor MN35 decreases. In this case, the voltages at the nodes N1 and N2 rise. As the voltage at the node N1 rises, the absolute value of the gate-source voltage Vgs(MP18) of the transistor MP18 increases, so that the current I18 flowing through the transistor MP18 increases. As the absolute value of the gate-source voltage Vgs(MP18) of the transistor MP18 increases in this way, as is clear from the equation EQ4, the absolute value of the gate-source voltage Vgs(MP22) of the transistor MP22 decreases, so that the current I22 flowing through the transistor MP22 decreases. Furthermore, as the voltage at node N2 rises, the gate-source voltage Vgs(MN36) of transistor MN36 decreases, and the current I36 flowing through transistor MN36 decreases. As the gate-source voltage Vgs(MN36) of transistor MN36 decreases, as is clear from equation EQ1, the gate-source voltage Vgs(MN40) of transistor MN40 increases, and the current I40 flowing through transistor MN40 increases. As such, in output circuit 93, the current I40 flowing through transistor MN40 increases and the current I22 flowing through transistor MP22 decreases, and the voltage at the output terminal OUT of amplifier 35 drops. In voltage follower circuit 34, the output terminal OUT of amplifier 35 is connected to the negative input terminal InN, and the voltage at the negative input terminal InN of amplifier 35 drops. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the steady state (equation EQ7) is restored.

[0075] In the voltage follower circuit 34, when the signal REF0 input to the positive input terminal InP of the amplifier 35 changes, the currents I22 and I40 in the output circuit 93 may change significantly. However, inside the voltage follower circuit 34, the voltage changes at various nodes are small. Also, for example, even if the voltage at the output terminal OUT is changed in a wide voltage range from the ground level to the power supply voltage level, the voltage changes at various nodes are small. As a result, the voltage follower circuit 34 can operate stably as shown below.

[0076] 9 shows the simulation results of oscillation analysis in the voltage follower circuit 34. A characteristic WG_0 indicates the gain characteristic when the load current is 0 mA, and a characteristic WP_0 indicates the phase characteristic when the load current is 0 mA. A characteristic WG_500 indicates the gain characteristic when the load current is 500 mA, and a characteristic WP_500 indicates the phase characteristic when the load current is 500 mA.

[0077] In this voltage follower circuit 34, even if the load current changes greatly, the fluctuation of the characteristics can be suppressed and a sufficient phase margin can be ensured, so that the voltage follower circuit 34 can operate stably under various load conditions.

[0078] In this way, in the imaging device 1, the voltage follower circuit 34 can operate stably, and therefore the quality of the captured image can be improved. That is, in the imaging device 1, since each of the multiple pixel circuits 20 in the pixel array 11 performs AD conversion, the reference signal generation unit 12 needs to supply the reference signal REF to these multiple pixel circuits 20. When supplying the reference signal REF to the multiple pixel circuits 20 in this way, it is desirable for the reference signal generation unit 12 to be able to pass a large output current so as to drive the input capacitances of these multiple pixel circuits 20 and the wiring capacitances to these multiple pixel circuits 20.

[0079] For example, as shown in FIG. 10, when the reference signal generating unit 12R is configured to supply the reference signal REF to a plurality of pixel circuits 20 using the source follower 34R, it is necessary to increase the gate width W of the transistor 18 of the source follower 34R. However, in this case, the parasitic capacitance between the gate and source of the transistor 18 increases, so that the cutoff frequency of the source follower 34R decreases and the output impedance of the source follower 34R increases in the high frequency range due to the cutoff frequency. Therefore, when the reference signal generating unit 12R tries to supply the reference signal REF to a plurality of pixel circuits 20, oscillation and ringing occur due to such frequency characteristics, making it difficult to supply the reference signal REF to a plurality of pixel circuits 20 in the pixel array 11. As a result, it is difficult to improve image quality in an imaging device equipped with such a reference signal generating unit 12R.

[0080] Also, for example, if a voltage follower circuit is configured using a general operational amplifier and a reference signal generating unit is configured to supply a reference signal REF to a plurality of pixel circuits 20 using such a voltage follower circuit, for example, if the load current changes significantly, the operating point of the operational amplifier changes significantly, and for example, the phase margin decreases significantly. Therefore, it is difficult for such a reference signal generating unit to supply the reference signal REF to a plurality of pixel circuits 20 in the pixel array 11. As a result, it is difficult to improve image quality in an imaging device equipped with such a reference signal generating unit.

[0081] On the other hand, in the imaging device 1, as shown in Figures 5 and 6, the operating point of the output circuit 93 is set by a bias circuit 92 utilizing the translinear principle. As a result, as described above, when the voltage at the output terminal OUT is changed in a wide voltage range from the ground level to the power supply voltage level or when the load current changes significantly, it is possible to reduce voltage changes at various nodes in the amplifier 35. Therefore, the reference signal generation unit 12 can supply the reference signal REF to a plurality of pixel circuits 20 in the pixel array 11. As a result, the imaging device 1 can improve image quality.

[0082] In this way, the imaging device 1 is provided with a signal generating circuit 31 that generates a signal REF0 having a ramp waveform, and a voltage follower circuit 34 that generates a reference signal REF by performing a voltage follower operation based on this signal REF0 and supplies this reference signal REF to a plurality of pixel circuits 20. This makes it possible to improve the image quality of the captured image compared to the case where a source follower is used.

[0083] In addition, in the imaging device 1, the output circuit 93 of the amplifier 35 includes a P-type transistor MP22 having a source connected to the power supply node NVDD and a drain connected to the output terminal OUT, and an N-type transistor MN40 having a source connected to the ground node NVSS and a drain connected to the output terminal OUT. This allows the output circuit 93 to perform rail-to-rail operation, so that the reference signal generating unit 12 can generate a reference signal REF having a large amplitude. This allows, for example, the imaging device 1 to improve the dynamic range of the captured image, so that the image quality of the captured image can be improved.

[0084] In the imaging device 1, the amplifier 35 is provided with a transistor MP17, transistors MP18, MN36, and transistor MN35 in one current path connecting the power supply node NVDD and the ground node NVSS. The transistor MP17 has a source connected to the power supply node NVDD, and the transistor MN35 has a source connected to the ground node NVSS. The transistor MP18 is provided between the transistors MP17 and MN35 in this current path, and has a source connected to a node N1 on this current path, a gate to which a bias voltage is supplied, and a drain connected to a node N2 on this current path. The transistor MN36 is provided between the transistors MP17 and MN35 in this current path, and has a source connected to the node N2, a gate to which a bias voltage is supplied, and a drain connected to the node N1. The amplifier 35 controls the current flowing between the nodes N1 and N2 based on the current flowing through the transistors MP14 and MP15 of the differential input circuit 19. Specifically, the transistor MP17 passes a current corresponding to the current flowing through the transistor MP15 of the differential input circuit 19, and the transistor MN35 passes a current corresponding to the current flowing through the transistor MP14 of the differential input circuit 19. This makes it possible to reduce voltage changes at various nodes in the voltage follower circuit 34, and the reference signal generating unit 12 can supply the reference signal REF to the multiple pixel circuits 20. As a result, the image pickup device 1 can improve image quality. Furthermore, the image pickup device 1 can also increase the frame rate. This makes it possible to further improve image quality in the image pickup device 1.

[0085] [effect] As described above, in the present embodiment, there is provided a signal generation circuit that generates a signal REF0 having a ramp waveform, and a voltage follower circuit that generates a reference signal by performing a voltage follower operation based on this signal REF0 and supplies this reference signal to a plurality of pixel circuits, thereby making it possible to improve the image quality of a captured image.

[0086] [Variation 1] In the above embodiment, the differential pair of the differential input circuit 91 is configured using P-type MOS transistors MP14 and MP15, but this is not limited thereto, and instead, the differential pair of the differential input circuit 91 may be configured using N-type MOS transistors. The amplifier 35A according to this modification will be described in detail below.

[0087] 12 shows an example of the configuration of the amplifier 35A. The amplifier 35A has transistors MN51 to MN54 and MP41 to MP43. The transistors MN51 to MN54 are N-type MOS transistors, and the transistors MP41 to MP43 are P-type MOS transistors.

[0088] The gate of the transistor MN51 is connected to the negative input terminal InN of the amplifier 35A, the drain is connected to the gate and drain of the transistor MP41 and to the gate of the transistor MP17, the source is connected to the source of the transistor MN52 and to the drain of the transistor MN53. The gate of the transistor MN52 is connected to the positive input terminal InP of the amplifier 35A, the drain is connected to the gate and drain of the transistor MP42 and to the gate of the transistor MP43, the source is connected to the source of the transistor MN51 and to the drain of the transistor MN53. The gate of the transistor MN53 is connected to the gate and drain of the transistor MN31 and to the drain of the transistor MP12 and the gate of the transistor MN39, the drain is connected to the sources of the transistors MN51 and MN52, and the source is connected to the ground node NVSS. The gate of the transistor MP41 is connected to the drains of the transistors MP41 and MN51 and to the gate of the transistor MP17, the source is connected to the power supply node NVDD, the drain is connected to the gate of the transistor MP41 and the drain of the transistor MN51 and to the gate of the transistor MP17. The gate of transistor MP42 is connected to the drains of transistors MP42 and MN52 and to the gate of transistor MP43, its source is connected to the power supply node NVDD, and its drain is connected to the gate of transistor MP42 and the drain of transistor MN52 and to the gate of transistor MP43. Transistors MN51 and MN52 form a differential pair, transistors MP41 and MP17 form a current mirror circuit, and transistors MP42 and MP43 form a current mirror circuit.

[0089] The transistors MN51 to MN53, MP41, and MP42 correspond to the differential input circuit 91 shown in FIG.

[0090] The gate of transistor MP43 is connected to the gate and drain of transistor MP42 and to the drain of transistor MN52, its source is connected to power supply node NVDD, its drain is connected to the gate and drain of transistor MN54 and to the gate of transistor MN35. The gate of transistor MN54 is connected to the drains of transistors MN54 and MP43 and to the gate of transistor MN35, its drain is connected to the gate of transistor MN54 and the drain of transistor MP43 and to the gate of transistor MN35, and its source is connected to ground node NVSS. Transistors MN54 and MN35 form a current mirror circuit.

[0091] The transistors MP43, MP17 to MP21, MN54, and MN35 to MN39 correspond to the bias circuit 92 shown in FIG.

[0092] The ground node NVSS corresponds to a specific example of a "first power supply node" in this disclosure. The power supply node NVDD corresponds to a specific example of a "second power supply node" in this disclosure. The transistor MN40 corresponds to a specific example of a "first transistor" in this disclosure. The transistor MP22 corresponds to a specific example of a "second transistor" in this disclosure. The pair of transistors MN51 and MN52 corresponds to a specific example of a "first differential transistor pair" in this disclosure. The transistor MN35 corresponds to a specific example of a "third transistor" in this disclosure. The transistor MP17 corresponds to a specific example of a "fourth transistor" in this disclosure. The transistor MN36 corresponds to a specific example of a "fifth transistor" in this disclosure. The transistor MP18 corresponds to a specific example of a "sixth transistor" in this disclosure. The node N2 corresponds to a specific example of a "first node" in this disclosure. The node N1 corresponds to a specific example of a "second node" in this disclosure. The transistor MP42 corresponds to a specific example of a "seventh transistor" in this disclosure. The transistor MP41 corresponds to a specific example of an "eighth transistor" in the present disclosure. The transistor MP43 corresponds to a specific example of a "ninth transistor" in the present disclosure. The transistor MN54 corresponds to a specific example of a "tenth transistor" in the present disclosure.

[0093] For example, when the voltage at the positive input terminal InP of the amplifier 35A rises, the current flowing through the transistor MN52 increases and the current flowing through the transistor MN51 decreases transiently, so that the current flowing through the transistor MN35 increases and the current flowing through the transistor MP17 decreases. In this case, the voltages at the nodes N1 and N2 decrease. As a result, as in the above embodiment, in the output circuit 93, the current flowing through the transistor MP22 increases and the current flowing through the transistor MN40 decreases, so that the voltage at the output terminal OUT of the amplifier 35A rises. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become substantially equal, the steady state is restored.

[0094] Similarly, for example, when the voltage at the positive input terminal InP of the amplifier 35A drops, the current flowing through the transistor MN51 increases and the current flowing through the transistor MN52 decreases transiently, so that the current flowing through the transistor MP17 increases and the current flowing through the transistor MN35 decreases. In this case, the voltages at the nodes N1 and N2 rise. As a result, as in the above embodiment, in the output circuit 93, the current flowing through the transistor MN40 increases and the current flowing through the transistor MP22 decreases, so that the voltage at the output terminal OUT of the amplifier 35A drops. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the steady state is restored.

[0095] [Variation 2] In the above embodiment, the differential input circuit 91 and the bias circuit 92 are connected using a current mirror circuit (transistors MN32 to MN35), but the present invention is not limited to this. An amplifier 35B according to this modification will be described in detail below.

[0096] 12 shows an example of the configuration of the amplifier 35B. The amplifier 35B has transistors MN61 and MN62. The transistors MN61 and MN62 are N-type MOS transistors.

[0097] The gate of transistor MN61 is connected to the gate and drain of transistor MN31 and also to the drain of transistor MP12 and the gates of transistors MN62 and MN39, its drain is connected to the drains of transistors MP14 and MP16 and the gates of transistors MP16 and MP17, and its source is connected to ground node NVSS. The gate of transistor MN62 is connected to the gate and drain of transistor MN31 and also to the drain of transistor MP12 and the gates of transistors MN61 and MN39, its drain is connected to node N2, and its source is connected to ground node NVSS. Transistors MN31, MN61, and MN62 form a current mirror circuit.

[0098] The transistors MP13 to MP15 correspond to the differential input circuit 91 shown in Fig. 5. The transistors MP16 to MP21, MN61, MN62, and MN36 to MN39 correspond to the bias circuit 92 shown in Fig. 5. In this manner, in the amplifier 35B, the differential input circuit 91 and the bias circuit 92 are connected using a folded cascode circuit.

[0099] The power supply node NVDD corresponds to a specific example of a "first power supply node" in this disclosure. The ground node NVSS corresponds to a specific example of a "second power supply node" in this disclosure. The transistor MP22 corresponds to a specific example of a "first transistor" in this disclosure. The transistor MN40 corresponds to a specific example of a "second transistor" in this disclosure. The pair of transistors MP14 and MP15 corresponds to a specific example of a "first differential transistor pair" in this disclosure. The transistor MP17 corresponds to a specific example of a "third transistor" in this disclosure. The transistor MN35 corresponds to a specific example of a "fourth transistor" in this disclosure. The transistor MP18 corresponds to a specific example of a "fifth transistor" in this disclosure. The transistor MN36 corresponds to a specific example of a "sixth transistor" in this disclosure. The node N1 corresponds to a specific example of a "first node" in this disclosure. The node N2 corresponds to a specific example of a "second node" in this disclosure. The transistor MN61 corresponds to a specific example of an "eleventh transistor" in this disclosure. The transistor MP16 corresponds to a specific example of a "seventh transistor" in the present disclosure. The transistor MP14 corresponds to a specific example of a "first input transistor" in the present disclosure. The transistor MP15 corresponds to a specific example of a "second input transistor" in the present disclosure.

[0100] A current of a predetermined value flows through transistor MN61, which is the sum of the current flowing through transistor MP14 of differential input circuit 91 and the current flowing through transistor MP16. That is, since transistor MN61 operates as a constant current source, the current value of this total current is constant. Similarly, a current of a predetermined value flows through transistor MN62, which is the sum of the current flowing through transistor MP15 of differential input circuit 91 and the current flowing through transistors MP18 and MN36. That is, since transistor MN62 operates as a constant current source, the current value of this total current is constant.

[0101] For example, when the voltage at the positive input terminal InP of the amplifier 35B rises, the current flowing through the transistor MP14 increases and the current flowing through the transistor MP15 decreases transiently. Since the current flowing through the transistor MP15 decreases in this way, the current flowing from the transistors MP18 and MN36 to the transistor MN62 increases. Also, since the current flowing through the transistor MP14 increases in this way, the current flowing from the transistor MP16 to the transistor MN61 decreases, and the current flowing through the transistor MP17 decreases. In this case, the voltages at the nodes N1 and N2 decrease. As a result, in the output circuit 93, the current flowing through the transistor MP22 increases and the current flowing through the transistor MN40 decreases, as in the case of the above embodiment, so that the voltage at the output terminal OUT of the amplifier 35B rises. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the steady state is restored.

[0102] Similarly, for example, when the voltage at the positive input terminal InP of the amplifier 35B drops, the current flowing through the transistor MP15 increases and the current flowing through the transistor MP14 decreases transiently. Since the current flowing through the transistor MP14 decreases in this way, the current flowing from the transistor MP16 to the transistor MN61 increases, and the current flowing through the transistor MP17 increases. Also, since the current flowing through the transistor MP15 increases in this way, the current flowing from the transistors MP18 and MN36 to the transistor MN62 decreases. In this case, the voltages at the nodes N1 and N2 increase. As a result, in the output circuit 93, the current flowing through the transistor MN40 increases and the current flowing through the transistor MP22 decreases, as in the case of the above embodiment, so that the voltage at the output terminal OUT of the amplifier 35B drops. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the steady state is restored.

[0103] [Variation 3] In the above embodiment, the differential input circuit 91 is configured using one differential pair, but this is not limited to this, and instead, the differential input circuit 91 may be configured using two differential pairs. The amplifier 35C according to this modification will be described in detail below.

[0104] 13 shows an example of the configuration of amplifier 35C. Amplifier 35C has transistors MN51 to MN53, MP71 to MP75, and MN81 to MN85, and bias circuits 38 and 39. Transistors MN51 to MN53, MN81 to MN85 are N-type MOS transistors, and transistors MP71 to MP75 are P-type MOS transistors.

[0105] The gate of transistor MN51 is connected to the negative input terminal InN of the amplifier 35C, its drain is connected to the drain of transistor MP71 and the source of transistor MP72, its source is connected to the source of transistor MN52 and to the drain of transistor MN53. The gate of transistor MN52 is connected to the positive input terminal InP of the amplifier 35C, its drain is connected to the drain of transistor MP74 and the source of transistor MP75, its source is connected to the source of transistor MN51 and to the drain of transistor MN53. The gate of transistor MN53 is connected to the gate and drain of transistor MN31 and to the drain of transistor MP12 and the gate of transistor MN39, its drain is connected to the sources of transistors MN51 and MN52, and its source is connected to the ground node NVSS. Transistors MN51 and MN52 form a differential pair.

[0106] The transistors MP13 to MP15 and MN51 to MN53 correspond to the differential input circuit 91 shown in FIG.

[0107] The gate of transistor MP71 is connected to node N3, its source is connected to power supply node NVDD, and its drain is connected to the drain of transistor MN51 and the source of transistor MP72. A bias voltage is supplied to the gate of transistor MP72 from bias circuit 38, its source is connected to the drains of transistors MP71 and MN51, and its drain is connected to node N3. The gate of transistor MP73 is connected to the gate and drain of transistor MP21, as well as to the drain of transistor MN39 and the gate of transistor MP18, its source is connected to node N3, and its drain is connected to node N4. The gate of transistor MN83 is connected to the gate and drain of transistor MN38, as well as to the drain of transistor MP19 and the gate of transistor MN36, its drain is connected to node N3, and its source is connected to node N4. A bias voltage is supplied to the gate of transistor MN82 from bias circuit 39, its drain is connected to node N4, and its source is connected to the drains of transistors MN81 and MP14. The gate of transistor MN81 is connected to node N4, its drain is connected to the drain of transistor MP14 and the source of transistor MN82, and its source is connected to ground node NVSS. Transistors MP71 and MP74 form a current mirror circuit, and transistors MN81 and MN84 form a current mirror circuit.

[0108] The gate of transistor MP74 is connected to node N3, its source is connected to power supply node NVDD, and its drain is connected to the drain of transistor MN52 and the source of transistor MP75. A bias voltage is supplied to the gate of transistor MP75 from bias circuit 38, its source is connected to the drains of transistors MP74 and MN52, and its drain is connected to node N1. A bias voltage is supplied to the gate of transistor MN85 from bias circuit 39, its drain is connected to node N2, and its source is connected to the drains of transistors MN84 and MP15. The gate of transistor MN84 is connected to node N4, its drain is connected to the drain of transistor MP15 and the source of transistor MN85, and its source is connected to the ground node NVSS.

[0109] Each of the bias circuits 38, 39 is configured to generate a bias voltage.

[0110] The transistors MP71 to MP75, MN81 to MN85, MP18 to MP21, and MN36 to MN39, and the bias circuits 38 and 39 correspond to the bias circuit 92 shown in FIG.

[0111] The power supply node NVDD corresponds to a specific example of a "first power supply node" in this disclosure. The ground node NVSS corresponds to a specific example of a "second power supply node" in this disclosure. The transistor MP22 corresponds to a specific example of a "first transistor" in this disclosure. The transistor MN40 corresponds to a specific example of a "second transistor" in this disclosure. The pair of transistors MP14 and MP15 corresponds to a specific example of a "first differential transistor pair" in this disclosure. The transistor MP14 corresponds to a specific example of a "first input transistor" in this disclosure. The transistor MP15 corresponds to a specific example of a "second input transistor" in this disclosure. The transistor MP17 corresponds to a specific example of a "third transistor" in this disclosure. The transistor MN35 corresponds to a specific example of a "fourth transistor" in this disclosure. The transistor MP18 corresponds to a specific example of a "fifth transistor" in this disclosure. The transistor MN36 corresponds to a specific example of a "sixth transistor" in this disclosure. The node N1 corresponds to a specific example of a "first node" in this disclosure. The node N2 corresponds to a specific example of a "second node" in this disclosure.

[0112] The pair of transistors MN52, MN51 corresponds to a specific example of a "second differential transistor pair" in this disclosure. Transistor MN52 corresponds to a specific example of a "third input transistor" in this disclosure. Transistor MN51 corresponds to a specific example of a "fourth input transistor" in this disclosure. Transistor MP71 corresponds to a specific example of a "thirteenth transistor" in this disclosure. Transistor MN81 corresponds to a specific example of a "fourteenth transistor" in this disclosure. Transistor MP73 corresponds to a specific example of a "fifteenth transistor" in this disclosure. Transistor MN83 corresponds to a specific example of a "sixteenth transistor" in this disclosure. Node N3 corresponds to a specific example of a "third node" in this disclosure. Node N4 corresponds to a specific example of a "fourth node" in this disclosure.

[0113] [Other variations] Also, two or more of these variations may be combined.

[0114] <2. Examples of use of imaging devices> 14 shows an example of use of the imaging device 1 according to the above embodiment. The imaging device 1 described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.

[0115] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as on-board sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving (such as automatic stopping) and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc. - A device used in home appliances such as televisions, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication - Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports use Agricultural equipment such as cameras for monitoring fields and crop conditions

[0116] <3. Application examples for mobile objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0117] FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0118] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 15, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0119] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0120] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0121] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0122] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0123] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0124] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0125] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0126] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0127] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 15, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0128] FIG. 16 is a diagram showing an example of the installation position of the imaging unit 12031.

[0129] In FIG. 16, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0130] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0131] 16 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0132] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0133] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0134] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0135] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0136] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. This allows the vehicle control system 12000 to improve the image quality of the captured image obtained by the imaging unit 12031. As a result, the vehicle control system 12000 can achieve a vehicle collision avoidance or collision mitigation function, a following driving function based on the inter-vehicle distance, a vehicle speed maintenance driving function, a vehicle collision warning function, a vehicle lane departure warning function, and the like with high accuracy.

[0137] The present technology has been described above by giving the embodiments and modifications thereof, as well as specific application examples thereof. However, the present technology is not limited to these embodiments, and various modifications are possible.

[0138] For example, in the above embodiment, pixel P is arranged across two semiconductor substrates 101, 102, but this is not limited to this, and pixel P may be arranged on one semiconductor substrate, or may be arranged across three or more semiconductor substrates.

[0139] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0140] The present technology can be configured as follows: According to the present technology configured as follows, it is possible to improve the image quality of a captured image.

[0141] (1) a plurality of pixel circuits, each of which generates a pixel signal including a pixel voltage corresponding to an amount of received light, and performs AD conversion by comparing the pixel signal with a reference signal; a reference signal generating unit including a signal generating circuit that generates a voltage signal having a ramp waveform, and a voltage follower circuit that generates the reference signal by performing a voltage follower operation based on the voltage signal and supplies the reference signal to the plurality of pixel circuits; An imaging device comprising: (2) the voltage follower circuit includes an amplifier having a positive input terminal to which the voltage signal is supplied, a negative input terminal, an output terminal connected to the negative input terminal and outputting the reference signal, and an output circuit connected to the output terminal; The output circuit includes: a first transistor of a first conductivity type having a source connected to a first power supply node, a drain connected to the output terminal, and a gate; a second transistor of a second conductivity type having a source connected to a second power supply node, a drain connected to the output terminal, and a gate; have The imaging device according to (1) above. (3) The amplifier is a first differential transistor pair coupled to the positive input terminal and the negative input terminal to generate a differential current comprising a first current and a second current; a third transistor of the first conductivity type provided in a first current path connecting the first power supply node and the second power supply node, the third transistor having a source connected to the first power supply node, a gate, and a drain; a fourth transistor of the second conductivity type provided in the first current path and having a source connected to the second power supply node, a gate, and a drain; a fifth transistor of the first conductivity type provided in the first current path between the third transistor and the fourth transistor, the fifth transistor having a source connected to a first node on the first current path, a drain connected to a second node on the first current path, and a gate to which a first bias voltage is supplied; a sixth transistor of the second conductivity type provided in the first current path between the third transistor and the fourth transistor, the sixth transistor having a drain connected to the first node, a source connected to the second node, and a gate to which a second bias voltage is supplied; having the amplifier controls a current flowing between the first node and the second node in the first current path based on the first current and the second current; the gate of the first transistor is connected to the first node; The gate of the second transistor is connected to the second node. The imaging device according to (2) above. (4) the third transistor passes a current corresponding to the first current; The fourth transistor passes a current corresponding to the second current. The imaging device according to (3) above. (5) The amplifier is a seventh transistor of the second conductivity type having a drain, a gate connected to the drain, and a source connected to the second power supply node, through which the first current flows; an eighth transistor of the second conductivity type having a drain, a gate connected to the drain and the gate of the fourth transistor, and a source connected to the second power supply node, through which the second current flows; a ninth transistor of the second conductivity type provided in a second current path connecting the first power supply node and the second power supply node, the ninth transistor having a drain, a gate connected to the gate and the drain of the seventh transistor, and a source connected to the second power supply node; a tenth transistor of the first conductivity type provided in the second current path, the tenth transistor having a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node; have The imaging device according to (3) or (4). (6) the third transistor passes a current corresponding to the first current; The fourth transistor passes a current having a predetermined current value including the second current. The imaging device according to (3) above. (7) The amplifier, an eleventh transistor of the second conductivity type, which is provided in a second current path connecting the first power supply node and the second power supply node, has a drain, a gate, and a source connected to the second power supply node, and passes a current of a predetermined current value including the first current; a twelfth transistor of the first conductivity type provided in the second current path, the twelfth transistor having a drain, a gate connected to the drain and to the gate of the third transistor, and a source connected to the first power supply node; and The first differential transistor pair includes: a first input transistor of the first conductivity type having a drain and generating the first current; a second input transistor of the first conductivity type having a drain and generating the second current; having the drain of the eleventh transistor is connected to the drain of the first input transistor; The drain of the fourth transistor is connected to the drain of the second input transistor. The imaging device according to (3) or (6). (8) the amplifier further comprises a second differential transistor pair connected to the positive input terminal and the negative input terminal to generate a differential current including a third current and a fourth current; The amplifier controls a current flowing between the first node and the second node based on the first current, the second current, the third current, and the fourth current. The imaging device according to (3) above. (9) The amplifier comprises: a thirteenth transistor of the first conductivity type provided in a second current path connecting the first power supply node and the second power supply node, the thirteenth transistor having a source connected to the first power supply node, a gate connected to a third node on the second current path, and a drain; a fourteenth transistor of the second conductivity type provided in the second current path, the fourteenth transistor having a source connected to the second power supply node, a gate connected to a fourth node on the second current path, and a drain; a fifteenth transistor of the first conductivity type provided in the second current path between the thirteenth transistor and the fourteenth transistor, the fifteenth transistor having a source connected to the third node, a drain connected to the fourth node, and a gate to which the first bias voltage is supplied; a sixteenth transistor of the second conductivity type provided in the second current path between the thirteenth transistor and the fourteenth transistor, the sixteenth transistor having a drain connected to the third node, a source connected to the fourth node, and a gate to which the second bias voltage is supplied; and The first differential transistor pair includes: a first input transistor of the first conductivity type having a drain and generating the first current; a second input transistor of the first conductivity type having a drain and generating the second current; having The second differential transistor pair includes: a third input transistor of the second conductivity type having a drain and generating the third current; a fourth input transistor of the second conductivity type having a drain and generating the fourth current; having the drain of the third transistor is connected to the drain of the third input transistor; the drain of the fourth transistor is connected to the drain of the second input transistor; the drain of the thirteenth transistor is connected to the drain of the fourth input transistor; The drain of the fourteenth transistor is connected to the drain of the first input transistor. The imaging device according to (3) or (8).

[0142] This application claims priority based on Japanese Patent Application No. 2020-052229, filed on March 24, 2020 in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0143] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur to those skilled in the art depending on design requirements and other factors, and that such modifications are within the scope of the appended claims and their equivalents.

Claims

1. A plurality of pixel circuits each generating a pixel signal including a pixel voltage corresponding to an amount of received light and performing AD conversion by comparing the pixel signal with a reference signal; a reference signal generating unit including a signal generating circuit that generates a voltage signal having a ramp waveform, and a voltage follower circuit that generates the reference signal by performing a voltage follower operation based on the voltage signal and supplies the reference signal to the plurality of pixel circuits; Equipped with the voltage follower circuit includes an amplifier having a positive input terminal to which the voltage signal is supplied, a negative input terminal, an output terminal connected to the negative input terminal and outputting the reference signal, and an output circuit connected to the output terminal; The output circuit includes: a first transistor of a first conductivity type having a source connected to a first power supply node, a drain connected to the output terminal, and a gate; a second transistor of a second conductivity type having a source connected to a second power supply node, a drain connected to the output terminal, and a gate; having The amplifier is a first differential transistor pair coupled to the positive input terminal and the negative input terminal to generate a differential current comprising a first current and a second current; a third transistor of the first conductivity type provided in a first current path connecting the first power supply node and the second power supply node, the third transistor having a source connected to the first power supply node, a gate, and a drain; a fourth transistor of the second conductivity type provided in the first current path and having a source connected to the second power supply node, a gate, and a drain; a fifth transistor of the first conductivity type provided in the first current path between the third transistor and the fourth transistor, the fifth transistor having a source connected to a first node on the first current path, a drain connected to a second node on the first current path, and a gate to which a first bias voltage is supplied; a sixth transistor of the second conductivity type provided in the first current path between the third transistor and the fourth transistor, the sixth transistor having a drain connected to the first node, a source connected to the second node, and a gate to which a second bias voltage is supplied; having the amplifier controls a current flowing between the first node and the second node in the first current path based on the first current and the second current; the gate of the first transistor is connected to the first node; The gate of the second transistor is connected to the second node. Imaging device.

2. the third transistor passes a current corresponding to the first current; The fourth transistor passes a current corresponding to the second current. The imaging device according to claim 1 .

3. The amplifier is a seventh transistor of the second conductivity type having a drain, a gate connected to the drain, and a source connected to the second power supply node, through which the first current flows; an eighth transistor of the second conductivity type having a drain, a gate connected to the drain and the gate of the fourth transistor, and a source connected to the second power supply node, through which the second current flows; a ninth transistor of the second conductivity type provided in a second current path connecting the first power supply node and the second power supply node, the ninth transistor having a drain, a gate connected to the gate and the drain of the seventh transistor, and a source connected to the second power supply node; a tenth transistor of the first conductivity type provided in the second current path, the tenth transistor having a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node; have The imaging device according to claim 1 .

4. the third transistor passes a current corresponding to the first current; The fourth transistor passes a current having a predetermined current value including the second current. The imaging device according to claim 1 .

5. The amplifier is an eleventh transistor of the second conductivity type, which is provided in a second current path connecting the first power supply node and the second power supply node, has a drain, a gate, and a source connected to the second power supply node, and passes a current of a predetermined current value including the first current; a twelfth transistor of the first conductivity type provided in the second current path, the twelfth transistor having a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node; and The first differential transistor pair includes: a first input transistor of the first conductivity type having a drain and generating the first current; a second input transistor of the first conductivity type having a drain and generating the second current; having the drain of the eleventh transistor is connected to the drain of the first input transistor; The drain of the fourth transistor is connected to the drain of the second input transistor. The imaging device according to claim 1 .

6. the amplifier further comprising a second differential transistor pair coupled to the positive input terminal and the negative input terminal to generate a differential current comprising a third current and a fourth current; The amplifier controls a current flowing between the first node and the second node based on the first current, the second current, the third current, and the fourth current. The imaging device according to claim 1 .

7. The amplifier is a thirteenth transistor of the first conductivity type provided in a second current path connecting the first power supply node and the second power supply node, the thirteenth transistor having a source connected to the first power supply node, a gate connected to a third node on the second current path, and a drain; a fourteenth transistor of the second conductivity type provided in the second current path, the fourteenth transistor having a source connected to the second power supply node, a gate connected to a fourth node on the second current path, and a drain; a fifteenth transistor of the first conductivity type provided in the second current path between the thirteenth transistor and the fourteenth transistor, the fifteenth transistor having a source connected to the third node, a drain connected to the fourth node, and a gate to which the first bias voltage is supplied; a sixteenth transistor of the second conductivity type provided in the second current path between the thirteenth transistor and the fourteenth transistor, the sixteenth transistor having a drain connected to the third node, a source connected to the fourth node, and a gate to which the second bias voltage is supplied; and The first differential transistor pair includes: a first input transistor of the first conductivity type having a drain and generating the first current; a second input transistor of the first conductivity type having a drain and generating the second current; having The second differential transistor pair includes: a third input transistor of the second conductivity type having a drain and generating the third current; a fourth input transistor of the second conductivity type having a drain and generating the fourth current; having the drain of the third transistor is connected to the drain of the third input transistor; the drain of the fourth transistor is connected to the drain of the second input transistor; the drain of the thirteenth transistor is connected to the drain of the fourth input transistor; The drain of the fourteenth transistor is connected to the drain of the first input transistor. The imaging device according to claim 6.

Images