Fault Detection Circuit

Abstract

To solve the problem that a conventional device cannot detect an occurrence of a failure that prevents an operation correction from being performed on any one of a plurality of driving phases.SOLUTION: A failure detection circuit according to the present disclosure includes: a plurality of phase difference detection circuits 51, 52 that generate phase difference measurement signals PF1 to PF4 each having a pulse width corresponding to a magnitude of a phase difference between two driving signals of different phases among driving signals Ds1 to Ds4; a plurality of smoothing circuits 53 to 56 that respectively smooth the phase difference measurement signals PF1 to PF4 previously associated with them and output phase difference detection voltages PF1s to PF4s each having a voltage value corresponding to a magnitude of the phase difference; and an error detection circuit 57 that compares the phase difference detection voltages PF1s to PF4s and switches abnormality detection signals ER1, ER2 from an invalid state to a valid state when there is a phase difference detection voltage having a voltage value exceeding a preset allowable range.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a fault detection circuit, and more particularly to a fault detection circuit that detects faults occurring in a multi-phase power supply. [Background technology]

[0002] In switching to supply power to a load circuit, the use of multiphase power supplies that combine power supply currents generated by drive signals of different phases and supply them to the load is increasing in order to cope with the increase in power consumption of the load circuit. In this multiphase power supply, it is required that each phase performs switching operation with a preset phase difference. Therefore, technology related to this multiphase power supply is disclosed in Patent Document 1.

[0003] The switching power supply device described in Patent Document 1 includes a main circuit in which a plurality of power conversion units, each having a switching element, are connected in parallel to one another; a control circuit that outputs a reference pulse signal based on an output of the entire main circuit; an overall current detection circuit that detects the output current of the entire main circuit as an overall current; a plurality of individual current detection circuits provided corresponding to the plurality of power conversion units and that detect the output current of each of the plurality of power conversion units as an individual current; and a pulse compensator that generates the individual pulse signal for each of the plurality of power conversion units based on the overall current, the individual current, and the reference pulse signal, and outputs the individual pulse signal for each of the plurality of power conversion units to each of the plurality of power conversion units as drive signals for the switching elements. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-176606 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, a multi-phase power supply has a problem that it does not operate correctly if a failure occurs in any one of the phases. Although the switching power supply device described in Patent Document 1 is a multi-phase power supply, it has a problem that it cannot detect the occurrence of a malfunction that makes it impossible to correct the operation of any of the multiple driving phases.

[0006] The present disclosure has been made in consideration of the above-mentioned problems, and provides a multi-phase power supply having high fault detection capability. [Means for solving the problem]

[0007] The fault detection circuit disclosed herein is a fault detection circuit that detects abnormalities in the drive signals of a plurality of drive circuits, each of which drives a load circuit connected in series between an output terminal and a ground wiring using drive signals of different phases, and includes a plurality of phase difference detection circuits, each of which generates a phase difference measurement signal having a pulse width corresponding to the magnitude of the phase difference between two of the plurality of drive signals of different phases, a plurality of smoothing circuits, each of which smoothes the pre-associated phase difference measurement signal and outputs a phase difference detection voltage having a voltage value corresponding to the magnitude of the phase difference, and an error detection circuit that compares the plurality of phase difference detection voltages, and switches the abnormality detection signal from an invalid state to an valid state if a phase difference detection voltage has a voltage value outside a pre-set tolerance range.

[0008] The fault detection circuit according to the present disclosure detects a fault occurring in each power supply circuit based on the phase difference between the drive signals of multiple power supply circuits that constitute a multi-phase power supply. Effect of the Invention

[0009] According to the present disclosure, a multi-phase power supply having high fault detection capability can be provided. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram of a multiphase power supply device according to a first embodiment. [Diagram 2] 1 is a block diagram of a fault detection circuit according to a first embodiment. [Diagram 3] 4 is a timing chart illustrating a first operation example of the failure detection circuit according to the first embodiment. [Figure 4] 6 is a timing chart illustrating a second operation example of the failure detection circuit according to the first embodiment. [Diagram 5] 6 is a timing chart illustrating a third operation example of the failure detection circuit according to the first embodiment. [Figure 6] 13 is a timing chart illustrating a fourth operation example of the failure detection circuit according to the first embodiment. [Figure 7] 13 is a timing chart illustrating a fifth operation example of the failure detection circuit according to the first embodiment. [Figure 8] 13 is a timing chart illustrating a sixth operation example of the failure detection circuit according to the first embodiment. [Figure 9] 13 is a timing chart illustrating a seventh operation example of the failure detection circuit according to the first embodiment. [Figure 10] FIG. 11 is a block diagram of a fault detection circuit according to a second embodiment. [Figure 11] 4 is a timing chart illustrating a first operation example of the failure detection circuit according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will be described below through embodiments of the invention, but the invention according to the claims is not limited to the following embodiments. Also, not all of the configurations described in the embodiments are necessarily essential as means for solving the problems. The embodiments will be described below with reference to the drawings.

[0012] First embodiment FIG. 1 shows a block diagram of a multiphase power supply device 1 according to a first embodiment. The multiphase power supply device 1 shown in FIG. 1 supplies power to a load circuit LD by four-phase drive signals whose phases differ by 90 degrees each. The multiphase power supply circuit may be a circuit that supplies power to the load circuit LD by drive signals of two or more different phases, and the more the number of phases of the drive signals increases, the higher the supply capacity of the load current to the load circuit LD becomes. The fault detection circuit 50 described below can be applied to a multiphase power supply device that supplies power to the load circuit LD by use of drive signals of two or more phases.

[0013] As shown in Fig. 1, the multi-phase power supply device 1 has a power supply main unit and a fault detection circuit 50. When the fault detection circuit 50 is notified of the occurrence of an abnormality using the abnormality detection signals ER1 and ER2, the power supply main unit changes the operation mode. As the operation mode, various operations are possible, such as a safe mode in which operation continues while reducing the number of driving phases, and a stop mode in which operation is stopped.

[0014] In the example shown in Fig. 1, the power supply main body includes switching power supplies 10-40, a power supply PWR, and a load circuit LD. The power supply PWR is a supply source of power supply current to the load circuit LD, and power supplies for other circuits are omitted from Fig. 1. The power supply PWR may be provided separately from the multiphase power supply device 1, and the load circuit LD is a circuit to which power is supplied by the multiphase power supply device 1, and is shown in Fig. 1 to more clearly show the configuration of the multiphase power supply device 1.

[0015] In the example shown in FIG. 1, switching power supply 10 corresponds to a drive signal with a phase of 0 degrees, switching power supply 20 corresponds to a drive signal with a phase of 90 degrees, switching power supply 30 corresponds to a drive signal with a phase of 180 degrees, and switching power supply 40 corresponds to a drive signal with a phase of 270 degrees.

[0016] The switching power supplies 10 to 40 have the same configuration, and each includes a drive control unit PM, a decoupling capacitor Cd, power transistors TU and TL, an inductor L, and an output capacitor Co.

[0017] The decoupling capacitor Cd is connected between the power supply wiring connected to the positive electrode side of the power supply PWR and the ground wiring. The power transistor TU and the power transistor TL are connected in series between the power supply wiring and the ground wiring. In the example shown in FIG. 1, both the power transistor TU and the power transistor TL are NMOS transistors, but NMOS transistors and PMOS transistors can be combined. One end of the inductor L is connected to the connection point between the power transistor TU and the power transistor TL, and the other end is connected to the load circuit LD. The output capacitor Co is connected between the other end of the inductor L and the ground wiring. In addition, the drive control unit PM is, for example, a PWM signal generating circuit that generates a PWM (Pulse Width Modulation) signal, and the power transistor TU and the power transistor TL are push-pull operated by the PWM signal. In addition, in the example shown in FIG. 1, an example is shown in which the drive control unit PM included in the switching power supplies 10 to 40 is realized by a plurality of PWM modules included in one drive processor MCU. The drive processor MCU includes a calculation unit (not shown) and executes a power supply control program in the calculation unit, thereby enabling the change of the frequency of the drive signal in the multiphase power supply device 1, the change of the number of drive phases, and the change of operating modes such as start-up and stop.

[0018] The switching power supplies 10 to 40 generate a rectangular wave drive signal at the output terminal, which is the connection point between the power transistor TU and the power transistor TL. Then, the drive signal is smoothed using an inductor L connected to the output terminal and an output capacitor Co connected to the other end of the inductor L to generate a power supply to be provided to a load circuit LD. In the example shown in FIG. 1, the drive signals output from the output terminals of the switching power supplies 10 to 40 are drive signals Ds1 to Ds4. Note that the drive signals are not limited to rectangular waves and may be sine waves, but power efficiency can be improved by using rectangular wave drive signals.

[0019] In the multiphase power supply 1, the drive signals Ds1 to Ds4 are monitored by a fault detection circuit 50, and when a malfunction is detected in the switching power supplies 10 to 40 based on the magnitude of the phase difference between the multiple drive signals, the error is notified to the drive processor MPU by the abnormality detection signals ER1 and ER2. When the drive processor MPU recognizes the occurrence of an error in this manner, for example, it stops the operation of the multiphase power supply 1. Note that when an error occurs, in addition to stopping the operation of the multiphase power supply 1, it is also possible to, for example, stop the switching power supply in which the malfunction has occurred and transition to a safe mode in which the number of drive phases is reduced.

[0020] Next, the fault detection circuit 50 will be described in detail. The fault detection circuit 50 detects an abnormality in the switching power supplies 10 to 40 based on the phase difference between the multiple drive signals output by the multiple drive circuits being shifted from a predetermined specified state. FIG. 2 shows a block diagram of the fault detection circuit 50 according to the first embodiment.

[0021] 2, the failure detection circuit 50 according to the first embodiment includes phase difference detection circuits 51 and 52, smoothing circuits 53 to 56, and an error detection circuit 57. The failure detection circuit 50 also includes level shift circuits 11, 21, 31, and 41.

[0022] The level shift circuit 11 suppresses the amplitude of the drive signal Ds1 output from the switching power supply 10 to a power supply voltage (e.g., 3.3 V) or less of the subsequent circuit, and provides the drive signal after the amplitude suppression to the phase difference detection circuit 51. The level shift circuit 21 suppresses the amplitude of the drive signal Ds2 output from the switching power supply 20 to a power supply voltage (e.g., 3.3 V) or less of the subsequent circuit, and provides the drive signal after the amplitude suppression to the phase difference detection circuit 51. The level shift circuit 31 suppresses the amplitude of the drive signal Ds3 output from the switching power supply 30 to a power supply voltage (e.g., 3.3 V) or less of the subsequent circuit, and provides the drive signal after the amplitude suppression to the phase difference detection circuit 52. The level shift circuit 41 suppresses the amplitude of the drive signal Ds4 output from the switching power supply 40 to a power supply voltage (e.g., 3.3 V) or less of the subsequent circuit, and provides the drive signal after the amplitude suppression to the phase difference detection circuit 52. When the drive signal is generated based on a higher drive power supply voltage, such as 12 V, the amplitude of the drive signal can be reduced to a voltage lower than the drive power supply voltage by a level shift circuit, thereby enabling the fault detection circuit 50 to be configured as a circuit that uses low-voltage elements, has low power consumption, and has a reduced circuit area.

[0023] In FIG. 2, a first phase difference detection circuit (for example, phase difference detection circuit 51) is shown as a plurality of phase detection circuits, and a phase difference detection circuit 52 is shown as a second phase difference detection. The phase difference detection circuit 51 outputs a first phase difference measurement signal (for example, phase difference detection signal PF1 and phase difference detection signal PF2) having a pulse width corresponding to the magnitude of the phase difference between two drive signals (for example, drive signal Ds1 and drive signal Ds2) of adjacent phases among the plurality of drive signals. In addition, the phase difference detection circuit 52 outputs a second phase difference measurement signal (for example, phase difference detection signal PF3 and phase difference detection signal PF4) which has a phase delay relative to the drive signal to be compared in phase difference by the phase difference detection circuit 51 and has a pulse width corresponding to the magnitude of the phase difference between two drive signals (for example, drive signal Ds3 and drive signal Ds4) of adjacent phases.

[0024] Here, the phase difference detection signals PF1 to PF4 each include the following phase difference information. The phase difference detection signal PF1 is a first phase difference detection signal, and indicates, for a first drive signal (e.g., drive signal Ds1) of the multiple drive signals, and a second drive signal (e.g., drive signal Ds2) whose phase lags behind the first drive signal, the amount of phase lead of the second drive signal relative to the first drive signal. The phase difference detection signal PF2 is a second phase difference detection signal, and indicates the amount of phase lag of the second drive signal relative to the first drive signal.

[0025] Furthermore, the phase difference detection signal PF3 is a third phase difference detection signal, and indicates the amount of phase lead of the fourth drive signal relative to the third drive signal, for a third drive signal (e.g., drive signal Ds3) whose phase lags behind the second drive signal among the multiple drive signals, and a fourth drive signal (e.g., drive signal Ds4) whose phase lags behind the third drive signal. The phase difference detection signal PF4 is a fourth phase difference detection signal, and indicates the amount of phase lag of the fourth drive signal relative to the third drive signal.

[0026] Furthermore, the phase difference detection circuit 51 outputs a phase difference determination signal PF1 and a phase difference determination signal PF2 based on the magnitude of the phase difference between the falling timings of the first drive signal and the second drive signal, and the phase difference detection circuit 52 outputs a phase difference determination signal PF3 and a phase difference determination signal PF4 based on the magnitude of the phase difference between the falling timings of the third drive signal and the fourth drive signal.

[0027] A specific circuit of the phase difference detection circuits 51 and 52 shown in FIG. 2 will be described. The phase difference detection circuits 51 and 52 shown in FIG. 2 have the same circuit configuration, but different corresponding input and output signals. The phase difference detection circuit 51 has JK flip-flops 12 and 22 and an AND gate AND1. The JK flip-flops 12 and 22 have input terminals J and K, a clock input terminal, a set terminal S, a reset terminal R, and output terminals Q and Qb. A power supply voltage is applied to the input terminal J and the set terminal S of the JK flip-flop 12. A ground voltage is applied to the input terminal K of the JK flip-flop 12. A drive signal Ds1 whose amplitude is suppressed by the level shift circuit 11 is input to the clock input terminal of the JK flip-flop 12. A phase difference detection signal PF1 is output from the output terminal Q of the JK flip-flop 12. The output terminal Qb of the JK flip-flop 12 is in an open state.

[0028] A power supply voltage is applied to the input terminal J and the set terminal S of the JK flip-flop 22. A ground voltage is applied to the input terminal K of the JK flip-flop 22. A drive signal Ds2 whose amplitude has been suppressed by the level shift circuit 21 is input to the clock input terminal of the JK flip-flop 22. The output terminal Q of the JK flip-flop 22 outputs a phase difference detection signal PF2. The output terminal Qb of the JK flip-flop 22 is in an open state. The phase difference detection signals PF1 and PF2 are input to the AND gate AND1, which outputs the logical sum of the phase difference detection signals PF1 and PF2. The output signal of the AND gate AND1 is input to the reset terminals R of the JK flip-flops 12 and 22.

[0029] The phase difference detection circuit 52 has JK flip-flops 32 and 42 and an AND gate AND2. The JK flip-flops 32 and 42 have input terminals J and K, a clock input terminal, a set terminal S, a reset terminal R, and output terminals Q and Qb. A power supply voltage is applied to the input terminal J and the set terminal S of the JK flip-flop 32. A ground voltage is applied to the input terminal K of the JK flip-flop 32. A drive signal Ds3 whose amplitude has been suppressed by the level shift circuit 31 is input to the clock input terminal of the JK flip-flop 32. A phase difference detection signal PF3 is output from the output terminal Q of the JK flip-flop 32. The output terminal Qb of the JK flip-flop 32 is in an open state.

[0030] A power supply voltage is applied to the input terminal J and the set terminal S of the JK flip-flop 42. A ground voltage is applied to the input terminal K of the JK flip-flop 42. A drive signal Ds4 whose amplitude has been suppressed by the level shift circuit 41 is input to the clock input terminal of the JK flip-flop 42. The output terminal Q of the JK flip-flop 42 outputs a phase difference detection signal PF4. The output terminal Qb of the JK flip-flop 42 is in an open state. The phase difference detection signals PF3 and PF4 are input to the AND gate AND2, which outputs the logical sum of the phase difference detection signals PF3 and PF4. The output signal of the AND gate AND2 is input to the reset terminals R of the JK flip-flops 32 and 42.

[0031] Here, the JK flip-flop changes the value of the signal output from the output terminal Q in response to the falling edge of the signal input to the clock input terminal depending on the values ​​given to the input terminals J and K. Specifically, if a falling edge is input to the clock input terminal when 0 (e.g., ground voltage) is input to both input terminals J and K, the JK flip-flop maintains the value of the output terminal Q. If a falling edge is input to the clock input terminal when 1 (e.g., power supply voltage) is input to both input terminals J and K, the JK flip-flop inverts the value of the output terminal Q. If a falling edge is input to the clock input terminal when 0 is input to the input terminal J and 1 is input to the input terminal K, the JK flip-flop sets the value of the output terminal Q to 0. If a falling edge is input to the clock input terminal when 1 is input to the input terminal J and 0 is input to the input terminal K, the JK flip-flop sets the value of the output terminal Q to 1.

[0032] The phase difference detection circuits 51 and 52 using the JK flip-flops 12, 22, 32, and 42 that operate in this way transition the phase difference detection signals PF1 and PF3 from low level to high level in response to the falling edge of the drive signal on the phase leading side, and maintain the phase difference detection signals PF1 and PF3 from high level to low level in response to the falling edge of the drive signal on the phase leading side. Here, the phase difference detection circuits 51 and 52 raise the phase difference detection signals PF2 and PF4 in response to the falling edge of the drive signal on the phase leading side, but at the moment the phase difference detection signals PF2 and PF4 rise, the AND gates raise the reset terminals R of the JK flip-flops 12, 22, 32, and 42 to high level, so that the JK flip-flops 12, 22, 32, and 42 are reset, and the phase difference detection signals PF1 to PF4 become high level and low level. As a result, the phase difference detection signals PF2 and PF4 become spike-shaped waveforms that become high level but substantially maintain low level.

[0033] Each of the smoothing circuits 53-56 smoothes a pre-associated phase difference measurement signal and outputs a phase difference detection voltage having a voltage value according to the magnitude of the phase difference. The smoothing circuits 53-56 all have the same circuit configuration, and include a resistor arranged on a signal transmission line, and a capacitor provided between a wiring on the signal output end side of the resistor and a ground wiring. The smoothing circuits 53-56 output a phase difference detection voltage from the signal output end, the DC voltage of which is determined according to the duty ratio of the phase difference detection signal.

[0034] Specifically, the smoothing circuit 53 includes a resistor R1 having one end to which the phase difference detection signal PF1 is input and the other end serving as a signal output end, and a capacitor Cs1 connected between the signal output end of the resistor R1 and a ground line. The signal output by the smoothing circuit 53 becomes the phase difference detection voltage PF1s.

[0035] The smoothing circuit 54 has a resistor R2 having one end to which the phase difference detection signal PF2 is input and the other end serving as a signal output end, and a capacitor Cs2 connected between the signal output end of the resistor R2 and the ground wiring. The signal output by the smoothing circuit 54 becomes the phase difference detection voltage PF2s.

[0036] The smoothing circuit 55 includes a resistor R3 having one end to which the phase difference detection signal PF3 is input and the other end serving as a signal output end, and a capacitor Cs3 connected between the signal output end of the resistor R3 and the ground line. The signal output by the smoothing circuit 55 becomes the phase difference detection voltage PF3s.

[0037] The smoothing circuit 56 includes a resistor R4 having one end to which the phase difference detection signal PF4 is input and the other end serving as a signal output end, and a capacitor Cs4 connected between the signal output end of the resistor R4 and the ground line. The signal output by the smoothing circuit 56 becomes the phase difference detection voltage PF4s.

[0038] The error detection circuit 57 compares a plurality of phase difference detection voltages, and switches the abnormality detection signals (e.g., abnormality detection signals ER1, ER2) from an inactive state to an active state when a phase difference detection voltage having a voltage value exceeding a preset tolerance range is detected. Here, the error detection circuit 57 uses the preset tolerance range as a range where the voltages of the compared signals cannot be regarded as the same in the circuit when different phase difference detection voltages generated from phase difference detection signals having the same duty ratio are compared during normal operation in which no failure occurs in the switching power supplies 10 to 40.

[0039] Specifically, the error detection circuit 57 has comparison circuits 58 and 59. The comparison circuit 58 compares a phase difference detection voltage PF1s and a phase difference detection voltage PF2s generated from the phase difference detection signal PF1 and the phase difference detection signal PF2, which have the same duty ratio when the switching power supplies 10 to 40 are operating normally, and switches the signal level of the abnormality detection signal ER1. The comparison circuit 59 compares a phase difference detection voltage PF2s and a phase difference detection voltage PF4s generated from the phase difference detection signal PF2 and the phase difference detection signal PF4, which have the same duty ratio when the switching power supplies 10 to 40 are operating normally, and switches the signal level of the abnormality detection signal ER2. The comparison circuits 58 and 59 enable (high level) the abnormality detection signal that is output when the voltage difference between the two input voltages is outside the range that can be regarded as the same on the circuit, and disable (low level) the abnormality detection signal if the voltage difference between the two voltages is within the range that can be regarded as the same on the circuit.

[0040] As described above, the error detection circuit 57 compares the phase difference detection voltage PF1s obtained by smoothing the phase difference determination signal PF1 by the smoothing circuit 53 with the phase difference detection voltage PF3s obtained by smoothing the phase difference determination signal PF3 by the smoothing circuit 55, and switches a first abnormality detection signal (for example, the abnormality detection signal ER1) included in the abnormality detection signal from an invalid state to an valid state in response to a voltage difference occurring between the two phase difference detection voltages. Also, the error detection circuit 57 compares the phase difference detection voltage PF2s obtained by smoothing the phase difference determination signal PF2 by the smoothing circuit 54 with the phase difference detection voltage PF4s obtained by smoothing the phase difference determination signal PF4 by the smoothing circuit 56, and switches a second abnormality detection signal (for example, the abnormality detection signal ER2) included in the abnormality detection signal from an invalid state to an valid state in response to a voltage difference occurring between the two phase difference detection voltages.

[0041] Next, the operation of the fault detection circuit 50 according to the first embodiment will be described. In the following description, the operation of the fault detection circuit 50 will be described with reference to a timing chart of a period during which two cycles of the drive signal are output. In addition, the drive signals Ds1 to Ds4 have a duty ratio of 50% and a phase shift of 90° under normal conditions. In the timing chart described below, an example is shown in which the drive signal Ds1 of the basic phase (for example, 0°) rises at timings T1 and T5, the drive signal Ds2 delayed by 90° phase from the basic phase rises at timings T2 and T6, the drive signal Ds3 delayed by 180° phase from the basic phase rises at timings T3 and T7, and the drive signal Ds4 delayed by 270° phase from the basic phase rises at timings T4 and T8.

[0042] 3 shows a timing chart for explaining a first operation example of the fault detection circuit according to the embodiment 1. The first operation example is an operation of the fault detection circuit 50 when all of the switching power supplies 10 to 40 are operating normally.

[0043] As shown in FIG. 3, when all of the switching power supplies 10 to 40 are operating normally, in the fault detection circuit 50, the JK flip-flop 12 raises the phase difference detection signal PF1 in response to the falling edge of the drive signal Ds1. Also, in the fault detection circuit 50, the JK flip-flop 22 raises the phase difference detection signal PF2 in response to the falling edge of the drive signal Ds2. Then, when both the phase difference detection signal PF1 and the phase difference detection signal PF2 become high level, the AND gate AND1 switches the signal provided to the reset terminal R of the JK flip-flops 12 and 22 from low level to high level, so that the phase difference detection signal PF1 is switched from high level to low level in response to the rising edge of the phase difference detection signal PF2. Also, since the high level is input to the reset terminal R of the JK flip-flop 22 immediately after the phase difference detection signal PF2 rises, the phase difference detection signal PF2 immediately becomes low level and has a waveform that substantially maintains the low level.

[0044] Through such an operation, the phase difference detection signal PF1 becomes a signal with a duty ratio of 25%, and the phase difference detection signal PF2 maintains a low level and becomes a signal with a duty ratio of 0%. In the fault detection circuit 50, the phase difference detection signals PF1, PF2 are smoothed by smoothing circuits 53, 54 to generate phase difference detection voltages PF1s, PF2s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 3, the phase difference detection voltage PF1s becomes 3.3V x 0.25, and the phase difference detection voltage PF2s is maintained at 0.0V.

[0045] In the fault detection circuit 50, the JK flip-flop 32 raises the phase difference detection signal PF3 in response to the falling edge of the drive signal Ds3. In the fault detection circuit 50, the JK flip-flop 42 raises the phase difference detection signal PF4 in response to the falling edge of the drive signal Ds4. When the phase difference detection signal PF3 and the phase difference detection signal PF4 both become high level, the AND gate AND2 switches the signal provided to the reset terminal R of the JK flip-flops 32 and 42 from low level to high level, so that the phase difference detection signal PF3 is switched from high level to low level in response to the rising edge of the phase difference detection signal PF4. In addition, since a high level is input to the reset terminal R of the JK flip-flop 42 immediately after the phase difference detection signal PF4 rises, the phase difference detection signal PF4 immediately becomes low level and has a waveform that substantially maintains the low level.

[0046] Through such an operation, the phase difference detection signal PF3 becomes a signal with a duty ratio of 25%, and the phase difference detection signal PF4 maintains a low level and becomes a signal with a duty ratio of 0%. In the fault detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 3, the phase difference detection voltage PF3s becomes 3.3V x 0.25, and the phase difference detection voltage PF4s is maintained at 0.0V.

[0047] In the failure detection circuit 50, the phase difference detection voltages PF1s and PF3s input to the comparison circuit 58 of the error detection circuit 57 are the same voltage, so the abnormality detection signal ER1 is at a low level. Also, the phase difference detection voltages PF2s and PF4s input to the comparison circuit 59 are the same voltage, so the abnormality detection signal ER2 is at a low level. In this way, the failure detection circuit 50 sets both of the abnormality detection signals ER1 and ER2 to a low level if no failure occurs in the switching power supplies 10 to 40.

[0048] Next, since the failure detection circuit 50 can detect failures for a plurality of failure modes, the following description will use timing charts to explain the operation of each failure mode that the failure detection circuit 50 can handle.

[0049] 4 shows a timing chart for explaining a second operation example of the fault detection circuit according to the embodiment 1. The second operation example is an example in which a short-to-power fault occurs in which the output terminal that outputs the drive signal Ds4 is stuck to the power supply source side.

[0050] As shown in FIG. 4, in this case, the operations of the phase difference detection circuit 51 and the smoothing circuits 53 and 54 which generate the phase difference detection voltages PF1s and PF2 for comparing the phase difference between the drive signals Ds1 and Ds2 are the same as those in the timing chart shown in FIG. 3, and therefore will not be described here.

[0051] On the other hand, if a short-to-power fault occurs at the output terminal of the drive signal Ds4, the drive signal Ds4 will maintain a high level. Therefore, when a rising edge of the drive signal Ds3 is input at a timing not shown (for example, the timing of the fault occurrence), the JK flip-flop 32 sets the phase difference detection signal PF3 to a high level, and the logical value level is maintained thereafter. This is because the JK flip-flops 32 and 42 are not reset because no falling edge occurs in the drive signal Ds4.

[0052] With this operation, the phase difference detection signal PF3 maintains a high level and becomes a signal with a duty ratio of 100%, and the phase difference detection signal PF4 maintains a low level and becomes a signal with a duty ratio of 0%. In the fault detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 4, the phase difference detection voltage PF3s becomes 3.3V, and the phase difference detection voltage PF4s maintains 0.0V.

[0053] In the fault detection circuit 50, a deviation has occurred in the phase difference detection voltages PF1s, PF3s input to the comparison circuit 58 of the error detection circuit 57, so the abnormality detection signal ER1 is set to a high level. Also, since the phase difference detection voltages PF2s, PF4s input to the comparison circuit 59 are the same voltage, the abnormality detection signal ER2 is set to a low level. In this way, when a short-to-power fault has occurred in the switching power supply 40, the fault detection circuit 50 sets the abnormality detection signal ER1 to a high level and the abnormality detection signal ER2 to a low level.

[0054] 5 shows a timing chart for explaining a third operation example of the fault detection circuit according to the first embodiment. The third operation example is an example in which a ground fault occurs in which the output terminal for outputting the drive signal Ds4 is stuck to the ground voltage supply source side.

[0055] As shown in Figure 5, in this case, the operations of the phase difference detection circuit 51 and the smoothing circuits 53 and 54 which generate phase difference detection voltages PF1s and PF2 for comparing the phase difference between the drive signals Ds1 and Ds2 are the same as those in the timing chart shown in Figure 3, and therefore will not be described here.

[0056] On the other hand, if a ground fault occurs at the output terminal of the drive signal Ds4, the drive signal Ds4 will maintain a low level. Therefore, when a rising edge of the drive signal Ds3 is input at a timing not shown (for example, the timing of the fault occurrence), the JK flip-flop 32 sets the phase difference detection signal PF3 to a high level, and the logical value level is maintained thereafter. This is because the JK flip-flops 32 and 42 are not reset because no falling edge occurs in the drive signal Ds4.

[0057] With this operation, the phase difference detection signal PF3 maintains a high level and becomes a signal with a duty ratio of 100%, and the phase difference detection signal PF4 maintains a low level and becomes a signal with a duty ratio of 0%. In the fault detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 5, the phase difference detection voltage PF3s becomes 3.3V, and the phase difference detection voltage PF4s maintains 0.0V.

[0058] In the fault detection circuit 50, a deviation has occurred in the phase difference detection voltages PF1s, PF3s input to the comparison circuit 58 of the error detection circuit 57, so the abnormality detection signal ER1 is set to a high level. Also, since the phase difference detection voltages PF2s, PF4s input to the comparison circuit 59 are the same voltage, the abnormality detection signal ER2 is set to a low level. In this way, when a short-to-power fault has occurred in the switching power supply 40, the fault detection circuit 50 sets the abnormality detection signal ER1 to a high level and the abnormality detection signal ER2 to a low level.

[0059] 6 shows a timing chart for explaining a fourth operation example of the fault detection circuit according to the first embodiment. The fourth operation example is an example in which an output voltage abnormality occurs in which the duty ratio of the drive signal Ds4 is larger than those of the other drive signals.

[0060] As shown in Figure 6, in this case, the operations of the phase difference detection circuit 51 and the smoothing circuits 53 and 54 which generate phase difference detection voltages PF1s and PF2 for comparing the phase difference between the drive signals Ds1 and Ds2 are the same as those in the timing chart shown in Figure 3, and therefore will not be described here.

[0061] On the other hand, in the example shown in FIG. 6, a duty abnormality occurs such that the falling timing of the drive signal Ds4 becomes slower than that during normal operation. As a result, in the fault detection circuit 50, a delay occurs in the timing at which the JK flip-flops 32 and 42 are reset, and the period during which the phase difference detection signal PF3 is at a high level becomes longer. That is, in the example shown in FIG. 6, the duty ratio of the phase difference detection signal PF3 becomes larger than those of the other drive signals. In the example shown in FIG. 6, the phase difference detection signal PF3 has a duty ratio of 37.5%. Note that, in the example shown in FIG. 6, the phase difference detection signal PF4 maintains a low level as in the example shown in FIG. 3, and becomes a signal with a duty ratio of 0%.

[0062] In the failure detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 6, the phase difference detection voltage PF3s is 3.3V x 0.375, and the phase difference detection voltage PF4s is maintained at 0.0V.

[0063] In the fault detection circuit 50, a deviation has occurred in the phase difference detection voltages PF1s, PF3s input to the comparison circuit 58 of the error detection circuit 57, so the abnormality detection signal ER1 is set to a high level. Also, since the phase difference detection voltages PF2s, PF4s input to the comparison circuit 59 are the same voltage, the abnormality detection signal ER2 is set to a low level. In this way, when an output voltage abnormality occurs in which only the drive signal Ds4 has a large duty ratio, the fault detection circuit 50 sets the abnormality detection signal ER1 to a high level and the abnormality detection signal ER2 to a low level.

[0064] 7 shows a timing chart for explaining a fifth operation example of the fault detection circuit according to the first embodiment. The fifth operation example is an example in which an output voltage abnormality occurs in which the duty ratio of the drive signal Ds4 is smaller than those of the other drive signals.

[0065] As shown in Figure 7, in this case, the operations of the phase difference detection circuit 51 and the smoothing circuits 53 and 54 which generate phase difference detection voltages PF1s and PF2 for comparing the phase difference between the drive signals Ds1 and Ds2 are the same as those in the timing chart shown in Figure 3, and therefore will not be described here.

[0066] On the other hand, in the example shown in FIG. 7, a duty abnormality occurs such that the falling timing of the drive signal Ds4 becomes earlier than that during normal operation. As a result, in the fault detection circuit 50, the timing at which the JK flip-flops 32 and 42 are reset becomes earlier, and the period during which the phase difference detection signal PF3 is at a high level becomes shorter. That is, in the example shown in FIG. 7, the duty ratio of the phase difference detection signal PF3 becomes smaller than those of the other drive signals. In the example shown in FIG. 7, the phase difference detection signal PF3 has a duty ratio of 12.5%. Note that, in the example shown in FIG. 7, the phase difference detection signal PF4 maintains a low level as in the example shown in FIG. 3, and becomes a signal with a duty ratio of 0%.

[0067] In the failure detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 7, the phase difference detection voltage PF3s is 3.3V x 0.125, and the phase difference detection voltage PF4s is maintained at 0.0V.

[0068] In the fault detection circuit 50, a deviation has occurred in the phase difference detection voltages PF1s, PF3s input to the comparison circuit 58 of the error detection circuit 57, so the abnormality detection signal ER1 is set to a high level. Also, since the phase difference detection voltages PF2s, PF4s input to the comparison circuit 59 are the same voltage, the abnormality detection signal ER2 is set to a low level. In this way, when an output voltage abnormality occurs in which only the drive signal Ds4 has a small duty ratio, the fault detection circuit 50 sets the abnormality detection signal ER1 to a high level and the abnormality detection signal ER2 to a low level.

[0069] 8 shows a timing chart for explaining a sixth operation example of the fault detection circuit according to the first embodiment. The sixth operation example is an example in which an oscillation abnormality occurs in which the frequency of the drive signal Ds4 becomes high.

[0070] As shown in Figure 8, in this case, the operations of the phase difference detection circuit 51 and the smoothing circuits 53 and 54 which generate phase difference detection voltages PF1s and PF2 for comparing the phase difference between the drive signals Ds1 and Ds2 are the same as those in the timing chart shown in Figure 3, and therefore will not be described here.

[0071] On the other hand, the example shown in Fig. 8 is an example in which the frequency of the drive signal Ds4 is approximately twice that of the drive signal Ds3, and the fall timings of the drive signals Ds3 and Ds4 are approximately simultaneous. Therefore, in the example shown in Fig. 8, the phase difference detection signal PF3 has a waveform that rises only for an instant. Note that, in the example shown in Fig. 8, the phase difference detection signal PF4 maintains a low level as in the example shown in Fig. 3, and becomes a signal with a duty ratio of 0%.

[0072] In the fault detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 8, the phase difference detection voltage PF3s is substantially about 0.0 V because the duty ratio of the phase difference detection signal PF3 is extremely small, and the phase difference detection voltage PF4s is maintained at 0.0 V.

[0073] In the fault detection circuit 50, a deviation has occurred in the phase difference detection voltages PF1s, PF3s input to the comparison circuit 58 of the error detection circuit 57, so the abnormality detection signal ER1 is set to a high level. Also, since the phase difference detection voltages PF2s, PF4s input to the comparison circuit 59 are the same voltage, the abnormality detection signal ER2 is set to a low level. In this way, when an oscillation abnormality has occurred in which the frequency of the drive signal Ds4 deviates from the other drive signals, the fault detection circuit 50 sets the abnormality detection signal ER1 to a high level and the abnormality detection signal ER2 to a low level.

[0074] 9 shows a timing chart for explaining a seventh operation example of the fault detection circuit according to the embodiment 1. The seventh operation example is an example in which an oscillation abnormality occurs in which the frequency of the drive signal Ds4 decreases.

[0075] As shown in Figure 9, in this case, the operations of the phase difference detection circuit 51 and the smoothing circuits 53 and 54 which generate the phase difference detection voltages PF1s and PF2 for comparing the phase difference between the drive signals Ds1 and Ds2 are the same as those in the timing chart shown in Figure 3, so their explanation will be omitted here.

[0076] On the other hand, the example shown in Fig. 9 is an example in which the frequency of the drive signal Ds4 is approximately half that of the drive signal Ds3. In the example shown in Fig. 9, the phase difference detection signal PF3 rises at the falling edge of the drive signal Ds3 at timing T1, and maintains a high level until the falling edge of the drive signal Ds4 at timing T7. As a result, in the example shown in Fig. 8, the duty ratio of the phase difference detection signal PF3 is 75%. Note that in the example shown in Fig. 8, the phase difference detection signal PF4 also maintains a low level as in the example shown in Fig. 3, and becomes a signal with a duty ratio of 0%.

[0077] In the failure detection circuit 50, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 8, the phase difference detection voltage PF3s is 3.3V x 0.75, and the phase difference detection voltage PF4s is maintained at 0.0V.

[0078] In the fault detection circuit 50, a deviation has occurred in the phase difference detection voltages PF1s, PF3s input to the comparison circuit 58 of the error detection circuit 57, so the abnormality detection signal ER1 is set to a high level. Also, since the phase difference detection voltages PF2s, PF4s input to the comparison circuit 59 are the same voltage, the abnormality detection signal ER2 is set to a low level. In this way, when an oscillation abnormality has occurred in which the frequency of the drive signal Ds4 deviates from the other drive signals, the fault detection circuit 50 sets the abnormality detection signal ER1 to a high level and the abnormality detection signal ER2 to a low level.

[0079] As described above, by using the fault detection circuit 50 according to the first embodiment, it is possible to detect short circuit faults, output voltage abnormalities (duty ratio abnormalities of drive signals), and oscillation abnormalities that occur in the switching power supplies 10 to 40 constituting the multiphase power supply device 1. As a result, in the multiphase power supply device 1, the operation mode is switched when an abnormality is detected, thereby improving safety.

[0080] In the above explanation, the fault detection circuit 50 is applied to a four-phase drive multiphase power supply device 1. However, by changing the number of phase difference detection circuits and smoothing circuits in the fault detection circuit 50 and the combination of drive signals input to one phase difference detection circuit, it is also possible to accommodate, for example, a three-phase drive multiphase power supply device or a multiphase power supply device with five or more phase drive signals.

[0081] Embodiment 2 In the second embodiment, a fault detection circuit 60 will be described which is another embodiment of the fault detection circuit 50 according to the first embodiment. In the description of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof will be omitted.

[0082] Fig. 10 shows a block diagram of a fault detection circuit 60 according to the second embodiment. As shown in Fig. 10, the fault detection circuit 60 according to the second embodiment is obtained by replacing the phase difference detection circuits 51 and 52 of the fault detection circuit 50 according to the first embodiment with phase difference detection circuits 61 and 62. Moreover, the phase difference detection circuits 61 and 62 are obtained by replacing the JK flip-flops of the phase difference detection circuits 51 and 52 with D flip-flops. Even if the JK flip-flops are changed to D flip-flops in this way, the same operation as the fault detection circuit 50 according to the first embodiment can be performed.

[0083] Moreover, a rising edge triggered D flip-flop is used as the D flip-flop in the failure detection circuit 60. In this way, by using a rising edge triggered flip-flop, it is possible to generate a phase difference detection signal according to the magnitude of the phase difference between two signals on the rising edge side.

[0084] 6, the phase difference detection circuit 61 has D flip-flops 13 and 23, and an AND gate AND1. The D flip-flop 13 has an input terminal D given a power supply voltage, and a reset terminal R given the output of the AND gate AND1. In addition, a drive signal Ds1 whose amplitude has been reduced by the level shift circuit 11 is input to a clock input terminal of the D flip-flop 13. Then, the D flip-flop 13 outputs a phase difference detection signal PF1 from an output terminal Q.

[0085] A power supply voltage is applied to an input terminal D of the D flip-flop 23, and the output of the AND gate AND1 is applied to a reset terminal R. A drive signal Ds2 whose amplitude has been reduced by the level shift circuit 21 is input to a clock input terminal of the D flip-flop 23. The D flip-flop 23 outputs a phase difference detection signal PF2 from an output terminal Q.

[0086] The phase difference detection circuit 62 has D flip-flops 33 and 43, and an AND gate AND2. The D flip-flop 33 has an input terminal D given with a power supply voltage, and a reset terminal R given with the output of the AND gate AND2. In addition, the drive signal Ds3, the amplitude of which has been reduced by the level shift circuit 31, is input to the clock input terminal of the D flip-flop 33. Then, the D flip-flop 33 outputs a phase difference detection signal PF3 from its output terminal Q.

[0087] A power supply voltage is applied to an input terminal D of the D flip-flop 43, and the output of the AND gate AND2 is applied to a reset terminal R. A drive signal Ds4 whose amplitude has been reduced by the level shift circuit 41 is input to a clock input terminal of the D flip-flop 43. The D flip-flop 43 outputs a phase difference detection signal PF4 from an output terminal Q.

[0088] Next, the operation of the fault detection circuit 60 according to the second embodiment will be described. Note that the operation of the fault detection circuit 60 is to change the duty ratio of the phase difference detection signal based on the phase difference on the rising edge side of the drive signal, and the change in the duty ratio of the phase difference detection signal conforms to that of the fault detection circuit 50. Therefore, only the case where the multiphase power supply device 1 is operating normally will be described below.

[0089] 11 shows a timing chart for explaining a first operation example of the failure detection circuit according to embodiment 2. This first operation example is an operation of the failure detection circuit 50 when all of the switching power supplies 10 to 40 are operating normally.

[0090] As shown in FIG. 11, when all of the switching power supplies 10 to 40 are operating normally, in the fault detection circuit 60, the D flip-flop 13 raises the phase difference detection signal PF1 in response to the rising edge of the drive signal Ds1. Also, in the fault detection circuit 60, the D flip-flop 23 raises the phase difference detection signal PF2 in response to the rising edge of the drive signal Ds2. Then, when both the phase difference detection signal PF1 and the phase difference detection signal PF2 are at high levels, the AND gate AND1 switches the signal provided to the reset terminals R of the D flip-flops 13 and 23 from low level to high level, so that the phase difference detection signal PF1 is switched from high level to low level in response to the rising edge of the phase difference detection signal PF2. Also, since a high level is input to the reset terminal R of the D flip-flop 23 immediately after the phase difference detection signal PF2 rises, the phase difference detection signal PF2 immediately becomes low level and has a waveform that substantially maintains the low level.

[0091] Through such an operation, the phase difference detection signal PF1 becomes a signal with a duty ratio of 25%, and the phase difference detection signal PF2 maintains a low level and becomes a signal with a duty ratio of 0%. In the fault detection circuit 60, the phase difference detection signals PF1, PF2 are smoothed by the smoothing circuits 53, 54 to generate phase difference detection voltages PF1s, PF2s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 11, the phase difference detection voltage PF1s becomes 3.3V x 0.25, and the phase difference detection voltage PF2s is maintained at 0.0V.

[0092] In the fault detection circuit 60, the D flip-flop 13 raises the phase difference detection signal PF3 in response to the rising edge of the drive signal Ds3. In the fault detection circuit 60, the D flip-flop 43 raises the phase difference detection signal PF4 in response to the rising edge of the drive signal Ds4. When the phase difference detection signals PF3 and PF4 both become high level, the AND gate AND2 switches the signal provided to the reset terminals R of the D flip-flops 33 and 43 from low level to high level, so that the phase difference detection signal PF3 is switched from high level to low level in response to the rising edge of the phase difference detection signal PF4. In addition, since a high level is input to the reset terminal R of the D flip-flop 43 immediately after the phase difference detection signal PF4 rises, the phase difference detection signal PF4 immediately becomes low level and has a waveform that substantially maintains the low level.

[0093] Through such an operation, the phase difference detection signal PF3 becomes a signal with a duty ratio of 25%, and the phase difference detection signal PF4 maintains a low level and becomes a signal with a duty ratio of 0%. In the fault detection circuit 60, the phase difference detection signals PF3 and PF4 are smoothed by the smoothing circuits 55 and 56 to generate phase difference detection voltages PF3s and PF4s having voltage values ​​obtained by multiplying the power supply voltage by the duty ratio. In the example shown in Fig. 11, the phase difference detection voltage PF3s becomes 3.3V x 0.25, and the phase difference detection voltage PF4s is maintained at 0.0V.

[0094] In the fault detection circuit 60, the phase difference detection voltages PF1s and PF3s input to the comparison circuit 58 of the error detection circuit 57 are the same voltage, so the abnormality detection signal ER1 is at a low level. Also, the phase difference detection voltages PF2s and PF4s input to the comparison circuit 59 are the same voltage, so the abnormality detection signal ER2 is at a low level. In this way, the fault detection circuit 50 sets both of the abnormality detection signals ER1 and ER2 to a low level if no fault has occurred in the switching power supplies 10 to 40.

[0095] As described above, the fault detection circuit 60 is a circuit that uses D flip-flops instead of JK flip-flops and achieves the same operation as the fault detection circuit 50 according to the first embodiment. Furthermore, the fault detection circuit 60 uses rising edge triggered flip-flops, making it possible to detect the phase difference on the rising edge side of the drive signal.

[0096] In the above explanation, an example has been described in which fault detection is performed by separately detecting the phase difference on the falling edge side and the phase difference on the rising edge side of the drive signal. However, the fault detection circuit 50 according to the first embodiment and the fault detection circuit 60 may be combined to detect the phase difference between two drive signals on both the falling edge side and the rising edge side.

[0097] The present disclosure is not limited to the above-described embodiment, and can be appropriately modified without departing from the spirit and scope of the present disclosure. In addition, the present disclosure includes implementation in which the examples in the above-described embodiment are appropriately combined. [Explanation of symbols]

[0098] 1 Multiphase Power Supply 10, 20, 30, 40 Switching power supply 11, 21, 31, 41 Level shift circuit 12, 22, 32, 42 JK Flip Flops 13, 23, 33, 43 D Flip Flops 50, 60 Fault detection circuit 51, 52, 61, 62 Phase difference detection circuit 53~56 Smoothing circuit 57 Error detection circuit 58, 59 Comparison circuit MCU-driven processor PM drive control unit AND1, AND2 AND gates R1~R4 resistance Cs1~Cs4 capacitors Cd Decoupling capacitor TU Power Transistor TL Power Transistor L Inductor Co Output capacitor Ds1~Ds4 drive signal PF1~PF4 Phase difference detection signal PF1s~PF4s Phase difference detection voltage PWR power supply LD load circuit ER1, ER2 Abnormality detection signal

Claims

1. A fault detection circuit for detecting an abnormality in a drive signal of a plurality of drive circuits, each of which drives a load circuit connected in series between an output terminal and a ground wiring, using drive signals having mutually different phases, the fault detection circuit comprising: a plurality of phase difference detection circuits each generating a phase difference measurement signal having a pulse width corresponding to the magnitude of a phase difference between two of the plurality of drive signals having different phases; a plurality of smoothing circuits each smoothing the corresponding phase difference measurement signal and outputting a phase difference detection voltage having a voltage value corresponding to the magnitude of the phase difference; an error detection circuit that compares a plurality of the phase difference detection voltages and switches an abnormality detection signal from an invalid state to an valid state when the phase difference detection voltage has a voltage value exceeding a preset allowable range; The plurality of phase difference detection circuits include a first phase difference detection circuit that outputs a first phase difference measurement signal having a pulse width corresponding to the magnitude of a phase difference between two of the plurality of drive signals having adjacent phases; a second phase difference detection circuit that outputs a second phase difference measurement signal that is delayed in phase with respect to the drive signal that is the subject of phase difference comparison in the first phase difference detection circuit and has a pulse width that corresponds to the magnitude of the phase difference between two drive signals that are adjacent in phase; the first phase difference detection circuit outputs, as the first phase difference measurement signals, a first phase difference determination signal indicating a phase lead amount of the second drive signal relative to the first drive signal and a second drive signal having a phase delay relative to the first drive signal, for a first drive signal among the plurality of drive signals and a second drive signal having a phase delay relative to the first drive signal; the second phase difference detection circuit outputs, as the second phase difference measurement signals, a third phase difference determination signal indicating a phase lead amount of the fourth drive signal relative to the third drive signal and a fourth drive signal indicating a phase delay amount of the fourth drive signal relative to the third drive signal, for a third drive signal among the plurality of drive signals that is delayed in phase from the second drive signal and a fourth drive signal that is delayed in phase from the third drive signal; The error detection circuit includes: a first phase difference detection voltage obtained by smoothing the first phase difference determination signal using one of the plurality of smoothing circuits is compared with a third phase difference detection voltage obtained by smoothing the third phase difference determination signal using one of the plurality of smoothing circuits, and in response to a voltage difference occurring between the two phase difference detection voltages, a first abnormality detection signal included in the abnormality detection signal is switched from an invalid state to an valid state; a fault detection circuit which compares a second phase difference detection voltage obtained by smoothing the second phase difference determination signal using one of the plurality of smoothing circuits with a fourth phase difference detection voltage obtained by smoothing the fourth phase difference determination signal using one of the plurality of smoothing circuits, and switches a second abnormality detection signal included in the abnormality detection signal from an invalid state to an valid state in response to a voltage difference occurring between the two phase difference detection voltages.

2. the first phase difference detection circuit outputs the first phase difference determination signal and the second phase difference determination signal based on one of a magnitude of a phase difference between a falling timing of the first drive signal and the second drive signal and a magnitude of a phase difference between a rising timing of the first drive signal and the second drive signal; 2. The fault detection circuit according to claim 1, wherein the second phase difference detection circuit outputs the third phase difference determination signal and the fourth phase difference determination signal based on one of the magnitude of a phase difference between the falling timings of the third drive signal and the fourth drive signal and the magnitude of a phase difference between the rising timings of the third drive signal and the fourth drive signal.

3. 2. The fault detection circuit according to claim 1, further comprising a level shift circuit provided in a stage preceding the plurality of phase difference detection circuits, for suppressing an amplitude of the drive signal to be equal to or lower than an operating power supply voltage of the plurality of phase difference detection circuits.

4. 2. The fault detection circuit of claim 1, wherein the drive signal is a square wave signal.

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