Semiconductor Device

Abstract

In the present invention, an n+-type source region (4), a low-concentration region (5), and a p++-type contact region (6) are selectively provided on the surface region of the front surface of a semiconductor substrate (30), and are in contact with a source electrode. The n+-type source region (4) and the low-concentration region (5) are in contact with a gate-insulating film (8) on the side wall of a trench (7), and adjoin a channel part of a p-type base region in a depth direction (Z). The p++-type contact region (6) is disposed away from the trench (7). In the surface region of an epitaxial layer (33) which becomes the p-type base region, the n--type or p--type low concentration region (5) is configured by the portion left without forming the n+-type source region (4) and the p++-type contact region (6). The low concentration region (5) is periodically disposed along the side wall of the trench (7) between the p++-type contact region (6) and the trench (7). Using such a structure, it is possible to increase the short circuit tolerance without increasing the number of steps.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS field effect transistors with an insulated gate made of a three-layer structure of metal-oxide-semiconductor) are optimally designed to reduce the saturation current value in order to suppress short circuit current. The short circuit current is the drain-source current that flows when the load or arm is short circuited, and it is a large current that exceeds the rated current. The saturation current value is the saturation value of the drain-source current that is determined depending on the gate-source voltage.

[0003] Generally, the p-type base region has a channel (n-type inversion layer) formed in the p-type base region, and the p-type impurity concentration is lower than that of the p-type base region. - By arranging a low-concentration region to make it easier to pinch off the channel, the time until the drain-source current is cut off is shortened, and the saturation current value is set small. In addition, the saturation current value is set small by utilizing the shape and impurity concentration gradient of the n-type JFET (junction FET) region formed adjacent to the channel in the current path of the drift current that flows between the drain and source in the on-state.

[0004] Using the shape of the JFET region means determining the width of the JFET region so that the width of the JFET region (the width of part of the current path of the drift current) becomes narrower. + This involves appropriately setting the arrangement of the dopant regions. Utilizing the impurity concentration gradient in the JFET region means setting the n-type impurity concentration in the JFET region lower than the p-type impurity concentration in the channel. By optimally designing the JFET region, the JFET region becomes more easily depleted when a positive voltage (forward voltage) is applied to the drain electrode relative to the source electrode, thereby reducing the saturation current value.

[0005] The structure of a conventional MOSFET will be described by taking as an example a vertical MOSFET with a trench gate structure using silicon carbide (SiC) as a semiconductor material. FIG. 6 is a perspective view showing the structure of a conventional semiconductor device. + type source region 104 and p ++ 7 is a plan view showing the layout of a conventional semiconductor device as viewed from the front surface side of a semiconductor substrate. + type source region 104 and p ++ The layout of the mold contact area 106 is shown.

[0006] 6 and 7 is a vertical MOSFET having a trench gate structure on the front surface side of a semiconductor substrate 130 made of silicon carbide. - The trench gate structure includes epitaxial layers that become the p-type drift region 102 and the p-type base region 103, and the main surface on the p-type epitaxial layer side that becomes the p-type base region 103 is defined as the front surface. + type source region 104, p ++ It is composed of a mold contact region 106 , a trench 107 , a gate insulating film 108 and a gate electrode 109 .

[0007] The trenches 107 are arranged in a stripe shape extending in a first direction X (the vertical direction in FIG. 7) parallel to the front surface of the semiconductor substrate 130. + type source region 104 and p ++ The n-type contact regions 106 are selectively provided between the front surface of the semiconductor substrate 130 and the p-type base region 103. + The source region 104 contacts the gate insulating film 108 on the side wall of the trench 107. ++ The contact region 106 is located away from the trench 107 and has an n + The source region 104 is provided adjacent to the source region 104 .

[0008] Between the adjacent trenches 107, p ++ The contact regions 106 are arranged in a first direction X.+ The source region 104 is p ++ The contact region 106 is surrounded by a ladder-like planar shape. + type source region 104 and p ++ The contact regions 106 are alternately and repeatedly arranged adjacent to each other in the first direction X. + The p type source region 104 is made up of a portion that extends linearly in the first direction X in contact with the gate insulating film 108 on the sidewall of the trench 107 and a p ++ and a portion sandwiched between the mold contact regions 106.

[0009] Therefore, the trench gate structure has n + The n-type source region 104, the p-type base region 103, and the n-type current diffusion region 123 are in contact with the gate insulating film 108 and extend in the first direction X. + type source region 104 and p ++ The contact regions 106 are each a diffusion region selectively formed by ion implantation in a surface region of the front surface of the semiconductor substrate 130. + The n-type regions 121 and 122 are located closer to the bottom of the trench 107 than the n-type regions 121 and 122. + The gate insulating film 111 is disposed at a deep position on the side of the type drain region (not shown).

[0010] In a conventional vertical MOSFET with a trench gate structure, the source region is + A type source region, + A device has been proposed that is configured with an n-type source region between a p-type source region and an n-type source region between a p-type base region (see, for example, Patent Document 1 below). In Patent Document 1 below, depletion is caused to penetrate widely into the n-type source region, which has a relatively low impurity concentration in the source region, making it difficult for drift current to flow, thereby reducing the saturation current value when the load is short-circuited and improving the short-circuit resistance.

[0011] Another vertical MOSFET with a conventional trench gate structure is the n + Type source region and p +A device has been proposed in which a part of a p-type base region is disposed between a contact region and a trench, and an n-type shunt resistor region is disposed between these regions and a channel formed in the remaining part of the p-type base region (see, for example, Patent Document 2 below). In Patent Document 2 below, in the event of an abnormality in which a drift current exceeding the rated current flows, the on-resistance is increased by the resistance value of the n-type shunt resistor region compared to the rated current, thereby improving short-circuit resistance.

[0012] Also, as another vertical MOSFET with a conventional trench gate structure, a device has been proposed in which an n-type source region is formed by ion implantation of phosphorus (P) only in a portion facing the channel in the depth direction, and the remaining portion is formed by ion implantation of arsenic (As) (see, for example, Patent Document 3 below). In Patent Document 3 below, phosphorus, which has a larger range and reaches deeper positions than arsenic, is used to make the n-type source region relatively deeper in the portion facing the channel in the depth direction, thereby shortening the channel length and improving the element characteristics.

[0013] In addition, as a vertical MOSFET with a conventional planar gate structure, a p-type base region and an n - Between the p-type drift region and the n-type base region, the n-type drift region is located farther from the JFET region than the p-type base region. - The n-type drift region has a lower impurity concentration than the - A device having a low concentration region has been proposed (see, for example, Patent Document 4 below). In Patent Document 4 below, - The depletion layer extending into the n-type drift region - The low concentration region deforms the semiconductor, preventing localized electric field concentration on the current path of the drift current and suppressing localized heat generation, thereby improving the short circuit resistance.

[0014] Also, as another vertical MOSFET with a conventional trench gate structure, a device has been proposed in which the impurity concentration of the n-type source region is relatively low on the trench side and relatively high in a portion away from the trench (see, for example, Patent Document 5 below). In Patent Document 5 below, the leak current density of the gate insulating film is kept low in the portion of the source region with a relatively low impurity concentration, and good contact (electrical contact portion) with the source electrode is formed in the portion with a relatively high impurity concentration.

[0015] In addition, as another vertical MOSFET with a conventional planar gate structure, + A device has been proposed in which the portion functioning as a channel between the source region and the JFET region has a lower p-type impurity concentration than the p-type base region, and the ratio of n-type impurities to p-type impurities is higher than that of the p-type base region (see, for example, Patent Document 6 below). + The gate threshold voltage is adjusted in the portion that functions as the channel between the type source region and the JFET region to improve electron mobility. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] JP 2020-141130 A [Patent Document 2] JP 2020-077800 A [Patent Document 3] Patent No. 6880669 [Patent Document 4] JP 2020-047782 A [Patent Document 5] JP 2012-191056 A [Patent Document 6] JP 2015-032674 A Summary of the Invention [Problem to be solved by the invention]

[0017] However, in the conventional semiconductor device 110 (see FIGS. 6 and 7), when the saturation current value is set to a small value, the trench gate structure causes the following problem. - When the saturation current value is set to be small by disposing a low concentration region, a p-type low concentration region is provided in a portion 103a of the p-type base region 103 where a channel is formed. - It is necessary to add an epitaxial growth step and an ion implantation step for forming a low concentration region (not shown), which increases the number of steps and leads to increased costs.

[0018] As mentioned above, the JFET region (adjacent p + When the saturation current value is set to a small value by utilizing the shape or impurity concentration gradient of the portion between the n-type regions 121 and 122, the on-resistance increases rapidly, and the electrical characteristics are sacrificed. + A special shape is used to obtain a desired saturation current value at the deep part on the side of the drain region (not shown). + Forming the mold regions 121 and 122 requires complicated steps and the preparation of an expensive ion implantation device capable of implanting ions at high acceleration energy, leading to increased costs.

[0019] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a semiconductor device capable of improving short-circuit resistance without increasing the number of steps. [Means for solving the problem]

[0020] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A trench penetrates the second semiconductor region from the first main surface of the semiconductor substrate in the depth direction and terminates inside the first semiconductor region. A gate electrode is provided inside the trench via a gate insulating film. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. The third semiconductor region is in contact with the gate insulating film on the sidewall of the trench. A fourth semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region.

[0021] The fourth semiconductor region is in contact with the gate insulating film on the sidewall of the trench. A fifth semiconductor region of a second conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, away from the trench. The fifth semiconductor region has a higher impurity concentration than the second semiconductor region. A first electrode is in contact with the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. A second electrode is in contact with the second main surface of the semiconductor substrate. The fourth semiconductor region is a first conductivity type region having a lower first conductivity type impurity concentration than the third semiconductor region, or a second conductivity type region having a lower second conductivity type impurity concentration than a portion of the second semiconductor region along the sidewall of the trench.

[0022] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the fourth semiconductor regions are periodically arranged along the sidewall of the trench in a direction parallel to the first main surface of the semiconductor substrate.

[0023] Moreover, in the semiconductor device according to the present invention, the fourth semiconductor region is disposed between the fifth semiconductor region and the trench.

[0024] In the semiconductor device according to the present invention, the impurity concentration of the fourth semiconductor region is 1×10 14 / cm 3 More than 1×10 18 / cm 3 It is characterized by being within the following range.

[0025] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the fourth semiconductor region is the first conductivity type region and has a first conductivity type impurity concentration distribution in which the impurity concentration is highest at the first main surface of the semiconductor substrate and decreases toward the second main surface of the semiconductor substrate.

[0026] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the fourth semiconductor region is the second conductivity type region and has a second conductivity type impurity concentration distribution in which the impurity concentration is lowest at the first main surface of the semiconductor substrate and increases toward the second main surface of the semiconductor substrate.

[0027] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the fourth semiconductor region contacts the gate insulating film on the sidewall of the trench in a direction parallel to the first main surface of the semiconductor substrate, with a length in the range of 1.0 μm or more and 4.0 μm or less.

[0028] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the trenches are arranged in a stripe pattern extending in a first direction parallel to the first main surface of the semiconductor substrate, the third semiconductor regions and the fourth semiconductor regions are arranged alternately and repeatedly in the first direction, and the third semiconductor regions and the fifth semiconductor regions are arranged alternately and repeatedly in the first direction.

[0029] In addition, in the semiconductor device according to the present invention, a width in the first direction of the fourth semiconductor region is equal to or smaller than a width in the first direction of the fifth semiconductor region.

[0030] Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the semiconductor substrate is made of silicon carbide.

[0031] According to the above-mentioned invention, since the fourth semiconductor region can reduce the pinch-off voltage of the channel, the time until the short-circuit current that flows when the load or arm is short-circuited can be cut off can be shortened, and the saturation current value can be reduced. Also, according to the above-mentioned invention, by appropriately changing the ion implantation mask patterns for forming the third semiconductor region and the fifth semiconductor region, respectively, the fourth semiconductor region can be formed by utilizing the manufacturing method of the conventional semiconductor device (see FIGS. 6 and 7). Effect of the Invention

[0032] The semiconductor device according to the present invention has an advantage that the short-circuit resistance can be improved without increasing the number of steps. [Brief description of the drawings]

[0033] [Figure 1] FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing a structure of the semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a perspective view showing a structure of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a plan view showing a layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. [Diagram 5] FIG. 5 is a characteristic diagram showing the results of a simulation of the relationship between the on-resistance per unit area and the saturation current value in the embodiment. [Figure 6] FIG. 6 is a perspective view showing the structure of a conventional semiconductor device. [Figure 7] FIG. 7 is a plan view showing the layout of a conventional semiconductor device as viewed from the front surface side of a semiconductor substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions not prefixed with them. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to similar configurations, and duplicated explanations will be omitted.

[0035] (Embodiment) The structure of the semiconductor device according to the embodiment will be described. FIGS. 1 and 2 are cross-sectional views showing the structure of the semiconductor device according to the embodiment. FIG. 3 is a perspective view showing the structure of the semiconductor device according to the embodiment. FIG. 4 is a plan view showing the layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. FIGS. 1 and 2 show cross-sectional structures taken along the cutting lines A-A' and B-B' in FIG. 4, respectively. FIG. 3 shows n in FIG. 4. + The source region 4, the low concentration region 5 and the p ++ The boundary between the n-type contact region 6 and the n-type contact region 6 is shown in an enlarged manner. + The source region 4, the low concentration region 5 (hatched area) and the p ++ The layout of the mold contact area 6 is shown.

[0036] The semiconductor device 10 according to the embodiment shown in Figs. 1 to 4 is a vertical MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material. + On the front surface of the starting mold substrate 31, - The epitaxial substrate 30 is formed by stacking epitaxial layers 32, 33 in this order to form the n-type drift region (first semiconductor region) 2 and the p-type base region (second semiconductor region) 3. The semiconductor substrate 30 has a main surface on the side of the epitaxial layer 33 that will become the p-type base region 3 as a front surface (first main surface), and+ The main surface on the mold starting substrate 31 side is defined as the back surface (second main surface).

[0037] n + The starting substrate 31 is n + The n-type drain region is - The drift region 2 is an n + The p-type base region 3 is adjacent to the front surface of the semiconductor substrate 30 and the n-type starting substrate 31. - The trench gate structure is provided between the p-type base region 3 and the n-type drift region 2. + A source region (third semiconductor region) 4, a low concentration region (fourth semiconductor region) 5, a p ++ The p-type contact region (fifth semiconductor region) 6, the trench 7, the gate insulating film 8 and the gate electrode 9. - Between the n-type drift region 2 and the bottom surface of the trench 7, + A n-type current diffusion region 23 and a p-type + The mold regions 21 and 22 may be selectively provided.

[0038] n-type current spreading region 23 and p + The n-type regions 21 and 22 are formed by ion implantation. - The n-type epitaxial layer 32 is a diffusion region formed inside the n-type epitaxial layer 32. - The n-type epitaxial layer 32 includes the n-type current spreading region 23 and the p + The part excluding the mold regions 21 and 22 is n - The n-type current diffusion region 23 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 23 is disposed between the p-type base region 3 and the n-type drift region 2 in the depth direction Z between the adjacent trenches 7. - The mold is in contact with the drift region 2.

[0039] The n-type current diffusion region 23 extends in a direction parallel to the front surface of the semiconductor substrate 30 up to the trench 7 and contacts the gate insulating film 8. +The portion between the n-type regions 21 and 22 is the JFET region. When the n-type current diffusion region 23 is not provided, the n-type current diffusion region 23 is replaced by - Type drift region 2 is n + The n-type drain region 1 extends from the p-type base region 3 to the trench 7 in a direction parallel to the front surface of the semiconductor substrate 30 and contacts the gate insulating film 8. - Adjacent p-type drift regions 2 + The area between the type regions 21 and 22 is the JFET region.

[0040] p + The n-type regions 21 and 22 are fixed to the potential of the source electrode (first electrode) 12 described later, and have the function of depleting (or depleting the n-type current diffusion region 23, or both) when the MOSFET (semiconductor device 10) is turned off, thereby reducing the electric field applied to the gate insulating film 8 at the bottom of the trench 7. + The mold regions 21 and 22 each extend linearly along the trench 7 in a first direction X, which will be described later. + The p-type region 21 is provided away from the p-type base region 3 and faces the bottom surface of the trench 7 in the depth direction Z. + The mold region 21 may be in contact with the gate insulating film 8 at the bottom surface of the trench 7, or may be separated from the bottom surface of the trench 7.

[0041] p + The mold region 21 preferably faces a bottom corner portion (corner portion) of the trench 7 in the depth direction Z. The bottom corner portion of the trench 7 is the boundary between the side wall and the bottom surface of the trench 7. + The type region 22 is formed between the adjacent trenches 7 and the p + It is provided away from the mold area 21. + The type region 22 is n + The surface of the p-type source region 4 contacts the p-type base region 3 and is electrically connected to the source electrode 12 via the p-type base region 3. + The mold region 22 has a depth direction Z of p ++ The contact region 6 faces the p + The width of the mold region 22 (width in the second direction Y) is p ++It is approximately equal to or greater than the width of the mold contact region 6 (width in the second direction Y).

[0042] The trench 7 penetrates the epitaxial layer 33 from the front surface of the semiconductor substrate 30 in the depth direction Z to form the n-type current diffusion region 23 (or n-type current diffusion region 23 if the n-type current diffusion region 23 is not provided). - 2) and enters the n-type current diffusion region 23 or the p-type drift region 24. + The trenches 7 are arranged in a stripe shape extending in a first direction X (the vertical direction in FIG. 4) parallel to the front surface of the semiconductor substrate 30. Between the adjacent trenches 7, an n-type + type source region 4, low concentration region 5 and p ++ Mold contact regions 6 are selectively provided.

[0043] The epitaxial layer 33, n + type source region 4, low concentration region 5 and p ++ The portion excluding the contact region 6 is the p-type base region 3. The epitaxial layer 33 is - or a p-type epitaxial layer having a lower p-type impurity concentration than the p-type base region 3. - p-type epitaxial layer. + Type source region 4 and p ++ The n-type contact region 6 is a diffusion region formed in the epitaxial layer 33 by ion implantation. The low concentration region 5 is a portion of the surface region of the epitaxial layer 33 (the surface region of the front surface of the semiconductor substrate 30) that is + Type source region 4 and p ++ This is the portion that remains without any of the mold contact regions 6 being formed.

[0044] Specifically, the epitaxial layer 33 is n - The n-type impurity concentration is the same as that of the n-type drift region 2. - type epitaxial layer or, for example, 1×10 15 / cm 3 More than 1×10 16 / cm3 p-type impurity concentration of less than - It is a type epitaxial layer. - In the case of a p-type epitaxial layer 33, a p-type region constituting a breakdown voltage structure can be formed by ion implantation into the surface region of the epitaxial layer 33 in an edge termination region (not shown) surrounding the active region. - In the case of the p-type epitaxial layer 33, it is possible to reduce the ion implantation time for forming the p-type base region 3 and the dose of the ion implantation.

[0045] In addition, p - In the case of a p-type epitaxial layer 33 in the edge termination region, - The epitaxial layer 33 is removed to form the lower n - The n-type epitaxial layer 32 is exposed. - A p-type region constituting a voltage-resistant structure may be formed in the exposed surface of the p-type epitaxial layer 32 by ion implantation. The active region is a region in which unit cells (constituent units of an element) of the MOSFET are arranged and through which a main current (drift current) flows. The active region is arranged, for example, approximately in the center of the semiconductor substrate 30. Although only one unit cell of the MOSFET is illustrated in FIGS. 1 and 2, multiple unit cells of the same structure are arranged adjacent to each other in the active region of the semiconductor substrate 30.

[0046] The edge termination region is a region between the active region and the chip edge (edge ​​of the semiconductor substrate 30), and surrounds the periphery of the active region to reduce the electric field on the front surface side of the semiconductor substrate 30 to maintain a breakdown voltage. The breakdown voltage is the limit voltage at which an avalanche breakdown occurs at the pn junction and the drain-source voltage does not increase any further even if the drain-source current is increased. In the edge termination region, for example, a typical breakdown voltage structure such as a junction termination extension (JTE) structure or a field limiting ring (FLR) structure is arranged.

[0047] The p-type base region 3 is formed by ion implantation of p-type impurities such as aluminum (Al) from the surface of the epitaxial layer 33 (front surface of the semiconductor substrate 30). This ion implantation adjusts the resistance value of a channel (n-type inversion layer) formed in a portion (hereinafter referred to as a channel portion) 3a of the p-type base region 3 along the trench 7 when the MOSFET is on. The p-type base region 3 has an impurity concentration distribution in which the impurity concentration reaches a peak concentration (maximum concentration) at the center in the depth direction Z, and the impurity concentration decreases from the depth position of the peak concentration toward the front surface side and the back surface side of the semiconductor substrate 30. The channel portion 3a of the p-type base region 3 has a length substantially equal to the length of the trench 7 in the longitudinal direction (first direction X) and extends linearly in the first direction X along the sidewall of the trench 7.

[0048] A p-type epitaxial layer 33 having substantially the same impurity concentration as that of the p-type base region 3 may be formed, and ion implantation for adjusting the channel resistance value may be performed only on the channel portion 3a of the p-type base region 3. In this case, the p-type base region 3 has an impurity concentration distribution in which the impurity concentration reaches a peak at the center in the depth direction Z only in the channel portion 3a, and the impurity concentration decreases from the depth position of the peak concentration toward the front surface side and the back surface side of the semiconductor substrate 30, respectively, and the remaining portion of the p-type epitaxial layer 33 without ion implantation has a uniform impurity concentration distribution in the depth direction Z. "Substantially the same impurity concentration" and "substantially the same length" respectively mean that the impurity concentration and the length are the same within a range including an allowable error due to process variations.

[0049] n + type source region 4, low concentration region 5 and p ++ The contact region 6 is exposed on the front surface of the semiconductor substrate 30. The contact region 6 is exposed on the front surface of the semiconductor substrate 30 in contact with a source electrode 12, which will be described later, on the front surface of the semiconductor substrate 30. + The n-type source region 4 and the low concentration region 5 contact the gate insulating film 8 on the side wall of the trench 7 and are adjacent to the channel portion 3a of the p-type base region 3 in the depth direction Z. +The source regions 4 and the low concentration regions 5 are alternately and repeatedly arranged adjacent to each other in the first direction X. ++ The contact region 6 is located away from the trench 7 and has an n + The n-type source region 4 is provided adjacent to the n-type source region 4. + Type source region 4 and p ++ The contact regions 6 are alternately and repeatedly arranged adjacent to each other in the first direction X.

[0050] The low concentration region 5 is formed by the trench 7 and p ++ It is preferable that the low concentration region 5 and the p-type contact region 6 are disposed only between the low concentration region 5 and the p-type contact region 6. ++ The low concentration region 5 and the p-type contact region 6 are preferably adjacent to each other in a second direction Y that is parallel to the front surface of the semiconductor substrate 30 and perpendicular to the first direction X. ++ When the low concentration regions 5 adjacent to each other in the first direction X are not adjacent to each other in the second direction Y, + The p type source region 4 and the p ++ Between the n-type contact regions 6 + The n-type source region 4 is divided into a complex pattern, + This is because there is a concern that it may become difficult to form the type source region 4.

[0051] That is, the low concentration region 5 and p ++ By arranging the p-type contact regions 6 adjacent to each other in the second direction Y, ++ The contact regions 6 are interspersed in the first direction X, and the low concentration regions 5 are interspersed with the trenches 7 and ++ The n-type contact regions 6 are disposed between the low concentration regions 5 adjacent to each other in the first direction X and are interspersed in the first direction X. + The p type source region 4 and the p ++ Between the n-type contact regions 6 + The low concentration region 5 and the p-type source region 4 are connected in the second direction Y and have a generally rectangular planar shape with a relatively large surface area. ++ It may be in contact with the mold contact region 6 .

[0052] The width w1 of the low concentration region 5 in the first direction X is p ++ The width of the contact region 6 in the first direction X is equal to or less than the width w2. + The source region 4 is arranged in the first direction X along a low concentration region 5 and a p ++ The n-type contact region 6 has a substantially rectangular planar shape that contacts the gate insulating film 8 on the side wall of the trench 7 in the second direction Y. + The p-type source region 4 extends in the first direction X in contact with the gate insulating film 8 on the side wall of the trench 7, and has an end in the first direction X that is in contact with the trench 7. ++ The straight line portion terminating between the contact region 6 and the p ++ The contact region 6 has a generally H-shaped planar shape and a portion sandwiched between the contact regions 6.

[0053] Specifically, the width w1 of the low concentration region 5 in the first direction X is preferably within a range of, for example, about 1.0 μm or more and 4.0 μm or less. The width w1 of the low concentration region 5 in the first direction X corresponds to the length of the low concentration region 5 in contact with the gate insulating film 8 on the sidewall of the trench 7 in the first direction X. For this reason, if the width w1 of the low concentration region 5 in the first direction X is less than the above-mentioned lower limit, it is not preferable because there is a risk that the effect of providing the low concentration region 5 will not be obtained. If the width w1 of the low concentration region 5 in the first direction X exceeds the above-mentioned upper limit, it is not preferable because the current path of the drift current becomes highly resistive when the MOSFET is on, and the on-resistance becomes high.

[0054] In the low concentration region 5, p-type impurities are introduced by ion implantation of p-type impurities to form the p-type base region 3 (or to adjust the channel resistance value). The ion implantation is performed under conditions such that the impurity concentration is maximum (peak concentration) at a depth position (range) at the center in the depth direction Z of the channel portion 3a of the p-type base region 3 from the surface of the epitaxial layer 33 (the front surface of the semiconductor substrate 30). Therefore, the low concentration region 5 has an impurity concentration distribution in which the impurity concentration is maximum (peak concentration) at a predetermined depth position and decreases with increasing distance in the depth direction Z from the depth position at which the peak concentration is reached.

[0055] Specifically, the epitaxial layer 33 is - In the case of the type, the low concentration region 5 is n + The n-type impurity concentration is lower than that of the n-type source region 4. - n type region (first conductivity type region). - The low concentration region 5 of the semiconductor substrate 30 has the highest impurity concentration near the front surface thereof and the lowest impurity concentration near the rear surface (n + The n-type impurity concentration distribution (first conductivity type impurity concentration distribution) has an n-type impurity concentration decreasing toward the n-type drain region 1 side. - The n-type impurity concentration of the low concentration region 5 is determined by introducing p-type impurities into the low concentration region 5 during the formation of the p-type base region 3. - The n-type impurity concentration is slightly lower than that of the n-type epitaxial layer 33 during epitaxial growth. - The n-type impurity concentration of the low concentration region 5 is, for example, 1×10 14 / cm 3 More than 1×10 18 / cm 3 It is set within the following range.

[0056] The epitaxial layer 33 is p - In the case where the base region 3 is a p-type or p-type, the low concentration region 5 has a p-type impurity concentration lower than that of the channel portion 3 a of the p-type base region 3. - p type region (second conductivity type region). - The low concentration region 5 of the p-type has a p-type impurity concentration distribution (second conductivity type impurity concentration distribution) in which the impurity concentration is lowest near the front surface of the semiconductor substrate 30 and the impurity concentration increases toward the rear surface side of the semiconductor substrate 30. - The p-type impurity concentration of the low concentration region 5 is determined by introducing p-type impurities into the low concentration region 5 during the formation of the p-type base region 3. - The p-type impurity concentration is slightly higher than that of the p-type epitaxial layer 33 during epitaxial growth. - The p-type impurity concentration of the low concentration region 5 is, for example, 1×10 14 / cm 3 More than 1×10 18 / cm 3 It is set within the following range.

[0057] n - By making the n-type impurity concentration relatively high in the surface region (the portion on the front surface side of the semiconductor substrate 30) of the low concentration region 5, the surface region of the low concentration region 5 has a low resistance when the MOSFET is on. - By making the p-type impurity concentration of the low concentration region 5 relatively low in the surface region, the surface region of the low concentration region 5 is inverted to n-type when the MOSFET is turned on, resulting in low resistance. - Type and p - Regardless of the type of low concentration region 5, when the MOSFET is turned on, + Since the drift current flows from the type source region 4 to the low-resistance surface region of the low-concentration region 5 and the area through which the drift current flows from the front surface of the semiconductor substrate 30 to the source electrode 12 becomes large, the on-resistance can be reduced.

[0058] Inside the trench 7, a gate insulating film 8 is provided along the inner wall of the trench 7, and a gate electrode 9 is provided on the gate insulating film 8. The gate insulating film 8 is + a p-type source region 4, a low concentration region 5, a p-type base region 3, and an n-type current diffusion region 23 (if the n-type current diffusion region 23 is not provided, - The trench gate structure is formed by connecting the n-type drift region 2 to the gate insulating film 8 on the side wall of the trench 7. + In the first direction X, a portion where the source region 4, the p-type base region 3, and the n-type current diffusion region 23 contact each other and a portion where the low concentration region 5, the p-type base region 3, and the n-type current diffusion region 23 contact each other are alternately and repeatedly arranged adjacent to each other.

[0059] The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 9. In the contact hole of the interlayer insulating film 11, + type source region 4, low concentration region 5 and p ++ The n-type contact region 6 is exposed. The source electrode 12 is connected to the n-type contact region 6 through a contact hole in the interlayer insulating film 11. + type source region 4, low concentration region 5 and p ++contact region 6, + Type source region 4 and p ++ The n-type contact region 6 is in ohmic contact with the rear surface (n + A drain electrode (second electrode) 13 is provided on the entire surface of the back surface of the starting substrate 31. The drain electrode 13 is an n + Type drain region 1(n + contacting the starting substrate 31), + The gate electrode 1 is electrically connected to the drain region 1 .

[0060] The operation of the semiconductor device 10 according to the embodiment will be described. When a gate-source voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 9 while a positive voltage (forward voltage) with respect to the source electrode 12 is applied to the drain electrode 13, a channel (n-type inversion layer) is formed in the portion (channel portion 3a) along the sidewall of the trench 7 of the p-type base region 3. As a result, + 1, n-type drain region - The n-type drift region 2, the n-type current diffusion region 23, the channel and the n + A drift current flows through the type source region 4 toward the source electrode 12, and the MOSFET (semiconductor device 10) is turned on.

[0061] When the MOSFET is on, + Directly below both the type source region 4 and the low concentration region 5 (n + A channel is formed in the n-type drain region (1 side), but the drift current flows from the channel to the n + The drift current flows only into the n-type source region 4 and does not flow from the channel to the low concentration region 5. Therefore, the drift current that flows into the channel just below the low concentration region 5 flows in a direction parallel to the front surface of the semiconductor substrate 30 along the interface between the channel and the low concentration region 5. + Therefore, a drift current flows from just below the low concentration region 5 to the n-type source region 4 in the channel. + The current path of the drift current becomes longer by the distance that the drift current flows toward the type source region 4, and the resistance becomes high.

[0062] By increasing the resistance of the current path of the drift current with the low concentration region 5, the channel pinches off at a lower drain-source voltage than in the conventional structure (see Figures 6 and 7) without the low concentration region 5. In other words, the low concentration region 5 can reduce the channel pinch-off voltage. This shortens the time until the drain-source current (short-circuit current) that flows when the load or arm is short-circuited is cut off, and reduces the saturation current value, improving the short-circuit resistance. The saturation current value is the saturation value of the drain-source current that is determined depending on the gate-source voltage.

[0063] By providing the low concentration region 5, the ohmic contact area with the source electrode 12 is reduced by the contact area between the source electrode 12 and the low concentration region 5, compared to a conventional structure without the low concentration region 5, and the on-resistance per unit area increases, but the effect of reducing the saturation current value is greater. This improves the trade-off between the reduction in on-resistance and the reduction in the saturation current value (see FIG. 5 described later). Furthermore, by setting the impurity concentration of the low concentration region 5 low within the above-mentioned range, the increase in on-resistance caused by providing the low concentration region 5 does not adversely affect the electrical characteristics of the MOSFET.

[0064] Also, n - In the low concentration region 5, the n-type impurity concentration in the surface region (the portion on the front surface side of the semiconductor substrate 30) is relatively high, or - By making the p-type impurity concentration in the surface region relatively low in the low concentration region 5 having the n-type impurity, the low concentration region 5 has a relatively low resistance in the surface region when the MOSFET is on. + A drift current flows from the type source region 4 to the relatively low-resistance surface region of the low-concentration region 5, and the area of ​​the current path of the drift current flowing from the semiconductor substrate 30 to the source electrode 12 becomes large at the junction surface between the semiconductor substrate 30 and the source electrode 12, thereby reducing the on-resistance.

[0065] On the other hand, when a gate-source voltage less than the gate threshold voltage is applied to the gate electrode 9 with a forward voltage applied between the source and drain, p + The p-type regions 21 and 22 and the p-type base region 3, and the n-type current diffusion region 23 and the n - By reverse-biasing the pn junction (main junction) between the type drift region 2 and the MOSFET, the drift current does not flow and the MOSFET remains in the off state. + The depletion layer spreads to the n-type regions 21 and 22 and / or the n-type current diffusion region 23, and thus the electric field applied to the gate insulating film 8 at the bottom surface of the trench 7 is reduced.

[0066] Next, a method for manufacturing the semiconductor device 10 according to the embodiment will be described. + Starting substrate (n + Next, a mold starting wafer (31) is prepared. + On the front surface of the starting substrate 31, - n type drift region 2 - Next, the n-type epitaxial layer 32 is epitaxially grown (deposited) by photolithography and ion implantation of p-type impurities. - The p + Type region 21 and p + The lower part of the mold region 22 (n + The portion on the side of the drain region 1 and the portion on the side of the drain region 2 are selectively formed.

[0067] By photolithography and ion implantation of n-type impurities, - In the surface region of the epitaxial layer 32, adjacent p + Type region 21 and p + Between the n-type region 22 and the n-type current diffusion region 23, a lower portion of the n-type current diffusion region 23 is formed. + type region 21, p + The order of forming the lower part of the n-type region 22 and the lower part of the n-type current diffusion region 23 can be changed as appropriate. - The p-type epitaxial layer 32 +The n-type regions 21 and 22 and the n-type current diffusion region 23 + The part on the mold starting substrate 31 side is n - Next, further epitaxial growth is performed to form n-type drift region 2. - The type epitaxial layer 32 is grown to a predetermined thickness.

[0068] Next, photolithography and ion implantation of p-type impurities are used to create n - In the portion of the epitaxial layer 32 where the thickness is increased, p + The p + The upper part of the mold region 22 (n + The n-type source region 4 side portion is selectively formed by photolithography and ion implantation of n-type impurities. - The upper part of the n-type current diffusion region 23 is formed in the thickened portion of the p-type epitaxial layer 32 so as to face and be connected to the lower part of the n-type current diffusion region 23 in the depth direction Z. + The order of forming the upper part of the n-type region 22 and the upper part of the n-type current diffusion region 23 can be changed as appropriate.

[0069] Next, n - On the epitaxial layer 32, an n-type base region 3 is formed. - Type or p - The epitaxial layer 33 of the n-type is epitaxially grown (deposited). + A semiconductor substrate (semiconductor wafer) 30 is produced (manufactured) by sequentially stacking epitaxial layers 32 and 33 on the front surface of a starting mold substrate 31. Next, p-type impurities such as aluminum are ion-implanted into the epitaxial layer 33 so that the peak impurity concentration is at the center depth position in the depth direction Z of the portion to be left as the p-type base region 3, thereby forming the p-type base region 3 and adjusting the channel resistance value of the channel portion 3a.

[0070] Next, the surface region of the epitaxial layer 33 is patterned into n-type doped regions by photolithography and ion implantation of n-type impurities. + A p-type source region 4 is selectively formed, and p-type impurity regions are formed by photolithography and ion implantation of p-type impurities.++ The low concentration region 5 in the surface region of the epitaxial layer 33 is selectively formed as an n-type contact region 6. + Type source region 4 and p ++ The conductivity type (n - Type or p - The epitaxial layer 33 is left as it is. + type source region 4, low concentration region 5 and p ++ n-type contact region 6 - The portion on the p-type epitaxial layer 32 side becomes the p-type base region 3 .

[0071] Photolithography and ion implantation of p-type impurities results in n-type - In the surface region or edge termination region of the epitaxial layer 33 of the p - The epitaxial layer 33 is removed to expose the n - A p-type region constituting a breakdown voltage structure is selectively formed in the surface region of the n-type epitaxial layer 32. + Type source region 4, p ++ The order of forming the p-type contact region 6 and the p-type region constituting the breakdown voltage structure can be changed as appropriate. Next, a heat treatment is performed to activate all of the ion-implanted impurities. This heat treatment for impurity activation may be performed after each ion implantation.

[0072] Next, by photolithography and etching, a n-type semiconductor substrate 30 is formed in a depth direction Z from the front surface (the surface of the epitaxial layer 33) of the semiconductor substrate 30. + A trench 7 is formed so as to penetrate through the p-type source region 4, the low concentration region 5, and the p-type base region 3 to reach the n-type current diffusion region 23 and terminate inside the n-type current diffusion region 23. Next, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 11, a source electrode 12, and a drain electrode 13 are formed by a general method. Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips, thereby completing the MOSFET (semiconductor device 10) shown in FIGS. 1 to 4.

[0073] As described above, according to the embodiment, the surface region of the front surface of the semiconductor substrate is provided with n + Instead of a part of the type source region, + The n-type source region has a lower impurity concentration than the - A low concentration region of p-type is provided, or a p-type impurity region having a lower p-type impurity concentration than the channel portion of the p-type base region is provided. - A low concentration region is provided in the MOSFET. This low concentration region can reduce the pinch-off voltage of the channel. This shortens the time until the drain-source current (short-circuit current) that flows when the load or arm is shorted is cut off, and the saturation current value can be reduced, improving the short-circuit resistance.

[0074] According to the embodiment, n - Type or p - The low concentration region of the surface region of the epitaxial layer of the type is n + Type source region and p ++ The conductivity type (n - Type or p - By leaving it as it is, n - Type or p - This allows the formation of a low concentration region of n + Type source region and p ++ By appropriately changing the ion implantation mask pattern for forming each of the contact regions, the low concentration regions can be formed by utilizing the manufacturing method of the conventional semiconductor device (see FIGS. 6 and 7). Therefore, the short circuit resistance can be improved without increasing the number of processes.

[0075] According to the embodiment, the surface region of the front surface of the semiconductor substrate is provided with n +By providing a low-concentration region in place of a part of the type source region, the ohmic contact area with the source electrode is reduced by the contact area between the source electrode and the low-concentration region, and the on-resistance per unit area increases, but the effect of reducing the saturation current value is increased. This improves the trade-off between the reduction in on-resistance and the reduction in the saturation current value. In addition, by setting the impurity concentration of the low-concentration region low within the above-mentioned range, the increase in on-resistance caused by providing the low-concentration region does not adversely affect the electrical characteristics of the MOSFET.

[0076] According to the embodiment, n - In the low concentration region, the n-type impurity concentration in the surface region (the portion on the front side of the semiconductor substrate) is relatively high, or - The p-type impurity concentration in the surface region is relatively low in the low concentration region where the p-type impurity is doped. This makes the low concentration region have a relatively low resistance in the surface region when the MOSFET is on, and the p-type impurity concentration in the surface region is relatively low. + A drift current flows from the source region to the relatively low-resistance surface region of the low-concentration region. As a result, the area of ​​the current path of the drift current flowing from the semiconductor substrate to the source electrode becomes large at the junction between the semiconductor substrate and the source electrode, thereby reducing the on-resistance.

[0077] According to the embodiment, n + Type source region and p ++ Since the low concentration regions can be formed by appropriately changing the ion implantation mask patterns for forming the p-type contact regions, the low concentration regions can be formed by designing the two-dimensional (first and second directions) conditions. This eliminates the need to consider design conditions by combining multiple three-dimensional (first, second and depth) conditions such as the thickness of the channel portion of the p-type base region, the thickness of the epitaxial layer that becomes the p-type base region, and the ion implantation conditions for the channel portion. This makes it possible to manufacture semiconductor devices with high short circuit resistance at low cost.

[0078] (Example) The relationship between the on-resistance and the saturation current value of the semiconductor device 10 according to the above-described embodiment (see FIGS. 1 to 4; hereinafter, referred to as an example) was examined. FIG. 5 is a characteristic diagram showing the results of simulating the relationship between the on-resistance per unit area and the saturation current value of the example. The horizontal axis of FIG. 5 represents the on-resistance per unit area [mΩ cm 2 ], and the vertical axis represents the saturation value (saturation current value) [A] of the saturation current Isat.

[0079] The results of simulating the saturation current value versus on-resistance per unit area for each of the embodiment and the conventional example (conventional semiconductor device 110 shown in FIGS. 6 and 7) are shown in FIG. 5. The conventional example differs from the embodiment in that it does not have a low concentration region 5. In both the embodiment and the conventional example, the impurity concentration of the channel portions 3a, 103a of the p-type base regions 3, 103 is changed to change the channel resistance value, thereby changing the on-resistance per unit area.

[0080] From the results shown in Fig. 5, it was confirmed that the saturation current value can be reduced in the embodiment compared to the conventional example having the same on-resistance per unit area. That is, the embodiment can improve the trade-off relationship between the reduction in on-resistance and the reduction in the saturation current value compared to the conventional example. Note that, in both the embodiment and the conventional example, even in the on-resistance range not shown, there is a proportional relationship in which the saturation current value decreases at a predetermined rate as the on-resistance increases.

[0081] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can be applied to a semiconductor device using silicon (Si) as a semiconductor material. In addition, the present invention has been described assuming that the first conductivity type is n-type and the second conductivity type is p-type, but the present invention can be applied in the same way even if the conductivity types are reversed, that is, the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0082] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for MOSFETs using silicon carbide as a semiconductor material. [Explanation of symbols]

[0083] 1n + Type drain region 2n - Type Drift Region 3 p-type base region 3a Channel part of p-type base region 4n + Type Source Area 5n - Type or p - Low concentration area of ​​mold 6 p ++ Mold Contact Area 7. Trench 8 Gate insulating film 9 Gate electrode 10 Semiconductor device 11 Interlayer insulating film 12 Source electrode 13 Drain electrode 21,22 p + type area 23 n-type current diffusion region 30 Semiconductor Substrate 31 n + Starting substrate 32n - Type epitaxial layer 33n - type, p - n-type or p-type epitaxial layer w1 Width of low concentration region in the first direction w2 p ++ Width of the mold contact region in the first direction X: A first direction parallel to the front surface of the semiconductor substrate Y: A second direction that is parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z depth direction

Claims

1. a first semiconductor region of a first conductivity type provided within a semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a trench that penetrates the second semiconductor region from the first main surface of the semiconductor substrate in a depth direction and terminates inside the first semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a third semiconductor region of the first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, the third semiconductor region being in contact with the gate insulating film on a sidewall of the trench; a fourth semiconductor region selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, the fourth semiconductor region being in contact with the gate insulating film on a sidewall of the trench; a fifth semiconductor region of a second conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and away from the trench, the fifth semiconductor region having an impurity concentration higher than that of the second semiconductor region; a first electrode in contact with the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a second electrode in contact with a second main surface of the semiconductor substrate; Equipped with a fourth semiconductor region being a first conductivity type region having a lower concentration of first conductivity type impurities than the third semiconductor region, or a second conductivity type region having a lower concentration of second conductivity type impurities than a portion of the second semiconductor region along a sidewall of the trench,

2. 2 . The semiconductor device according to claim 1 , wherein the fourth semiconductor regions are periodically arranged along the sidewall of the trench in a direction parallel to the first main surface of the semiconductor substrate.

3. 2 . The semiconductor device according to claim 1 , wherein the fourth semiconductor region is disposed between the fifth semiconductor region and the trench.

4. The impurity concentration of the fourth semiconductor region is 1×10 14 / cm 3 Above 1 x 10 18 / cm 3 2. The semiconductor device according to claim 1, wherein the semiconductor device is within the following range.

5. The fourth semiconductor region is the first conductivity type region, 2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a first conductivity type impurity concentration distribution in which the impurity concentration is highest at a first main surface of the semiconductor substrate and decreases toward a second main surface of the semiconductor substrate.

6. The fourth semiconductor region is the second conductivity type region, 2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a first main surface having a lowest impurity concentration, and the second conductive type impurity concentration increases toward a second main surface of the semiconductor substrate.

7. 2. The semiconductor device according to claim 1, wherein the fourth semiconductor region contacts the gate insulating film on the sidewall of the trench in a direction parallel to the first main surface of the semiconductor substrate with a length in the range of 1.0 μm to 4.0 μm.

8. The trenches are arranged in a stripe shape extending in a first direction parallel to the first main surface of the semiconductor substrate, The third semiconductor region and the fourth semiconductor region are alternately and repeatedly arranged in the first direction, 2 . The semiconductor device according to claim 1 , wherein the third semiconductor region and the fifth semiconductor region are repeatedly arranged alternately in the first direction.

9. 9. The semiconductor device according to claim 8, wherein the width of the fourth semiconductor region in the first direction is equal to or smaller than the width of the fifth semiconductor region in the first direction.

10. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.

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