Memory Device

Abstract

To provide a memory device.SOLUTION: A memory device includes a substrate, a multilayer structure including a plurality of gate layers and a plurality of interlayer insulating layers that are stacked alternately in a vertical direction on the substrate, and a row of channel structures arranged in a first horizontal direction, extending in the vertical direction, and penetrating the gate layers in a cell region of the multilayer structure. Each of the multilayer structures includes a row of cutting parts extending in the first horizontal direction and cutting the gate layers. The cutting parts are apart from each other and are arranged in the first horizontal direction in the cell region.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present disclosure relates to semiconductor memory devices. [Background technology]

[0002] Electronic products that are smaller in size, capable of processing larger amounts of data, and less expensive are being developed. For example, memory devices are being fabricated with higher integration densities. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present disclosure is to provide a memory device having a high integration density. [Means for solving the problem]

[0004] The embodiment includes a substrate, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate, and rows of channel structures arranged in a first horizontal direction within a cell region of the stacked structure, each extending in the vertical direction and penetrating the plurality of gate layers, the stacked structure including rows of cutting portions each extending in the first horizontal direction and cutting the plurality of gate layers, the cutting portions being spaced apart from one another and arranged in the first horizontal direction within the cell region.

[0005] In order to solve the above-mentioned problems, a memory device according to an embodiment of the present disclosure includes a substrate, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate, and channel structures arranged in a first row, a second row, and a third row extending in a first horizontal direction in a cell region of the stacked structure, each extending in the vertical direction and penetrating the plurality of gate layers, the stacked structure including a first row of discontinuous cut portions that discontinuously cut the plurality of gate layers in the first horizontal direction between the first row of the channel structures and the second row of the channel structures in the cell region, the stacked structure further including a continuous cut portion that continuously cuts the plurality of gate layers in the first horizontal direction in the cell region, and the second row and the third row of the channel structures are located between the first row of the discontinuous cut portions and the continuous cut portions.

[0006] In order to solve the above-mentioned problems, a memory device according to an embodiment of the present disclosure includes a substrate, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate, and a plurality of channel structures extending vertically in a cell region of the stacked structure and penetrating the plurality of gate layers, the stacked structure including rows of cell region cutting portions each extending in a first horizontal direction and cutting the plurality of gate layers, the cell region cutting portions being spaced apart from each other and arranged along the first horizontal direction in the cell region, the stacked structure further including rows of connection region cutting portions each extending in the first horizontal direction and cutting the plurality of gate layers, the connection region cutting portions being spaced apart from each other and arranged along the first horizontal direction in the connection region of the stacked structure. Effect of the Invention

[0007] The stacked structure of a memory device according to the technical idea of ​​the present disclosure includes a row of cuts that discontinuously cuts a plurality of gate layers of the stacked structure in a horizontal direction in a cell region of the stacked structure. The uncut portion in the cell region of the stacked structure between two adjacent cuts in the row of cuts can reduce tilt of the stacked structure due to internal stress and distortion (e.g., expansion, contraction, or twist) of materials that occurs during the manufacturing process of the memory device. As a result, even when manufacturing a memory device including a stacked structure in which a larger number of gate layers are stacked, process difficulties caused by tilt of the stacked structure are reduced. Thus, according to the present disclosure, a memory device having a higher integration density is provided. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating a memory device according to an example embodiment; [Diagram 2] 2 is a circuit diagram illustrating one of memory blocks included in a memory cell array included in a memory device according to an exemplary embodiment; [Diagram 3] 1 is a plan view illustrating a memory device according to an exemplary embodiment; [Figure 4A] FIG. 4 is a plan view illustrating a schematic view of an A1 region illustrated in FIG. [Figure 4B] 4B is a cross-sectional view taken along line B4-B4' shown in FIG. 4A. [Figure 4C] 4B is a cross-sectional view taken along line C4-C4' shown in FIG. 4A. [Figure 4D] 4B is a cross-sectional view taken along line D4-D4' shown in FIG. 4A. [Diagram 5] 4C is a cross-sectional view illustrating a row of cell region discontinuous cuts and channel structures according to an exemplary embodiment at a first height shown in FIG. 4B. [Figure 6] 4C is a cross-sectional view that illustrates a schematic representation of a cell region discontinuity cut according to an exemplary embodiment at a second height that is lower than the first height illustrated in FIG. 4B. [Figure 7]4C is a cross-sectional view that illustrates a schematic representation of a cell region discontinuity cut according to an exemplary embodiment at a second height that is lower than the first height illustrated in FIG. 4B. [Figure 8A] FIG. 4 is a plan view illustrating a schematic view of an A2 region illustrated in FIG. [Figure 8B] 8B is a cross-sectional view taken along line B8-B8' shown in FIG. 8A. [Figure 8C] 8B is a cross-sectional view taken along line C8-C8' shown in FIG. 8A. [Figure 9] 8C is a cross-sectional view illustrating a schematic diagram of a connection region discontinuous cut according to an exemplary embodiment at the first height illustrated in FIG. 8B. [Figure 10] 8C is a cross-sectional view illustrating a schematic diagram of a connection region discontinuity cut according to an exemplary embodiment at a second height that is lower than the first height shown in FIG. 8B. [Figure 11] 8C is a cross-sectional view illustrating a schematic diagram of a connection region discontinuity cut according to an exemplary embodiment at a second height that is lower than the first height shown in FIG. 8B. [Figure 12] 1 is a cross-sectional view illustrating a memory device according to an exemplary embodiment; [Figure 13] 1 is a cross-sectional view illustrating a memory device according to an exemplary embodiment; [Figure 14A] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14B] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14C] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14D] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14E] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14F] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14G] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14H]1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14I] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14J] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. [Figure 14K] 1A-1D are cross-sectional views illustrating a method for manufacturing a memory device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] 1 is a block diagram illustrating a memory device 10 according to an exemplary embodiment. Referring to FIG. 1, the memory device 10 includes a memory cell array 11 and peripheral circuits PC. The peripheral circuits PC include a row decoder 12, an input / output circuit 13, and a control logic 14.

[0010] The memory cell array 11 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells capable of storing data. The memory cells included in the memory cell array 11 may be non-volatile memory cells that retain the stored data even when the power supply is cut off. For example, the memory cell array 11 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase-change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM). In the following, an exemplary embodiment will be described in detail assuming that the memory cells are NAND flash memory cells.

[0011] The row decoder 12 is connected to the memory cell array 11 by a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The row decoder 12 selects at least one of a plurality of memory blocks BLK1 to BLKz of the memory cell array 11 in response to an address ADDR provided from a memory controller (not shown). The row decoder 12 selects at least one of the word lines WL, the string selection lines SSL, and the ground selection lines GSL of the selected memory block in response to the address ADDR provided from the memory controller (not shown).

[0012] The input / output circuit 13 is connected to the memory cell array 11 via a plurality of bit lines BL. The input / output circuit 13 selects at least one of the bit lines BL. The input / output circuit 13 stores data DATA input from a memory controller (not shown) in the memory cell array 11. The input / output circuit 13 also outputs data DATA read from the memory cell array 11 to the memory controller (not shown).

[0013] The control logic 14 controls the overall operation of the memory device 10. Specifically, the control logic 14 controls the operation of the row decoder 12 and the input / output circuit 13. For example, the control logic 14 controls the memory device 10 so that a memory operation corresponding to a command CMD provided from a memory controller (not shown) is performed. The control logic 14 also generates various internal control signals used within the memory device 10 in response to a control signal CTRL provided from the memory controller (not shown).

[0014] FIG. 2 is a circuit diagram illustrating one (BLK1) of memory blocks BLK1 to BLKz constituting memory cell array 11 (FIG. 1) included in memory device 10 (FIG. 1) according to an exemplary embodiment.

[0015] Referring to FIG. 2, the memory block BLK1 includes a number of NAND strings NS11 to NS33. FIG. 2 shows one memory block BLK1 including nine NAND strings NS11 to NS33, but the number of NAND strings included in one memory block BLK1 can be changed. Each of the NAND strings NS11 to NS33 includes at least one string selection transistor SST, a number of memory cells MC1 to MC8, and at least one ground selection transistor GST, which are connected in series. FIG. 2 shows one NAND string NS11 to NS33 including one string selection transistor SST, eight memory cells MC1 to MC8, and one ground selection transistor GST, but the number of string selection transistors, memory cells, and ground selection transistors included in each of the NAND strings NS11 to NS33 can be changed.

[0016] The NAND strings NS11 through NS33 are connected between the bit lines BL1 through BL3 and a common source line CSL. The gates of the string selection transistors SST are connected to the string selection lines SSL1 through SSL3, the gates of the memory cells MC1 through MC8 are connected to the word lines WL1 through WL8, and the gates of the ground selection transistors GST are connected to the ground selection lines GSL1 through GSL3. The common source line CSL is commonly connected to the NAND strings NS11 through NS33. Also, the word lines WL1 through WL8 are commonly connected to the NAND strings NS11 through NS33.

[0017] FIG. 3 is a plan view illustrating a memory device 100 according to an exemplary embodiment. Referring to FIG. 3, the memory device 100 includes a substrate 110, a memory cell array 11 arranged side-by-side on the substrate 110, and a peripheral circuit PC. The memory cell array 11 includes a stacked structure SS on the substrate 110. The stacked structure SS includes a cell region CELL and a connection region EXT. The connection region EXT is located on one side of the cell region CELL. The connection region EXT is arranged along a first horizontal direction (X direction) together with the cell region CELL. In an exemplary embodiment, the stacked structure SS may have another connection region EXT. For example, the two connection regions EXT may be located on opposite sides of the cell region CELL. The two connection regions EXT and the cell region CELL may be arranged along a first horizontal direction (X direction). The two connection regions EXT may be spaced apart in the first horizontal direction (X direction), and the cell region CELL may be located between the two connection regions EXT. In an exemplary embodiment, the laminated structure SS may include four connecting regions EXT located on four sides of the cell region CELL, respectively.

[0018] FIG. 4A is a plan view showing a schematic view of the A1 region shown in FIG. 3. FIG. 4B is a cross-sectional view taken along the line B4-B4' shown in FIG. 4A. FIG. 4C is a cross-sectional view taken along the line C4-C4' shown in FIG. 4A. FIG. 4D is a cross-sectional view taken along the line D4-D4' shown in FIG. 4A. FIG. 8A is a plan view showing a schematic view of the A2 region shown in FIG. 3. FIG. 8B is a cross-sectional view taken along the line B8-B8' shown in FIG. 8A. FIG. 8C is a cross-sectional view taken along the line C8-C8' shown in FIG. 8A.

[0019] 4A to 4D and 8A to 8C, the memory device 100 includes a substrate 110, a stacked structure SS on the substrate 110, a plurality of channel structures CH penetrating a cell region CELL of the stacked structure SS, and a plurality of dummy channel structures DCH penetrating a connection region EXT of the stacked structure SS.

[0020] The substrate 110 includes a semiconductor material including a group IV semiconductor material, a group III-V semiconductor material, a group II-VI semiconductor material, or a combination thereof. The group IV semiconductor material includes, for example, silicon (Si), germanium (Ge), silicon-germanium (Si-Ge), or a combination thereof. The group III-V semiconductor material includes, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), indium gallium arsenide (InGaAs), or a combination thereof. The group II-VI semiconductor material includes, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof.

[0021] The stacked structure SS includes a plurality of gate layers 150a-150c and a plurality of interlayer insulating layers 140 alternately stacked on the substrate 110. Two adjacent gate layers in the plurality of gate layers 150a-150c are separated by one interlayer insulating layer. The plurality of gate layers 150a-150c includes at least one lower gate layer 150a, a plurality of intermediate gate layers 150b on the at least one lower gate layer 150a, and at least one upper gate layer 150c on the plurality of intermediate gate layers 150b. Each of the gate layers 150a-150c includes a conductive material such as tungsten (W), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or a combination thereof. Each of the interlayer insulating layers 140 may include an insulating material including, but not limited to, silicon oxide, silicon nitride, or a combination thereof.

[0022] As shown in Figures 4B and 4C, the cell region CELL of the stacked structure SS is flat, while as shown in Figure 8C, the connection region EXT of the stacked structure SS has a stepped shape. Therefore, the length in the second horizontal direction (Y direction) of the gate layer located at a lower height among the multiple gate layers 150a to 150c is longer than the length in the second horizontal direction (Y direction) of the gate layer located at a higher height among the multiple gate layers 150a to 150c. Similarly, the length in the second horizontal direction (Y direction) of the interlayer insulating layer 140 located at a lower height is longer than the length in the second horizontal direction (Y direction) of the interlayer insulating layer 140 located at a higher height.

[0023] The channel structure CH extends in a direction substantially parallel to the vertical direction (Z direction) and penetrates the cell region CELL of the laminate structure SS. The dummy channel structure DCH extends in a direction substantially parallel to the vertical direction (Z direction) and penetrates the connection region EXT of the laminate structure SS. Due to internal stress or deformation (e.g., expansion, contraction or twisting) of a material occurring during processing, the extension direction of the channel structure CH and / or the dummy channel structure DCH may not be perfectly parallel to the vertical direction (Z direction). The extension direction of the channel structure CH and / or the dummy channel structure DCH being substantially parallel to the vertical direction (Z direction) means that the angle between the extension direction of the channel structure CH and / or the dummy channel structure DCH and the vertical direction (Z direction) is about 0° to about 10°, for example, about 0° to about 5°, for example, about 0° to about 2°.

[0024] The channel structures CH are two-dimensionally arranged in a cell region CELL of the stacked structure SS, and the dummy channel structures DCH are two-dimensionally arranged in a connection region EXT of the stacked structure SS. The channel structures CH arranged in a first horizontal direction (X direction) are called a row of channel structures CH. For example, the memory device 100 may include first to third rows CH1 to CH3 of channel structures. The first to third rows CH1 to CH3 of channel structures may be spaced apart in a second horizontal direction (Y direction).

[0025] Each channel structure CH and each dummy channel structure DCH includes a channel pattern 162, a buried insulating pattern 161, a pad pattern 164, and a gate insulating pattern 163. The channel pattern 162 penetrates the gate layers 150a-150c and the interlayer insulating layers 140. The channel pattern 162 includes a semiconductor material. In an exemplary embodiment, the channel pattern 162 may be cup-shaped (or hollow cylinder-shaped with a bottom). Thus, the channel pattern 162 extends along the side and bottom of the channel structure CH. The cavity defined by the channel pattern 162 is filled with the buried insulating pattern 161. The buried insulating pattern 161 includes an insulating material. Unlike the embodiment shown in FIG. 4B and FIG. 4C, in some embodiments, the channel pattern 162 is cylindrical or columnar, and the buried insulating pattern 161 may be omitted. The pad pattern 164 is located on the top surface of the channel structure CH. The pad pattern 164 includes a semiconductor material.

[0026] The gate insulating pattern 163 is located between the channel pattern 162 and the stack structure SS. The gate insulating pattern 163 extends along the side and bottom surfaces of the channel structure CH. In an exemplary embodiment, unlike the examples shown in FIGS. 4B, 4C, and 8B, at least a portion of the gate insulating pattern 163 may not be included in the channel structure CH or the dummy channel structure DCH and may be located between the interlayer insulating layer 140 and the gate layers 150a to 150c. The gate insulating pattern 163 includes a blocking insulating layer, a tunnel insulating layer, and a charge storage layer between the blocking insulating layer and the tunnel insulating layer. The blocking insulating layer includes an insulating material such as silicon oxide, hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, or a combination thereof. The charge storage layer includes an insulating material such as silicon oxide, silicon nitride, or a combination thereof. The charge storage layer may be a trap type. For example, the charge storage layer may further include quantum dots or nanocrystals. Here, the quantum dots or nanocrystals include fine particles of a conductive material. The tunnel insulating layer includes an insulating material such as silicon oxide, hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, or a combination thereof. In an exemplary embodiment, the blocking insulating layer and the tunnel insulating layer may include an oxide, and the charge storage layer may include a nitride.

[0027] The laminated structure SS includes a plurality of cut portions, for example, cut portions HWC, FW, HS, FS, HGC, HWE, DWE, and HGE. The cut portions HWC, FW, HS, FS, HGC, HWE, DWE, and HGE of the laminated structure SS are openings or recesses formed in the laminated structure SS.

[0028] The laminated structure SS includes a cell region discontinuous cut portion HWC. For example, the laminated structure SS includes a first row HWC1 and a second row HWC2 of the cell region discontinuous cut portion HWC. Each of the first row HWC1 and the second row HWC2 includes a plurality of cell region discontinuous cut portions HWC.

[0029] The cell area discontinuity cut HWC is also referred to as a discontinuity cut, a cell area cut or a cut.

[0030] The rows HWC1, HWC2 of the cell region discontinuous cut portion are spaced apart from each other, extend in the cell region CELL of the stacked structure SS, and are arranged along the first horizontal direction (X direction). The cell region discontinuous cut portion HWC of the stacked structure SS extends along the first horizontal direction (X direction) and cuts the multiple gate layers 150a to 150c of the stacked structure SS. Therefore, the rows HWC1, HWC2 of the cell region discontinuous cut portion can discontinuously cut the multiple gate layers 150a to 150c in the first horizontal direction (X direction) in the cell region CELL of the stacked structure SS.

[0031] In an exemplary embodiment, as shown in FIG. 4D, the lower surface of at least one cell region discontinuous cut HWC is convex upward. The vertical (Z-direction) depth D1 of the end of at least one cell region discontinuous cut HWC is deeper than the vertical (Z-direction) depth D2 of the center of at least one cell region discontinuous cut HWC. In another exemplary embodiment, unlike that shown in FIG. 4D, the lower surface of at least one cell region discontinuous cut HWC is convex downward or flat.

[0032] In an exemplary embodiment, the cell region discontinuous cut portion HWC may have an end portion PaC and a center portion PbC, as shown in Fig. 5. As shown in Fig. 5, the greater the maximum width Wa1 in the second horizontal direction (Y direction) of the end portion PaC of the cell region discontinuous cut portion HWC at the first height H1 is than the maximum width Wb1 in the second horizontal direction (Y direction) of the center portion PbC of the cell region discontinuous cut portion HWC at the first height H1, the greater the tendency for the lower surface of at least one cell region discontinuous cut portion HWC to be formed in an upward convex shape.

[0033] For example, as shown in FIG. 5, the maximum width Wa1 (in the second horizontal direction (Y direction)) of the end portion PaC at the first height H1 in the Z direction (FIG. 4B) is wider than the maximum width Wb1 (in the second horizontal direction (Y direction)) of the center portion PbC.

[0034] 4A again, the first row HWC1 and the second row HWC2 of the discontinuous cut portion of the cell region are spaced apart in the second horizontal direction (Y direction). The first row HWC1 of the discontinuous cut portion of the cell region may be located between the first row CH1 and the second row CH2 of the channel structure. The second row HWC2 of the discontinuous cut portion of the cell region may be located between the second row CH2 and the third row CH3 of the channel structure.

[0035] Two adjacent cell region discontinuous cuts HWC in the first row HWC1 have a gap G1 between them. Two adjacent cell region discontinuous cuts HWC in the second row HWC2 have a gap G2 between them. In an exemplary embodiment, the gap G1 in the first row HWC1 may not be aligned with the gap G2 in the second row HWC2 in the second horizontal direction (Y direction). That is, the gaps G1, G2 may be offset in the X direction. It can facilitate the steps of removing the sacrificial layers 180a-180c described in FIG. 14I-FIG. 14K and then filling the gate layers 150a-150c. It can also relieve the tilt of the stacked structure SS caused by the internal stress and strain (e.g., deformation, expansion, contraction) of the material during the manufacturing process.

[0036] In an exemplary embodiment, the cell region discontinuous cut HWC may be filled with an insulating material IM. In an exemplary embodiment, as shown in FIG. 4C, at least one cell region discontinuous cut HWC may include a void VD in the insulating material. In particular, as described in more detail with reference to FIG. 5, in a structure similar to that described in detail above with reference to FIG. 5, the more the maximum width Wa1 in the second horizontal direction (Y direction) of the end PaC of the cell region discontinuous cut HWC at the first height H1 is wider than the maximum width Wb1 in the second horizontal direction (Y direction) of the center PbC of the cell region discontinuous cut HWC at the first height H1, the more likely the void VD is formed at the end PaC of the cell region discontinuous cut HWC.

[0037] In other exemplary embodiments, the cell region discontinuous cut portion HWC may be filled with a common source line (not shown) extending vertically (Z direction) within the cell region discontinuous cut portion HWC, and an insulating spacer (not shown) located on a sidewall of the cell region discontinuous cut portion HWC and surrounding the common source line.

[0038] According to an exemplary embodiment, the uncut portion in the cell region CELL of the stacked structure SS between two adjacent cell region discontinuous cut portions HWC in each row HWC1, HWC2 of the cell region discontinuous cut portion can reduce tilt of the stacked structure SS due to internal stress and deformation (e.g., expansion, contraction, or twist) of the material generated during the manufacturing process of the memory device 100. Therefore, even when manufacturing a memory device including a stacked structure SS in which a larger number of gate layers 150a to 150c and an interlayer insulating layer 140 are stacked, the process difficulty caused by the tilt of the stacked structure SS can be reduced. Therefore, the memory device 100 can have a higher integration density.

[0039] In an exemplary embodiment, the continuous cutting portion FW extends along the first horizontal direction (X direction) across the cell region CELL and the connection region EXT of the stacked structure SS, and cuts the multiple gate layers 150a to 150c of the stacked structure SS. Thus, the continuous cutting portion FW can cut the multiple gate layers 150a to 150c continuously in the first horizontal direction (X direction) within the cell region CELL and the connection region EXT of the stacked structure SS. The continuous cutting portion FW can be filled with an insulating material.

[0040] The second row CH2 and the third row CH3 of the channel structure may be located between the continuous cut FW and the first row HWC1 of the discontinuous cut of the cell region. The third row CH3 of the channel structure may be located between the continuous cut FW and the second row HWC2 of the discontinuous cut of the cell region. The second row CH2 of the channel structure may be located between the first row HWC1 and the second row HWC2 of the discontinuous cut of the cell region.

[0041] 4B, due to internal stresses and strains (e.g., deformation, expansion, or contraction) of the material occurring during the manufacturing process, the maximum width Wb1 of the center of the cell region discontinuous cut portion HWC in the second horizontal direction (Y direction) at the first height H1 is narrower than the maximum width W5 of the continuous cut portion FW in the second horizontal direction (Y direction) at the first height H1. The maximum width of the center of the cell region discontinuous cut portion HWC in the second horizontal direction (Y direction) decreases as the height increases, while the maximum width of the continuous cut portion FW in the second horizontal direction (Y direction) increases as the height increases.

[0042] The discontinuous top cut HS is also referred to as the top cut. The discontinuous top cut HS may be filled with an insulating material.

[0043] The discontinuous upper cuts HS are arranged in a first row HS1 and a second row HS2. The first row HS1 and the second row HS2 of the discontinuous upper cuts HS are spaced apart from each other in a second horizontal direction (Y direction). The rows HS1, HS2 of the discontinuous upper cuts HS extend in the cell region CELL of the stacked structure SS and are arranged along the first horizontal direction (X direction). The discontinuous upper cuts HS may extend along the first horizontal direction (X direction) and cut at least one upper gate layer 150c but not cut the multiple intermediate gate layers 150b and at least one lower gate layer 150a. Thus, each row HS1, HS2 of the discontinuous upper cuts may discontinuously cut only the upper gate layer 150c in the first horizontal direction (X direction) in the cell region CELL of the stacked structure SS.

[0044] The discontinuous top cut HS in the first row HS1 of the discontinuous top cut may be located between two adjacent cell area discontinuity cuts HWC in the first row HWC1 of the cell area discontinuity cut. The discontinuous top cut HS in the second row HS2 of the discontinuous top cut may extend between two adjacent cell area discontinuity cuts HWC in the second row HWC2 of the cell area discontinuity cut.

[0045] In an exemplary embodiment, the discontinuous top cuts HS in a first row HS1 of discontinuous top cuts may not be collinearly aligned in a second horizontal direction (Y direction) with the discontinuous top cuts HS in a second row HS2 of discontinuous top cuts.

[0046] Each of the continuous upper cut parts FS1 to FS3 may extend along the first horizontal direction (X direction) and cut at least one upper gate layer 150c but not cut the multiple intermediate gate layers 150b and at least one lower gate layer 150a. Therefore, each of the continuous upper cut parts FS1 to FS3 can cut only at least one upper gate layer 150c continuously in the first horizontal direction (X direction) in the cell region CELL of the stacked structure SS.

[0047] The continuous top cuts FS1 to FS3 are spaced apart in a second horizontal direction (Y direction). The second continuous top cut FS2 may be located between the first row HWC1 and the second row HWC2 of the discontinuous cut of the cell region, and the third continuous top cut FS3 may be located between the second row HWC2 of the discontinuous cut of the cell region and the continuous cut FW. The first row HWC1 of the discontinuous cut of the cell region may be located between the first continuous top cut FS1 and the second continuous top cut FS2, and the second row HWC2 of the discontinuous cut of the cell region may be located between the second continuous top cut FS2 and the third continuous top cut FS3. The continuous top cuts FS1 to FS3 may be filled with an insulating material.

[0048] The cell region discontinuous lower cut portion HGC is also referred to as a cell region lower cut portion or a lower cut portion. The respective rows HGC1, HGC2 of the cell region discontinuous lower cut portion are spaced apart from each other, extend in the cell region CELL of the stacked structure SS, and are arranged along the first horizontal direction (X direction). The cell region discontinuous lower cut portion HGC may extend along the first horizontal direction (X direction) and cut at least one lower gate layer 150a, but not cut a plurality of intermediate gate layers 150b and at least one upper gate layer 150c. Thus, the respective rows HGC1, HGC2 of the cell region discontinuous lower cut portion may cut only the lower gate layer 150a discontinuously in the first horizontal direction (X direction) in the cell region CELL of the stacked structure SS.

[0049] The cell area discontinuous lower cut portion HGC in the first row HGC1 of the cell area discontinuous lower cut portion may be located between two adjacent cell area discontinuous cut portions HWC in the first row HWC1 of the cell area discontinuous cut portion, and the cell area discontinuous lower cut portion HGC in the second row HGC2 of the cell area discontinuous lower cut portion may extend between two adjacent cell area discontinuous cut portions HWC in the second row HWC2 of the cell area discontinuous cut portion.

[0050] The first row HGC1 and the second row HGC2 of the cell region discontinuous lower cuts are spaced apart in a second horizontal direction (Y direction). In an exemplary embodiment, the cell region discontinuous lower cuts HGC in the first row HGC1 of the cell region discontinuous lower cuts may be misaligned in the second horizontal direction (Y direction) with the cell region discontinuous lower cuts HGC in the second row HGC2 of the cell region discontinuous lower cuts. The cell region discontinuous lower cuts HGC may be filled with an insulating material. In an exemplary embodiment, the cell region discontinuous lower cuts HGC may be overlapped in a vertical direction (Z direction) with the discontinuous upper cuts HS.

[0051] The link region discontinuity break HWE is also called a link region break.

[0052] For example, as shown in FIG. 8A, the rows HWE1, HWE2 of the connection region discontinuous cut portion are spaced apart from each other, extend within the connection region EXT of the stacked structure SS, and are arranged along a first horizontal direction (X direction). The connection region discontinuous cut portion HWE extends along the first horizontal direction (X direction) and cuts the multiple gate layers 150a to 150c of the stacked structure SS. Thus, the rows HWE1, HWE2 of the connection region discontinuous cut portion can discontinuously cut the multiple gate layers 150a to 150c in the first horizontal direction (X direction) within the connection region EXT of the stacked structure SS.

[0053] In an exemplary embodiment, a gap G3 between two adjacent linking region discontinuity breaks HWE in a first row HWE1 of linking region discontinuity breaks is aligned in the second horizontal direction (Y direction) with a gap G4 between two adjacent linking region discontinuity breaks HWE in a second row HWE2 of linking region discontinuity breaks. However, in other embodiments, unlike that shown in FIG 8A, a gap G3 between two adjacent linking region discontinuity breaks HWE in a first row HWE1 of linking region discontinuity breaks may not be aligned in the second horizontal direction (Y direction) with a gap G4 between two adjacent linking region discontinuity breaks HWE in a second row HWE2 of linking region discontinuity breaks.

[0054] The first row HWE1 and the second row HWE2 of the connection region discontinuous cut portion are spaced apart in a second horizontal direction (Y direction). In an exemplary embodiment, the first row HWE1 of the connection region discontinuous cut portion may be aligned with the first row HWC1 of the cell region discontinuous cut portion in the first horizontal direction (X direction), and the second row HWE2 of the connection region discontinuous cut portion may be aligned with the second row HWC2 of the cell region discontinuous cut portion in the first horizontal direction (X direction).

[0055] In an exemplary embodiment, the link region discontinuity breaks HWE may be filled with insulating material. In an exemplary embodiment, at least one link region discontinuity break HWE may include a void (not shown) in the insulating material.

[0056] In an exemplary embodiment, as shown in FIG. 9, the wider the maximum width Wa3 in the second horizontal direction (Y direction) of the end PaE of the discontinuous disconnection portion HWE at the first height H1 is than the maximum width Wb3 in the second horizontal direction (Y direction) of the central portion PbE of the discontinuous disconnection portion HWE at the first height H1, the more likely it is that a void (not shown) will be formed at the end of the discontinuous disconnection portion HWE.

[0057] In other exemplary embodiments, the connection region discontinuous cut HWE may be filled with a common source line (not shown) extending vertically (Z direction) within the connection region discontinuous cut HWE, and an insulating spacer (not shown) located on a sidewall of the connection region discontinuous cut HWE and surrounding the common source line.

[0058] 8A again, the uncut portion in the connection region EXT of the stack structure SS between two adjacent connection region discontinuous cut portions HWE in each row HWE1, HWE2 of the connection region discontinuous cut portion can reduce the tilt of the stack structure SS due to internal stress and distortion (e.g., expansion, contraction, or twist) of the material generated during the manufacturing process of the memory device 100. Therefore, even when manufacturing a memory device including a stack structure SS in which a larger number of gate layers 150a to 150c and interlayer insulating layers 140 are stacked, the process difficulty caused by the tilt of the stack structure SS is reduced. Therefore, a memory device 100 having a higher integration density is provided.

[0059] The rows DWE1 to DWE3 of the dummy discontinuous cutting parts are spaced apart from one another, extend within the connection region EXT of the stacked structure SS, and are arranged along a first horizontal direction (X direction). The dummy discontinuous cutting parts DWE extend along the first horizontal direction (X direction) and cut the multiple gate layers 150a to 150c of the stacked structure SS. Thus, the rows DWE1 to DWE3 of the dummy discontinuous cutting parts can discontinuously cut the multiple gate layers 150a to 150c in the first horizontal direction (X direction) within the connection region EXT of the stacked structure SS.

[0060] The second row DWE2 of the dummy discontinuous cut may be located between the first row HWE1 and the second row HWE2 of the linking region discontinuous cut, and the third row DWE3 of the dummy discontinuous cut may be located between the second row HWE2 of the linking region discontinuous cut and the continuous cut FW. The first row HWE1 of the linking region discontinuous cut may be located between the first row DWE1 and the second row DWE2 of the dummy discontinuous cut, and the second row HWE2 of the linking region discontinuous cut may be located between the second row DWE2 and the third row DWE3 of the dummy discontinuous cut.

[0061] The first row DWE1 and the second row DWE2 of the dummy discontinuous cuts are spaced apart in a second horizontal direction (Y direction). In an example embodiment, the first row DWE1 of the dummy discontinuous cuts may be aligned with the first consecutive top cut FS1 in the first horizontal direction (X direction), the second row DWE2 of the dummy discontinuous cuts may be aligned with the second consecutive top cut FS2 in the first horizontal direction (X direction), and the third row DWE3 of the dummy discontinuous cuts may be aligned with the third consecutive top cut FS3 in the first horizontal direction (X direction).

[0062] In an exemplary embodiment, the dummy discontinuous breaks DWE may be filled with an insulating material. In an exemplary embodiment, at least one dummy discontinuous break DWE may include a void (not shown) in the insulating material. In particular, the greater the maximum width of the end of the dummy discontinuous break DWE in the second horizontal direction (Y direction) is compared with the maximum width of the center of the dummy discontinuous break HWE in the second horizontal direction (Y direction), the greater the tendency for a void (not shown) to be formed at the end of the dummy discontinuous break HWE.

[0063] The link region discontinuous lower cut HGE is also referred to as a link region lower cut. In an exemplary embodiment, the link region discontinuous lower cut HGE can be filled with an insulating material.

[0064] The rows HGE1, HGE2 of the connection region discontinuous lower cut parts are spaced apart from each other, extend in the cell region CELL of the stacked structure SS, and are arranged along the first horizontal direction (X direction). The connection region discontinuous lower cut parts HGE extend along the first horizontal direction (X direction) and may cut at least one lower gate layer 150a but not cut a plurality of intermediate gate layers 150b and at least one upper gate layer 150c. Thus, the rows HGE1, HGE2 of the connection region discontinuous lower cut parts may cut only the lower gate layer 150a discontinuously in the first horizontal direction (X direction) within the connection region EXT of the stacked structure SS.

[0065] The connection region discontinuous lower cut portion HGE in the first row HGE1 of the connection region discontinuous lower cut portion may be located between two adjacent connection region discontinuous cut portions HWE in the first row HWE1 of the connection region discontinuous cut portion, and the connection region discontinuous lower cut portion HGE in the second row HGE2 of the connection region discontinuous lower cut portion may extend between two adjacent connection region discontinuous cut portions HWE in the second row HWE2 of the connection region discontinuous cut portion.

[0066] The first row HGE1 and the second row HGE2 of the connection region discontinuous lower cut portion are spaced apart in a second horizontal direction (Y direction). In an exemplary embodiment, the connection region discontinuous lower cut portion HGE in the first row HGE1 of the connection region discontinuous lower cut portion is aligned in the second horizontal direction (Y direction) with the cell region discontinuous lower cut portion HGE in the second row HGE2 of the connection region discontinuous lower cut portion.

[0067] In another exemplary embodiment, unlike that shown in FIG. 8A, the connection region discontinuous lower cut portion HGE in the first row HGE1 of the connection region discontinuous lower cut portion may not be aligned in the second horizontal direction (Y direction) with the connection region discontinuous lower cut portion HGE in the second row HGE2 of the connection region discontinuous lower cut portion.

[0068] For example, as shown in FIG. 4B, in an exemplary embodiment, the memory device 100 may further include a first semiconductor layer 132, an etching stop layer 133, and a plurality of support patterns SP between the substrate 110 and the stack structure SS. The gate insulating patterns 163 of the channel structures CH and the dummy channel structures DCH expose the lower portions of the channel patterns 162, and the first semiconductor layer 132 contacts the exposed portions of the channel patterns 162 of the channel structures CH and the dummy channel structures DCH. The etching stop layer 133 is located between the first semiconductor layer 132 and the stack structure SS. The etching stop layer 133 includes a semiconductor material. The etching stop layer 133 can prevent the etching of the first interlayer insulating layer 140a when forming the first gap 181G between the substrate 110 and the first interlayer insulating layer 140a by removing the sacrificial layer 181 shown in FIG. 14G and FIG. 14H.

[0069] The plurality of support patterns SP are planarly surrounded by the first semiconductor layer 132. The support patterns SP include a semiconductor material. The plurality of support patterns SP are two-dimensionally arranged on the substrate 110. In an exemplary embodiment, the etching stop layer 133 and the plurality of support patterns SP may be integrally formed. Thus, the etching stop layer 133 and the plurality of support patterns SP are simultaneously formed of the same material.

[0070] For example, as shown in Fig. 4B, in an exemplary embodiment, the support pattern SP may be overlapped with the cell region discontinuous cut portion HWC in the vertical direction (Z direction), thereby preventing the cell region discontinuous cut portion HWC from being formed to penetrate the sacrificial layer 181 in the stage shown in Fig. 14G, which makes it difficult to remove the sacrificial layer 181 in the stages shown in Fig. 14G and Fig. 14H.

[0071] In an exemplary embodiment, the support pattern SP is located between two adjacent cell region discontinuous cuts in each row HWC1, HWC2 of the cell region discontinuous cuts, and at least one of the multiple support patterns SP may be overlapped in the vertical direction (Z direction) with two adjacent cell region discontinuous cuts in each row HWC1, HWC2 of the cell region discontinuous cuts. Thereby, when the lower surface of at least one cell region discontinuous cut HWC is formed to be upwardly convex, it is possible to prevent the cell region discontinuous cut HWC from being formed to penetrate the sacrificial layer 181 in the stage shown in FIG. 14G, and the sacrificial layer 181 from being difficult to remove in the stage shown in FIG. 14H.

[0072] The memory device 100 may further include an interlayer insulating layer 170 on the stack structure SS. The memory device 100 may further include a plurality of contact plugs CP on a connection region EXT of the stack structure SS extending in a vertical direction (Z direction). The plurality of contact plugs CP are electrically connected to the plurality of gate layers 150a to 150c, respectively. The contact plugs CP include a conductive material.

[0073] FIG. 5 is a schematic cross-sectional view of a cell region discontinuity cut HWC and a row CH1 of a channel structure according to an exemplary embodiment at the first height H1 shown in FIG. 4B.

[0074] 5, the cell region discontinuous cut portion HWC includes an end portion PaC and a center portion PbC arranged along a first horizontal direction (X direction). The cell region discontinuous cut portion HWC includes two end portions PaC spaced apart from each other in the first horizontal direction (X direction) and a center portion PbC between the two end portions PaC.

[0075] In an exemplary embodiment, the cell region discontinuous cut HWC may have a dumbbell-shaped cross section at the first height H1. Thus, the width of the center PbC of the cell region discontinuous cut HWC at the first height H1 in the second horizontal direction (Y direction) is substantially constant regardless of the position in the X direction, while the width of the end PaC of the cell region discontinuous cut HWC at the first height H1 in the second horizontal direction (Y direction) increases as it moves away from the center PbC, and then decreases. The maximum width Wa1 of the end PaC of the cell region discontinuous cut HWC at the first height H1 in the second horizontal direction (Y direction) is wider than the maximum width Wb1 of the center PbC of the cell region discontinuous cut HWC at the first height H1 in the second horizontal direction (Y direction). Therefore, the distance Da1 in the second horizontal direction (Y direction) from the end PaC of the cell region discontinuous cut portion HWC at the first height H1 to the row CH1 of the channel structure is shorter than the distance Db1 in the second horizontal direction (Y direction) from the center PbC of the cell region discontinuous cut portion HWC at the first height H1 to the row CH1 of the channel structure. By forming the maximum width Wa1 in the second horizontal direction (Y direction) of the end PaC of the cell region discontinuous cut portion HWC wider than the maximum width Wb1 in the second horizontal direction (Y direction) of the center PbC of the cell region discontinuous cut portion HWC at the first height H1, the step of forming the cell region discontinuous cut portion HWC and the step of forming the gate layers 150a to 150c can be facilitated.

[0076] FIG. 6 is a cross-sectional view that illustrates a schematic representation of a cell region discontinuous cut HWC according to an embodiment at a second height H2 that is lower (eg, closer to the substrate 110) than the first height H1 illustrated in FIG. 4B.

[0077] 6, in some embodiments, the cell region discontinuous cut portion HWC may have a dumbbell-shaped cross section at the second height H2. Thus, the width in the second horizontal direction (Y direction) of the center PbC of the cell region discontinuous cut portion HWC at the second height H2 is substantially constant regardless of the position in the X direction, while the width in the second horizontal direction (Y direction) of the end PaC of the cell region discontinuous cut portion HWC at the second height H2 increases as it gets farther from the center PbC and then decreases. The maximum width Wa2 in the second horizontal direction (Y direction) of the end PaC of the cell region discontinuous cut portion HWC at the second height H2 is wider than the maximum width Wb2 in the second horizontal direction (Y direction) of the center PbC of the cell region discontinuous cut portion HWC at the second height H2.

[0078] 5 and 6, the maximum width Wa2 in the second horizontal direction (Y direction) of the end PaC of the discontinuous cut portion HWC at the second height H2 is narrower than the maximum width Wa1 in the second horizontal direction (Y direction) of the end PaC of the discontinuous cut portion HWC at the first height H1. The maximum width Wb2 in the second horizontal direction (Y direction) of the center PbC of the discontinuous cut portion HWC at the second height H2 is narrower than or equal to the maximum width Wb1 in the second horizontal direction (Y direction) of the center PbC of the discontinuous cut portion HWC at the first height H1.

[0079] FIG. 7 is a cross-sectional view that illustrates a schematic diagram of a cell region discontinuous cut HWC according to an embodiment of the present disclosure at a second height H2 that is lower than the first height H1 illustrated in FIG. 4B.

[0080] 7, in an exemplary embodiment, the width in the second horizontal direction (Y direction) of the center PbC of the cell region discontinuous cut HWC at the second height H2 is approximately constant regardless of the position in the X direction, while the width in the second horizontal direction (Y direction) of the end PaC of the cell region discontinuous cut HWC at the second height H2 decreases as it moves away from the center PbC. The maximum width Wa2 in the second horizontal direction (Y direction) of the end PaC of the cell region discontinuous cut HWC at the second height H2 is narrower than or equal to the maximum width Wb2 in the second horizontal direction (Y direction) of the center PbC of the cell region discontinuous cut HWC at the second height H2.

[0081] FIG. 9 is a schematic cross-sectional view of a connection region discontinuity cut HWE according to an exemplary embodiment at the first height H1 shown in FIG. 8B.

[0082] 9, the connection region discontinuous cut portion HWE includes an end portion PaE and a center portion PbE arranged along a first horizontal direction (X direction). The connection region discontinuous cut portion HWE includes two end portions PaE spaced apart from each other in the first horizontal direction (X direction) and a center portion PbE between the two end portions PaE.

[0083] In an exemplary embodiment, the connection region discontinuous cut HWE may have a dumbbell-shaped cross section at the first height H1. Thus, the width of the center PbE of the connection region discontinuous cut HWE at the first height H1 in the second horizontal direction (Y direction) is approximately constant regardless of the position in the X direction, while the width of the end PaE of the connection region discontinuous cut HWE at the first height H1 in the second horizontal direction (Y direction) increases as it gets farther from the center PbE, and then decreases. The maximum width Wa3 of the end PaE of the connection region discontinuous cut HWE at the first height H1 in the second horizontal direction (Y direction) is wider than the maximum width Wb3 of the center PbE of the connection region discontinuous cut HWE at the first height H1 in the second horizontal direction (Y direction).

[0084] Comparing Figures 5 and 9, in some embodiments, the maximum width Wa1 in the second horizontal direction (Y direction) of the end PaC of the cell area discontinuous cut portion HWC at the first height H1 is narrower than the maximum width Wa3 in the second horizontal direction (Y direction) of the end PaE of the connecting area discontinuous cut portion HWE at the first height H1.

[0085] FIG. 10 is a cross-sectional view that illustrates a schematic diagram of a connection region discontinuity cut HWE according to an example embodiment at a second height H2 that is lower (eg, closer to the substrate 110) than the first height H1 illustrated in FIG. 8B.

[0086] 10, in an exemplary embodiment, the discontinuous cut portion HWE of the connection region may have a dumbbell-shaped cross section at the second height H2. Thus, the width of the center PbE of the discontinuous cut portion HWE of the connection region at the second height H2 in the second horizontal direction (Y direction) is substantially constant regardless of the position in the X direction, while the width of the end PaE of the discontinuous cut portion HWE of the connection region at the second height H2 in the second horizontal direction (Y direction) increases as it gets farther from the center PbE and then decreases. In an exemplary embodiment, the maximum width Wa4 of the end PaE of the discontinuous cut portion HWE of the connection region at the second height H2 in the second horizontal direction (Y direction) is wider than the maximum width Wb4 of the center PbE of the discontinuous cut portion HWE of the connection region at the second height H2 in the second horizontal direction (Y direction).

[0087] 9 and 10, the maximum width Wa4 in the second horizontal direction (Y direction) of the end PaE of the discontinuous cut portion HWE at the second height H2 is narrower than the maximum width Wa3 in the second horizontal direction (Y direction) of the end PaE of the discontinuous cut portion HWE at the first height H1. The maximum width Wb4 in the second horizontal direction (Y direction) of the center PbE of the discontinuous cut portion HWE at the second height H2 is narrower than or the same as the maximum width Wb3 in the second horizontal direction (Y direction) of the center PbE of the discontinuous cut portion HWE at the first height H1.

[0088] Comparing Figures 6 and 10, in some embodiments, the maximum width Wa2 in the second horizontal direction (Y direction) of the end PaC of the cell area discontinuous cut portion HWC at the second height H2 is wider than the maximum width Wa4 in the second horizontal direction (Y direction) of the end PaE of the connecting area discontinuous cut portion HWE at the second height H2.

[0089] FIG. 11 is a schematic cross-sectional view of a connection region discontinuity cut HWE according to one embodiment at a second height H2 that is lower (eg, closer to the substrate 110) than the first height H1 shown in FIG. 8B.

[0090] 11, in an exemplary embodiment, the width in the second horizontal direction (Y direction) of the center PbE of the discontinuous disconnection HWE at the second height H2 is approximately constant regardless of the position in the X direction, while the width in the second horizontal direction (Y direction) of the end PaE of the discontinuous disconnection HWE at the second height H2 decreases as it gets farther from the center PbE. The maximum width Wa4 in the second horizontal direction (Y direction) of the end PaE of the discontinuous disconnection HWE at the second height H2 is narrower than or equal to the maximum width Wb4 in the second horizontal direction (Y direction) of the center PbE of the discontinuous disconnection HWE at the second height H2.

[0091] FIG. 12 is a schematic cross-sectional view of a memory device 100a according to an example embodiment.

[0092] 12, the memory device 100a may have a COP (Cell on Peri) structure. Thus, the peripheral circuit PC is located between the substrate 110 and the stacked structure SS. The memory device 100a may further include an interlayer insulating layer 120 covering the upper surface of the substrate 110 and the peripheral circuit PC, and a second semiconductor layer 131 between the interlayer insulating layer 120 and the first semiconductor layer 132.

[0093] FIG. 13 is a schematic cross-sectional view of a memory device 100b according to an exemplary embodiment.

[0094] 13, the memory device 100b may have a multi-stack structure. The memory device 100b includes a substrate 110, a first stack structure SS1 on the substrate 110, a second stack structure SS2 on the first stack structure SS1, a plurality of first channel structures CH1 each penetrating the first stack structure SS1, and a plurality of second channel structures CH2 each penetrating the second stack structure SS2 and stacked in the vertical direction (Z direction) on the plurality of first channel structures CH1.

[0095] The first stacked structure SS1 includes a cell region discontinuous lower cut portion HGC2 that cuts only at least one lower gate layer 150a, and the second stacked structure SS2 includes continuous upper cut portions FS1 to FS3 and a discontinuous upper cut portion HS2 that cut only at least one upper gate layer 150c. The cell region discontinuous cut portion HWC1 and the continuous cut portion FW cut the gate layers 150a and 150b of the first stacked structure SS1 and the gate layers 150b and 150c of the second stacked structure SS2. The first interlayer insulating layer 170 is located between the first stacked structure SS1 and the second stacked structure SS2, and the second interlayer insulating layer 171 is located on the second stacked structure SS2.

[0096] 14A through 14K are cross-sectional views illustrating a method for manufacturing a memory device according to an example embodiment. Line B4-B4' in FIG. 14A through 14K corresponds to line B4-B4' in FIG. 4A.

[0097] 14A, a sacrificial layer 181, a plurality of support patterns SP surrounded by the sacrificial layer 181, and an etch stop layer 133 on the sacrificial layer 181 are formed on a substrate 110. The sacrificial layer 181 includes a material having a high etch selectivity with respect to the etch stop layer 133. The sacrificial layer 181 includes, for example, silicon nitride. In an exemplary embodiment, the plurality of support patterns SP and the etch stop layer 133 may be integrally formed at the same time.

[0098] 14B, a first interlayer insulating layer 140a and a first sacrificial layer 180a are formed on the etching stop layer 133. The first sacrificial layer 180a includes a material having a high etching selectivity with respect to the first interlayer insulating layer 140a, for example, silicon nitride. Then, the cell region discontinuous lower cut portions HGC1, HGC2 (FIGS. 4A to 4C) and the connection region discontinuous lower cut portions HGE1, HGE2 (FIGS. 8A and 8B) are formed to cut the first sacrificial layer 180a, and then the cell region discontinuous lower cut portions HGC1, HGC2 (FIGS. 4A to 4C) and the connection region discontinuous lower cut portions HGE1, HGE2 (FIGS. 8A and 8B) are filled with an insulating material.

[0099] 14C, a plurality of interlayer insulating layers 140 and a plurality of sacrificial layers 180b, 180c are alternately formed on the first sacrificial layer 180a. The plurality of interlayer insulating layers 140 and the plurality of sacrificial layers 180b, 180c are patterned in a stepped shape as shown in FIG. 8C. Then, an interlayer insulating layer 170 is formed on the upper sacrificial layer 180c.

[0100] Referring to FIG. 14D, a plurality of channel holes CHO penetrating the plurality of sacrificial layers 180a through 180c, 181, the plurality of interlayer insulating layers 140, 140a, 170 and the etch stop layer 133, and a plurality of dummy channel holes (not shown) are formed.

[0101] 14E, a plurality of channel structures CH are formed in a plurality of channel holes CHO, and a plurality of dummy channel structures DCH (FIGS. 8A and 8B) are formed in a plurality of dummy channel holes (not shown). For example, a gate insulating layer, a channel layer, and a buried insulating layer are formed on the plurality of channel holes CHO and the plurality of dummy channel holes (not shown), and then the gate insulating layer, the channel layer, and the buried insulating layer are planarized to expose the interlayer insulating layer 170, thereby forming a gate insulating pattern 163, a channel pattern 162, and a buried insulating pattern 161. Then, upper portions of the gate insulating pattern 163, the channel pattern 162, and the buried insulating pattern 161 are removed to form a recess, a pad layer is formed on the recess, and the pad layer is planarized to form a pad pattern 164.

[0102] Referring to FIG. 14F, continuous upper cut portions FS1 to FS3 and discontinuous upper cut portions HS1 and HS2 (FIGS. 4A and 4B) are formed to cut at least one upper sacrificial layer 180c, and the continuous upper cut portions FS1 to FS3 and the discontinuous upper cut portions HS1 and HS2 are filled with an insulating material.

[0103] 14G, the cell region discontinuous cut portions HWC1 and HWC2 (FIGS. 4A to 4C), the connection region discontinuous cut portion HWE (FIGS. 8A and 8B), the dummy discontinuous cut portion DWE (FIGS. 8A and 8B), and the continuous cut portion FW are formed to cut the plurality of sacrificial layers 180a to 180c. In an exemplary embodiment, the maximum width Wb1g in the second horizontal direction (Y direction) of the center portion of the cell region discontinuous cut portion HWC1 at the first height H1 may be substantially the same as the maximum width W5g in the second horizontal direction (Y direction) of the continuous cut portion FW at the first height H1.

[0104] Although not shown in FIG. 14G, referring to FIG. 4D, the cell region discontinuous cut portions HWC1, HWC2 (FIGS. 4A to 4C), the connection region discontinuous cut portion HWE (FIGS. 8A and 8B), the dummy discontinuous cut portion DWE (FIGS. 8A and 8B) and the continuous cut portion FW expose portions of the sacrificial layer 181.

[0105] Then, a cover layer 190 is formed on the sidewalls of the cell region discontinuous cuts HWC1 and HWC2 (FIGS. 4A to 4C), the connection region discontinuous cuts HWE (FIGS. 8A and 8B), the dummy discontinuous cuts DWE (FIGS. 8A and 8B), and the continuous cuts FW. The cover layer 190 may not cover the bottoms of the cell region discontinuous cuts HWC1 and HWC2 (FIGS. 4A to 4C), the connection region discontinuous cuts HWE (FIGS. 8A and 8B), the dummy discontinuous cuts DWE (FIGS. 8A and 8B), and the continuous cuts FW. Thus, although not shown in FIG. 14G, referring to FIG. 4D, the cover layer 190 exposes a portion of the sacrificial layer 181. The cover layer 190 includes a material having a high selectivity with respect to the sacrificial layer 181, for example, a semiconductor material.

[0106] 14G and 14H, the sacrificial layer 181 is removed by wet etching or dry etching through the cell region discontinuous cut portions HWC1 and HWC2 (FIGS. 4A to 4C), the connection region discontinuous cut portion HWE (FIGS. 8A and 8B), the dummy discontinuous cut portion DWE (FIGS. 8A and 8B), and the continuous cut portion FW to form a first gap 181G between the substrate 110 and the etching stop layer 133. The first gap 181G exposes a portion of the sidewall of the gate insulating pattern 163 of the channel structure CH and the dummy channel structure DCH (FIG. 8B). Even when the first gap 181G is formed, the etching stop layer 133, the interlayer insulating layers 140, and the sacrificial layers 180a to 180c are supported by the channel structures CH, the dummy channel structures DCH, and the support patterns SP to prevent them from collapsing.

[0107] Next, a portion of the gate insulation pattern 163 of the channel structure CH and the dummy channel structure DCH (FIG. 8B) exposed by the first gap 181G is removed, thereby exposing a portion of the channel pattern 162 of the channel structure CH and the dummy channel structure DCH (FIG. 8B) to the first gap 181G.

[0108] 14H and 14I, the first gap 181G is filled with a first semiconductor layer 132. As shown in FIG.

[0109] 14I and 14J, the cover layer 190 and the sacrificial layers 180a to 180c are removed to form the second gaps 180G between the interlayer insulating layers 140. While the sacrificial layers 180a to 180c are removed, the sidewalls of the cell region discontinuous cut portion HWC1 and the continuous cut portion FW are tilted due to the expansion of the interlayer insulating layers 140. For example, the maximum width Wb1j in the second horizontal direction (Y direction) of the center of the cell region discontinuous cut portion HWC1 at the first height H1 is wider than the maximum width Wb1g in the second horizontal direction (Y direction) of the center of the cell region discontinuous cut portion HWC1 just formed at the stage shown in FIG. 14G. On the other hand, the maximum width W5j in the second horizontal direction (Y direction) of the continuous cut portion FW at the first height H1 is narrower than the maximum width W5g in the second horizontal direction (Y direction) of the continuous cut portion FW just formed at the stage shown in Fig. 14G. Therefore, the maximum width Wb1j in the second horizontal direction (Y direction) of the center portion of the cell region discontinuous cut portion HWC1 at the first height H1 is wider than the maximum width W5j in the second horizontal direction (Y direction) of the continuous cut portion FW at the first height H1.

[0110] 14J and 14K, the second gaps 180G are filled with the gate layers 150a to 150c, respectively. During the formation of the gate layers 150a to 150c, the sidewalls of the cell region discontinuous cut portion HWC1 and the continuous cut portion FW are tilted due to material shrinkage. For example, the maximum width Wb1k in the second horizontal direction (Y direction) of the center of the cell region discontinuous cut portion HWC1 at the first height H1 is narrower than the maximum width Wb1g in the second horizontal direction (Y direction) of the center of the cell region discontinuous cut portion HWC1 just formed at the stage shown in FIG. 14G. Meanwhile, the maximum width W5k in the second horizontal direction (Y direction) of the continuous cut portion FW at the first height H1 is wider than the maximum width W5g in the second horizontal direction (Y direction) of the continuous cut portion FW just formed at the stage shown in FIG. 14G. Therefore, the maximum width Wb1k in the second horizontal direction (Y direction) of the center of the cell area discontinuous cut portion HWC1 at the first height H1 is narrower than the maximum width W5k in the second horizontal direction (Y direction) of the continuous cut portion FW at the first height H1.

[0111] 4A to 4D and 8A to 8C, the cell region discontinuous cut portion HWC, the connection region discontinuous cut portion HWE, the dummy discontinuous cut portion DWE, and the continuous cut portion FW are filled with an insulating material IM. Also, a plurality of contact plugs CP may be formed in contact with the plurality of gate layers 150a to 150c, respectively. Thus, the memory device 100 is manufactured.

[0112] The embodiments of the present disclosure are intended to explain the technical idea of ​​the present disclosure, not to limit it, and the scope of the technical idea of ​​the present disclosure is not limited by the embodiments. The scope of protection of the present disclosure should be interpreted according to the claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of rights of the present disclosure. [Industrial Applicability]

[0113] The present invention is applicable, for example, to technical fields related to memory devices. [Explanation of symbols]

[0114] 10, 100, 100a, 100b Memory device 11 Memory Cell Array 12 Row Decoder 13 Input / Output Circuit 14 Control Logic 110 Substrate 120, 140, 170, 171 Interlayer insulation layer 131 Second semiconductor layer 132 First semiconductor layer 133 Etch stop layer 150a to 150c Gate layer 161 Buried insulation pattern 162 Channel Patterns 163 Gate insulation pattern 164 Pad Patterns BL Bit Line BLK1 or BLKz memory block CELL Cell area CH Channel structure CSL Common Source Line DCH Dummy channel structure DWE, DWE1 or DWE3 Dummy discontinuity cut EXT concatenation area FS1 to FS3 Continuous upper cut FW Continuous cutting section GSL Ground Selection Line GST Ground Select Transistor Discontinuous lower section of the HE, HGE1, and HGE2 junction region HGC, HGC1, HGC2 Cell area discontinuous lower cut HS, HS1, HS2 Discontinuous upper cut HWC, HWC1, HWC2 Cell area discontinuity cut Discontinuous breaks in the HWE, HWE1, and HWE2 connected regions MC1 to MC8 memory cells NS11 or NS33 NAND string PC peripheral circuits SP Support Pattern SS laminated structure SS1 First laminated structure SS2 Second laminated structure SSL String Selection Line SST String Select Transistor WL Word Line

Claims

1. A substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate; a row of channel structures arranged in a first horizontal direction within a cell region of the stack structure, each row extending in the vertical direction and passing through the plurality of gate layers; the stacked structures each include a cutting row extending in the first horizontal direction and cutting the gate layers; The cut portions are spaced apart from each other and arranged in the first horizontal direction within the cell region, a maximum width, measured in a second horizontal direction perpendicular to the first horizontal direction, of an end of at least one of the rows of cut portions in the first horizontal direction at a first height from the substrate, which is greater than a maximum width, measured in the second horizontal direction, of a center of the at least one cut portion in the first horizontal direction.

2. 2. The memory device of claim 1 , wherein at the first height, the second horizontal distance from the end to the row of channel structures is less than the second horizontal distance from the center to the row of channel structures.

3. 2. The memory device of claim 1, wherein a maximum width measured in the second horizontal direction of the edge at the second height is narrower than the maximum width of the edge at the first height, and the second height is lower than the first height relative to the substrate.

4. 2. The memory device of claim 1, wherein at a second height relative to the substrate that is lower than the first height, a maximum width measured in the second horizontal direction of the end portion is narrower than or equal to a maximum width measured in the second horizontal direction of the center portion.

5. the plurality of gate layers include at least one lower gate layer, a plurality of intermediate gate layers on the at least one lower gate layer, and at least one upper gate layer on the plurality of intermediate gate layers; 2. The memory device of claim 1, wherein the stacked structure further comprises upper cut section rows spaced apart from each other and arranged along the first horizontal direction in the cell region, each extending in the first horizontal direction between two adjacent cut sections in the cut section row, cutting the at least one upper gate layer, but not cutting the multiple intermediate gate layers and the at least one lower gate layer.

6. the plurality of gate layers include at least one lower gate layer, a plurality of intermediate gate layers on the at least one lower gate layer, and at least one upper gate layer on the plurality of intermediate gate layers; 2. The memory device of claim 1, wherein the stacked structure further comprises lower cut section rows spaced apart from each other and arranged along the first horizontal direction in the cell region, each extending in the first horizontal direction between two adjacent cut sections in the cut section row, cutting the at least one lower gate layer, but not cutting the plurality of intermediate gate layers and the at least one upper gate layer.

7. A substrate, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate; rows of channel structures arranged in a first horizontal direction within a cell region of the stack structure, each row extending in the vertical direction and passing through the plurality of gate layers; a semiconductor layer between the substrate and the laminated structure, and a plurality of supporting patterns each surrounded by the semiconductor layer; the stacked structures each include a cutting row extending in the first horizontal direction and cutting the gate layers; The cut portions are spaced apart from each other and arranged in the first horizontal direction within the cell region, At least one of the plurality of support patterns is vertically overlapped with at least one of the rows of the cut portion.

8. 8. The memory device of claim 7, wherein the at least one of the plurality of support patterns overlaps two adjacent cuts in the row of cuts in the vertical direction.

9. The memory device according to claim 8 , wherein a lower surface of at least one of the two cut portions is convex upward with respect to the substrate.

10. A substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate; a channel structure arranged in a cell region of the stacked structure in a first row, a second row, and a third row extending in a first horizontal direction, each of the channel structures extending in the vertical direction and penetrating the plurality of gate layers; the stacked structure includes a first row of discontinuous cut portions that discontinuously cut the plurality of gate layers in the first horizontal direction between a first row of the channel structures and a second row of the channel structures in the cell region; the stacked structure further includes a continuous cutting portion that continuously cuts the plurality of gate layers in the cell region in the first horizontal direction, a second row and a third row of the channel structure are located between the first row of the discontinuous cut and the continuous cut; A memory device characterized in that, at a first height from the substrate, a maximum width measured in a second horizontal direction perpendicular to the first horizontal direction of an end portion in the first horizontal direction of at least one discontinuous cut of a first row of the discontinuous cuts is wider than a maximum width measured in the second horizontal direction of a center portion in the first horizontal direction of the at least one discontinuous cut.

11. 11. The memory device of claim 10, wherein the maximum width of the central portion of the at least one discontinuous cut at the first height relative to the substrate is less than the maximum width of the continuous cut measured in the second horizontal direction.

12. 11. The memory device of claim 10, wherein the continuous cutting portion continuously cuts the plurality of gate layers in the first horizontal direction within a connection region of the stacked structure.

13. 11. The memory device of claim 10, wherein the stack structure further comprises a second row of discontinuous cuts that discontinuously cut the plurality of gate layers in the first horizontal direction between the second row of the channel structures and the third row of the channel structures in the cell region.

14. The method of claim 13, wherein the plurality of gate layers includes at least one lower gate layer, a plurality of intermediate gate layers on the at least one lower gate layer, and at least one upper gate layer on the plurality of intermediate gate layers; a gap exists between two adjacent discontinuous cuts in a first row of the discontinuous cuts that does not cut at least the plurality of intermediate gate layers; a gap exists between two adjacent discontinuous cuts in a second row of the discontinuous cuts that does not cut at least the plurality of intermediate gate layers; 14. The memory device of claim 13, wherein the gap between two adjacent discontinuous cuts in a first row of discontinuous cuts is not aligned in the second horizontal direction with the gap between two adjacent discontinuous cuts in a second row of discontinuous cuts.

15. the plurality of gate layers include at least one lower gate layer, a plurality of intermediate gate layers on the at least one lower gate layer, and at least one upper gate layer on the plurality of intermediate gate layers; The stacked structure further includes a row of discontinuous upper cuts that discontinuously cut the at least one upper gate layer along the first horizontal direction and do not cut the plurality of intermediate gate layers and the at least one lower gate layer; 11. The memory device of claim 10, wherein each of the discontinuous top cuts extends between two adjacent discontinuous cuts in a first row of the discontinuous cuts.

16. A substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers stacked alternately in a vertical direction on the substrate; a plurality of channel structures extending vertically within a cell region of the stack structure and penetrating the plurality of gate layers; a semiconductor layer between the substrate and the laminated structure, and a plurality of supporting patterns each surrounded by the semiconductor layer; the stacked structure includes rows of cell area cutting portions each extending in a first horizontal direction and cutting the gate layers; The cell area cut portions are spaced apart from each other and arranged along the first horizontal direction within the cell area, The stack structure further includes a row of connecting region disconnecting portions each extending in the first horizontal direction and disconnecting the plurality of gate layers; The connection region cut portions are spaced apart from each other and are arranged along the first horizontal direction within the connection region of the laminated structure, 13. The memory device according to claim 12, wherein at least one of the plurality of support patterns vertically overlaps at least one of the rows of the cell region cutting portion and the rows of the connection region cutting portion.

17. At a first height relative to the substrate, a maximum width measured in a second horizontal direction perpendicular to the first horizontal direction of an end portion of at least one of the rows of the cell area cut portions in the first horizontal direction is wider than a maximum width measured in the second horizontal direction of a center portion of the at least one cell area cut portion in the first horizontal direction; 17. The memory device of claim 16, wherein at the first height, a maximum width measured in the second horizontal direction of an end of at least one connection region cut portion in the first horizontal direction is greater than a maximum width measured in the second horizontal direction of a center of the at least one connection region cut portion in the first horizontal direction.

18. 20. The memory device of claim 17, wherein the maximum width of the end of the at least one cell region cut portion at the first height is narrower than the maximum width of the end of the at least one connection region cut portion.

19. 17. The memory device of claim 16, wherein a maximum width measured in a second horizontal direction perpendicular to the first horizontal direction of an end of at least one cell area cut portion of the rows of the cell area cut portion at a second height relative to the substrate is wider than a maximum width measured in the second horizontal direction of an end of at least one connection area cut portion of the rows of the connection area cut portion in the first horizontal direction.

Images