Vertical Memory Device

Abstract

To provide a vertical memory device with improved electric characteristics.SOLUTION: A vertical memory device includes: gate electrode structures separated from each other on a substrate along a first direction perpendicular to an upper surface of the substrate, each including a gate electrode extending in a second direction parallel to the upper surface of the substrate, and disposed along a third direction intersecting with the second direction in parallel to the upper surface of the substrate; channels 200 each extending in the first direction penetrating each gate electrode structure; a first separation pattern 230 extending in the second direction between the gate electrode structures and separating the gate electrode structures in the third direction; second and third separation patterns 235 and 350 disposed between the gate electrode structures alternately in the second direction, connected to each other, and separating the gate electrode structures; and a first supporting film formed on the gate electrode structure, having the same height as an upper part of the first and second separation patterns, and being in contact with these. The first separation pattern and the second separation pattern are disposed in a zigzag pattern in the second direction in a plan view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to vertical memory devices. [Background technology]

[0002] In a VNAND flash memory device, as the number of gate electrodes stacked increases, there is a concern that the mold including the sacrificial film for forming the gate electrodes may bend or collapse during the process of forming the gate electrodes, which may affect the electrical characteristics. Therefore, a method for preventing the mold from bending and / or collapsing is required. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT EMBODIMENT It is an object of the present invention to provide a vertical memory device having improved electrical characteristics. [Means for solving the problem]

[0004] In order to achieve the above-mentioned object of the present invention, a vertical memory device according to an exemplary embodiment may include gate electrodes spaced apart from each other on a substrate along a first direction perpendicular to an upper surface of the substrate, each extending in a second direction parallel to the upper surface of the substrate, and arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction, channels extending in the first direction through the gate electrode structures, a first isolation pattern extending in the second direction between the gate electrode structures and separating them in the third direction, second and third isolation patterns alternately arranged in the second direction between the gate electrode structures and connected to each other, both separating the gate electrode structures, and a first support layer formed on the gate electrode structures and formed at the same height as upper portions of the first and second isolation patterns and in contact with them, the first isolation pattern and the second isolation pattern being arranged in a zigzag pattern in the second direction in a plan view.

[0005] In order to achieve the above-mentioned object of the present invention, a vertical memory device according to another exemplary embodiment may include gate electrodes spaced apart on a substrate along a first direction perpendicular to an upper surface of the substrate, the gate electrodes each extending in a second direction parallel to the upper surface of the substrate, the gate electrodes being arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction, channels extending in the first direction through the gate electrode structures, first lower parts extending in the second direction between the gate electrode structures and separating them in the third direction, and first upper parts contacting upper surfaces of the first lower parts and spaced apart from each other in the second direction, a second isolated pattern including second lower parts spaced apart from each other in the second direction between the gate electrode structures and second upper parts contacting upper surfaces of the second lower parts, a third isolated pattern formed between the second lower parts of the second isolated patterns and connected to each other, and a supporting layer formed on the gate electrode structures and facing sidewalls of the first and second upper parts of the first and second isolated patterns.

[0006] In order to achieve the above-mentioned object of the present invention, a vertical memory device according to yet another exemplary embodiment may include gate electrodes spaced apart on a substrate along a first direction perpendicular to an upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate, gate electrode structures arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction, channels extending through the gate electrode structures in the first direction, first isolation patterns extending in the second direction between the gate electrode structures and separating them in the third direction, second isolation patterns spaced apart from each other along the second direction between the gate electrode structures, a support layer formed on the gate electrode structures and the first and second isolation patterns, the support layer including first and second openings at least partially exposing upper surfaces of the first and second isolation patterns, and first and second insulating patterns filling the first and second openings, respectively, and the first and second insulating patterns may be arranged in a zigzag pattern toward the third direction.

[0007] In order to achieve the above-described object of the present invention, a vertical memory device according to still another exemplary embodiment includes a common electrode plate (CSP) formed on a substrate, a channel connection pattern and a first supporting film stacked on the CSP along a first direction perpendicular to an upper surface of the substrate, gate electrodes spaced apart from each other along the first direction on the first supporting film and each extending in a second direction parallel to the upper surface of the substrate, and arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction, gate electrode structures each extending in the first direction through the gate electrode structures, the first supporting film, and the channel connection pattern on the CSP, a first isolation pattern formed on the CSP and extending in the second direction between the gate electrode structures to separate them in the third direction; second and third isolation patterns formed on the CSP and alternately disposed in the second direction between the gate electrode structures and connected to each other to both separate the gate electrode structures; and a second support layer formed on the gate electrode structures and formed to the same height as upper portions of the first and second isolation patterns and in contact with them, wherein the first isolation pattern and the second isolation pattern are arranged in a zigzag pattern in the second direction in a plan view. Effect of the Invention

[0008] A vertical memory device according to an exemplary embodiment may include second to fourth isolation patterns formed between the gate electrode structures and a second support film formed on the gate electrode structures, which may prevent the gate electrode structures from bending or collapsing. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view illustrating a vertical memory device according to an example embodiment; [Figure 2A] 1 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment; [Figure 2B]1 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment; [Diagram 3] 1 is a cross-sectional view illustrating a vertical memory device according to an exemplary embodiment; [Figure 4] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 6] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 8] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 10] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 16] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 17]1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 18] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 20] 1A to 1C are plan views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Diagram 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Diagram 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical memory device according to an example embodiment. [Figure 26] 1 is a plan view illustrating a vertical memory device according to an example embodiment; [Figure 27] 1 is a plan view illustrating a vertical memory device according to an example embodiment; [Figure 28] 1 is a plan view illustrating a vertical memory device according to an example embodiment; [Figure 29] 1 is a plan view illustrating a vertical memory device according to an example embodiment; [Diagram 30] 1 is a plan view illustrating a vertical memory device according to an example embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a vertical memory device and a manufacturing method thereof according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. In the present invention, terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another component.

[0011] In the following detailed description of the invention (excluding the claims), a direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two mutually intersecting horizontal directions substantially parallel to the upper surface of the substrate are defined as a second direction and a third direction, respectively. In an exemplary embodiment, the second direction and the third direction may be orthogonal to each other.

[0012] 1, 2a, 2b, and 3 are plan and cross-sectional views for explaining a vertical memory device according to an exemplary embodiment. Specifically, FIG 1 is a plan view, FIG 2a and FIG 2b are cross-sectional views taken along line A-A' in FIG 1, and FIG 3 is a cross-sectional view taken along line B-B' in FIG 1. To avoid complicating the drawings, fourth and fifth interlayer insulating films, contact plugs, and wiring are not shown in FIG 1.

[0013] 1, 2a, and 3, the vertical memory device may include a common source plate (CSP) 100, a channel connection pattern 280, a first supporting film 150, a second supporting film 300, a gate electrode structure, a channel 200, a charge storage structure 190, and first to fourth isolation patterns 230, 235, 350, and 355 formed on a substrate 10. The vertical memory device may further include a lower circuit pattern, a charging pattern 210, a capping pattern 220, an insulating pattern 165, first to fourth interlayer insulating films 20, 180, 240, and 360, a fifth interlayer insulating film, a contact plug 370, and an upper wiring 380.

[0014] The substrate 10 may include a semiconductor material such as silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0015] In an exemplary embodiment, the vertical memory device may have a cell over peri (COP) structure. That is, a lower circuit pattern may be formed on the substrate 10, and memory cells may be formed on the lower circuit pattern. The lower circuit pattern may include, for example, a transistor, a lower contact plug, a lower wiring, a lower via, etc. The lower circuit pattern may be covered by a first interlayer insulating film 20 formed on the substrate 10.

[0016] The CSP 100 may be formed on the first interlayer insulating film 20 and may include, for example, polysilicon doped with n-type impurities.

[0017] The gate electrode structure may include a plurality of gate electrodes 342, 344, 346 spaced apart from one another along a first direction on the CSP 100. Each of the gate electrodes 342, 344, 346 may extend in a second direction, and the length of each of the gate electrodes 342, 344, 346 extending in the second direction may become smaller from the lower layer to the upper layer, so that the gate electrode structure may have a stepped shape.

[0018] The gate electrodes 342, 344, and 346 may include first to third gate electrodes 342, 344, and 346 sequentially stacked along a first direction. In this case, the first gate electrode 342 extending in the second direction may act as a ground selection line (GSL), the second gate electrode 344 extending in the second direction may act as a word line (WL), and the third gate electrode 346 extending in the second direction may act as a string selection line (SSL).

[0019] Each of the first to third gate electrodes 342, 344, 346 may be formed in one or more layers. In an exemplary embodiment, the first gate electrode 342 is formed in the bottom layer, the third gate electrode 346 is formed in the top layer and one layer below it, and the second gate electrode 344 may be formed in multiple layers between the first gate electrode 342 and the third gate electrode 346. The top layer is located farthest from the substrate 10, and the bottom layer is located closest to the substrate 10. In other words, the top layer or upper layer is closer to the first support film 150 than the substrate 10.

[0020] Meanwhile, each of the gate electrodes 342, 344, and 346 may include a conductive pattern and a barrier pattern covering the upper and lower surfaces and some of the side walls thereof. The conductive pattern may include a metal having low electrical resistance, such as tungsten, titanium, tantalum, or platinum, and the barrier pattern may include a metal nitride, such as titanium nitride or tantalum nitride.

[0021] The top and bottom surfaces of the gate electrodes 342, 344, and 346, and sidewalls facing the channel 200 may be covered by a second blocking pattern 335. The second blocking pattern 335 may include a metal oxide such as aluminum oxide or hafnium oxide, and may also cover the insulating patterns 165, the first and second support films 150 and 300, the channel connecting pattern 280, the sidewalls of the second and third interlayer insulating films 180 and 240, and a part of the top surface of the CSP 100.

[0022] An insulating pattern 165 may be formed between the gate electrodes 342, 344, and 346 adjacent to each other in the first direction, and the gate electrodes 342, 344, and 346 and the insulating pattern 165 may form a stepped mold together. The insulating pattern 165 may include an oxide, such as silicon oxide.

[0023] In an exemplary embodiment, the gate electrode structure may extend in the second direction and may be formed in a plurality of gate electrode structures along the third direction, and second to fourth isolation patterns 235, 350, 355 may be formed between the gate electrode structures such that they are isolated from each other in the third direction.

[0024] The third isolation pattern 350 may include first lower portions 350a extending in the second direction between the gate electrode structures and first upper portions 350b each in contact with an upper surface of the first lower portion 350a and spaced apart from each other in the second direction. The first lower portions 350a of the third isolation pattern 350 may separate the gate electrode structures from each other in the third direction.

[0025] In one embodiment, the width of each of the first upper portions 350b in the third direction may be greater than the width of the first lower portion 350a in the third direction, but the concept of the present invention is not limited thereto. The second blocking pattern 335 may cover a portion of a sidewall of the first lower portion 350a and a sidewall of the first upper portion 350b of the third isolated pattern 350. The third isolated pattern 350 may be formed in a plurality of portions spaced apart from each other in the third direction.

[0026] The fourth isolated patterns 355 may include second lower portions 355a spaced apart from each other in the second direction between the gate electrode structures, and second upper portions 355b commonly contacting top surfaces of the second lower portions 355a adjacent to each other in the second direction. In an exemplary embodiment, the fourth isolated patterns 355 may be formed between the third isolated patterns 350 adjacent to each other in the third direction.

[0027] In one embodiment, the width of each second upper portion 355b in the third direction may be greater than the width of each second lower portion 355a in the third direction, but the concept of the present invention is not limited thereto. The second blocking pattern 335 may cover a portion of a sidewall of the second lower portion 355a of the fourth separated pattern 355 and a sidewall of the second upper portion 355b. In other words, the second upper portion 355b and the second lower portion 355a of the fourth separated pattern 335 may be similar to the first upper portion 350b and the first lower portion 350a of the third separated pattern 350, but the concept of the present invention is not limited thereto.

[0028] In an exemplary embodiment, the first upper portion 350b of the third separated pattern 350 and the second upper portion 355b of the fourth separated pattern 355 may be arranged in a zigzag pattern in the second or third direction when viewed from above. Alternatively, the third and fourth separated patterns may be arranged alternately in a plan view. In an exemplary embodiment, each first upper portion 350b of the third separated pattern 350 may partially overlap the second upper portion 355b of the fourth separated pattern 355 when viewed along the third direction. In an exemplary embodiment, the first upper portion 350b of the third separated pattern 350 and the second upper portion 355b of the fourth separated pattern 355 may be arranged at substantially the same height.

[0029] The third and fourth isolated patterns 350, 355 may include the same insulating material, for example, an oxide such as silicon oxide. Thus, the entire third and fourth isolated patterns 350, 355, or the first and second upper portions 350b, 355b, or the first and second lower portions 350a, 355a of the third and fourth isolated patterns 350, 355 may be simply referred to as first and second insulating patterns, respectively. In this case, when the first and second upper portions 350b, 355b of the third and fourth isolated patterns 350, 355 are referred to as first and second insulating patterns, respectively, they may be arranged in a zigzag pattern along the second or third direction, and each first insulating pattern may partially overlap with the second insulating pattern when viewed along the third direction.

[0030] The second isolated patterns 235 may be formed between and connected to the second lower portions 355a of the fourth isolated patterns 355 adjacent to each other in the second direction. Thus, the gate electrode structures may be separated from each other in the third direction by the second isolated patterns 235 and the second lower portions 355a of the fourth isolated patterns 355. In an exemplary embodiment, each second isolated pattern 235 may overlap with the second upper portion 355b of the fourth isolated pattern 355 when viewed along the first direction.

[0031] In an exemplary embodiment, the height of the upper surface of the second isolated pattern 235 may be the same as the height of the upper surface of the second interlayer insulating film 180 formed on the top insulating pattern 165 and the capping pattern 220, and thus may be lower than the height of the upper surfaces of the first and second lower portions 350a, 355a of the third and fourth isolated patterns 350, 355, which is the same as the height of the upper surface of the third interlayer insulating film 240 formed on the second interlayer insulating film 180. In other words, the distance between the first and second lower portions 350a, 355a of the third and fourth isolated patterns 350, 355 and the substrate 10 may be greater than the distance between the upper surface of the second isolated pattern 235 and the substrate 10.

[0032] The second isolated pattern 235 may include an oxide, such as silicon oxide, such that the second to fourth isolated patterns 235, 350, and 355 may include substantially the same material as one another.

[0033] The channel 200 may be formed in a channel hole that exposes the top surface of the CSP 100 by penetrating a mold including first to third gate electrodes 342, 344, and 346 stacked along a first direction on the CSP 100 and an insulating pattern 165 interposed therebetween, and a second interlayer insulating film 180 formed on the mold, and thus may extend in the first direction.

[0034] The channel 200 may extend in a first direction over the CSP 100 and may have a cup shape. The channel 200 may include polysilicon, which may or may not be doped with impurities, or single crystal silicon.

[0035] In an exemplary embodiment, the channels 200 may be formed in a plurality of pieces spaced apart from each other along the second and third directions. In this case, the plurality of channels 200 arranged in the second direction may form a channel row, the plurality of channel rows spaced apart from each other in the third direction may form a channel group, and the plurality of channel groups spaced apart from each other in the third direction may form a channel block. Although the drawing shows an example in which one channel block includes two channel groups and each channel group includes nine channel rows, the concept of the present invention is not necessarily limited thereto.

[0036] The charge storage structure 190 may include a cylindrical upper portion extending in a first direction to cover most of the outer wall of the channel 200, and a cup-shaped lower portion formed on the CSP 100, separated from the upper portion, and covering the bottom and lower sidewall of the channel 200. Each of the upper and lower portions of the charge storage structure 190 may include a tunnel insulating pattern, a charge storage pattern, and a first blocking pattern, which are sequentially stacked from the outer wall and / or bottom of the channel 200.

[0037] The tunnel insulating pattern may include an oxide such as, for example, silicon oxide, the charge storage pattern may include a nitride such as, for example, silicon nitride, and the first blocking pattern may include an oxide such as, for example, silicon oxide.

[0038] The charging pattern 210 may fill the space formed by the inner walls of the channel 200. The charging pattern 210 may include an oxide, such as, for example, silicon oxide.

[0039] The channel 200, the charge storage structure 190, and the charge pattern 210 may be formed in a channel hole formed on the CSP 100, and a capping pattern 220 may be formed on the upper portion of the channel hole, i.e., on the channel 200, the charge storage structure 190, and the charge pattern 210. The capping pattern 220 may include, for example, polysilicon doped with n-type impurities.

[0040] The first isolation pattern 230 may penetrate the upper portion of the channel 200 belonging to the channel row formed in the middle portion in the third direction of each channel group, and may extend in the second direction. That is, the first isolation pattern 230 may extend in the second direction between the third and fourth isolation patterns 350 and 355. In an exemplary embodiment, the first isolation pattern 230 may penetrate not only the upper portion of the channel 200, but also the upper portion of the charge storage structure 190 and the charge pattern 210, the capping pattern 220, the second interlayer insulating film 180, the insulating pattern 165 formed in the upper two layers, and the third gate electrode 346. Thus, the third gate electrode 346 formed in the upper two layers of each gate electrode structure may be separated in the third direction by the first isolation pattern 230.

[0041] The channel connection pattern 280 and the first support film 150 may be sequentially stacked along a first direction on the CSP 100. The channel connection pattern 280 may be formed on the lower outer wall of each channel 200, i.e., between the upper and lower parts of the charge storage structure 190, and may contact the outer wall of each channel 200 that is not covered thereby, thereby connecting the channels 200 included in each channel group to each other. The channel connection pattern 280 may include, for example, polysilicon doped with n-type impurities, and may have an air gap 285 formed therein.

[0042] The first support layer 150 may be formed between the channel connection pattern 280 and the first gate electrode 342. However, a portion of the first support layer 150 may penetrate the channel connection pattern 280 and contact the top surface of the CSP 100, and this portion may be referred to as a support pattern (not shown). A plurality of support patterns may be formed and may be formed in various layouts. The first support layer 150 may include, for example, polysilicon doped with n-type impurities.

[0043] A second interlayer insulating film 180 may be formed on the CSP 100 and the top insulating pattern 165 while covering the mold, and a third interlayer insulating film 240 may be formed on the second interlayer insulating film 180, the capping pattern 220, and the first and second isolation patterns 230 and 235.

[0044] The second supporting film 300 may be formed on the third interlayer insulating film 240 and may include fifth and sixth openings 310, 315 (see FIG. 18). Thus, the second supporting film 300 may be formed to the same height as the first and second upper portions 350b, 355b of the third and fourth isolation patterns 350, 355 formed in the fifth and sixth openings 310, 315, respectively, and may face the second blocking pattern 335 formed on the sidewalls thereof. The second supporting film 300 may include an oxide such as silicon oxide.

[0045] A fourth interlayer insulating layer 360 may be formed on the second supporting layer 300 and the first and second upper portions 350 b , 355 b of the third and fourth isolation patterns 350 , 355 , and a fifth interlayer insulating layer may be formed on the fourth interlayer insulating layer 360 .

[0046] The contact plug 370 may penetrate the third and fourth interlayer insulating layers 240 and 360 and the second supporting layer 300 to contact an upper surface of the capping pattern 220, and the upper interconnection 380 may extend in the third direction to contact the lower contact plug 370. In an exemplary embodiment, the upper interconnection 380 may be formed in a plurality of pieces along the second direction. The upper interconnection 380 may serve as a bit line of the vertical memory device.

[0047] Meanwhile, the fourth separated pattern 355 may include a protruding portion 355c, at least a portion of which is formed to the same height as the channel connecting pattern 280 and protruding in the second direction below the second separated pattern 235. In this case, the surface of the protruding portion 355c of the fourth separated pattern 355 may be covered by the second blocking pattern 335.

[0048] 2b, instead of forming the protrusion 355c of the fourth separation pattern 355 under the second separation pattern 235, a channel connecting pattern 280 may be formed. In this case, the channels 200 belonging to each channel group adjacent to each other in the second direction may be electrically connected to each other by the channel connecting pattern 280.

[0049] As described above, the vertical memory device may include second to fourth isolation patterns 235, 350, 355 formed between the gate electrode structures, and a second support film 300 formed on the gate electrode structures, which, as will be described below, allow a mold including each gate electrode structure to not bend or collapse even if the mold has a high top height or a long extension length.

[0050] 4 to 25 are plan views and cross-sectional views illustrating a method for manufacturing a vertical memory device according to an exemplary embodiment. Specifically, FIGS. 4, 6, 8, 10, 16, 18, and 20 are plan views, and FIGS. 5, 7, 9, 11 to 15, 17, 19, and 21 to 25 are cross-sectional views.

[0051] In this regard, Figures 5, 7, 9, 12, 14, 22, and 24 are cross-sectional views taken along line A-A' in each of the corresponding plan views, and Figures 11, 13, 15, 17, 19, 21, 23, and 25 are cross-sectional views taken along line B-B' in each of the corresponding plan views.

[0052] 4 and 5, a lower circuit pattern (not shown) may be formed on a substrate 10, and a first interlayer insulating film 20 may be formed on the substrate 10 to cover the lower circuit pattern.

[0053] Thereafter, a common electrode plate (CSP) 100 , a sacrificial layer structure 140 , and a first supporting layer 150 may be sequentially formed on the first interlayer insulating layer 20 .

[0054] The sacrificial layer structure 140 may include first to third sacrificial layers 110, 120, and 130 that are sequentially stacked. In this case, the first and third sacrificial layers 110 and 130 may each include an oxide such as silicon oxide, and the second sacrificial layer 120 may include a nitride such as silicon nitride.

[0055] The first support film 150 may include a material having an etching selectivity with respect to the first to third sacrificial films 110, 120, and 130, for example, polysilicon doped with n-type impurities. However, the first support film 150 may be formed to include polysilicon doped with n-type impurities by performing a separate column processing process after depositing amorphous silicon doped with n-type impurities, or by being crystallized by heat generated during a deposition process of another film, etc. Although not shown, a portion of the first support film 150 may penetrate the sacrificial film structure 140 to form a support pattern (not shown) in contact with the upper surface of the CSP 100.

[0056] Thereafter, the insulating film 160 and the fourth sacrificial film 170 may be alternately stacked on the first support film 150 in the first direction, thereby forming a mold film including the insulating film 160 and the fourth sacrificial film 170. The insulating film 160 may include an oxide such as silicon oxide, and the fourth sacrificial film 170 may include a material having a high etch selectivity with respect to the insulating film 160, such as a nitride such as silicon nitride.

[0057] 6 and 7, by alternately performing an etching process using a photoresist pattern (not shown) and a trimming process for reducing the area of ​​the photoresist pattern at a certain rate, a mold having an overall stepped shape can be formed, which includes a plurality of stepped layers each composed of a fourth sacrificial film 170 and an insulating film 160 stacked in sequence.

[0058] Thereafter, a second interlayer insulating film 180 covering the mold may be formed on the CSP 100, and a channel hole may be formed penetrating the second interlayer insulating film 180, the insulating film 160, the fourth sacrificial film 170, the first supporting film 150, and the sacrificial film structure 140 to expose the top surface of the CSP 100. A plurality of channel holes may be formed spaced apart from each other along the second and third directions.

[0059] Thereafter, a charge storage structure film and a channel film are formed on the sidewalls of each channel hole, the exposed top surface of CSP 100, and the top surface of second interlayer insulating film 180, and a charge film filling the remaining part of the channel hole is formed on the channel film. Thereafter, the charge film, the channel film, and the charge storage structure film are planarized until the top surface of second interlayer insulating film 180 is exposed, so that the charge storage structure 190, the channel 200, and the charge pattern 210, which are sequentially stacked in each channel hole, can be formed.

[0060] In an exemplary embodiment, the channels 200 may be formed in a plurality of spaces spaced apart from one another along the second and third directions, where a plurality of channels 200 spaced apart from one another in the second direction may form a channel row, a plurality of channel rows spaced apart from one another in the third direction may form a channel group, and a plurality of channel groups spaced apart from one another in the third direction may form a channel block.

[0061] In an exemplary embodiment, the charge storage structure 190 may include a tunnel insulating pattern, a charge storage pattern, and a first blocking pattern, which are sequentially stacked from the outer wall of the channel 200 along a horizontal direction parallel to the top surface of the substrate 10 .

[0062] Then, a trench may be formed by removing the upper portion of the pillar structure including the charge storage structure 190, the channel 200, and the charge pattern 210 sequentially stacked inside each channel hole, and a capping pattern 220 for filling the trench may be formed.

[0063] 8 and 9, the second interlayer insulating film 180, a portion of the insulating film 160, and a portion of the fourth sacrificial film 170 can be etched to form a first opening penetrating them and extending in the second direction, and then a first separation pattern 230 can be formed to fill the first opening.

[0064] In one embodiment, the first separation pattern 230 may penetrate some of the channels 200, for example, the upper portions of the channels 200 included in the channel row located in the middle of each channel group in the third direction. The first separation pattern 230 may penetrate not only the upper portions of some of the channels 200, but also the second interlayer insulating film 180, the fourth sacrificial film 170 formed in the upper two layers, and the insulating film 160 formed in the upper two layers, and may also partially penetrate the insulating film 160 formed in one layer below. In this case, the first separation pattern 230 may extend in the second direction and penetrate the upper two step layers included in the mold. As a result, the fourth sacrificial films 170 formed in the upper two layers may be separated from each other along the third direction by the first separation pattern 230.

[0065] In addition, the second interlayer insulating film 180, the mold, the first supporting film 150, and the sacrificial film structure 140 may be etched to form a second opening penetrating the second interlayer insulating film 180, exposing the top surface of the CSP 100, and then a second isolated pattern 235 may be formed to fill the second opening. In an exemplary embodiment, the second isolated pattern 235 may be formed in a plurality of pieces spaced apart from each other along the second direction between the first isolated patterns 230 adjacent to each other in the third direction, more specifically, between the channel groups adjacent to each other in the third direction within each channel block.

[0066] The first and second isolated patterns 230 and 235 may be formed by the same etching and deposition process, or by sequentially performing separate etching and deposition processes, respectively.

[0067] 10 and 11, after forming a third interlayer insulating film 240 on the second interlayer insulating film 180, the capping pattern 220, and the first and second isolation patterns 230, 235, third and fourth openings 260, 265 penetrating the second and third interlayer insulating films 180, 240 and the mold can be formed, for example, by a dry etching process.

[0068] The dry etching process may be performed until the third and fourth openings 260, 265 expose the top surface of the first support film 150, and may even be formed to penetrate a portion of the top of the first support film 150. As the third and fourth openings 260, 265 are formed, the insulating film 160 and the fourth sacrificial film 170 included in the mold may be exposed through their sidewalls.

[0069] In an exemplary embodiment, the third opening 260 may extend in the second direction between adjacent channel blocks in the third direction, and may be formed in a plurality of pieces along the third direction. In an exemplary embodiment, the fourth opening 265 may be formed between the second separated patterns 235 arranged in the second direction, and may be connected to both ends of each second separated pattern 235 in the second direction. That is, the fourth opening 265 may be formed in a plurality of pieces along the second direction, spaced apart from each other, between adjacent channel groups in the third direction in each channel block.

[0070] As the third and fourth openings 260, 265 are formed along with the previously formed second isolation pattern 235, the insulating film 160 can be converted into a first insulating pattern 165 extending in the second direction, and the fourth sacrificial film 170 can be converted into a fourth sacrificial pattern 175 extending in the second direction.

[0071] The fourth openings 265, which extend in the second direction and are formed between adjacent third openings 260 in the third direction, may be formed in a plurality of pieces spaced apart from each other in the second direction, with the second separation patterns 235 formed between them. As a result, even if the height of the upper surface of the mold is high and the length extending in the second direction is long, the fourth openings 265 do not extend to both ends of the mold in the second direction, but are formed in a plurality of pieces spaced apart from each other, with the second separation patterns 235 formed between them, reducing concerns that the mold will tilt or fall in the third direction.

[0072] Thereafter, a first spacer film is formed on the sidewalls of the third and fourth openings 260, 265 and the third interlayer insulating film 240, and then the portions formed on the bottom surfaces of the third and fourth openings 260, 265 are removed by an anisotropic etching process to form the first spacer 250, thereby partially exposing the top surface of the first support film 150.

[0073] Thereafter, the exposed first support film 150 and the underlying sacrificial film structure 140 are removed, thereby expanding the third and fourth openings 260, 265 downwards, so that the third and fourth openings 260, 265 can expose the top surface of the CSP 100 and can even penetrate a portion of the top of the CSP 100.

[0074] In an exemplary embodiment, the first spacer 250 may include, for example, amorphous silicon not doped with impurities or polysilicon not doped with impurities. However, if the first spacer 250 includes amorphous silicon not doped with impurities, it may be crystallized by heat generated during a deposition process of another film to form the first spacer 250 including polysilicon.

[0075] 12 and 13, the sacrificial layer structure 140 may be removed through the third and fourth openings 260 and 265, for example, by a wet etching process, thereby forming a first gap 270.

[0076] The wet etching process may be carried out using, for example, hydrofluoric acid (HF) and / or phosphoric acid (H 3 PO 4 ) can be used to accomplish this.

[0077] When the sacrificial film structure 140 is partially removed, the sidewalls of each of the third and fourth openings 260, 265 are covered by the first spacer 250, so the insulating pattern 165 and the fourth sacrificial pattern 175 included in the mold may not be removed.

[0078] As the first gap 270 is formed, the bottom surface of the first support film 150 and the top surface of the CSP 100 may be exposed. In addition, a portion of the sidewall of the charge storage structure 190 may be exposed by the first gap 270, and the exposed sidewall of the charge storage structure 190 may also be removed during the wet etching process to expose the outer wall of the channel 200. As a result, the charge storage structure 190 may be separated into an upper portion that penetrates the mold and covers most of the outer wall of the channel 200, and a lower portion that covers the bottom surface of the channel 200 and is formed on the upper portion of the CSP 100.

[0079] Meanwhile, when the first gap 270 is formed, the portion of the second isolation pattern 235 formed at the same height as the sacrificial layer structure 140 is also removed, so that the second gap 275 can be formed.

[0080] 14 and 15, the first spacer 250 may be removed, and a channel connection layer may be formed on the sidewalls of the third and fourth openings 260 and 265 and in the first and second gaps 270 and 275. Thereafter, a channel connection pattern 280 may be formed in the first gap 270 by removing portions of the channel connection layer formed in the third and fourth openings 260 and 265, for example, by performing an etch-back process or a wet etching process.

[0081] At this time, the channel connection layer portion formed in the second gap 275 may also be removed, but the concept of the present invention is not necessarily limited to this. The channel connection layer portion may not be removed and may remain in the channel connection pattern 280.

[0082] As the channel connection pattern 280 is formed, the channels 200 formed in each channel group can be connected to each other, and if the channel connection pattern 280 remains in the second gap 275, the channels 200 formed in each channel block can be connected to each other through it.

[0083] The channel connection pattern 280 may include, for example, amorphous silicon doped with n-type impurities, and may subsequently be crystallized by heat generated during the deposition process of other layers to include polysilicon doped with n-type impurities.

[0084] Meanwhile, an air gap 285 may be formed within the channel connection pattern 280 .

[0085] 16 and 17, a second spacer 290 may be formed on the sidewalls of the third and fourth openings 260, 265 and the upper surface of the CSP 100 exposed thereby, and a fifth sacrificial layer 295 may be formed on the second spacer 290 to fill the remaining portions of the third and fourth openings 260, 265.

[0086] Meanwhile, if the channel connection pattern 280 does not remain in the second gap 275, a second spacer 290 may be formed on the upper and lower surfaces and sidewalls of the second gap 275, and a fifth sacrificial layer 295 may be formed on the remaining portion of the second gap 275.

[0087] The second spacer 290 may include, for example, a nitride, such as silicon nitride, and the fifth sacrificial film 295 may include, for example, polysilicon.

[0088] 18 and 19, a second support film 300 may be formed on the third interlayer insulating film 240, the second spacer 290, and the fifth sacrificial film 295, and then partially etched to form fifth and sixth openings 310, 315.

[0089] In an exemplary embodiment, the fifth opening 310 may overlap the third opening 260 in which the second spacer 290 and the fifth sacrificial layer 295 are formed when viewed along the first direction, and may be formed in a plurality of parts spaced apart from each other in the second direction on each third opening 260. In one embodiment, the fifth opening 310 may be wider in the third direction than the third opening 260, but the concept of the present invention is not necessarily limited thereto.

[0090] In an exemplary embodiment, the sixth opening 315 may overlap the fourth opening 265 and the second isolated pattern 235 on which the second spacer 290 and the fifth sacrificial layer 295 are formed when viewed along the first direction, and may be formed in a plurality of openings spaced apart from each other in the second direction on the fourth opening 265 and the second isolated pattern 235. In one embodiment, the sixth opening 315 may have a width in the third direction greater than that of the fourth opening 265 and the second isolated pattern 235, but the concept of the present invention is not necessarily limited thereto.

[0091] In one embodiment, the sixth opening 315 may be formed to overlap opposing portions of the fourth openings 265 adjacent to each other in the second direction and the second separation pattern 235 formed therebetween when viewed along the first direction.

[0092] In an exemplary embodiment, the fifth and sixth openings 310, 315 may be arranged in a zigzag shape along the second direction, and the fifth and sixth openings 310, 315 may partially overlap each other when viewed along the third direction.

[0093] 20 and 21, the second spacer 290 and the fifth sacrificial layer 295 formed in the third and fourth openings 260, 265 can be removed through the fifth and sixth openings 310, 315, thereby forming the third and fourth openings 260, 265 again.

[0094] Even if the third and fourth openings 260, 265 are also formed, their upper surfaces can be at least partially covered by the second support film 300. As a result, even if the height of the upper surface of the mold is high and the length extending in the second direction is long, the second support film 300 formed on these upper surfaces and at least partially covering the areas where the third and fourth openings 260, 265 are formed can reduce concerns that the mold will tilt or fall in the third direction.

[0095] In an exemplary embodiment, the second spacer 290 and the fifth sacrificial layer 295 may be removed by a wet etching process, and at this time, if the second spacer 290 and the fifth sacrificial layer 295 are formed in the second gap 275, they may also be removed together to form the second gap 275 again.

[0096] Thereafter, the fourth sacrificial pattern 175 exposed by the third and fourth openings 260, 265 may be removed to form a third gap between the insulating patterns 165 formed in each layer, and a portion of the outer wall of the charge storage structure 190 may be exposed through the third gap.

[0097] According to an exemplary embodiment, phosphoric acid (H 3 PO 4 ) or sulfuric acid (H 2 SO 4 ) may be used to remove the fourth sacrificial pattern 175 by a wet etching process using .

[0098] 22 and 23, a second blocking film 330 may be formed on the exposed outer wall of the charge storage structure 190, the inner wall of the third gap, the surface of the insulating pattern 165, the sidewall of the first support film 150, the sidewall of the channel connection pattern 280, the top surface of the CSP 100, the sidewall and a portion of the top surface of the third interlayer insulating film 240, and the sidewall and top surface of the second support film 300, and a gate electrode film may be formed on the second blocking film 330.

[0099] Meanwhile, if the second gap 275 is also formed, a second blocking layer 330 and a gate electrode layer can be formed therein.

[0100] The gate electrode layer may include a gate barrier layer and a gate conductive layer, which are sequentially stacked. The gate barrier layer may include a metal nitride, and the gate conductive layer may include a metal.

[0101] Thereafter, a gate electrode may be formed within each of the third gaps by partially removing the gate electrode film. According to an exemplary embodiment, the gate electrode film may be partially removed by a wet etching process. Meanwhile, if the second blocking film 330 and the gate electrode film are formed within the second gaps 275, the gate electrode film may be removed.

[0102] In an exemplary embodiment, the gate electrode may extend in the second direction and may be stacked in a plurality of layers spaced apart from each other along the first direction to form a gate electrode structure, and the gate electrode structure may have a step shape with each gate electrode being a step layer.

[0103] Also, the gate electrode structure may be formed in a plurality of pieces along the third direction, and may be spaced apart from each other in the third direction by the third and fourth openings 260, 265 and the second separation pattern 235. The gate electrode structure may include first to third gate electrodes 342, 344, 346 sequentially formed along the first direction. In an exemplary embodiment, the first gate electrode 342 may be formed in the bottom layer and may function as a ground selection line (GSL), the third gate electrode 346 may be formed in the top layer and a layer therebelow and may function as a string selection line (SSL), and the second gate electrode 344 may be formed in a plurality of layers between the first and third gate electrodes 342, 346 and may function as a word line.

[0104] 24 and 25 together with FIG. 1, a third isolation layer filling the third to sixth openings 260, 265, 310, and 315 is formed on the second blocking layer 330, and the third isolation layer and the second blocking layer 330 are planarized until the top surface of the second support layer 300 is exposed, thereby forming third and fourth isolation patterns 350, 355 and second blocking pattern 335, respectively.

[0105] The third separated pattern 350 may fill the third and fifth openings 260, 310 and may extend in the second direction. In this case, the width of the first upper portion 350b filling the fifth opening 310 in the third direction may be greater than the width of the first lower portion 350a filling the third opening 260, and the first upper portion 350b may be formed in a plurality of pieces spaced apart from each other along the second direction on the first lower portion 350a extending in the second direction.

[0106] The fourth separated pattern 355 may fill the fourth and sixth openings 265, 315. In this case, the width in the third direction of the second upper portion 355b filling the sixth opening 315 may be greater than that of the second lower portion 355a filling the fourth opening 265. The second lower portion 355a may extend in the second direction and be partially cut by the second separated pattern 235, and the second upper portion 355b may be formed in a plurality of portions spaced apart from each other along the second direction on the lower portion 355a and the second separated pattern 235.

[0107] Meanwhile, when the second blocking layer 330 is formed in the second gap 275 and the gate electrode layer is removed, a protrusion 355c of the fourth isolation pattern 355 may be formed in the remaining portion of the second gap 275.

[0108] Also, referring to Figures 2a, 2b, and 3, a fourth interlayer insulating film 360 may be formed on the second support film 300, the third and fourth isolation patterns 350, 355, and the second blocking pattern 335, and a contact plug 370 may be formed penetrating the third and fourth interlayer insulating films 240, 360 and the second support film 300 to contact the upper surface of the capping pattern 220.

[0109] Thereafter, a fifth interlayer insulating film (not shown) may be formed on the fourth interlayer insulating film 360 and the contact plug 370, and an upper interconnection 380 may be formed through the fifth interlayer insulating film to contact an upper surface of the contact plug 370. The upper interconnection 380 may function as a bit line of the vertical memory device. In an exemplary embodiment, the upper interconnection 380 may extend in the third direction and may be formed in a plurality of pieces spaced apart from each other along the second direction.

[0110] Through the above-described process, a vertical memory device can be completed.

[0111] As described above, the second support film 300, which at least partially covers the upper surface of the third opening 260 extending through the mold in the second direction, and the second separation pattern 235 formed between the fourth openings 265 which extend through the mold and are spaced apart from each other in the second direction, prevent the mold from tilting or falling in the third direction even if the upper surface of the mold is high and has a long length extending in the second direction.

[0112] 26 and 27 are plan views illustrating a vertical memory device according to an exemplary embodiment. The vertical memory device is the same or similar to the vertical memory device described with reference to FIGS. 1 to 3 except for some components. Therefore, the same components are given the same reference numerals and the duplicated description thereof will be omitted.

[0113] 26, the fourth separated pattern 355 may include a second lower portion 355a connected to the second separated pattern 235 and a second upper portion 355b spaced apart from each other in the second direction and in contact with an upper surface of the second lower portion 355a.

[0114] In this case, the first and second upper portions 350b, 355b of the third and fourth separated patterns 350, 355 may be arranged in a zigzag pattern in the second or third direction, and the first upper portion 350b of each third separated pattern 350 may overlap the second upper portion 355b of the fourth separated pattern 355 when viewed along the third direction.

[0115] Referring to FIG. 27, the fourth separated pattern 355 may include second lower portions 355a spaced apart from each other in the second direction and connected to the second separated pattern 235, and second upper portions 355b spaced apart from each other in the second direction and in contact with the upper surfaces of the second lower portions 355a.

[0116] In this case, the first and second upper portions 350b, 355b of the third and fourth separated patterns 350, 355 may be arranged in a zigzag pattern in the second or third direction, and the first upper portion 350b of each third separated pattern 350 may overlap the second upper portion 355b of the fourth separated pattern 355 when viewed along the third direction.

[0117] 28 to 30 are plan views illustrating a vertical memory device according to an exemplary embodiment. The vertical memory device is the same as or similar to the vertical memory devices described with reference to FIGS. 1, 26, and 27, except for some components. Therefore, the same components are given the same reference numerals, and duplicated descriptions thereof will be omitted.

[0118] 28 to 30, the fourth isolated patterns 355 may be formed in a plurality of pieces spaced apart from each other in the third direction between the third isolated patterns 350 adjacent to each other in the third direction.

[0119] That is, the fourth separated patterns 355 spaced apart from each other in the second direction may form a fourth separated pattern row, and the fourth separated pattern row may be formed in a plurality of rows so as to be spaced apart from each other in the third direction between the third separated patterns 350 adjacent to each other in the third direction.

[0120] As mentioned above, the present invention has been described with reference to a preferred embodiment, but a person having ordinary skill in the art will understand that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as set forth in the claims.

Claims

1. gate electrode structures each including gate electrodes spaced apart from one another on the substrate along a first direction perpendicular to an upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate, the gate electrode structures being arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction; a channel extending in the first direction through each of the gate electrode structures; a first isolation pattern extending in the second direction between the gate electrode structures and isolating them in the third direction; second and third isolation patterns alternately disposed between the gate electrode structures in the second direction and connected to each other, and which together isolate the gate electrode structures; a first supporting layer formed on the gate electrode structure and flush with and in contact with the first and second isolation patterns; the first separated pattern and the second separated pattern are arranged in a zigzag pattern in the second direction in a plan view, an upper portion of the first isolation pattern is disposed at substantially the same height as an upper portion of the second isolation pattern, the second isolation pattern including a lower portion spaced apart from each other in the second direction and connected to the third isolation pattern.

2. 2. The vertical memory device of claim 1, wherein an upper portion of each of the first isolation patterns partially overlaps an upper portion of the second isolation pattern when viewed along the third direction.

3. the first isolated pattern is formed in a plurality of pieces spaced apart from each other in the third direction, 2. The vertical memory device of claim 1, wherein the second isolation patterns are formed between the first isolation patterns adjacent to each other in the third direction.

4. 4. The vertical memory device of claim 3, wherein the second isolation patterns are formed in a plurality of pieces spaced apart from each other in the third direction between the first isolation patterns adjacent to each other in the third direction.

5. The first separation pattern is A lower portion extending in the second direction; 5. The vertical memory device of claim 1, further comprising the upper portions each contacting an upper surface of the lower portion and spaced apart from each other in the second direction.

6. 6. The vertical memory device of claim 5, wherein a width of each of the upper portions of the first isolation patterns in the third direction is greater than a width of each of the lower portions.

7. 6. The vertical memory device of claim 5, wherein a distance between an upper surface of the lower portion of the first isolation pattern and the substrate is greater than a distance between an upper surface of the third isolation pattern and the substrate.

8. 6. The vertical memory device of claim 5, further comprising a metal oxide pattern covering each of the upper sidewalls of the first isolation patterns.

9. a blocking pattern covering upper and lower surfaces and one sidewall of each of the gate electrodes, 9. The vertical memory device of claim 8, wherein the blocking pattern comprises the same material as the metal oxide pattern.

10. The second separation pattern is 5. The vertical memory device of claim 1, further comprising the upper portions commonly contacting upper surfaces of the lower portions adjacent to each other in the second direction.

11. 11. The vertical memory device of claim 10, wherein the third isolation pattern overlaps an upper portion of the second isolation pattern when viewed along the first direction.

12. 11. The vertical memory device of claim 10, wherein a width of the upper portion of the second isolation pattern in the third direction is greater than a width of the lower portion.

13. 11. The vertical memory device of claim 10, wherein a distance between an upper surface of the lower portion of the second isolation pattern and the substrate is greater than a distance between an upper surface of the third isolation pattern and the substrate.

14. The second separation pattern is a lower portion spaced apart from each other in the second direction and connected to the third isolated pattern; 2. The vertical memory device of claim 1, further comprising the upper portions each contacting a top surface of the lower portions.

15. The second separation pattern is a lower portion spaced apart from each other in the second direction and connected to the third isolated pattern; 2. The vertical memory device of claim 1, further comprising: the upper portions spaced apart from each other in the second direction and in contact with upper surfaces of the lower portions.

16. gate electrode structures each including gate electrodes spaced apart from one another on the substrate along a first direction perpendicular to an upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate, the gate electrode structures being arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction; a channel extending in the first direction through each of the gate electrode structures; a first lower portion extending in the second direction between the gate electrode structures and separating them in the third direction; a first separation pattern including first upper portions each contacting an upper surface of the first lower portion and spaced apart from each other in the second direction; second lower portions spaced apart from each other in the second direction between the gate electrode structures; a second separation pattern including a second upper portion contacting an upper surface of the second lower portion; a third isolated pattern formed between the second lower portions of the second isolated patterns and connected thereto; a support layer formed on the gate electrode structure and facing sidewalls of the first and second upper portions of the first and second isolation patterns, A first top portion of the first isolation pattern is disposed at substantially the same height as a second top portion of the second isolation pattern.

17. 17. The vertical memory device of claim 16, wherein a first top portion of the first isolation pattern partially overlaps a second top portion of the second isolation pattern when viewed along the third direction.

18. 17. The vertical memory device of claim 16, wherein a width of each of the first and second upper portions of the first and second isolation patterns in the third direction is greater than a width of each of the first and second lower portions.

19. a common electrode plate (CSP) formed on the substrate; a channel connection pattern and a first support film stacked on the CSP along a first direction perpendicular to an upper surface of the substrate; gate electrode structures including gate electrodes spaced apart from each other along the first direction on the first support film and extending in a second direction parallel to an upper surface of the substrate, the gate electrode structures being arranged along a third direction parallel to the upper surface of the substrate and intersecting the second direction; channels extending in the first direction through the gate electrode structures, the first supporting film, and the channel connecting pattern on the CSP and electrically connected to each other by the channel connecting pattern; a first isolation pattern formed on the CSP and extending in the second direction between the gate electrode structures to isolate them in the third direction; second and third isolation patterns formed on the CSP, alternately disposed between the gate electrode structures in the second direction and connected to each other, thereby isolating the gate electrode structures together; a second supporting layer formed on the gate electrode structure and flush with and in contact with the first and second isolation patterns; the first separated pattern and the second separated pattern are arranged in a zigzag pattern in a second direction in a plan view, an upper portion of the first isolation pattern is disposed at substantially the same height as an upper portion of the second isolation pattern, the second isolation pattern including a lower portion spaced apart from each other in the second direction and connected to the third isolation pattern.

20. 20. The vertical memory device of claim 19, further comprising a charge storage structure covering an outer wall of each of the channels.

Images