Semiconductor integrated circuit device

Abstract

According to the present invention, a nano sheet (21a) which is positioned in a P-type region to be furthest from an N-type region has a surface that is exposed from a gate wiring line (31), said surface being on the reverse side from the N-type region in the Y direction; a nano sheet (28a) which is positioned in the N-type region to be furthest from the P-type region has a surface that is exposed from a gate wiring line (33), said surface being on the reverse side from the P-type region in the Y direction; a nano sheet (23a) which is positioned in the P-type region to be closest to the N-type region has a surface that is exposed from the gate wiring line (31), said surface being on the N-type region side in the Y direction; and a nano sheet (26a) which is positioned in the N-type region to be closest to the P-type region has a surface that is exposed from the gate wiring line (33), said surface being on the P-type region side in the Y direction.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor integrated circuit device including a nanosheet (nanowire) FET (Field Effect Transistor). [Background technology]

[0002] The standard cell method is known as a method for forming semiconductor integrated circuits on a semiconductor substrate. The standard cell method is a method for designing an LSI chip by preparing basic units with specific logical functions (e.g. inverters, latches, flip-flops, full adders, etc.) as standard cells in advance, arranging multiple standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0003] Furthermore, transistors, which are the basic building blocks of LSIs, have achieved increased integration density, reduced operating voltages, and increased operating speeds through the reduction of gate lengths (scaling). In recent years, however, excessive scaling has caused problems with off-current and the resulting dramatic increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional one. One such transistor that has attracted attention is the nanosheet (nanowire) FET.

[0004] Non-Patent Document 1 discloses a layout of an SRAM memory cell using a nanosheet FET with a fork-shaped gate electrode. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505~508 Summary of the Invention [Problem to be solved by the invention]

[0006] In this specification, a nanosheet FET having a fork-shaped gate electrode is referred to as a fork sheet FET, following the description in Non-Patent Document 1.

[0007] So far, there has been no document disclosing a layout structure of a standard cell using a fork sheet FET or a layout of a semiconductor integrated circuit using a fork sheet FET.

[0008] An object of the present disclosure is to provide a layout structure for a semiconductor integrated circuit device using a small-area fork-sheet FET. [Means for solving the problem]

[0009] In a first aspect of the present disclosure, in a semiconductor integrated circuit device including standard cells arranged in a first direction, the standard cells include a P-type region in which a P-type transistor is formed and an N-type region in which an N-type transistor is formed, which are formed adjacent to each other in a second direction perpendicular to the first direction, a first nanosheet group in the P-type region, each extending in the first direction and consisting of two or more nanosheets aligned in the second direction, a second nanosheet group in the N-type region, each extending in the first direction and consisting of two or more nanosheets aligned in the second direction, a first gate wiring extending in the second direction and formed so as to surround the periphery of each nanosheet of the first nanosheet group in the second direction and in a third direction perpendicular to the first and second directions, and and a second gate wiring extending in the second direction and formed so as to surround the outer periphery of each nanosheet of the second nanosheet group in the second and third directions, wherein in the first nanosheet group, a first nanosheet furthest from the N-type region has a surface opposite to the N-type region in the second direction exposed from the first gate wiring, and a second nanosheet closest to the N-type region has a surface facing the N-type region in the second direction exposed from the first gate wiring, and a third nanosheet in the second nanosheet group furthest from the P-type region has a surface opposite to the P-type region in the second direction exposed from the second gate wiring, and a fourth nanosheet closest to the P-type region has a surface facing the P-type region in the second direction exposed from the second gate wiring.

[0010] According to this embodiment, in the first nanosheet group in the P-type region, the first nanosheet farthest from the N-type region has a surface opposite to the N-type region in the second direction exposed from the first gate wiring. In the second nanosheet group in the N-type region, the third nanosheet farthest from the P-type region has a surface opposite to the P-type region in the second direction exposed from the second gate wiring. That is, the first gate wiring does not overlap the first nanosheet group toward the outside of the standard cell, and the second gate wiring does not overlap the second nanosheet group toward the outside of the standard cell. In addition, in the first nanosheet group in the P-type region, the second nanosheet closest to the N-type region has a surface on the N-type region side in the second direction exposed from the first gate wiring. In the second nanosheet group in the N-type region, the fourth nanosheet closest to the P-type region has a surface on the P-type region side in the second direction exposed from the second gate wiring. That is, the first gate wiring does not overlap the first nanosheet group toward the second nanosheet group, and the second gate wiring does not overlap the second nanosheet group toward the first nanosheet group. This makes it possible to reduce the size of the standard cell in the second direction, thereby realizing a layout structure with a small area.

[0011] In a second aspect of the present disclosure, a semiconductor integrated circuit device includes a first power supply wiring extending in a first direction and supplying a first power supply voltage, and a second power supply wiring extending in the first direction and supplying a second power supply voltage, and between the first power supply wiring and the second power supply wiring, a P-type region in which a P-type transistor is formed and an N-type region in which an N-type transistor is formed are formed adjacent to each other in a second direction perpendicular to the first direction, and further includes a first nanosheet group extending in the first direction in the P-type region and consisting of two or more nanosheets aligned in the second direction, a second nanosheet group extending in the first direction in the N-type region and consisting of two or more nanosheets aligned in the second direction, and an outer periphery of each nanosheet of the first nanosheet group in the second direction and in a third direction perpendicular to the first and second directions. the first nanosheet group has a first gate wiring formed so as to surround the periphery, and a second gate wiring extending in the second direction and formed so as to surround the periphery of each nanosheet in the second and third directions, wherein the first nanosheet in the first nanosheet group is farthest from the N-type region, and the second nanosheet closest to the N-type region has a surface facing the N-type region in the second direction exposed from the first gate wiring, the third nanosheet in the second nanosheet group is farthest from the P-type region, and the third nanosheet is closest to the P-type region, and the third nanosheet is closest to the P-type region, and the third nanosheet is closest to the P-type region, and the third nanosheet is closest to the P-type region, and the third nanosheet is closest to the P-type region, and the fourth nanosheet is closest to the P-type region, and the fourth nanosheet is closest to the P-type region, and the fourth nanosheet is closest to the P-type region, and the

[0012] According to this embodiment, in the first nanosheet group in the P-type region, the first nanosheet farthest from the N-type region has a surface opposite to the N-type region in the second direction exposed from the first gate wiring. In the second nanosheet group in the N-type region, the third nanosheet farthest from the P-type region has a surface opposite to the P-type region in the second direction exposed from the second gate wiring. That is, the first gate wiring does not overlap the first nanosheet group toward the power supply wiring side, and the second gate wiring does not overlap the second nanosheet group toward the power supply wiring side. Also, in the first nanosheet group in the P-type region, the second nanosheet closest to the N-type region has a surface on the N-type region side in the second direction exposed from the first gate wiring. In the second nanosheet group in the N-type region, the fourth nanosheet closest to the P-type region has a surface on the P-type region side in the second direction exposed from the second gate wiring. That is, the first gate wiring does not overlap the first nanosheet group toward the second nanosheet group, and the second gate wiring does not overlap the second nanosheet group toward the first nanosheet group. This makes it possible to reduce the size of the semiconductor integrated circuit device in the second direction, thereby realizing a layout structure with a small area. Effect of the Invention

[0013] According to the present disclosure, a small-area layout structure can be realized for a semiconductor integrated circuit device using a fork-sheet FET. [Brief description of the drawings]

[0014] [Figure 1] 1A and 1B are diagrams showing an example of a basic structure of a standard cell having a fork-sheet FET according to an embodiment, in which (a) is a plan view and (b) is a cross-sectional view. [Diagram 2] (a) is a plan view showing the layout structure of a two-input NAND cell, and (b) is a circuit diagram of the two-input NAND. [Diagram 3] (a) and (b) are cross-sectional views of the two-input NAND cell in Fig. 2(a). [Figure 4](a) is a plan view showing the layout structure of a tri-state inverter cell, and (b) is a circuit diagram of the tri-state inverter. [Diagram 5] (a) and (b) are cross-sectional views of the tri-state inverter cell in Fig. 4(a). [Figure 6] (a) is a plan view showing the layout structure of an inverter cell, and (b) is a circuit diagram of the inverter. [Figure 7] (a) is a plan view showing the layout structure of a two-input NOR cell, and (b) is a circuit diagram of a two-input NOR. [Figure 8] 1A and 1B are diagrams showing a basic structure of a standard cell having a fork-sheet FET according to a modified example, in which (a) is a plan view and (b) is a cross-sectional view. [Figure 9] 1A and 1B are diagrams showing a basic structure of a standard cell having a fork-sheet FET according to a modified example, in which (a) is a plan view and (b) is a cross-sectional view. [Figure 10] 1A and 1B are diagrams showing the basic structure of a fork-sheet FET, where (a) is a plan view and (b) is a cross-sectional view. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (in this specification, simply referred to as cells as appropriate), and at least some of the plurality of standard cells include nanosheet FETs (field effect transistors). A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with a fork-shaped gate electrode.

[0016] In addition, in the present disclosure, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals serving as the source or drain of the nanosheet FET are referred to as "pads." In addition, in the following description, in plan views such as Fig. 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction).

[0017] First, the basic structure of the fork seat FET will be described.

[0018] 10 shows the basic structure of a fork-sheet FET, where (a) is a plan view and (b) is a cross-sectional view taken along line Y-Y' in (a). In the basic structure of FIG. 10, two transistors TR1 and TR2 are arranged side by side with a gap S therebetween in the Y direction. A gate wiring 531 serving as the gate of transistor TR1 and a gate wiring 532 serving as the gate of transistor TR2 both extend in the Y direction and are arranged at the same position in the X direction.

[0019] A channel portion 521 that becomes the channel region of the transistor TR1 and a channel portion 526 that becomes the channel region of the transistor TR2 are composed of nanosheets. In FIG. 10, the channel portions 521 and 526 are each composed of a nanosheet having a three-sheet structure that overlaps in a plan view. Pads 522a and 522b that become the source region or drain region of the transistor TR1 are formed on both sides of the channel portion 521 in the X direction. Pads 527a and 527b that become the source region or drain region of the transistor TR2 are formed on both sides of the channel portion 526 in the X direction. The pads 522a and 522b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 521. The pads 527a and 527b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 526.

[0020] The gate wiring 531 surrounds the outer periphery in the Y direction and Z direction of the channel section 521 made of the nanosheet via a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel section 521 on the side of the transistor TR2 in the Y direction is not covered by the gate wiring 531 and is exposed from the gate wiring 531. That is, in the cross-sectional view of FIG. 10(b), the gate wiring 531 does not cover the right side of the nanosheet constituting the channel section 521 in the drawing, but covers the upper side, left side, and lower side in the drawing. The gate wiring 531 overlaps the nanosheet constituting the channel section 521 on the opposite side of the transistor TR2 in the Y direction by a length OL.

[0021] The gate wiring 532 surrounds the outer periphery in the Y direction and Z direction of the channel section 526 made of the nanosheet via a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel section 526 on the side of the transistor TR1 in the Y direction is not covered by the gate wiring 532 and is exposed from the gate wiring 532. That is, in the cross-sectional view of FIG. 10(b), the gate wiring 532 does not cover the left side of the nanosheet constituting the channel section 526 in the drawing, but covers the upper side, right side, and lower side in the drawing. The gate wiring 532 overlaps the nanosheet constituting the channel section 526 on the opposite side of the transistor TR1 in the Y direction by a length OL.

[0022] If the width (size in the Y direction) of each nanosheet is W and its height (size in the Z direction) is H, then the effective gate width Weff is Weff=2×W+H Since the channel portions 521 and 526 of the transistors TR1 and TR2 are formed of three nanosheets, the effective gate widths of the transistors TR1 and TR2 are 3×(2×W+H) It becomes.

[0023] 10, the gate wiring 531 does not overlap the nanosheet constituting the channel portion 521 on the side of the transistor TR2 in the Y direction. Also, the gate wiring 532 does not overlap the nanosheet constituting the channel portion 526 on the side of the transistor TR1 in the Y direction. This allows the transistors TR1 and TR2 to be closer to each other, thereby realizing a smaller area.

[0024] The number of nanosheets constituting the channel portion of the transistor is not limited to three. That is, the nanosheet may be composed of a single sheet structure, or may be composed of a plurality of sheets overlapping in a plan view. In addition, in FIG. 10(b), the cross-sectional shape of the nanosheet is illustrated as a rectangle, but is not limited thereto, and the cross-sectional shape of the nanosheet may be, for example, a square, a circle, an ellipse, or the like.

[0025] Furthermore, a semiconductor integrated circuit device may contain a mixture of fork-sheet FETs and nanosheet FETs in which the gate wiring surrounds the entire periphery of the nanosheet.

[0026] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In addition, in this specification, expressions such as "same wiring width" that mean the width is the same, include the range of manufacturing variations.

[0027] (Embodiment) 1A and 1B are diagrams showing an example of a basic structure of a standard cell having a fork-sheet FET according to an embodiment, where (a) is a plan view and (b) is a cross-sectional view taken along line Y-Y' in (a). In (a) of FIG. 1, a cell frame CL of the standard cell is shown. The same is true for the subsequent plan views.

[0028] The standard cell in Fig. 1 is arranged with other standard cells in the X direction with their cell frames CL in contact to form a cell row. In addition, multiple cell rows are arranged in the Y direction with their cell frames CL in contact. However, every other cell row is flipped upside down.

[0029] As shown in Fig. 1, power supply wiring 11, 12 extending in the X direction are provided at both ends in the Y direction of the standard cell. Both power supply wiring 11, 12 are buried power supply wiring (BPR: Buried Power Rail) formed in a buried wiring layer. The power supply wiring 11 supplies a power supply voltage VDD, and the power supply wiring 12 supplies a power supply voltage VSS. The power supply wiring 11, 12 are shared with other cells arranged side by side in the X direction and constitute power supply wiring arranged between cell columns.

[0030] P-type transistors P11, P12, P21, and P22 are formed in a P-type region on an N-well. N-type transistors N11, N12, N21, and N22 are formed in an N-type region on a P-type substrate. The transistors P11, P12, N11, and N12 are aligned in a row in the Y direction. The transistors P21, P22, N21, and N22 are aligned in a row in the Y direction.

[0031] The transistors P11, P12, P21, and P22 each have a channel portion formed of three nanosheets 21a, 23a, 21b, and 23b, respectively, that is, the transistors P11, P12, P21, and P22 are nanosheet FETs.

[0032] As shown in FIG. 1(a), pads 22a, 22b, and 22c made of an integral semiconductor layer connected to the three sheets are formed on the left side of the nanosheet 21a, between the nanosheets 21a and 21b, and on the right side of the nanosheet 21b. The pads 22a and 22b become the source and drain regions of the transistor P11. The pads 22b and 22c become the source and drain regions of the transistor P21.

[0033] Pads 24a, 24b, and 24c made of an integral semiconductor layer connected to the three sheets are formed on the left side of the nanosheet 23a, between the nanosheets 23a and 23b, and on the right side of the nanosheet 23b. The pads 24a and 24b are the source and drain regions of the transistor P12. The pads 24b and 24c are the source and drain regions of the transistor P22.

[0034] The transistors N11, N12, N21, and N22 each have, as a channel portion, nanosheets 26a, 28a, 26b, and 28b each made up of three sheets, that is, the transistors N11, N12, N21, and N22 are nanosheet FETs.

[0035] As shown in FIG. 1(a), pads 27a, 27b, and 27c made of an integral semiconductor layer connected to the three sheets are formed on the left side of nanosheet 26a, between nanosheets 26a and 26b, and on the right side of nanosheet 26b. Pads 27a and 27b are the source and drain regions of transistor N11. Pads 27b and 27c are the source and drain regions of transistor N21.

[0036] Pads 29a, 29b, and 29c made of an integral semiconductor layer connected to the three sheets are formed on the left side of nanosheet 28a, between nanosheets 28a and 28b, and on the right side of nanosheet 28b. Pads 29a and 29b are the source and drain regions of transistor N12. Pads 29b and 29c are the source and drain regions of transistor N22.

[0037] Gate wirings 31 and 32 extending in parallel in the Y direction are formed in the P-type region. Dummy gate wirings 35a and 35b are formed on the cell frames CL on both sides in the X direction of the gate wirings 31 and 32. The gate wirings 31 and 32 and the dummy gate wirings 35a and 35b are formed to have the same width and are arranged at the same pitch.

[0038] Gate wirings 33 and 34 extending in parallel in the Y direction are formed in the N-type region. Dummy gate wirings 35c and 35d are formed on the cell frame CL on both sides in the X direction of the gate wirings 33 and 34. The gate wirings 33 and 34 and the dummy gate wirings 35c and 35d are formed to have the same width and are arranged at the same pitch.

[0039] The gate wiring 31 surrounds the outer peripheries in the Y and Z directions of the nanosheet 21a of the transistor P11 and the nanosheet 23a of the transistor P12 via a gate insulating film (not shown). The gate wiring 31 serves as the gates of the transistors P11 and P12. The gate wiring 32 surrounds the outer peripheries in the Y and Z directions of the nanosheet 21b of the transistor P21 and the nanosheet 23b of the transistor P22 via a gate insulating film (not shown). The gate wiring 32 serves as the gates of the transistors P21 and P22.

[0040] The gate wiring 33 surrounds the outer peripheries in the Y and Z directions of the nanosheet 26a of the transistor N11 and the nanosheet 28a of the transistor N12 via a gate insulating film (not shown). The gate wiring 33 serves as the gates of the transistors N11 and N12. The gate wiring 34 surrounds the outer peripheries in the Y and Z directions of the nanosheet 26b of the transistor N21 and the nanosheet 28b of the transistor N22 via a gate insulating film (not shown). The gate wiring 34 serves as the gates of the transistors N21 and N22.

[0041] Here, the surfaces of nanosheets 21a and 21b opposite the N-type region in the Y direction (the surfaces closer to power supply wiring 11) are not covered by gate wirings 31 and 32 and are exposed from gate wirings 31 and 32. The surfaces of nanosheets 23a and 23b facing the N-type region in the Y direction are not covered by gate wirings 31 and 32 and are exposed from gate wirings 31 and 32. For example, nanosheets 21a and 23a constitute a first nanosheet group, nanosheet 21a corresponds to the first nanosheet that is the furthest from the N-type region in the first nanosheet group, and nanosheet 23a corresponds to the second nanosheet that is the closest to the N-type region in the first nanosheet group.

[0042] Furthermore, the surfaces of nanosheets 26a, 26b facing the P-type region in the Y direction are not covered by gate wirings 33, 34 and are exposed from gate wirings 33, 34. The surfaces of nanosheets 28a, 28b opposite the P-type region in the Y direction (the surfaces closer to power supply wiring 12) are not covered by gate wirings 33, 34 and are exposed from gate wirings 33, 34. For example, nanosheets 26a, 28a constitute a second nanosheet group, nanosheet 28a corresponds to the third nanosheet that is the farthest from the P-type region in the second nanosheet group, and nanosheet 26a corresponds to the fourth nanosheet that is the closest to the P-type region in the second nanosheet group.

[0043] Based on this basic structure, a standard cell that realizes a logic function is formed by forming vias and wiring (local wiring, metal wiring) for connecting transistors.

[0044] Although the power supply wirings 11 and 12 are described as embedded power supply wirings, the present invention is not limited to this. For example, the power supply wirings may be formed in an upper metal wiring layer.

[0045] In addition, although the transistors are arranged two by two in the X direction, this is not limited to this. For example, only one transistor may be arranged in the X direction, or three or more transistors may be arranged in the X direction.

[0046] An example of a standard cell that is formed based on the above-mentioned basic structure and realizes a logic function will be described below.

[0047] (Example 1: 2-input NAND) 2(a) is a plan view showing the layout structure of a two-input NAND cell, FIG. 2(b) is a circuit diagram of the two-input NAND, FIG. 3(a) is a cross-sectional view along line Y1-Y1' in FIG. 2(a), and FIG. 3(b) is a cross-sectional view along line Y2-Y2' in FIG. 2(a).

[0048] In the local wiring layer, local wirings 41, 42, 43, 44, and 45 extending in the Y direction are formed. The local wiring 41 is connected to the pads 22a and 24a. The local wiring 42 is connected to the pads 22b and 24b, and is also connected to the power supply wiring 11 through a via. The local wiring 43 is connected to the pads 22c, 24c, 27c, and 29c. The local wiring 44 is connected to the pads 27a and 29a, and is also connected to the power supply wiring 12 through a via. The local wiring 45 is connected to the pads 27b and 29b.

[0049] The gate wirings 31 and 33 aligned in the Y direction are connected via a bridge portion 36a formed between the gate wiring 31 and the gate wiring 33. The gate wirings 32 and 34 aligned in the Y direction are connected via a bridge portion 36b formed between the gate wiring 32 and the gate wiring 34. The bridge portions 36a and 36b are an example of a gate connection portion.

[0050] In the M1 wiring layer, metal wirings 51, 52, and 53 extending in the X direction are formed. The metal wiring 51 is connected to the local wirings 41 and 43 through vias. The metal wiring 52 is connected to the gate wirings 32 and 34 through vias. The metal wiring 53 is connected to the gate wirings 31 and 33 through vias. The metal wirings 51, 52, and 53 correspond to the output Y and the inputs A and B of the two-input NAND, respectively.

[0051] (Example 2: Tri-state inverter) 4(a) is a plan view showing the layout structure of a tri-state inverter cell, FIG. 4(b) is a circuit diagram of the tri-state inverter, FIG. 5(a) is a cross-sectional view along line Y1-Y1' in FIG. 4(a), and FIG. 4(b) is a cross-sectional view along line Y2-Y2' in FIG. 4(a).

[0052] In the local wiring layer, local wirings 61, 62, 63, 64, and 65 extending in the Y direction are formed. The local wiring 61 is connected to the pads 22a and 24a, and is also connected to the power supply wiring 11 through a via. The local wiring 62 is connected to the pads 22b and 24b. The local wiring 63 is connected to the pads 22c, 24c, 27c, and 29c. The local wiring 64 is connected to the pads 27a and 29a, and is also connected to the power supply wiring 12 through a via. The local wiring 65 is connected to the pads 27b and 29b.

[0053] The gate wirings 31 and 33 arranged in the Y direction are connected via a bridge portion 37 formed between the gate wirings 31 and 33. The gate wirings 32 and 34 arranged in the Y direction are not connected and remain separated.

[0054] In the M1 wiring layer, metal wirings 71, 72, 73, and 74 extending in the X direction are formed. The metal wiring 71 is connected to the gate wiring 32 through a via. The metal wiring 72 is connected to the gate wirings 31 and 33 through a via. The metal wiring 73 is connected to the gate wiring 34 through a via. The metal wiring 74 is connected to the local wiring 63 through a via. The metal wirings 71, 72, 73, and 74 correspond to the inputs NE, A, and E and the output Y of the tri-state inverter, respectively.

[0055] (Example 3: Inverter cell) Fig. 6(a) is a plan view showing the layout structure of an inverter cell, and Fig. 6(b) is a circuit diagram of the inverter. This inverter cell is based on a basic structure in which only one transistor is arranged in the X direction. In this basic structure, only the transistors P11, P12, N11, and N12 in Fig. 1 are formed.

[0056] In the local wiring layer, local wirings 81, 82, and 83 extending in the Y direction are formed. The local wiring 81 is connected to the pads 22a and 24a, and is also connected to the power supply wiring 11 through a via. The local wiring 82 is connected to the pads 22b, 24b, 27b, and 29b. The local wiring 83 is connected to the pads 27a and 29a, and is also connected to the power supply wiring 12 through a via.

[0057] The gate wirings 31 and 33 arranged side by side in the Y direction are connected via a bridge portion 38 formed between the gate wiring 31 and the gate wiring 33 .

[0058] In the M1 wiring layer, metal wirings 91 and 92 extending in the X direction are formed. The metal wiring 91 is connected to the gate wirings 31 and 33 through vias. The metal wiring 92 is connected to the local wiring 82 through a via. The metal wirings 91 and 92 correspond to the input A and output Y of the inverter, respectively.

[0059] (Example 4: 2-input NOR) FIG. 7(a) is a plan view showing the layout structure of a two-input NOR cell, and FIG. 7(b) is a circuit diagram of the two-input NOR.

[0060] In the local wiring layer, local wirings 101, 102, 103, 104, and 105 extending in the Y direction are formed. The local wiring 101 is connected to the pads 22a and 24a, and is also connected to the power supply wiring 11 through a via. The local wiring 102 is connected to the pads 22b and 24b. The local wiring 103 is connected to the pads 22c, 24c, 27c, and 29c. The local wiring 104 is connected to the pads 27a and 29a. The local wiring 105 is connected to the pads 27b and 29b, and is also connected to the power supply wiring 12 through a via.

[0061] The gate wirings 31 and 33 arranged in the Y direction are connected via a bridge portion 39a formed between the gate wiring 31 and the gate wiring 33. The gate wirings 32 and 34 arranged in the Y direction are connected via a bridge portion 39b formed between the gate wiring 32 and the gate wiring 34.

[0062] In the M1 wiring layer, metal wirings 111, 112, and 113 extending in the X direction are formed. The metal wiring 111 is connected to the gate wirings 31 and 33 through vias. The metal wiring 112 is connected to the gate wirings 32 and 34 through vias. The metal wiring 113 is connected to the local wirings 103 and 104 through vias. The metal wirings 111, 112, and 113 correspond to the inputs B, A, and output Y of the two-input NOR, respectively.

[0063] As described above, according to this embodiment, in the standard cell having the fork sheet FET, the surfaces of the nanosheets 21a and 21b farther from the N-type region in the Y direction are exposed from the gate wirings 31 and 32. In other words, the gate wirings 31 and 32 do not overlap the nanosheets 21a and 21b toward the power supply wiring 11 side. In addition, the surfaces of the nanosheets 28a and 28b farther from the P-type region in the Y direction are exposed from the gate wirings 33 and 34. In other words, the gate wirings 33 and 34 do not overlap the nanosheets 28a and 28b toward the power supply wiring 12 side. Therefore, at the boundary portion between adjacent cells in the Y direction, the space required between the nanosheet of one cell and the nanosheet of the other cell becomes smaller.

[0064] In addition, the surfaces of the nanosheets 23a and 23b on the N-type region side in the Y direction are exposed from the gate wirings 31 and 32. In other words, the gate wirings 31 and 32 do not overlap the nanosheets 23a and 23b on the N-type region side. In addition, the surfaces of the nanosheets 26a and 26b on the P-type region side in the Y direction are exposed from the gate wirings 33 and 34. In other words, the gate wirings 33 and 34 do not overlap the nanosheets 26a and 26b on the P-type region side. Therefore, the space required between the nanosheets of the P-type region and the nanosheets of the N-type region at the boundary between the P-type region and the N-type region is smaller.

[0065] Therefore, the size in the Y direction of a semiconductor integrated circuit device having a fork-sheet FET can be effectively reduced.

[0066] (Variation 1) FIG. 8 shows a basic structure of a standard cell having a fork-sheet FET according to a modified example, where (a) is a plan view and (b) is a cross-sectional view taken along line YY' in (a).

[0067] In the example of Fig. 8, in the P-type region on the N-well, transistors are arranged in three rows in the Y direction, and in the N-type region on the P-type substrate, transistors are arranged in three rows in the Y direction. That is, P-type transistors P11, P12, P13, P21, P22, and P23 are formed in the P-type region. N-type transistors N11, N12, N13, N21, N22, and N23 are formed in the N-type region. The transistors P11, P12, P13, N11, N12, and N13 are arranged in a row in the Y direction. The transistors P21, P22, P23, N21, N22, and N23 are arranged in a row in the Y direction.

[0068] The transistors P11, P12, P13, P21, P22, and P23 have, as their channel portions, nanosheets 121a, 122a, 123a, 121b, 122b, and 123b each made up of three sheets. The transistors N11, N12, N13, N21, N22, and N23 have, as their channel portions, nanosheets 124a, 125a, 126a, 124b, 125b, and 126b each made up of three sheets.

[0069] Gate wirings 131 and 132 extending in parallel in the Y direction are formed in the P-type region. The gate wiring 131 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 121a of the transistor P11, the nanosheet 122a of the transistor P12, and the nanosheet 123a of the transistor P13, via a gate insulating film (not shown). The gate wiring 131 becomes the gates of the transistors P11, P12, and P13. The gate wiring 132 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 121b of the transistor P21, the nanosheet 122b of the transistor P22, and the nanosheet 123b of the transistor P23, via a gate insulating film (not shown). The gate wiring 132 becomes the gates of the transistors P21, P22, and P23.

[0070] Gate wirings 133 and 134 extending in parallel in the Y direction are formed in the N-type region. The gate wiring 133 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 124a of the transistor N11, the nanosheet 125a of the transistor N12, and the nanosheet 126a of the transistor N13 via a gate insulating film (not shown). The gate wiring 133 becomes the gates of the transistors N11, N12, and N13. The gate wiring 134 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 124b of the transistor N21, the nanosheet 125b of the transistor N22, and the nanosheet 126b of the transistor N23 via a gate insulating film (not shown). The gate wiring 134 becomes the gates of the transistors N21, N22, and N23.

[0071] Here, the surfaces of nanosheets 121a and 121b opposite the N-type region in the Y direction (the surfaces closer to power supply wiring 11) are not covered by gate wirings 131 and 132 and are exposed from gate wirings 131 and 132. The surfaces of nanosheets 123a and 123b facing the N-type region in the Y direction are not covered by gate wirings 131 and 132 and are exposed from gate wirings 131 and 132. For example, nanosheets 121a, 122a, and 123a constitute a first nanosheet group, nanosheet 121a corresponds to the first nanosheet that is farthest from the N-type region in the first nanosheet group, and nanosheet 123a corresponds to the second nanosheet that is closest to the N-type region in the first nanosheet group.

[0072] The surfaces of the nanosheets 124a and 124b facing the P-type region in the Y direction are not covered by the gate wirings 133 and 134, and are exposed from the gate wirings 133 and 134. The surfaces of the nanosheets 126a and 126b opposite the P-type region in the Y direction (the surfaces closer to the power supply wiring 12) are not covered by the gate wirings 133 and 134, and are exposed from the gate wirings 133 and 134. For example, the nanosheets 124a, 125a, and 126a constitute a second nanosheet group, the nanosheet 126a corresponds to the third nanosheet that is the furthest from the P-type region in the second nanosheet group, and the nanosheet 124a corresponds to the fourth nanosheet that is the closest to the P-type region in the second nanosheet group.

[0073] The nanosheets 122a and 122b are surrounded by the gate wirings 131 and 132 all around in the Y direction. The nanosheets 125a and 125b are surrounded by the gate wirings 133 and 134 all around in the Y direction.

[0074] In this modified example, the same effect as that of the above embodiment can be obtained. That is, at the boundary portion of adjacent cells in the Y direction, the space required between the nanosheet of one cell and the nanosheet of the other cell becomes smaller. Also, at the boundary portion between the P-type region and the N-type region, the space required between the nanosheet of the P-type region and the nanosheet of the N-type region becomes smaller. Therefore, the size in the Y direction of the semiconductor integrated circuit device having the fork sheet FET can be effectively reduced.

[0075] (Variation 2) FIG. 9 shows a basic structure of a standard cell having a fork-sheet FET according to a modified example, where (a) is a plan view and (b) is a cross-sectional view taken along line YY' in (a).

[0076] In the example of FIG. 9, in the P-type region on the N-well, transistors are arranged in four rows in the Y direction, and in the N-type region on the P-type substrate, transistors are arranged in four rows in the Y direction. That is, P-type transistors P11, P12, P13, P14, P21, P22, P23, and P24 are formed in the P-type region. N-type transistors N11, N12, N13, N14, N21, N22, N23, and N24 are formed in the N-type region. The transistors P11, P12, P13, P14, N11, N12, N13, and N14 are arranged in a row in the Y direction. The transistors P21, P22, P23, P24, N21, N22, N23, and N24 are arranged in a row in the Y direction.

[0077] The transistors P11, P12, P13, P14, P21, P22, P23, and P24 each have a channel portion formed of three nanosheets 221a, 222a, 223a, 224a, 221b, 222b, 223b, and 224b. The transistors N11, N12, N13, N14, N21, N22, N23, and N24 each have a channel portion formed of three nanosheets 225a, 226a, 227a, 228a, 225b, 226b, 227b, and 228b.

[0078] Gate wirings 231 and 232 extending in parallel in the Y direction are formed in the P-type region. The gate wiring 231 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 221a of the transistor P11 and the nanosheet 222a of the transistor P12 via a gate insulating film (not shown). The gate wiring 231 becomes the gates of the transistors P11 and P12. The gate wiring 232 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 221b of the transistor P21 and the nanosheet 222b of the transistor P22 via a gate insulating film (not shown). The gate wiring 232 becomes the gates of the transistors P21 and P22.

[0079] Further, gate wirings 233 and 234 extending in parallel in the Y direction are formed in the P-type region. The gate wiring 233 is located at the same position in the X direction as the gate wiring 231, and the gate wiring 234 is located at the same position in the X direction as the gate wiring 232. The gate wiring 233 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 223a of the transistor P13 and the nanosheet 224a of the transistor P14 via a gate insulating film (not shown). The gate wiring 233 becomes the gates of the transistors P13 and P14. The gate wiring 234 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 223b of the transistor P23 and the nanosheet 224b of the transistor P24 via a gate insulating film (not shown). The gate wiring 234 becomes the gates of the transistors P23 and P24.

[0080] Gate wirings 235 and 236 extending in parallel in the Y direction are formed in the N-type region. The gate wiring 235 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 225a of the transistor N11 and the nanosheet 226a of the transistor N12 via a gate insulating film (not shown). The gate wiring 235 becomes the gates of the transistors N11 and N12. The gate wiring 236 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 225b of the transistor N21 and the nanosheet 226b of the transistor N22 via a gate insulating film (not shown). The gate wiring 236 becomes the gates of the transistors N21 and N22.

[0081] Further, gate wirings 237 and 238 extending in parallel in the Y direction are formed in the N-type region. The gate wiring 237 is located at the same position in the X direction as the gate wiring 235, and the gate wiring 238 is located at the same position in the X direction as the gate wiring 236. The gate wiring 237 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 227a of the transistor N13 and the nanosheet 228a of the transistor N14 via a gate insulating film (not shown). The gate wiring 237 becomes the gates of the transistors N13 and N14. The gate wiring 238 surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 227b of the transistor N23 and the nanosheet 228b of the transistor N24 via a gate insulating film (not shown). The gate wiring 238 becomes the gates of the transistors N23 and N24.

[0082] Here, the surfaces of the nanosheets 221a and 221b opposite the N-type region in the Y direction (the surfaces closer to the power supply wiring 11) are not covered by the gate wirings 231 and 232 and are exposed from the gate wirings 231 and 232. The surfaces of the nanosheets 224a and 224b facing the N-type region in the Y direction are not covered by the gate wirings 233 and 234 and are exposed from the gate wirings 233 and 234. For example, the nanosheets 221a, 222a, 223a, and 224a constitute a first nanosheet group, the nanosheet 221a corresponds to the first nanosheet that is the furthest from the N-type region in the first nanosheet group, and the nanosheet 224a corresponds to the second nanosheet that is the closest to the N-type region in the first nanosheet group. Also, the gate wirings 231 and 233 correspond to the first gate wiring. However, in this modification, the first gate wiring is separated between nanosheet 222a and nanosheet 223a.

[0083] The surfaces of the nanosheets 225a and 225b on the P-type region side in the Y direction are not covered by the gate wirings 235 and 236, and are exposed from the gate wirings 235 and 236. The surfaces of the nanosheets 228a and 228b on the opposite side to the P-type region in the Y direction (the surfaces closer to the power supply wiring 12) are not covered by the gate wirings 237 and 238, and are exposed from the gate wirings 237 and 238. For example, the nanosheets 225a, 226a, 227a, and 228a constitute a second nanosheet group, the nanosheet 228a corresponds to the third nanosheet that is the furthest from the P-type region in the second nanosheet group, and the nanosheet 225a corresponds to the fourth nanosheet that is the closest to the P-type region in the second nanosheet group. In addition, the gate wirings 235 and 237 correspond to the second gate wiring. However, in this modification, the second gate wiring is separated between the nanosheets 226a and 227a.

[0084] In this modified example, the same effect as that of the above embodiment can be obtained. That is, at the boundary portion of adjacent cells in the Y direction, the space required between the nanosheet of one cell and the nanosheet of the other cell becomes smaller. Also, at the boundary portion between the P-type region and the N-type region, the space required between the nanosheet of the P-type region and the nanosheet of the N-type region becomes smaller. Therefore, the size in the Y direction of the semiconductor integrated circuit device having the fork sheet FET can be effectively reduced.

[0085] Furthermore, in this modification, the surfaces of nanosheets 222a and 222b facing nanosheets 223a and 223b are not covered by gate wirings 231 and 232, and are exposed from gate wirings 231 and 232. The surfaces of nanosheets 223a and 223b facing nanosheets 222a and 222b are not covered by gate wirings 233 and 234, and are exposed from gate wirings 233 and 234. For example, nanosheets 222a and 223a are between the first nanosheet and the second nanosheet in the first nanosheet group, and correspond to the fifth and sixth nanosheets adjacent to each other in the Y direction.

[0086] The surfaces of nanosheets 226a and 226b facing nanosheets 227a and 227b are not covered by gate wirings 235 and 236, and are exposed from gate wirings 235 and 236. The surfaces of nanosheets 227a and 227b facing nanosheets 226a and 226b are not covered by gate wirings 237 and 238, and are exposed from gate wirings 237 and 238. For example, nanosheets 226a and 227a are located between the third nanosheet and the fourth nanosheet in the second nanosheet group, and correspond to the seventh and eighth nanosheets adjacent to each other in the Y direction.

[0087] With this configuration, since the gate wiring 231 and the gate wiring 233 are separated, different signals can be applied to the gates of the transistors P11 and P12 and the gates of the transistors P13 and P14. Since the gate wiring 232 and the gate wiring 234 are separated, different signals can be applied to the gates of the transistors P21 and P22 and the gates of the transistors P23 and P24. Furthermore, since the gate wiring 235 and the gate wiring 237 are separated, different signals can be applied to the gates of the transistors N11 and N12 and the gates of the transistors N13 and N14. Since the gate wiring 236 and the gate wiring 238 are separated, different signals can be applied to the gates of the transistors N21 and N22 and the gates of the transistors N23 and N24. This increases the degree of freedom of the logic circuit that can be configured.

[0088] In addition, the space required between the transistors P12, P22 and the transistors P13, P23, i.e., between the nanosheets 222a, 222b and the nanosheets 223a, 223b, is small. Also, the space required between the transistors N12, N22 and the transistors N13, N23, i.e., between the nanosheets 226a, 226b and the nanosheets 227a, 227b, is small. Therefore, the size in the Y direction of the semiconductor integrated circuit device having the fork sheet FET can be further effectively reduced.

[0089] In the configuration of FIG. 9, the gate wirings 231 and 233, the gate wirings 232 and 234, the gate wirings 235 and 237, and the gate wirings 236 and 238 may be formed integrally without being separated from each other. [Industrial Applicability]

[0090] In the present disclosure, a layout structure with a small area can be realized for a semiconductor integrated circuit device using a fork sheet FET, which is useful for miniaturizing semiconductor chips and improving their integration, for example. [Explanation of symbols]

[0091] 11,12 Power wiring 21a, 21b, 23a, 23b, 26a, 26b, 28a, 28b Nanosheets 31, 32, 33, 34 Gate wiring 36a, 36b, 37, 38, 39a, 39b Bridge section (gate connection section) 121a, 121b, 122a, 122b, 123a, 123b, 124a, 124b, 125a, 125b, 126a, 126b Nanosheets 131,132,133,134 Gate wiring 221a, 221b, 222a, 222b, 223a, 224a, 224b, 225a, 225b, 226a, 226b, 227a, 227b, 228a, 228b Nanosheets 231,232,233,234,235,236,237,238 Gate wiring

Claims

1. A semiconductor integrated circuit device including standard cells arranged in a first direction, The standard cell is a P-type region in which a P-type transistor is formed and an N-type region in which an N-type transistor is formed are formed adjacent to each other in a second direction perpendicular to the first direction, In the P-type region, a first nanosheet group is formed of two or more nanosheets each extending in the first direction and aligned in the second direction; In the N-type region, a second nanosheet group is formed of two or more nanosheets each extending in the first direction and aligned in the second direction; a first gate wiring extending in the second direction and formed so as to surround the periphery of each nanosheet of the first nanosheet group in the second direction and in a third direction perpendicular to the first and second directions; a second gate wiring extending in the second direction and formed so as to surround the outer periphery of each nanosheet of the second nanosheet group in the second direction and the third direction; In the first group of nanosheets, a first nanosheet farthest from the N-type region has a surface opposite to the N-type region in the second direction exposed from the first gate wiring, and a second nanosheet closest to the N-type region has a surface facing the N-type region in the second direction exposed from the first gate wiring, In the second group of nanosheets, a third nanosheet farthest from the P-type region has a surface opposite to the P-type region in the second direction exposed from the second gate wiring, and a fourth nanosheet closest to the P-type region has a surface facing the P-type region in the second direction exposed from the second gate wiring, The first nanosheet group includes fifth and sixth nanosheets that are located between the first nanosheet and the second nanosheet and are adjacent to each other in the second direction, The second nanosheet group includes seventh and eighth nanosheets that are located between the third nanosheet and the fourth nanosheet and are adjacent to each other in the second direction, the fifth and sixth nanosheets have surfaces facing each other in the second direction exposed from the first gate wiring, The seventh and eighth nanosheets have surfaces facing each other in the second direction exposed from the second gate wiring. A semiconductor integrated circuit device comprising:

2. 2. The semiconductor integrated circuit device according to claim 1, Each of the first and second nanosheet groups has a single sheet structure or a plurality of sheet structures overlapping in a plan view. A semiconductor integrated circuit device comprising:

3. 2. The semiconductor integrated circuit device according to claim 1, The first and second gate wirings are disposed at the same position in the first direction. A semiconductor integrated circuit device comprising:

4. 4. The semiconductor integrated circuit device according to claim 3, The standard cell is a gate connection portion formed between the first gate wiring and the second gate wiring and connecting the first gate wiring and the second gate wiring; A semiconductor integrated circuit device comprising:

5. 2. The semiconductor integrated circuit device according to claim 1, a first power supply wiring extending in the first direction and supplying a first power supply voltage; a second power supply wiring extending in the first direction and supplying a second power supply voltage; The P-type region and the N-type region are formed between the first power supply wiring and the second power supply wiring. A semiconductor integrated circuit device comprising:

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