Semiconductor Device

Abstract

To provide a semiconductor device that reduces a leakage current when a reverse voltage is applied.SOLUTION: A semiconductor element 3 includes: a semiconductor chip 12; a first conductive film 51 formed on a first main surface 12A of the semiconductor chip; a fourth conductive film 54 formed on a second main surface 12B of the semiconductor chip; a third impurity region 123 formed in the semiconductor chip; a vertical semiconductor element structure formed in an active region 64 and allowing a current to flow between the first conductive film and the fourth conductive film; a third conductive film 53 formed on the first main surface of the semiconductor chip so as to be physically separated from the first conductive film, and connected to the semiconductor chip at an outer peripheral region 63; and a second impurity region 122 which is continuously formed ranging from the active region to the outer peripheral region in a surface portion of the third impurity region, and constitutes at least a part of the semiconductor element structure. A first conductivity type region 130 in which no second impurity region is selectively formed exists in the outer peripheral region.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses a trench-gate vertical MOSFET including an epitaxial layer in which an active cell array and a gate bus area are formed, a gate trench formed in the active cell array, a gate oxide film formed in the gate trench, a gate electrode made of polysilicon embedded in the gate trench, a trench formed in the gate bus area and connected to the gate trench, and a gate bus made of polysilicon embedded in the trench so as to cover the surface of the epitaxial layer in the gate bus area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2006-520091 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the semiconductor device according to an embodiment of the present disclosure is to reduce leakage current when a reverse voltage is applied. [Means for solving the problem]

[0005] According to one embodiment of the present disclosure, there is provided a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and an end surface surrounding the first main surface, with an active region and a peripheral region around the active region set on the first main surface side, a first electrode formed on the first main surface of the semiconductor chip, a second electrode formed on the second main surface of the semiconductor chip, a first region of a first conductivity type formed on the semiconductor chip, a vertical semiconductor element structure formed in the active region and passing a current between the first electrode and the second electrode, a peripheral electrode formed on the first main surface of the semiconductor chip and physically separated from the first electrode and connected to the semiconductor chip in the peripheral region, and a well region of a second conductivity type formed continuously from the active region to the peripheral region in a surface layer portion of the first region and constituting at least a part of the semiconductor element structure, wherein a first conductivity type region in which the well region is not selectively formed is present in the peripheral region. Effect of the Invention

[0006] According to the semiconductor device according to the embodiment of the present disclosure, it is possible to reduce the leakage current when a reverse voltage is applied between the first electrode and the second electrode. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing a planar structure of the active region of FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2 (first embodiment). [Figure 4] FIG. 4 is a cross-sectional view taken along line III-III of FIG. 2 (second embodiment). [Diagram 5] FIG. 5 is a diagram showing a planar structure of the peripheral region of FIG. [Figure 6] FIG. 6 is an enlarged view of a portion surrounded by a two-dot chain line VI in FIG. [Figure 7]FIG. 7 is an enlarged view of a portion surrounded by a two-dot chain line VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. [Figure 10] FIG. 10 is a diagram for comparing the breakdown voltages of the semiconductor elements according to Samples 1 to 4. In FIG. [Figure 11] FIG. 11 is a schematic plan view of the semiconductor devices according to Samples 5 to 8. As shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to Sample 5. As shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to Sample 6. As shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to Sample 7. As shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to Sample 8. As shown in FIG. [Figure 16] FIG. 16 is a schematic plan view of a semiconductor device according to Sample 9. As shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of a semiconductor device according to Sample 9. As shown in FIG. [Figure 18] FIG. 18 is a schematic plan view of a semiconductor device according to sample 10. As shown in FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view of a semiconductor device according to sample 10. As shown in FIG. [Figure 20] FIG. 20 is a schematic plan view of a semiconductor device according to Sample 11. As shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of a semiconductor device according to Sample 11. As shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of a semiconductor device according to sample 12. As shown in FIG. [Figure 23] FIG. 23 is a diagram for comparing the breakdown voltages of the semiconductor elements according to Samples 5 to 7 and Samples 9 to 11. In FIG. [Figure 24]FIG. 24 is a schematic diagram showing the extension of a depletion layer in the peripheral region of the semiconductor element of sample 5. As shown in FIG. [Diagram 25] FIG. 25 is a schematic diagram showing the extension of a depletion layer in the peripheral region of the semiconductor element of sample 6. As shown in FIG. [Figure 26] FIG. 26 is a schematic diagram showing the extension of a depletion layer in the peripheral region of the semiconductor element of sample 7. In FIG. [Figure 27] FIG. 27 is a schematic diagram showing the extension of a depletion layer in the peripheral region of the semiconductor element of Sample 9. In FIG. [Figure 28] FIG. 28 is a schematic diagram showing the extension of a depletion layer in the peripheral region of the semiconductor element of sample 10. As shown in FIG. [Figure 29] FIG. 29 is a schematic diagram showing the extension of a depletion layer in the peripheral region of the semiconductor element of sample 11. As shown in FIG. [Diagram 30] FIG. 30 is a schematic cross-sectional view of a semiconductor device according to Sample 13. As shown in FIG. [Diagram 31] FIG. 31 is a schematic cross-sectional view of a semiconductor device according to Sample 14. As shown in FIG. [Diagram 32] FIG. 32 is a schematic cross-sectional view of a semiconductor device according to sample 15. As shown in FIG. [Diagram 33] FIG. 33 is a schematic cross-sectional view of a semiconductor device according to sample 16. As shown in FIG. [Diagram 34] FIG. 34 is a diagram showing the relationship between the first peripheral pitch and the device withstand voltage. [Diagram 35] FIG. 35 is a diagram showing the relationship between the second outer circumferential pitch and the device withstand voltage. [Diagram 36] FIG. 36 is a diagram showing the relationship between the third outer circumferential pitch and the device withstand voltage. [Figure 37] FIG. 37 is a schematic cross-sectional view of a semiconductor element according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there are a number of components whose names are assigned ordinal numbers, but the ordinal numbers do not necessarily match the ordinal numbers of the components described in the claims. [Overall configuration of semiconductor device 1] Fig. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure. For clarity, in Fig. 1, a package 4 is shown by an imaginary line (dashed line) and other components are shown by solid lines.

[0009] The semiconductor device 1 includes a lead frame 2, a semiconductor element 3, and a package 4. The lead frame 2 is formed in the shape of a metal plate. The lead frame 2 is formed by punching, cutting, bending, or the like from a thin metal plate such as Cu having a rectangular shape in a plan view. Therefore, the main component of the material of the lead frame 2 is Cu. However, the material of the lead frame 2 is not limited to this.

[0010] The lead frame 2 may include a die pad portion 21, a first lead portion 22, a second lead portion 23, and a third lead portion 24. In this embodiment, the first lead portion 22, the second lead portion 23, and the third lead portion 24 may be referred to as a source lead portion, a gate lead portion, and a drain lead portion, respectively. In addition, the first lead portion 22, the second lead portion 23, and the third lead portion 24 have portions exposed from the package 4 and connected to an external circuit of the semiconductor device 1, and therefore may be referred to as a first terminal (source terminal), a second terminal (gate terminal), and a third terminal (drain terminal).

[0011] In a plan view, the die pad portion 21 has a rectangular shape having a pair of first sides 211A, 211B extending in a first direction X and a pair of second sides 212A, 212B extending in a direction intersecting the first direction X (in this embodiment, a direction perpendicular to the first direction X). The first lead portion 22, the second lead portion 23, and the third lead portion 24 are arranged around the die pad portion 21. In this embodiment, the first lead portion 22, the second lead portion 23, and the third lead portion 24 are arranged adjacent to the first sides 211A and 211B of the die pad portion 21. More specifically, the first lead portion 22 and the second lead portion 23 are arranged adjacent to one first side 211A of the die pad portion 21, and the third lead portion 24 is arranged adjacent to the other first side 211B of the die pad. In other words, the first lead portion 22 and the second lead portion 23 are arranged on the opposite side of the third lead portion 24 across the die pad portion 21.

[0012] The first lead portion 22 is formed away from the die pad portion 21. The first lead portion 22 may include a first pad portion 221 and a first lead 222. The first pad portion 221 is formed in a substantially rectangular shape elongated along the first side 211A of the die pad portion 21 in a plan view. The first lead 222 is formed integrally with the first pad portion 221 and extends from the first pad portion 221 in a direction intersecting the longitudinal direction of the first pad portion 221. A plurality of first leads 222 (three in this embodiment) are formed. The plurality of first leads 222 are arranged at intervals from each other along the longitudinal direction of the common first pad portion 221 and are connected to the common first pad portion 221.

[0013] The second lead portion 23 is formed away from the die pad portion 21 and the first lead portion 22. The second lead portion 23 may include a second pad portion 231 and a second lead 232. The second pad portion 231 is formed in a substantially rectangular shape extending along the first side 211A of the die pad portion 21. The second lead 232 is formed integrally with the second pad portion 231 and extends from the second pad portion 231 in a direction intersecting the longitudinal direction of the second pad portion 231. The second lead 232 is connected to the second pad portion 231 in a one-to-one relationship. In this embodiment, the second lead portion 23 is disposed near one end of one first side 211A of the die pad portion 21 (one corner of the die pad portion 21), and the first lead portion 22 extends from the end toward the other end along the first side 211A of the die pad portion 21.

[0014] Unlike the first lead portion 22 and the second lead portion 23, the third lead portion 24 is formed integrally with the die pad portion 21. The third lead portion 24 extends from the other first side 211B of the die pad portion 21 in a direction intersecting the first side 211B. A plurality of third lead portions 24 (four in this embodiment) are formed. The multiple third lead portions 24 are arranged at intervals along the first side 211B of the die pad portion 21.

[0015] The semiconductor element 3 is disposed on the die pad portion 21 of the lead frame 2 and is supported by the die pad portion 21. In a plan view, the semiconductor element 3 has a rectangular shape smaller than the die pad portion 21, and has a pair of first end faces 31A, 31B and a pair of second end faces 32A, 32B. In this embodiment, the semiconductor element 3 is disposed on the die pad portion 21 such that the first end faces 31A, 31B are parallel to the first sides 211A, 211B of the die pad portion 21, and the second end faces 32A, 32B are parallel to the second sides 212A, 212B of the die pad portion 21. A first distance D1 between the first sides 211A, 211B of the die pad portion 21 and the first end faces 31A, 31B of the semiconductor element 3 is narrower than a second distance D2 between the second sides 212A, 212B of the die pad portion 21 and the second end faces 32A, 32B of the semiconductor element 3. For example, the first distance D1 may be equal to or less than half the second distance D2.

[0016] A conductive film 5 as an example of a surface electrode and an insulating film 6 are formed on one surface (the upper surface in this embodiment) of the semiconductor element 3. The conductive film 5 is partially covered with the insulating film 6. In Fig. 1, the portion of the conductive film 5 covered with the insulating film 6 is shown as a hatched area, and the portion exposed from the insulating film 6 is shown as a white area. The conductive film 5 is a portion to which a first wire 8 and a second wire 10, which will be described later, are connected, and may be referred to as an electrode film or a surface electrode film.

[0017] The conductive film 5 is formed over almost the entire upper surface of the semiconductor element 3. The conductive film 5 may include a first conductive film 51, a second conductive film 52, and a third conductive film 53. The first conductive film 51, the second conductive film 52, and the third conductive film 53 are formed separately from each other. A plurality of first conductive films 51 are formed. The plurality of first conductive films 51 are formed adjacent to each other in a direction along the second end faces 32A, 32B of the semiconductor element 3, and a gap region 61 is formed between adjacent first conductive films 51. The region around the first conductive film 51 may be an outer periphery region 63. In other words, when the formation region of the first conductive film 51 (the region covered with the first conductive film 51) is referred to as an active region 64, the outer periphery region 63 may be the outer periphery region 63 surrounding the active region 64. In this embodiment, the outer periphery region 63 is annular and formed along the outer periphery of the semiconductor element 3.

[0018] In this embodiment, each of the first conductive films 51 is formed in a rectangular shape in a plan view and extends along the first end faces 31A, 31B of the semiconductor element 3. A portion of the first conductive film 51 is exposed from the insulating film 6 as a first pad 7. A first wire 8 is connected to the first pad 7. In this embodiment, the first wire 8 is a so-called Cu wire, which is mainly composed of Cu. Examples of wires mainly composed of Cu include wires made of simple Cu (for example, Cu purity of 99.99% or more), wires made of Cu alloys in which Cu is alloyed with other alloy components, and wires in which a simple Cu wire or a Cu alloy wire is covered with a conductive layer. Examples of alloy components of Cu alloy wire include Ag, Au, Al, Ni, Be, Fe, Ti, Pd, Zn, Sn, etc. Examples of coating components of conductive layer-coated Cu wire include Pd, etc. Note that Au wire or Al wire may be used as a modified example of the first wire 8. When Au wire is used as a bonding wire, Au is expensive and the cost is unstable due to price fluctuations, and in a high-temperature environment, wire peeling is likely to occur due to compound growth between gold and aluminum. When Al wire is used as a bonding wire, aluminum has a relatively low melting point and is likely to recrystallize in a high-temperature environment. A semiconductor device having higher reliability than a case where an Au wire or an Al wire is used can be provided by using a Cu wire as the first wire 8. When the first wire 8 is a Cu wire, for example, the wire may have a diameter of 18 μm or more and 50 μm or less.

[0019] The first wire 8 connects the first pad 7 and the first pad portion 221 of the first lead portion 22. The first wire 8 may include a long wire 81 and a short wire 82 that is shorter than the long wire 81. The long wire 81 may be connected to the first pad 7 of a pair of adjacent first pads 7 that is farther from the first lead portion 22. On the other hand, the short wire 82 may be connected to the first pad 7 of the pair of first pads 7 that is closer to the first lead portion 22.

[0020] The long wires 81 and the short wires 82 may each be provided in plurality, and may be arranged alternately along the longitudinal direction of the first pad portion 221. Furthermore, the bonding portion 811 of the long wire 81 on the first pad portion 221 side and the bonding portion 821 of the short wire 82 on the first pad portion 221 side are arranged biased to one side and the other side in the width direction intersecting the longitudinal direction of the first pad portion 221, respectively. As a result, the bonding portion 811 of the long wire 81 and the bonding portion 821 of the short wire 82 are arranged offset from each other, and it is possible to prevent them from contacting each other. As a result, it is possible to save space in the first lead portion 22.

[0021] The second conductive film 52 may integrally include a pad electrode portion 521 and a finger electrode portion 522. The pad electrode portion 521 is formed in the outer peripheral region 63, and in this embodiment, is disposed at one corner of the semiconductor element 3. The finger electrode portion 522 is formed in the outer peripheral region 63 from the pad electrode portion 521 along the periphery of the semiconductor element 3. In this embodiment, the finger electrode portion 522 is formed along the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor element 3 so as to surround the first conductive film 51. The finger electrode portion 522 may also be formed in the gap region 61 between the adjacent first conductive films 51. As a result, each first conductive film 51 is individually surrounded by the finger electrode portion 522.

[0022] The finger electrode portion 522 is covered with the insulating film 6, while a part of the pad electrode portion 521 is exposed from the insulating film 6 as a second pad 9. A second wire 10 is connected to the second pad 9. The second wire 10 may be made of the same material as the first wire 8. That is, in this embodiment, the second wire 10 may be a so-called Cu wire whose main component is Cu, but as a modified example, an Au wire or an Al wire may be used. The second wire 10 may have the same diameter as the first wire 8. That is, the second wire 10 may have a diameter of 18 μm or more and 50 μm or less in the case of a Cu wire, for example.

[0023] The second wire 10 connects the second pad 9 and the second pad portion 231 of the second lead portion 23. The second wire 10 may have a length shorter than the short wire 82 of the first wire 8. The third conductive film 53 is formed in an outer circumferential region 63 along the periphery of the semiconductor element 3, outside the second conductive film 52. In this embodiment, the third conductive film 53 is formed in a closed ring shape along the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor element 3 so as to surround the second conductive film 52.

[0024] The package 4 covers the semiconductor element 3, the first wires 8, the second wires 10, and a part of the lead frame 2, and may be called a sealing resin. The package 4 is made of an insulating material. In this embodiment, the package 4 is made of, for example, a black epoxy resin. [Structure of active area 64] Fig. 2 is a partial enlarged view showing a planar structure of the active region 64 in Fig. 1. Figs. 3 and 4 are cross-sectional views taken along line III-III in Fig. 2, showing a first form and a second form of the second impurity region 122, respectively.

[0025] The semiconductor device 1 includes a semiconductor chip 12, a first impurity region 121 (source), a second impurity region 122 (body), a third impurity region 123 (drain), a gate trench 15 (cell trench), a gate insulating film 16, a gate electrode 13 (control electrode), an interlayer insulating film 17, a source contact 18, and a first contact plug 11. The semiconductor chip 12 forms the outer shape of the semiconductor element 3, and is, for example, a structure in which a single crystal semiconductor material is formed into a chip shape (rectangular parallelepiped shape). The semiconductor chip 12 is formed of a semiconductor material such as Si or SiC. The semiconductor chip 12 has a first main surface 12A and a second main surface 12B opposite to the first main surface 12A. The first main surface 12A is a device surface on which functional devices are formed. The second main surface 12B is a non-device surface on which functional devices are not formed. In this embodiment, the semiconductor chip 12 may include a semiconductor substrate 127 and an epitaxial layer 129.

[0026] The semiconductor substrate 127 supports the epitaxial layer 129. The semiconductor substrate 127 may be a p-type impurity region formed in a surface layer portion of the second main surface 12B of the semiconductor chip 12. The thickness of the semiconductor substrate 127 may be, for example, 50 μm or more and 300 μm or less. The p-type impurity concentration of the semiconductor substrate 127 is 1×10 18 cm -3 More than 1×10 20 cm -3 It may be the following.

[0027] 3 and 4, the first impurity region 121 is a p-type impurity region selectively formed in the surface layer portion of the first main surface 12A of the semiconductor chip 12 below the first conductive film 51. The p-type impurity concentration of the first impurity region 121 is 1×10 18 cm -3 More than 1×10 20 cm -3 In this embodiment, the first impurity region 121 may be referred to as a p-type source region.

[0028] The second impurity region 122 is an n-type impurity region formed in a surface layer portion of the first main surface 12A of the semiconductor chip 12. In the active region 64, the second impurity region 122 is formed so as to be spaced from the first main surface 12A toward the second main surface 12B and to be in contact with the first impurity region 121. In other words, the second impurity region 122 faces the first main surface 12A with the first impurity region 121 in between. The n-type impurity concentration of the second impurity region 122 is 1×10 15 cm -3 More than 1×10 19 cm -3 The second impurity region 122 may be referred to as an n-type channel region 125 since it is a region in which a channel is formed in the active region 64. In other words, the channel region 125 may be referred to as a body region.

[0029] The channel region 125 may include a side portion 124 forming the side surface of the gate trench 15, and a convex bottom portion 126 extending from the lower end of the side portion 124 toward the second main surface 12B side so as to be away from the side surface of the gate trench 15. As shown in FIG. 3, the bottom portion 126 of the channel region 125 may face the gate trench 15 across a gap 128 formed of a part of the third impurity region 123. That is, the bottom portion 126 of the channel region 125 may be located closer to the first main surface 12A than the lower end 152 of the gate trench 15. On the other hand, as shown in FIG. 4, the bottom portion 126 of the channel region 125 may be located closer to the second main surface 12B than the lower end 152 of the gate trench 15. In this case, the bottom portion 126 of the channel region 125 may protrude closer to the second main surface 12B than the lower end 152 of the gate trench 15.

[0030] The third impurity region 123 is a p-type impurity region formed in a surface layer portion of the first main surface 12A of the semiconductor chip 12. The third impurity region 123 is formed so as to be in contact with the channel region 125. The third impurity region 123 has a resistivity of 3.5 Ω·cm or more and 4.5 Ω·cm or less. This allows the semiconductor device 1 to have a breakdown voltage of 100V or more. Here, the "breakdown voltage" may be defined as, for example, the maximum voltage that can be applied between the source and drain (between the first conductive film 51 and the fourth conductive film 54) in a range in which the semiconductor element 3 does not break down in an off state in which no voltage is applied to the gate electrode 13.

[0031] The third impurity region 123 may be formed of an epitaxial layer 129. The p-type impurity concentration of the third impurity region 123 is lower than the p-type impurity concentrations of the semiconductor substrate 127 and the first impurity region 121, and is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The thickness of the third impurity region 123 (epitaxial layer 129) may be 1 μm or more and 500 μm or less. In this embodiment, the third impurity region 123 may be referred to as a p-type drift region or a p-type drain region.

[0032] The gate trench 15 is a recess that penetrates the first impurity region 121 and the channel region 125 and reaches the third impurity region 123. As shown in FIG. 2, the gate trench 15 surrounds the first impurity region 121, the channel region 125, and the third impurity region 123, thereby defining a transistor cell 14 (semiconductor element structure) including these regions 121, 122, and 123. In this embodiment, the transistor cell 14 is selectively formed in a region below the first conductive film 51, as shown in FIG. 2. That is, the transistor cell 14 is covered with the first conductive film 51, but is not covered with the second conductive film 52 and the third conductive film 53.

[0033] The arrangement pattern of the transistor cells 14 is staggered in Fig. 2. Although not shown, the arrangement pattern of the transistor cells 14 may be a matrix or stripe pattern. Each transistor cell 14 is formed in a quadrangular shape in the plan view shown in Fig. 2, and in this embodiment, is formed in a rectangular shape. The gate trench 15 is formed between the plurality of transistor cells 14 arranged as described above. The gate trench 15 is formed in a tapered shape in which the opening width W1 gradually narrows toward the depth direction of the gate trench 15. The width W1 of the gate trench 15 may be, for example, 0.17 μm or more and 0.22 μm or less at the opening end of the gate trench 15. As shown in FIG. 3 and FIG. 4, the pitch P1 of the adjacent gate trenches 15 is, for example, 1 μm or less. As shown in FIG. 2, when the gate trenches 15 are connected to surround each of the plurality of transistor cells 14, the pitch P1 of the gate trenches 15 may be, for example, the distance between the gate trenches 15 facing each other with one transistor cell 14 sandwiched therebetween. The depth D1 of the gate trench 15 may be, for example, 0.8 μm or more and 1.2 μm or less.

[0034] 3 and 4, the gate insulating film 16 covers the inner surface of the gate trench 15. The gate insulating film 16 also covers the first main surface 12A of the semiconductor chip 12. The gate insulating film 16 is formed of an insulating material containing, for example, SiO2, SiN, or the like. Of the entire gate insulating film 16, a portion formed in the active region 64 and a portion formed on the inner surface of the gate trench 15 may be referred to as a first insulating film 161 of the gate insulating film 16 to be distinguished from a second insulating film 162 and a third insulating film 163 described later.

[0035] The gate electrode 13 is contained (embedded) in the gate trench 15. This structure allows for finer processing and lower on-resistance compared to a planar structure. Furthermore, the gate electrode 13 is insulated from the semiconductor chip 12 by the gate insulating film 16, thereby preventing leakage current. The gate electrode 13 is made of a conductive material containing polysilicon and the like. Since polysilicon has a melting point almost equal to that of single crystal silicon, the use of polysilicon as the gate electrode 13 eliminates temperature-related process limitations in processes after the formation of the gate electrode 13.

[0036] The gate electrode 13 faces the channel region 125 via the gate insulating film 16. In the channel region 125, a side portion 124 facing the gate electrode 13 is a channel portion. By applying a voltage to the gate electrode 13, carriers (electrons in this embodiment) are induced in the side portion 124 of the channel region 125 to form a channel, and electrical conduction is established between the first impurity region 121 and the third impurity region 123. That is, in the semiconductor device 1, the transistor cells 14 and the gate electrode 13 form a vertical element structure in which a current flows in the thickness direction of the semiconductor chip 12.

[0037] 3 and 4, the gate electrode 13 may have an upper surface 131 that is flush with the first main surface 12A of the semiconductor chip 12 or recessed toward the second main surface 12B. An interlayer insulating film 17 is formed on the first main surface 12A of the semiconductor chip 12 so as to cover the gate insulating film 16 and the gate electrode 13. The interlayer insulating film 17 insulates the gate electrode 13 from the first conductive film 51. Therefore, the gate electrode 13 is configured to be covered by the gate insulating film 16 and the interlayer insulating film 17. The interlayer insulating film 17 is made of an insulating material containing SiO2, SiN, or the like.

[0038] 2 to 4, a source contact 18 is formed in each transistor cell 14. In this embodiment, one source contact 18 is formed in each transistor cell 14, but a plurality of source contacts may be formed in each transistor cell 14. The source contact 18 is formed in a long rectangular shape in plan view along the longitudinal direction of the transistor cell 14 which has a rectangular shape in plan view.

[0039] 3 and 4, the source contact 18 is a recess that penetrates the interlayer insulating film 17, the gate insulating film 16, and the first impurity region 121 and reaches the channel region 125. The source contact 18 is formed in a tapered shape in which the opening width gradually narrows toward the depth direction of the source contact 18. The pitch between adjacent source contacts 18 is the same as the pitch P1 of the gate trenches 15, and is, for example, 1 μm or less.

[0040] The first contact plug 11 is embedded in the source contact 18 via the first barrier film 191. With this configuration, electric field concentration at the bottom of the gate trench 15 is alleviated, and a semiconductor device 1 with improved reliability can be provided. The first barrier film 191 suppresses diffusion of the material forming the first contact plug 11 into the interlayer insulating film 17. In this embodiment, the first contact plug 11 contains W (tungsten), and the first barrier film 191 may contain a material containing Ti (e.g., a single layer structure of Ti, or a laminated structure of Ti and TiN). The thickness of the first barrier film 191 is, for example, not less than 500 Å and not more than 800 Å.

[0041] The first barrier film 191 has one and the other surfaces formed following the inner surface of the source contact 18 and the upper surface of the interlayer insulating film 17, and has direct conduction with the first impurity region 121 and the channel region 125. The first barrier film 191 is also continuous across the upper region of the gate trench 15, which is the boundary between adjacent transistor cells 14. The first contact plug 11 is electrically connected to the first impurity region 121 and the channel region 125 via the first barrier film 191. The first contact plug 11 has an upper surface 111 that is recessed toward the first main surface 12A of the semiconductor chip 12 with respect to the upper surface of the interlayer insulating film 17.

[0042] The first conductive film 51 is formed on the interlayer insulating film 17. The first conductive film 51 may be called a source electrode film based on what it is electrically connected to. The first conductive film 51 is electrically connected to the first impurity region 121 and the channel region 125 via the first contact plug 11 and the first barrier film 191. The first conductive film 51 is made of a material containing Al, for example, and is made of AlCu in this embodiment.

[0043] As described above, the upper surface 111 of the first contact plug 11 is recessed with respect to the upper surface of the interlayer insulating film 17. Therefore, the upper surface of the first conductive film 51 may have a recess 511 formed at a position facing the upper surface 111 in the stacking direction of the first conductive film 51. A fourth conductive film 54 connected to the third impurity region 123 is formed on the second main surface 12B of the semiconductor chip 12. The fourth conductive film 54 is a common electrode for all the transistor cells 14, and may be referred to as a drain electrode layer. [Structure of outer region 63] Fig. 5 is a diagram showing the planar structure of the peripheral region 63 in Fig. 1, and is an enlarged diagram showing a corner of the semiconductor element 3 in Fig. 1. Fig. 6 is an enlarged diagram of a portion surrounded by a two-dot chain line VI in Fig. 5. Fig. 7 is an enlarged diagram of a portion surrounded by a two-dot chain line VII in Fig. 5. Fig. 8 is a diagram showing a VIII-VIII cross section in Fig. 6. Fig. 9 is a diagram showing a IX-IX cross section in Fig. 7.

[0044] 8 and 9, the semiconductor device 1 has the above-mentioned second impurity region 122 and third impurity region 123 as impurity regions in the peripheral region 63. The second impurity region 122 is exposed from the first main surface 12A of the semiconductor chip 12. In the peripheral region 63, the semiconductor device 1 has a first peripheral trench 40, a connection trench 41, a second peripheral trench 42, a gate insulating film 16, a first buried electrode 43, a connection electrode 44, a second buried electrode 45, and a second contact plug 46.

[0045] The first outer periphery trench 40 is a recess that penetrates the second impurity region 122 and reaches the third impurity region 123. The first outer periphery trench 40 is formed in an annular shape surrounding the collection of transistor cells 14 formed in the active region 64 (see also FIGS. 11, 16, 18, and 20). The first outer periphery trench 40 is covered with the second conductive film 52 (finger electrode portion 522).

[0046] 8 and 9, the first outer periphery trench 40 is formed in a tapered shape such that an opening width W2 gradually narrows toward the depth direction of the first outer periphery trench 40. The width W2 of the first outer periphery trench 40 is larger than the width W1 of the gate trench 15, and may be, for example, 0.5 μm or more and 1.0 μm or less at the opening end of the first outer periphery trench 40. The depth D2 of the first outer periphery trench 40 is larger than the depth D1 of the gate trench 15, and may be, for example, 1.0 μm or more and 1.4 μm or less.

[0047] 5, the first outer periphery trench 40 includes a first linear portion 401 extending along the first direction X, a second linear portion 402 extending along the second direction Y, and a corner portion 403 connecting the first linear portion 401 and the second linear portion 402. That is, in this embodiment, the first outer periphery trench 40 may be formed in a quadrangular ring shape in a plan view. The corner portion 403 may be an intersection of the first linear portion 401 and the second linear portion 402. The corner portion 403 has a curved shape that is convex toward the outside of the outer periphery region 63. For example, the corner portion 403 may be curved to have a predetermined radius of curvature R (for example, 15 μm or more and 50 μm or less).

[0048] The connection trench 41 is a recess that connects the gate trench 15 and the first outer periphery trench 40. The connection trench 41 is formed across the active region 64 and the outer periphery region 63 (see also FIGS. 11, 16, 18, and 20). In other words, the connection trench 41 crosses the boundary between the active region 64 and the outer periphery region 63 (for example, the gap region 19 between the first conductive film 51 and the second conductive film 52 as shown in FIG. 5). In this embodiment, the connection trench 41 extends from the annular outer gate trench 151 that forms the outer periphery of the collection of transistor cells 14 along the first direction X and the second direction Y, respectively, as shown in FIG. 5, and is connected to the first straight portion 401 and the second straight portion 402 of the first outer periphery trench 40.

[0049] The connection trench 41 may include a plurality of connection trenches 41 in the form of stripes parallel to each other, and each connection trench 41 may be connected to a different position of the first outer periphery trench 40. For example, referring to Fig. 6, the connection trench 41 may include a first connection trench 41A connected to the first outer periphery trench 40 at a first connection point 411, a second connection trench 41B connected to the first outer periphery trench 40 at a second connection point 412, and a third connection trench 41C connected to the first outer periphery trench 40 at a third connection point 413. The first to third connection points 411 to 413 may be intersections formed by the first to third connection trenches 14A to 14C and the first outer periphery trench 40 intersecting in a T-shape, respectively.

[0050] Here, the first outer periphery trench 40 includes a plurality of first outer periphery trenches 40. In this embodiment, the first outer periphery trench 40 may include an inner trench 404 and an outer trench 405. As shown in FIGS. 5 and 6, the inner trench 404 surrounds a group of transistor cells 14 formed in the active region 64 and is physically connected to the connection trench 41 (see also FIGS. 11, 16, 18, and 20). The connection trench 41 selectively communicates with the inner trench 404 out of the inner trench 404 and the outer trench 405, but does not communicate with the outer trench 405. The outer trench 405 is annular and surrounds the inner trench 404, and is formed outside the inner trench 404 at a distance from the inner trench 404, and is physically independent from the inner trench 404 (see also FIGS. 11, 16, 18, and 20).

[0051] The second outer periphery trench 42 is a recess that penetrates the second impurity region 122 and reaches the third impurity region 123. The second outer periphery trench 42 is formed outside the first outer periphery trench 40 and physically independent from the first outer periphery trench 40, and is formed in an annular shape surrounding the collection of transistor cells 14 formed in the active region 64 (see also FIGS. 11, 16, 18, and 20). In this embodiment, the second outer periphery trench 42 faces the first outer periphery trench 40 (in this embodiment, the outer trench 405) with the second impurity region 122 in between. Referring to FIG. 5, a plurality of second outer periphery trenches 42 are formed. The plurality of second outer periphery trenches 42 may be referred to as a second outer periphery trench group 42. In a planar view, some of the multiple second outer peripheral trenches 42 are covered (overlapping) by the second conductive film 52 (finger electrode portions 522), and the remainder are formed in the boundary between the second conductive film 52 and the third conductive film 53 (for example, in the gap region 20 between the second conductive film 52 and the third conductive film 53 as shown in FIG. 5 ) and may surround the second conductive film 52.

[0052] 8 and 9, the second outer periphery trench 42 is formed in a tapered shape in which an opening width W3 gradually narrows toward the depth direction of the second outer periphery trench 42. The width W3 of the second outer periphery trench 42 is greater than the width W1 of the gate trench 15 and smaller than the width W2 of the first outer periphery trench 40. The width W3 of the second outer periphery trench 42 may be, for example, 0.23 μm or more and 0.28 μm or less at the opening end of the second outer periphery trench 42. The depth D3 of the second outer periphery trench 42 is smaller than the depth D2 of the first outer periphery trench 40 and may be, for example, 0.8 μm or more and 1.2 μm or less.

[0053] With reference to FIG. 5, the second outer periphery trench 42 may be a quadrangular ring-shaped in plan view formed along the first outer periphery trench 40. The second outer periphery trench 42 includes a first straight portion 423 extending along the first direction X, a second straight portion 424 extending along the second direction Y, and a corner portion 425 connecting the first straight portion 423 and the second straight portion 424. That is, in this embodiment, the second outer periphery trench 42 may be formed in a quadrangular ring-shaped in plan view. The corner portion 425 may be an intersection portion between the first straight portion 423 and the second straight portion 424. The corner portion 425 has a curved shape that is convex toward the outside of the outer periphery region 63.

[0054] 8 and 9, in the outer periphery region 63, the gate insulating film 16 covers the inner surface of the first outer periphery trench 40 and the inner surface of the second outer periphery trench 42, and also covers the first main surface 12A of the semiconductor chip 12. Of the entire gate insulating film 16, the parts formed on the inner surface of the first outer periphery trench 40 and the inner surface of the second outer periphery trench 42 may be referred to as the second insulating film 162 and the third insulating film 163, respectively. That is, in this embodiment, the first insulating film 161 formed in the active region 64 and the second insulating film 162 and the third insulating film 163 formed in the outer periphery region 63 are integrally formed via the gate insulating film 16 on the first main surface 12A. Although not shown, the inner surface of the connection trench 41 is also covered with the gate insulating film 16.

[0055] The first buried electrode 43 is accommodated (embedded) in the first outer peripheral trench 40. The first buried electrode 43 may be made of the same material as the gate electrode 13. That is, the first buried electrode 43 is a conductive material containing polysilicon or the like. Since polysilicon has a melting point almost equal to that of single crystal silicon, by using polysilicon as the first buried electrode 43, there is no limitation on the process due to temperature in the process after the formation of the first buried electrode 43. The first buried electrode 43 faces the second impurity region 122 via the second insulating film 162. The first buried electrode 43 may have an upper surface 431 recessed toward the second main surface 12B side with respect to the first main surface 12A of the semiconductor chip 12, as shown in FIG. 8 and FIG. 9.

[0056] Referring to FIG. 6, the connection electrode 44 is accommodated (embedded) in the connection trench 41. The connection electrode 44 may be made of the same material as the gate electrode 13. That is, the connection electrode 44 is a material having conductivity including polysilicon or the like. Since polysilicon has a melting point almost equal to that of single crystal silicon, by using polysilicon as the connection electrode 44, there is no limitation on the process due to temperature in the process after the connection electrode 44 is formed. Although not shown in the figure, the connection electrode 44 faces the second impurity region 122 via the gate insulating film 16 formed on the inner surface of the connection trench 41, similar to the first buried electrode 43. The connection electrode 44 is formed integrally with the gate electrode 13 and the first buried electrode 43 in the inner trench 404, thereby electrically connecting the gate electrode 13 and the first buried electrode 43.

[0057] The second buried electrode 45 is accommodated (embedded) in the second outer peripheral trench 42. The second buried electrode 45 may be made of the same material as the gate electrode 13. That is, the second buried electrode 45 is a material having conductivity including polysilicon or the like. Since polysilicon has a melting point almost equal to that of single crystal silicon, by using polysilicon as the second buried electrode 45, there is no limitation on the process due to temperature in the process after the formation of the second buried electrode 45. The second buried electrode 45 faces the second impurity region 122 via the third insulating film 163. The second buried electrode 45 is electrically isolated from the gate electrode 13 and the first buried electrode 43, and is an electrically floating electrode in this embodiment. The second buried electrode 45 may have an upper surface 451 that is flush with the first main surface 12A of the semiconductor chip 12 or recessed toward the second main surface 12B side, as shown in FIG. 8 and FIG. 9.

[0058] The interlayer insulating film 17 is formed so as to cover the gate insulating film 16, the first buried electrode 43, the connection electrode 44, and the second buried electrode 45. The interlayer insulating film 17 insulates the first buried electrode 43, the connection electrode 44, and the second buried electrode 45 from the second conductive film 52. A contact hole 47 is formed in the interlayer insulating film 17. The contact hole 47 reaches an intermediate portion of the first buried electrode 43 in the depth direction of the first outer periphery trench 40. Therefore, the side surface of the contact hole 47 may include a first side surface 48 (upper side surface) made of an insulating region formed by the interlayer insulating film 17, and a second side surface 49 (lower side surface) made of a conductive region formed by the first buried electrode 43. In addition, a step 50 may be formed on the second side surface 49 of the contact hole 47 so that the width of the contact hole 47 narrows stepwise within the first buried electrode 43.

[0059] The contact hole 47 is formed in the first straight portion 401 and the second straight portion 402 of the first outer periphery trench 40. Here, the structure of the contact hole 47 formed in the second straight portion 402 will be described with reference to Fig. 6, but the following description can also be applied to the first straight portion 401. The contact hole 47 is formed in the second straight portion 402 at a position that avoids the connection points of the connection trench 41 (first to third connection points 411 to 413 in FIG. 6). Specifically, the contact hole 47 is formed in a portion of the first outer periphery trench 40 between the adjacent connection points 411 to 413. In the first to third connection points 411 to 413, the side surface of the first outer periphery trench 40 is replaced with the connection trench 41, so that a portion having a width W2' wider than the width W2 of the first outer periphery trench 40 is generated. The wider the trench width, the lower the embeddability of the embedded electrode (e.g., polysilicon), and there is a risk of a cavity-like defect called a void occurring after embedding. For example, in the example of FIG. 6, a defect may occur in the first embedded electrode 43 near the center of the first to third connection points 411 to 413. Therefore, by forming the contact hole 47 so as to avoid the first to third connection points 411 to 413, the second contact plug 46 can be connected to the first embedded electrode 43 in a good condition.

[0060] The second contact plug 46 is embedded in the contact hole 47 via a second barrier film 192. The second barrier film 192 suppresses diffusion of the material forming the second contact plug 46 into the interlayer insulating film 17. In this embodiment, the second contact plug 46 contains W (tungsten), and the second barrier film 192 may contain a material containing Ti (e.g., a single layer structure of Ti, or a laminated structure of Ti and TiN). The thickness of the second barrier film 192 is, for example, not less than 500 Å and not more than 800 Å.

[0061] The second barrier film 192 has one and the other surfaces formed following the inner surface of the contact hole 47 and the upper surface of the interlayer insulating film 17, and is directly conductive with the first embedded electrode 43. The second contact plug 46 is conductive with the first embedded electrode 43 via the second barrier film 192. The second contact plug 46 has an upper surface 461 that is recessed toward the first main surface 12A of the semiconductor chip 12 with respect to the upper surface of the interlayer insulating film 17.

[0062] The second conductive film 52 is formed on the interlayer insulating film 17. The second conductive film 52 may be called a gate electrode film based on the object of its electrical connection. The second conductive film 52 is electrically connected to the gate electrode 13 via the second contact plug 46, the second barrier film 192, the first buried electrode 43 in the inner trench 404, and the connection electrode 44. The second conductive film 52 is made of a material containing Al, for example, and is made of AlCu in this embodiment. The first buried electrode 43 in the outer trench 405 is not physically connected to the connection electrode 44. However, since the first buried electrode 43 in the outer trench 405 is electrically connected to the second conductive film 52 via the second contact plug 46, it is electrically connected to the gate electrode 13 via the second conductive film 52, the first buried electrode 43 in the inner trench 404, and the connection electrode 44. That is, both of the first buried electrodes 43 in the inner trench 404 and the outer trench 405 are held at the potential of the second conductive film 52 (gate potential).

[0063] As described above, the upper surface 461 of the second contact plug 46 is recessed with respect to the upper surface of the interlayer insulating film 17. Therefore, the upper surface of the second conductive film 52 may have a recess 520 formed at a position facing the upper surface 461 in the stacking direction of the second conductive film 52. [Relationship between the depth of the channel region 125 and the leakage current] Fig. 10 is a diagram for comparing the breakdown voltage of the semiconductor devices according to Samples 1 to 4. The horizontal axis of Fig. 10 indicates the magnitude of the reverse voltage (drain voltage VD) applied between the source and drain, with the absolute value of the reverse voltage increasing toward the right of the horizontal axis. The vertical axis of Fig. 10 indicates the magnitude of the leakage current (drain current ID) when a reverse voltage is applied between the source and drain, with the leakage current increasing toward the upper side of the vertical axis.

[0064] 10, a simulation was performed to verify how the leakage current changes depending on the depth of the channel region 125. Specifically, the leakage currents of samples 1 to 4, which have different depths of the channel region 125, were compared. The depth of the channel region 125 is, for example, a depth D from the first main surface 12A of the semiconductor chip 12 to the lower end of the bottom 126 of the channel region 125 in FIGS. 3 and 4. C1 (Fig. 3) and depth D C2 (FIG. 4). The depth of the channel region 125 can be controlled, for example, by changing the acceleration voltage of ion implantation when the second impurity region 122 is formed in the third impurity region 123 (the epitaxial layer 129 described later) by ion implantation and thermal diffusion. The resistivity of the third impurity region 123, which is the target of the ion implantation, is 3.5 Ω cm or more and 4.5 Ω cm or less here.

[0065] Sample 1 is configured to have a channel region 125 formed by injecting an n-type impurity (in this embodiment, P (phosphorus)) into the third impurity region 123 in two steps, at 180 keV and 70 keV, and thermally diffusing the impurity. Sample 2 is configured to have a channel region 125 formed by injecting an n-type impurity (in this embodiment, P (phosphorus)) into the third impurity region 123 in two steps, at 180 keV and 140 keV, and thermally diffusing the impurity. The channel region 125 of Samples 1 and 2 may have a bottom 126 located closer to the first main surface 12A than the lower end 152 of the gate trench 15, as shown in FIG. 3, for example.

[0066] Sample 3 is configured to have a channel region 125 formed by injecting an n-type impurity (in this embodiment, P (phosphorus)) into the third impurity region 123 in two steps of 280 keV and 140 keV and thermally diffusing the n-type impurity (in this embodiment, P (phosphorus)) into the third impurity region 123 in three steps of 280 keV, 140 keV, and 70 keV and thermally diffusing the n-type impurity (in this embodiment, P (phosphorus)). The channel region 125 of Samples 3 and 4 has a bottom 126 located closer to the second main surface 12B than the lower end 152 of the gate trench 15, as shown in FIG. 4, for example.

[0067] Comparing the leakage currents of samples 1 to 4 with reference to FIG. 10, it can be seen that the leakage currents of samples 1 and 2 are smaller than those of samples 3 and 4 over the entire application range of the reverse voltage. Therefore, from the viewpoint of reducing the leakage current, it is preferable that the depth position of the bottom 126 of the channel region 125 is closer to the first main surface 12A side (FIG. 3) than to the second main surface 12B side (FIG. 4) with respect to the lower end 152 of the gate trench 15. In this embodiment, in order to impart a withstand voltage of 100 V or more to the semiconductor device 1, the resistivity of the third impurity region 123 is 3.5 Ω·cm or more and 4.5 Ω·cm or less, which is relatively high. Therefore, the diffusion range of the implanted n-type impurity ions is likely to expand, and the channel region 125 is likely to protrude from the lower end 152 of the gate trench 15. Therefore, as in samples 1 and 2, the leakage current can be reduced by lowering the acceleration voltage during ion implantation. That is, a method for reducing the leakage current can be provided by lowering the acceleration voltage during ion implantation into the second impurity region 122. [Relationship between the structure of the peripheral region 63, leakage current, and device breakdown voltage] Next, the effect of the structure of the peripheral region 63 of the semiconductor element 3 on the leakage current and the device withstand voltage will be described. <Effect of Reducing Leakage Current by Forming the First Conductive Type Region 130 of the Second Impurity Region 122> In the following, based on Samples 5 to 11, it will be described how the leakage current is reduced by forming the first conductivity type region 130 in the second impurity region 122 of the peripheral region 63.

[0068] FIG. 11 is a schematic plan view of the semiconductor element 3 according to Samples 5 to 8. FIG. 12 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 5. FIG. 13 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 6. FIG. 14 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 7. FIG. 15 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 8. FIG. 16 is a schematic plan view of the semiconductor element 3 according to Sample 9. FIG. 17 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 9. FIG. 18 is a schematic plan view of the semiconductor element 3 according to Sample 10. FIG. 19 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 10. FIG. 20 is a schematic plan view of the semiconductor element 3 according to Sample 11. FIG. 21 is a schematic cross-sectional view of the semiconductor element 3 according to Sample 11. In FIG. 11, FIG. 16, FIG. 18, and FIG. 20, the structure above the first main surface 12A of the semiconductor chip 12 is omitted.

[0069] 11 to 21 selectively show configurations necessary for explaining the effect of reducing leakage current by forming the first conductivity type region 130 of the second impurity region 122, and for example, the gate insulating film 16 and the like are omitted. First, the structure of the peripheral region 63 of the semiconductor element 3 common to Samples 5 to 11 will be described with reference to FIGS.

[0070] As described above, the semiconductor chip 12 has a first main surface 12A and a second main surface 12B opposite to the first main surface 12A. In the peripheral region 63, a third impurity region 123 is formed in a surface layer portion on the first main surface 12A side of the semiconductor chip 12, and a second impurity region 122 is formed in a surface layer portion of the third impurity region 123. 11, 16, 18, and 20, the second impurity region 122 is a well region continuously formed from the active region 64 toward the peripheral region 63 over the entire surface layer of the third impurity region 123. Here, the continuous formation of the second impurity region 122 from the active region 64 to the peripheral region 63 means that an impurity region of the same conductivity type is continuous from the channel region 125 of the active region 64 along the lateral direction along the first main surface 12A of the semiconductor chip 12. For example, the second impurity region 122 may be formed over the entire first main surface 12A in a plan view, except for the portions where the first conductivity type region 130, the first peripheral trench 40, and the second peripheral trench 42 are formed.

[0071] The second impurity region 122 may include a first potential well region 132 and a floating region 133. The first potential well region 132 is formed in an inner region of the first outer periphery trench 40. The first potential well region 132 is electrically connected to the first conductive film 51 in the active region 64 via a third contact plug 134 formed in the interlayer insulating film 17. This makes the first potential well region 132 have the same potential as the first conductive film 51. In this embodiment, the first potential well region 132 may be a source potential well region fixed to the source potential.

[0072] The floating region 133 is formed in an outer region of the first outer periphery trench 40. The floating region 133 is physically separated from the first potential well region 132 by the first outer periphery trench 40. In addition, the floating region 133 is not connected to the first conductive film 51, the second conductive film 52, and the third conductive film 53, and is an electrically floating region.

[0073] The first conductivity type region 130 is a region in the peripheral region 63 where the second impurity region 122 is not selectively formed, and is exposed from the first main surface 12A of the semiconductor chip 12. The first conductivity type region 130 may be a region having a different conductivity type from the second impurity region 122. For example, the second impurity region 122 may be defined as a well region of the first conductivity type. In this embodiment, the second impurity region 122 is n-type, and the first conductivity type region 130 is p-type.

[0074] The second outer periphery trench 42 may include a first trench 421 and a second trench 422. The first trench 421 is a trench of the second outer periphery trench 42 adjacent to the first outer periphery trench 40. The first trench 421 is formed at a first outer periphery pitch P2 away from the first outer periphery trench 40 on the side of the first end faces 31A, 31B and second end faces 32A, 32B of the semiconductor chip 12. The first trench 421 faces the second conductive film 52 (finger electrode portions 522) with the interlayer insulating film 17 interposed therebetween.

[0075] The second trenches 422 are a plurality of trenches formed at a second periphery pitch P3 from the first trench 421 toward the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12. The second periphery pitch P3 may be the distance between the first trench 421 and the innermost second trench 422. The second trenches 422 are arranged at an equal third periphery pitch P4. Some of the second trenches 422 face the second conductive film 52 (finger electrode portion 522) with the interlayer insulating film 17 interposed therebetween. The rest of the second trenches 422 face the gap region 20 with the interlayer insulating film 17 interposed therebetween.

[0076] The third conductive film 53 is a peripheral electrode formed in the vicinity of the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12. The third conductive film 53 is connected to the semiconductor chip 12 via a peripheral contact plug 135 (peripheral contact portion) formed in the interlayer insulating film 17. The peripheral contact plug 135 is formed in a ring shape surrounding the second trench 422 in a plan view, as shown in FIGS. 11, 16, 18, and 20. In this embodiment, a plurality of peripheral contact plugs 135 are formed.

[0077] In this embodiment, the trench group 136 may be defined as a group including the first outer periphery trench 40 and the second outer periphery trench 42, which are annular trenches formed in the outer periphery region 63. The trench group 136 is shown in Figures 12 to 15, 17, 19, and 21 as including all of the first outer periphery trenches 40 and the second outer periphery trenches 42, but may selectively include some of the first outer periphery trenches 40 and the second outer periphery trenches 42 that are continuous along the first main surface 12A.

[0078] Next, a description will be given of the structures of the outer circumferential region 63 which differ from one another among Samples 5 to 8. First, Sample 5 will be described with reference to Figs. 11 , in sample 5, the first conductivity type region 130 is formed in a ring shape surrounding the active region 64. As a result, in the outer circumferential region 63, the second impurity region 122 is divided into a first portion 70 and a second portion 71.

[0079] The first-conductivity-type region 130 is formed by exposing a part of the third impurity region 123 from the first main surface 12A of the semiconductor chip 12. Therefore, the p-type impurity concentration of the first-conductivity-type region 130 may be the p-type impurity concentration of the third impurity region 123. The first-conductivity-type region 130 may be a first-conductivity-type (p-type in this embodiment) impurity region 80 having a concentration difference of one digit or less between the third impurity region 123 and the first-conductivity-type region 130 in the thickness direction of the semiconductor chip 12. In other words, the first-conductivity-type region 130 is an impurity region 80 consisting of a part of the third impurity region 123, but due to the influence of the manufacturing conditions of the semiconductor element 3, there may be a concentration difference of one digit or less between the second impurity region 122 and the third impurity region 123 on the second main surface 12B side. For example, if the p-type impurity concentration of the third impurity region 123 on the second main surface 12B side is 10 15 cm -3 whereas the p-type impurity concentration of the impurity region 80 is expressed as 1×10 16 cm -3 It may be expressed as:

[0080] The first-conductivity-type region 130 is formed across the region immediately below the gap region 20 and the region immediately below the third conductive film 53. The first-conductivity-type region 130 is formed in an annular shape along the first outer periphery trench 40 and the second outer periphery trench 42, and selectively includes some of the multiple second outer periphery trenches 42 on the inside and overlaps the second outer periphery trench 42. More specifically, the annular first-conductivity-type region 130 includes the same second outer periphery trench 42 on the inside over its entire circumference. In other words, the second outer periphery trench 42 included in the first-conductivity-type region 130 does not protrude from the first-conductivity-type region 130 in a plan view, and is completely contained within the first-conductivity-type region 130.

[0081] 11, the first portion 70 of the second impurity region 122 is formed in an island shape in an inner region surrounded by the first-conductivity type region 130, and the second portion 71 is formed in an annular shape in an outer region surrounding the first-conductivity type region 130. A boundary portion (first boundary portion 75) between the first portion 70 and the first-conductivity type region 130 is formed in a region immediately below the gap region 20. The first boundary portion 75 may be formed in the middle of a radial direction of a trench group 136 including trenches 40, 42 that spread in an annular shape with a gap toward the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12. On the other hand, a boundary portion (second boundary portion 77) between the first-conductivity type region 130 and the second portion 71 is formed in a region immediately below the third conductive film 53 and inside a connection position of the peripheral contact plug 135 in the semiconductor chip 12. The second portion 71 is formed to extend from the second boundary portion 77 to the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12. The second portion 71 of the second impurity region 122 is exposed to the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12.

[0082] Among the plurality of second outer periphery trenches 42, the plurality of second outer periphery trenches 42 arranged continuously toward the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12 and formed in the first conductivity type region 130 exposed from the first main surface 12A may be defined as a first trench group 73. On the other hand, among the plurality of second outer periphery trenches 42, the plurality of second outer periphery trenches 42 arranged continuously toward the first end faces 31A, 31B and the second end faces 32A, 32B and formed so as to penetrate the second impurity region 122 from the first main surface 12A and reach the third impurity region 123 may be defined as a second trench group 74. The first trench group 73 may be formed relatively outside, and the second trench group 74 may be formed relatively inside so as to be surrounded by the first trench group 73.

[0083] The side surfaces of the second outer periphery trenches 42 belonging to the first trench group 73 are formed by the first conductivity type region 130 (in sample 5, part of the third impurity region 123), and the side surfaces of the second outer periphery trenches 42 belonging to the second trench group 74 are formed by the second impurity region 122. Furthermore, the second outer periphery trench 42, which is located at the boundary between the first trench group 73 and the second trench group 74 and forms the first boundary portion 75 between the second impurity region 122 and the first conductivity type region 130, may be a boundary trench 76. One side of the boundary trench 76 in cross section (e.g., the inner side) is formed by the second impurity region 122, and the other side (e.g., the outer side) in cross section is formed by the first conductivity type region 130. The boundary trench 76 (first boundary portion 75) is located in the region directly below the gap region 20.

[0084] As shown in FIG. 11, since the first boundary 75 is the boundary trench 76 (second outer peripheral trench 42), the first boundary 75 is formed in a quadrangular ring shape in plan view having an arc-shaped corner 85, similar to the shape of the second outer peripheral trench 42. The second boundary 77 is also formed in a quadrangular ring shape in plan view having an arc-shaped corner 86. Therefore, the first conductivity type region 130 is formed in a quadrangular ring shape in plan view having arc-shaped corners 85, 86 at both the inner and outer periphery edges. By curving the corners of the first boundary 75 and the second boundary 77 in an arc-shaped manner, it is possible to suppress the electric field from concentrating at the corners of these boundaries 75, 77.

[0085] Furthermore, the width W4 of the first conductivity type region 130 sandwiched between the first portion 70 and the second portion 71 of the second impurity region 122 may be, for example, not less than 8 μm and not more than 15 μm (preferably, about 10 μm). To form the first conductivity type region 130, for example, an epitaxial layer 129 is grown on the semiconductor substrate 127, and then n-type impurities are injected into the semiconductor chip 12 through a mask corresponding to the pattern of the first conductivity type region 130, and thermal diffusion is performed to form the second impurity region 122. In the portion of the semiconductor chip 12 covered with the mask, n-type impurities are not injected, and the first conductivity type region 130 is formed in which the conductivity type of the epitaxial layer 129 (third impurity region 123) is maintained.

[0086] Next, sample 6 will be described with reference to FIGS. Sample 6 has a width W5 of the first conductivity type region 130 narrower than the width W4 of the first conductivity type region 130 of Sample 5. The width W5 may be, for example, not less than 3 μm and not more than 7 μm (preferably, about 6 μm). The other configurations of Sample 6 are similar to those of Sample 5. Note that the width W4 of the first conductivity type region 130 can be changed to width W5 by changing the pattern (width) of the mask used when forming the second impurity region 122.

[0087] Next, sample 7 will be described with reference to FIGS. Sample 7 has a width W6 of the first conductivity type region 130 that is wider than the width W4 of the first conductivity type region 130 of Sample 5. The width W6 may be, for example, not less than 8 μm and not more than 15 μm (preferably, about 13 μm). The other configurations of Sample 7 are similar to those of Sample 5. Note that the width W4 of the first conductivity type region 130 can be changed to width W6 by changing the pattern (width) of the mask used when forming the second impurity region 122.

[0088] Next, sample 8 will be described with reference to FIGS. In the sample 8, the first conductivity type region 130 is formed by a high concentration impurity region 78 having a higher impurity concentration than the third impurity region 123. For example, when the p-type impurity concentration of the third impurity region 123 is 1×10 15 cm -3 More than 1×10 18 cm -3 whereas the p-type impurity concentration of the high concentration impurity region 78 is 1×10 18 cm -3 More than 1×10 20 cm -3 The p-type impurity concentration of the high concentration impurity region 78 may be the same as the p-type impurity concentration of the semiconductor substrate 127 and the first impurity region 121.

[0089] The high-concentration impurity region 78 is selectively formed in a surface layer portion of the third impurity region 123. Furthermore, as shown in FIG. 15, the depth of the high-concentration impurity region 78 may be deeper than the second outer periphery trench 42. As a result, the high-concentration impurity region 78 may have a bottom 79 that protrudes toward the second main surface 12B side further than the lower end of the second outer periphery trench 42. The other configurations of Sample 8 are similar to those of Sample 5.

[0090] To form the high-concentration impurity region 78, for example, after growing the epitaxial layer 129 on the semiconductor substrate 127, n-type impurities are injected into the entire surface of the first main surface 12A of the semiconductor chip 12 without using a mask, and the second impurity region 122 is formed by thermal diffusion. Next, p-type impurities are injected into the first main surface 12A of the semiconductor chip 12 through a mask having openings corresponding to the pattern of the high-concentration impurity region 78, and the high-concentration impurity region 78 is formed by thermal diffusion.

[0091] Next, Sample 9 will be described with reference to FIGS. Sample 9 has a width W7 of the first-conductivity type region 130 that is wider than the width W4 of the first-conductivity type region 130 of Sample 5. The width W7 may be, for example, 20 μm or more and 27 μm or less (preferably, about 27 μm). More specifically, in Sample 9, the first trench 421 forms a boundary trench 76. Therefore, the second impurity region 122 is divided into an inner first portion 70 and an outer second portion 71 with the first trench 421 as a boundary. The position of the second boundary portion 77 may be the same as that of Sample 5. As a result, all of the second trenches 422 (excluding the boundary trench 76) may be included in the first trench group 73 formed in the first-conductivity type region 130. The other configurations of Sample 9 are the same as those of Sample 5. Note that, in order to change the width W4 of the first-conductivity type region 130 to the width W7, the pattern (width) of the mask used when forming the second impurity region 122 may be changed.

[0092] Next, the sample 10 will be described with reference to FIGS. Sample 10 has a width W8 of the first conductivity type region 130 that is narrower than the width W4 of the first conductivity type region 130 of sample 5. Width W8 may be, for example, not less than 3 μm and not more than 7 μm (preferably, about 5 μm). More specifically, in sample 10, the outermost trench of the second outer periphery trench 42 forms the boundary trench 76. Thus, the entire second outer periphery trench 42 is formed penetrating the second impurity region 122.

[0093] In sample 10, second boundary 77 is formed in a region immediately below third conductive film 53 and outside the connection position of peripheral contact plug 135 in semiconductor chip 12. As a result, first conductivity type region 130 includes peripheral contact plug 135 inside and is formed facing third conductive film 53 in the thickness direction of semiconductor chip 12. Other configurations of sample 10 are similar to those of sample 5. Note that width W4 of first conductivity type region 130 can be changed to width W8 by changing the pattern (width) of the mask used when forming second impurity region 122.

[0094] Next, sample 11 will be described with reference to FIGS. In sample 11, the second portion 71 of the second impurity region 122 of sample 5 is omitted. Therefore, the first conductivity type region 130 is formed so as to extend from the boundary trench 76 to the first end faces 31A, 31B and the second end faces 32A, 32B of the semiconductor chip 12. As a result, the first conductivity type region 130 includes the peripheral contact plug 135 therein, and is formed facing the third conductive film 53 in the thickness direction of the semiconductor chip 12. The other configurations of sample 11 are similar to those of sample 5.

[0095] Then, a high temperature reverse bias test (HTRB: High Temperature Reverse Bias Test) was performed on Samples 5 to 11 and Sample 12 (see FIG. 22) in which the first conductivity type region 130 was not formed. In the HTRB test, a voltage of −100V was continuously applied to the first conductive film 51 (front surface source electrode) with respect to the fourth conductive film 54 (rear surface drain electrode) in an environment of 150° C. for 1000 hours. Meanwhile, the current-voltage characteristics at room temperature were measured (initial characteristics). Then, by comparing the initial characteristics with the characteristics 250 hours or more after the start of the HTRB test, it was confirmed whether the leakage current was reduced by forming the first conductivity type region 130.

[0096] As a result, the leakage current was sufficiently suppressed even after stress was applied for 250 hours or more in Samples 5 to 11. In particular, in Samples 5 and 7, in which the widths W4, W6 of the first conductivity type region 130 were 8 μm or more and 15 μm or less, the leakage current value hardly changed from the initial leakage current before stress was applied. In this regard, the current path when a reverse voltage under the same conditions as in the HTRB test was applied was verified by simulation for each of Samples 5 to 12. As a result, it was revealed that in Sample 12 in which the first conductivity type region 130 was not formed, a part of the current flowing in the thickness direction of the semiconductor chip 12 leaked along the first main surface 12A to the third conductive film 53 (peripheral electrode). In contrast, in Samples 5 to 11, such leakage to the peripheral portion was not confirmed. In other words, it is considered that the leakage component from the periphery of the semiconductor chip 12 can be suppressed by selectively removing the second impurity region 122 in the peripheral region 63.

[0097] From the above, it has become clear that the semiconductor device 1 according to the embodiment of the present disclosure provides a structure capable of reducing the reverse leakage current. <Improvement of Device Withstand Voltage by Forming the First Conduction Type Region 130 of the Second Impurity Region 122> Next, a simulation was performed to confirm whether the formation of the first conductivity type region 130 improved the device breakdown voltage. Fig. 23 shows the results. The horizontal axis of Fig. 23 indicates the magnitude of the reverse voltage (drain voltage VD) applied between the source and drain, with the absolute value of the reverse voltage increasing toward the right of the horizontal axis. The vertical axis of Fig. 23 indicates the magnitude of the leakage current (drain current ID) when a reverse voltage is applied between the source and drain, with the leakage current increasing toward the upper side of the vertical axis.

[0098] 23, Samples 5 to 11 all broke down at voltages V2 and V3 higher than the breakdown voltage V1 of Sample 12. In particular, Samples 5 to 8 and Samples 10 to 11, except for Sample 9 in which the width W7 of the first conductivity type region 130 in FIG. 17 is relatively wide (e.g., 20 μm or more and 27 μm or less), broke down at a higher voltage V3. In other words, it became clear that while the formation of the first conductivity type region 130 can improve the device withstand voltage, the device withstand voltage can be further improved by not making the width of the first conductivity type region 130 too wide.

[0099] In this regard, the extension of the depletion layer 83 in the peripheral region 63 of Samples 5 to 11 was verified by simulation. As a result, in Sample 9, the first conductivity type region 130 from which the second impurity region 122 has been removed continues from the first trench 421 to the region immediately below the third conductive film 53, and therefore, for example, in the vicinity of the portion indicated by the arrow 84 in Fig. 27, the effect of extending the depletion layer 83 outward was weakened. On the other hand, as shown in Figs. 24 to 26 and Figs. 28 and 29, in Samples 5 to 8 and Samples 10 to 11, the depletion layer 83 extended sufficiently outward even in the vicinity of the portion indicated by the arrow 84. It is considered that this difference in the extension of the depletion layer 83 influenced the effect of improving the device breakdown voltage.

[0100] From the above, it has become clear that the semiconductor device 1 according to the embodiment of the present disclosure provides a structure capable of improving the device withstand voltage. <Improvement of Device Withstand Voltage by Changing the Pitch of the Peripheral Trenches 40, 42> In the following, based on Samples 13 to 16, it will be described how the device breakdown voltage is improved by changing the number of first periphery trenches 40 and the periphery pitches P2, P3, and P4.

[0101] Fig. 30 is a schematic cross-sectional view of the semiconductor device 3 of sample 13. Fig. 31 is a schematic cross-sectional view of the semiconductor device 3 of sample 13. Fig. 32 is a schematic cross-sectional view of the semiconductor device 3 of sample 14. Fig. 33 is a schematic cross-sectional view of the semiconductor device 3 of sample 15. The structures of Samples 13 to 16 are basically the same as that of Sample 5, but differ from Sample 5 in the following respects.

[0102] First, Sample 13 differs from Sample 5, which has two first outer periphery trenches 40, in that Sample 13 has one first outer periphery trench 40. In Sample 13, the outer trench 405 of Sample 5 is omitted. Sample 13 has the same structure as Sample 5. Sample 14 differs from Sample 5, which has two first outer periphery trenches 40, in that Sample 14 has three first outer periphery trenches 40. In Sample 14, a first outer periphery trench 40 is added further inside (toward the active region 64) the inner trench 404 of Sample 5, and the added first outer periphery trench 40 is designated as the inner trench 404. On the other hand, the existing first outer periphery trench 40 of Sample 5 is designated as the outer trench 405.

[0103] Sample 15 differs from Sample 5, which has two first outer periphery trenches 40, in that Sample 15 has four first outer periphery trenches 40. In Sample 14, two first outer periphery trenches 40 are added further inside (toward the active region 64) the inner trench 404 of Sample 5, and the inner trench of the added first outer periphery trenches 40 is defined as inner trench 404. On the other hand, the outer trench of the added first outer periphery trenches 40 and the existing first outer periphery trench 40 of Sample 5 are defined as outer trench 405.

[0104] Next, a simulation was performed to verify how the breakdown voltage varies with the change in the circumferential pitches P2, P3, P4 of Samples 13 to 16, using the circumferential pitches P2, P3, P4 as variables. Figures 34 to 36 show the results. Fig. 34 is a diagram showing the relationship between the first periphery pitch P2 and the device breakdown voltage, and shows the verification results of Samples 13 to 15. The horizontal axis of Fig. 34 represents the magnitude of the first periphery pitch P2. The vertical axis of Fig. 34 represents the magnitude of the breakdown voltage (BVDSS) when a reverse voltage is applied between the source and drain, with the breakdown voltage (BVDSS) increasing toward the upper side of the vertical axis.

[0105] In the verification related to the first outer periphery pitch P2, 1.28 μm, 2.28 μm, 3.28 μm, 4.28 μm, 5.28 μm, and 6.28 μm were adopted as the values ​​of the first outer periphery pitch P2, and the breakdown voltage was confirmed for each first outer periphery pitch P2. Note that since the pitch P1 of the gate trenches 15 is set to 1 μm, the values ​​of the first outer periphery pitch P2 may be defined as 1.28 times, 2.28 times, 3.28 times, 4.28 times, 5.28 times, and 6.28 times the pitch P1 (cell pitch) of the gate trenches 15, respectively.

[0106] 34, comparing the breakdown voltages of Samples 13 to 15, a relatively high breakdown voltage was achieved when the first outer periphery pitch P2 was 2.28 μm (2.28 times the cell pitch), 3.28 μm (3.28 times the cell pitch), and 4.28 μm (4.28 times the cell pitch) in all of Samples 13 to 15. From the above, it has become clear that the device withstand voltage can be particularly improved when the first outer periphery pitch P2 is 2.0 μm or more and 4.0 μm or less, or when the first outer periphery pitch P2 is 2 times or more and 4 times or less the pitch P1 of the gate trenches 15.

[0107] In this regard, the breakdown location was confirmed by simulation based on the impact ionization rate in the semiconductor chip 12. As a result, as in the case where the first outer periphery pitch P2 was 1.28 μm, when the distance between the first outer periphery trench 40 in which the first buried electrode 43 fixed to the gate potential was buried and the second outer periphery trench 42 in which the electrically floating second buried electrode 45 was buried was short, breakdown selectively occurred near the first outer periphery trench 40. Also, as in the case where the first outer periphery pitch P2 was 6.28 μm, when the distance between the first outer periphery trench 40 in which the first buried electrode 43 fixed to the gate potential was buried and the second outer periphery trench 42 in which the electrically floating second buried electrode 45 was buried was long, breakdown selectively occurred near the second outer periphery trench 42.

[0108] In contrast, when the first periphery pitch P2 was 3.28 μm, breakdown occurred in both the first periphery trench 40 in which the first buried electrode 43 fixed to the gate potential was buried, and the second periphery trench 42 in which the electrically floating second buried electrode 45 was buried. In other words, it can be said that from the viewpoint of improving the device withstand voltage, it is preferable for the first periphery pitch P2 to be neither too narrow nor too wide, as this allows the electric field to be distributed to the first periphery trench 40 and the second periphery trench 42.

[0109] Fig. 35 is a diagram showing the relationship between the second periphery pitch P3 and the device breakdown voltage, and shows the verification results of Samples 13 to 16. The horizontal axis of Fig. 35 represents the magnitude of the second periphery pitch P3. The vertical axis of Fig. 35 represents the magnitude of the breakdown voltage (BVDSS) when a reverse voltage is applied between the source and drain, with the breakdown voltage (BVDSS) increasing toward the upper side of the vertical axis.

[0110] In the verification related to the second outer periphery pitch P3, the value of the first outer periphery pitch P2 was fixed at 3.28 μm, and the values ​​of the second outer periphery pitch P3 were 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm, and the breakdown voltage was confirmed for each second outer periphery pitch P3. Note that since the pitch P1 of the gate trenches 15 is set to 1 μm, the values ​​of the second outer periphery pitch P3 may be defined as 1, 2, 3, 4, and 5 times the pitch P1 (cell pitch) of the gate trenches 15, respectively.

[0111] Referring to FIG. 35, when the breakdown voltages of Samples 13 to 16 are compared, in all of Samples 13 to 16, a relatively high breakdown voltage was achieved when the second periphery pitch P3 was 2 μm (twice the cell pitch), 3 μm (three times the cell pitch), 4 μm (four times the cell pitch), and 5 μm (five times the cell pitch). In addition, when the second periphery pitch P3 was in the range of 2 μm to 5 μm, the breakdown voltage was not significantly affected even if the second periphery pitch P3 was wider. From the above, it was revealed that the device breakdown voltage can be particularly improved when the second periphery pitch P3 is 2.0 μm or more and 6.0 μm or less, or when the second periphery pitch P3 is 2 times or more and 6 times or less the pitch P1 of the gate trenches 15. In addition, in consideration of the viewpoint of recommending the miniaturization of the semiconductor element 3, it can be said that it is preferable to keep the second periphery pitch P3 at the same level as or smaller than the first periphery pitch P2.

[0112] Fig. 36 is a diagram showing the relationship between the third periphery pitch P4 and the device breakdown voltage, and shows the verification results of Samples 13 to 16. The horizontal axis of Fig. 36 represents the magnitude of the third periphery pitch P4. The vertical axis of Fig. 36 represents the magnitude of the breakdown voltage (BVDSS) when a reverse voltage is applied between the source and drain, with the breakdown voltage (BVDSS) increasing toward the upper side of the vertical axis.

[0113] In the verification related to the third outer periphery pitch P4, the value of the first outer periphery pitch P2 was fixed at 3.28 μm and the value of the second outer periphery pitch P3 was fixed at 3 μm, and the values ​​of the third outer periphery pitch P4 were adopted as 1 μm, 2 μm, 3 μm, 4 μm and 5 μm, and the breakdown voltage was confirmed for each third outer periphery pitch P4. Note that since the pitch P1 of the gate trenches 15 is set to 1 μm, the values ​​of the third outer periphery pitch P4 may be defined as 1, 2, 3, 4 and 5 times the pitch P1 (cell pitch) of the gate trenches 15, respectively.

[0114] 36, when the breakdown voltages of Samples 13 to 16 are compared, there is almost no variation in the breakdown voltage when the third periphery pitch P4 is in the range of 2 μm to 5 μm in all of Samples 13 to 16. From the above, in consideration of the recommendation to reduce the size of the semiconductor element 3, it can be said that it is preferable to keep the third periphery pitch P4 at the same level as the pitch P1 of the gate trenches 15 (about 1 μm in this embodiment). This makes it clear that it is possible to achieve both the reduction in size of the semiconductor element 3 and an improvement in the device breakdown voltage.

[0115] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms. For example, in the verification results based on Samples 1 to 11, the magnitudes of the circumferential pitches P2, P3, and P4 do not particularly contribute to the effect of reducing the leakage current. Therefore, as shown in Fig. 37, even if the first circumferential pitch P2, the second circumferential pitch P3, and the third circumferential pitch P4 are equal to one another, the leakage current can be sufficiently reduced as long as the first conductivity type region 130 is formed.

[0116] Also, for example, a configuration may be adopted in which the conductivity type of each semiconductor portion of the semiconductor device 1 is inverted. For example, in the semiconductor device 1, a p-type portion may be n-type, and an n-type portion may be p-type. In the above embodiment, the MISFET is taken as an example of the element structure of the semiconductor device 1, but the element structure of the semiconductor device 1 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0117] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects. The following characteristics can be extracted from the description of this specification and the drawings. [Appendix 1-1] a semiconductor chip (12) having a first main surface (12A), a second main surface (12B) opposite to the first main surface (12A), and end surfaces (31A, 31B, 32A, 32B) surrounding the first main surface (12A), in which an active area (64) and an outer peripheral area (63) around the active area (64) are defined on the first main surface (12A); a first electrode (51) formed on the first main surface (12A) of the semiconductor chip (12); a second electrode (54) formed on the second main surface (12B) of the semiconductor chip (12); a first region (123, 129) of a first conductivity type formed in the semiconductor chip (12) and electrically connected to the second electrode (54); a vertical semiconductor element structure (14) formed in the active region (64) and passing a current between the first electrode (51) and the second electrode (54); a peripheral electrode (53) formed on the first main surface (12A) of the semiconductor chip (12) and physically separated from the first electrode (51) and connected to the semiconductor chip (12) in the peripheral region (63); a well region (122) of a second conductivity type that is continuously formed from the active region (64) to the peripheral region (63) in a surface layer portion of the first region (123, 129) and that constitutes at least a part of the semiconductor element structure (14); The semiconductor device (1), wherein the peripheral region (63) includes a first conductivity type region (130) in which the well region (122) is not selectively formed. [Appendix 1-2] a trench group (136) including a plurality of annular trenches (40, 42) formed in the peripheral region (63) on the inner side of the peripheral electrode (53) and surrounding the active region (64); The semiconductor device (1) described in Appendix 1-1, wherein the first conductivity type region (130) includes some of the plurality of annular trenches (40, 42) therein and is formed overlapping the trench group (136). [Appendix 1-3] a peripheral contact portion (135) that connects the peripheral electrode (53) and the semiconductor chip (12); The semiconductor device (1) described in Appendix 1-1 or Appendix 1-2, wherein the first conductivity type region (130) includes the peripheral contact portion (135) therein and is formed opposite the peripheral electrode (53) in the thickness direction of the semiconductor chip (12). [Appendix 1-4] the first conductive type region (130) is formed to reach the end faces (31A, 31B, 32A, 32B) of the semiconductor chip (12); The semiconductor device (1) according to appendix 1-3, wherein the well region (122) is formed in an inner region surrounded by the first conductivity type region (130). [Appendix 1-5] The first conductive region (130) is formed in a ring shape surrounding the active region (64), The semiconductor device (1) according to any one of Appendices 1-1 to 1-3, wherein the well region (122) is divided into a first portion (70) formed in an inner region surrounded by the first conductivity type region (130) and a second portion (71) formed in an annular outer region surrounding the first conductivity type region (130). [Appendix 1-6] The semiconductor device (1) according to appendix 1-5, wherein a width (W4, W6) of the first conductivity type region (130) sandwiched between the first portion (70) and the second portion (71) is not less than 8 μm and not more than 15 μm. [Appendix 1-7] The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the first conductivity type region (130) is formed by exposing a portion (80) of the first region (123, 129) from the first main surface (12A) of the semiconductor chip (12). [Appendix 1-8] The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the first conductivity type region (130) includes a second region (78) selectively formed in a surface layer portion of the first region (123, 129) and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first region (123, 129). [Appendix 1-9] The semiconductor device structure (14) includes a cell trench (15), a control electrode (13) embedded in the cell trench (15), and a channel region (125) formed on a side of the cell trench (15) and constituted by the well region (122); a first annular trench (40) formed in the outer peripheral region (63) on the inner side of the outer peripheral electrode (53); a first buried electrode (43) buried in the first outer periphery trench (40) and electrically connected to the control electrode (13); a second peripheral trench group (42) including a plurality of annular second peripheral trenches (42) formed in the peripheral region (63) outside the first peripheral trench (40) and inside the peripheral electrode (53), the second peripheral trench group (42) being physically separated from the first peripheral trench (40); a second buried electrode (45) buried in the second outer periphery trench (42) and electrically isolated from the first buried electrode (43); The semiconductor device (1) according to Appendix 1-1, wherein the well region (122) is continuous in a lateral direction along the first main surface (12A) from the channel region (125), except for the portions where the first outer periphery trench (40) and the second outer periphery trench group (42) are formed, and the first conductivity type region (130). [Appendix 1-10] the first conductive type region (130) is formed to selectively include some of the second peripheral trench group (42) inside and overlap the second peripheral trench group (42); The semiconductor device (1) described in Appendix 1-9, wherein the first outer peripheral trench (40) is formed so as to penetrate the well region (122) in the thickness direction of the semiconductor chip (12) and reach the first region (123). [Appendix 1-11] a peripheral contact portion (135) that connects the peripheral electrode (53) and the semiconductor chip (12); The semiconductor device (1) described in Appendix 1-9 or Appendix 1-10, wherein the first conductivity type region (130) includes the peripheral contact portion (135) therein and is formed opposite the peripheral electrode (53) in the thickness direction of the semiconductor chip (12). [Appendix 1-12] the second outer periphery trench group (42) includes a first trench (421) formed at a first outer periphery pitch (P2) from the first outer periphery trench (40) toward the end face (31A, 31B, 32A, 32B), and a plurality of second trenches (422) formed at a second outer periphery pitch (P3) from the first trench (421) toward the end face (31A, 31B, 32A, 32B) and arranged at a third outer periphery pitch (P4) narrower than the first outer periphery pitch (P2) and the second outer periphery pitch (P3); The semiconductor device (1) according to any one of Appendices 1-9 to 1-11, wherein the plurality of second trenches (422) include a boundary trench (76) forming a first boundary portion (75) between the well region (122) and the first conductivity type region (130). [Appendix 1-13] The semiconductor device (1) described in Appendix 1-12, wherein the well region (122) includes a first portion (70) formed in an inner region surrounded by the boundary trench (76), and a second portion (71) formed in an annular outer region having a second boundary portion (77) with the first conductivity type region (130) in a region directly below the peripheral electrode (53) and on the end face (31A, 31B, 32A, 32B) side of the second boundary portion (77). [Appendix 1-14] The semiconductor device (1) according to appendix 1-13, wherein a width (W4, W6) of the first conductivity type region (130) sandwiched between the first portion (70) and the second portion (71) is not less than 8 μm and not more than 15 μm. [Appendix 1-15] the first conductivity type region (130) is formed to extend from the boundary trench (76) to the end faces (31A, 31B, 32A, 32B) of the semiconductor chip (12); The semiconductor device (1) according to any one of claims 1 to 12, wherein the well region (122) is formed in an inner region surrounded by the boundary trench (76). [Appendix 1-16] The semiconductor device (1) according to any one of Appendices 1-9 to 1-15, wherein the well region (122) includes a first potential well region (132) formed in an inner region surrounded by the first outer periphery trench (40) and electrically connected to the first electrode (51), and an electrically floating floating region (133) formed in an outer region of the first outer periphery trench (40). [Appendix 1-17] The semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-16, having a breakdown voltage of 100V or more. [Appendix 1-18] The semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-17, wherein the first region (123, 129) has a resistivity of 3.5 Ω·cm or more and 4.5 Ω·cm or less. [Appendix 1-19] The semiconductor chip (12) includes a semiconductor substrate (127) of a first conductivity type having a first impurity concentration, and an epitaxial layer (129) of the first conductivity type formed on the semiconductor substrate (127), having a second impurity concentration lower than the first impurity concentration, and constituting the first region (123); The semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-18, wherein the epitaxial layer (129) has a thickness of 7 μm or more and 15 μm or less. [Appendix 1-20] The first impurity concentration is 1×10 18cm -3 More than 1×10 20 cm -3 is as follows: The second impurity concentration is 1×10 15 cm -3 More than 1×10 19 cm -3 A semiconductor device (1) according to appendix 1-19, which is as follows: [Appendix 1-21] the channel region (125) includes a side portion (124) that forms a side surface of the cell trench (15), and a convex bottom portion (126) that protrudes from a lower end of the side portion (124) toward the second main surface (12B) so as to be away from the side surface of the cell trench (15); The semiconductor device (1) according to any one of Supplementary Notes 1-9 to 1-16, wherein a bottom of the channel region (125) is located closer to the first main surface (12A) than a lower end (152) of the cell trench (15). [Appendix 1-22] The semiconductor device (1) according to any one of Supplementary Notes 1-9 to 1-16, wherein the first outer periphery trench (40) is formed with a width (W2) larger than that of the cell trench (15). [Appendix 1-23] The semiconductor device (1) according to appendix 1-22, wherein the first outer periphery trench (40) has a depth (D2) greater than that of the cell trench (15). [Appendix 1-24] The semiconductor element structure (14) includes a source region (121) of a first conductivity type, the channel region (125) of a second conductivity type, and a drift region (123) of a first conductivity type, which are formed in this order from the first main surface (12A) of the semiconductor chip (12) in a depth direction of the cell trench (15), The semiconductor device (1) according to any one of Supplementary Notes 1-9 to 1-16, wherein the control electrode (13) includes a gate electrode (13) that forms a channel in the channel region (125). [Appendix 1-25] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-24, wherein the semiconductor chip (12) includes a silicon chip. [Appendix 1-26] The cell trenches (15) are arranged at a predetermined cell pitch (P1) in the active region (64), The semiconductor device (1) according to any one of Appendix 1-12 to Appendix 1-15, wherein the first outer periphery pitch (P2) is equal to or greater than two times and equal to or less than four times the cell pitch (P1). [Appendix 1-27] The semiconductor device (1) according to appendix 1-26, wherein the second outer periphery pitch (P3) is greater than or equal to two times and less than or equal to six times the cell pitch (P1). [Appendix 1-28] The semiconductor device (1) according to Appendix 1-26 or Appendix 1-27, wherein the second circumferential pitch (P3) is smaller than the first circumferential pitch (P2). [Appendix 1-29] The semiconductor device (1) according to any one of Supplementary Notes 1-26 to 1-28, wherein the third outer periphery pitch (P4) is equal to the cell pitch (P1). [Appendix 1-30] The cell pitch (P1) is 0.8 μm or more and 1.2 μm or less, The semiconductor device (1) according to any one of Supplementary Notes 1-26 to 1-29, wherein the first outer circumferential pitch (P2) is equal to or greater than 2.0 μm and equal to or less than 4.0 μm. [Appendix 1-31] The cell pitch (P1) is 0.8 μm or more and 1.2 μm or less, The first peripheral pitch (P2) is 2.0 μm or more and 4.0 μm or less, The semiconductor device (1) according to any one of Appendix 1-26 to Appendix 1-29, wherein the second outer circumferential pitch (P3) is equal to or greater than 2.0 μm and equal to or less than 6.0 μm. [Appendix 2-1] a semiconductor chip (12) having a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A), and an active area (64) and an outer peripheral area (63) around the active area (64) are defined on the first main surface (12A); a first electrode (51) formed on the first main surface (12A) of the semiconductor chip (12); a second electrode (54) formed on the second main surface (12B) of the semiconductor chip (12); a first region (123, 129) of a first conductivity type formed in the semiconductor chip (12) and electrically connected to a second electrode (54); a semiconductor element structure (14) including cell trenches (15) formed in the active region (64) and arranged at a predetermined cell pitch (P1), a control electrode (13) embedded in the cell trenches (15), and a second conductivity type channel region (125) formed on a side of the cell trenches (15), and for allowing a current to flow between the first electrode (51) and the second electrode (54); a first annular peripheral trench (40) formed in the peripheral region (63); a first buried electrode (43) buried in the first outer periphery trench (40) and electrically connected to the control electrode (13); a second peripheral trench group (42) including a plurality of annular second peripheral trenches (42) formed in the peripheral region (63) outside the first peripheral trench (40) and physically separated from the first peripheral trench (40); a second buried electrode (45) buried in the second outer periphery trench (42) and electrically isolated from the first buried electrode (43); A semiconductor device (1), wherein a first perimeter pitch (P2) between the first perimeter trench (40) and the second perimeter trench group (42) is at least two times and at most four times the cell pitch (P1). [Appendix 2-2] The second peripheral trench group (42) includes a first trench (421) formed outwardly from the first peripheral trench (40) at the first peripheral pitch (P2) and a second trench (422) formed outwardly from the first trench (421) at a second peripheral pitch (P3), The semiconductor device (1) according to appendix 2-1, wherein the second outer periphery pitch (P3) is equal to or greater than two times and equal to or less than six times the cell pitch (P1). [Appendix 2-3] The semiconductor device (1) according to appendix 2-2, wherein the second circumferential pitch (P3) is smaller than the first circumferential pitch (P2). [Appendix 2-4] the second periphery trench group (42) includes a plurality of the second trenches (422) arranged at a third periphery pitch (P4) narrower than the first periphery pitch (P2) and the second periphery pitch (P3), The semiconductor device (1) according to appendix 2-2 or appendix 2-3, wherein the third outer periphery pitch (P4) is equal to the cell pitch (P1). [Appendix 2-5] The cell pitch (P1) is 0.8 μm or more and 1.2 μm or less, The semiconductor device (1) according to any one of Appendix 2-1 to Appendix 2-4, wherein the first outer circumferential pitch (P2) is equal to or greater than 2.0 μm and equal to or less than 4.0 μm. [Appendix 2-6] The cell pitch (P1) is 0.8 μm or more and 1.2 μm or less, The first peripheral pitch (P2) is 2.0 μm or more and 4.0 μm or less, The semiconductor device (1) according to any one of Appendix 2-2 to Appendix 2-4, wherein the second outer circumferential pitch (P3) is equal to or greater than 2.0 μm and equal to or less than 6.0 μm. [Appendix 2-7] a semiconductor chip (12) having a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A), and an active area (64) and an outer peripheral area (63) around the active area (64) are defined on the first main surface (12A); a first electrode (51) formed on the first main surface (12A) of the semiconductor chip (12); a second electrode (54) formed on the second main surface (12B) of the semiconductor chip (12); a first region (123, 129) of a first conductivity type formed in the semiconductor chip (12) and electrically connected to a second electrode (54); a semiconductor element structure (14) including a cell trench (15) formed in the active region (64), a control electrode (13) embedded in the cell trench (15), and a second conductivity type channel region (125) formed on a side of the cell trench (15), and allowing a current to flow between the first electrode (51) and the second electrode (54); a first annular peripheral trench (40) formed in the peripheral region (63); a first buried electrode (43) buried in the first outer periphery trench (40) and electrically connected to the control electrode (13); a second peripheral trench group (42) including a plurality of annular second peripheral trenches (42) formed in the peripheral region (63) outside the first peripheral trench (40) and physically separated from the first peripheral trench (40); a second buried electrode (45) buried in the second outer periphery trench (42) and electrically isolated from the first buried electrode (43); A semiconductor device (1), wherein a first perimeter pitch (P2) between the first perimeter trench (40) and the second perimeter trench group (42) is not less than 2.0 μm and not more than 4.0 μm. [Appendix 2-8] The second peripheral trench group (42) includes a first trench (421) formed outwardly from the first peripheral trench (40) at the first peripheral pitch (P2) and a second trench (422) formed outwardly from the first trench (421) at a second peripheral pitch (P3), The semiconductor device (1) according to appendix 2-7, wherein the second outer circumferential pitch (P3) is equal to or greater than 2.0 μm and equal to or less than 6.0 μm. [Appendix 2-9] The semiconductor device (1) according to any one of Appendix 2-1 to Appendix 2-8, wherein the first outer peripheral trench (40) includes an inner trench (404) surrounding the active region (64) and an outer trench (405) surrounding the inner trench (404). [Appendix 2-10] a connection electrode (44) embedded in the semiconductor chip (12) and connecting the first embedded electrode (43) in the inner trench (404) and the control electrode (13); a third electrode (52) formed on the first main surface (12A) of the semiconductor chip (12) and connected to the first buried electrode (43) in the inner trench (404) and the first buried electrode (43) in the outer trench (405); The semiconductor device (1) described in Appendix 2-9, wherein the first buried electrode (43) in the outer trench (405) is electrically connected to the control electrode (13) via the third electrode (52), the first buried electrode (43) in the inner trench (404), and the connection electrode (44). [Appendix 2-11] The semiconductor device (1) according to appendix 2-9 or appendix 2-10, wherein one to three of the outer trenches (405) are formed. [Appendix 2-12] a well region (122) of a second conductivity type that is formed in a surface layer portion of the first region (123, 129) from the active region (64) to the outer periphery region (63) and is continuous in a lateral direction along the first main surface (12A) except for a portion where the first outer periphery trench (40) and the second outer periphery trench (42) are formed; The channel region (125) is formed of a part of the well region (122), The semiconductor device (1) according to any one of Appendices 2-1 to 2-11, wherein the well region (122) includes the first periphery trench (40) and the second periphery trench group (42) therein, and is formed overlapping the first periphery trench (40) and the second periphery trench group (42). [Appendix 2-13] The semiconductor device (1) according to any one of Appendices 2-1 to 2-12, comprising a peripheral electrode (53) formed on the first main surface (12A) of the semiconductor chip (12) and connected to the semiconductor chip (12) outside the second peripheral trench group (42) in the peripheral region (63). [Appendix 2-14] The semiconductor device (1) according to any one of Appendix 2-1 to Appendix 2-13, having a breakdown voltage of 100V or more. [Appendix 2-15] The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-14, wherein the first region (123, 129) has a resistivity of 3.5 Ω·cm or more and 4.5 Ω·cm or less. [Appendix 2-16] The semiconductor chip (12) includes a semiconductor substrate (127) of a first conductivity type having a first impurity concentration, and an epitaxial layer (129) of the first conductivity type formed on the semiconductor substrate (127), having a second impurity concentration lower than the first impurity concentration, and constituting the first region (123); The semiconductor device (1) according to any one of Appendix 2-1 to Appendix 2-15, wherein the epitaxial layer (129) has a thickness of 7 μm or more and 15 μm or less. [Appendix 2-17] The first impurity concentration is 1×10 18 cm -3 More than 1×10 20 cm -3 is as follows: The second impurity concentration is 1×10 15 cm -3 More than 1×10 19 cm -3 A semiconductor device (1) according to any one of claims 2 to 2-16, which is as follows: [Appendix 2-18] the channel region (125) includes a side portion (124) that forms a side surface of the cell trench (15), and a convex bottom portion (126) that protrudes from a lower end of the side portion (124) toward the second main surface (12B) so as to be away from the side surface of the cell trench (15); The semiconductor device (1) according to any one of Appendix 2-1 to Appendix 2-17, wherein a bottom (126) of the channel region (125) is located closer to the first main surface (12A) than a lower end (152) of the cell trench (15). [Appendix 2-19] The semiconductor device (1) according to any one of Supplementary Note 2-1 to Supplementary Note 2-18, wherein the first outer periphery trench (40) is formed with a width (W2) larger than that of the cell trench (15). [Appendix 2-20] The semiconductor device (1) according to appendix 2-19, wherein the first outer periphery trench (40) has a depth (D2) greater than that of the cell trench (15). [Appendix 2-21] The semiconductor element structure (14) includes a source region (121) of a first conductivity type, the channel region (125) of a second conductivity type, and a drift region (123) of a first conductivity type, which are formed in this order from the first main surface (12A) of the semiconductor chip (12) in a depth direction of the cell trench (15), The semiconductor device (1) according to any one of Supplementary Note 2-1 to Supplementary Note 2-20, wherein the control electrode (13) includes a gate electrode (13) that forms a channel in the channel region (125). [Appendix 2-22] The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-21, wherein the semiconductor chip (12) includes a silicon chip. [Explanation of symbols]

[0118] 1: Semiconductor device 2: Lead frame 3: Semiconductor elements 4:Package 5: Conductive film 6: Insulating film 7: First pad 8: First wire 9: 2nd pad 10: Second wire 11: First contact plug 12: Semiconductor chips 12A: First main surface 12B: Second main surface 13: Gate electrode 14: Transistor cell 14A: 3rd connection trench 14B: 3rd connection trench 14C: 3rd connection trench 15: Gate trench 16: Gate insulating film 17: Interlayer insulating film 18: Source Contact 19: Gap area 20: Gap area 21: Die pad section 22: First lead part 23: Second lead part 24: Third lead section 31A: 1st end surface 31B: First end surface 32A: 2nd end surface 32B: 2nd end face 40: First outer perimeter trench 41: Connection trench 41A: First connection trench 41B: Second connection trench 41C: 3rd connection trench 42: Second outer perimeter trench 43: First buried electrode 44: Connection electrode 45: Second buried electrode 46: Second contact plug 47: Contact hole 48 :1st side 49:Second side 50: Step 51: First conductive film 52: Second conductive film 53: Third conductive film 54: Fourth conductive film 61: Gap area 63:Outer area 64: Active area 70 :1st part 71:Second part 73: First trench group 74: Second trench group 75: First boundary 76: Boundary trench 77: Second boundary 78: High concentration impurity region 79: Bottom 80: Impurity region 81: Long wire 82: Short wire 83: Depletion layer 84: Arrow 85: Corner 86: Corner 111:Top surface 121: First impurity region 122:Second impurity region 123:Third impurity region 124: Side 125: Channel region 126: Bottom 127: Semiconductor substrate 128: Gap 129: Epitaxial layer 130: 1st conductivity type region 131:Top surface 132: First potential well region 133: Floating area 134: Third contact plug 135: Peripheral contact plug 136: Trench Group 151: Outer gate trench 152: Bottom edge 161: First insulating film 162: Second insulating film 163: Third insulating film 191: First barrier film 192: Second barrier film 211A: First side 211B: Side 1 212A: Side 2 212B: Side 2 221: First pad section 222: 1st lead 231: Second pad section 232: 2nd Lead 401: 1st straight section 402: 2nd straight section 403: Corner 404: Inner trench 405: Outer trench 411: First connection point 412: Second connection point 413: Third connection point 421: First trench 422: Second trench 423: 1st straight section 424: 2nd straight section 425: Corner 431:Top surface 451:Top surface 461:Top surface 511: Recess 520: Recess 521: Pad electrode part 522: Finger electrode part 811: Bonding section 821: Bonding section D1:Depth D2:Depth D3:Depth D C1 :Depth D C2 :Depth P1: Pitch P2: First peripheral pitch P3: Second peripheral pitch P4: 3rd peripheral pitch R: radius of curvature W1: Width W2:Width W3:Width W4:Width W5: Width W6:Width W7:Width W8:Width

Claims

1. a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and an end surface surrounding the first main surface, the semiconductor chip having an active area and a peripheral area around the active area defined on the first main surface side; a first electrode formed on the first main surface of the semiconductor chip; a second electrode formed on the second main surface of the semiconductor chip; a first region of a first conductivity type formed in the semiconductor chip and electrically connected to the second electrode; a vertical semiconductor element structure formed in the active region and configured to pass a current between the first electrode and the second electrode; a peripheral electrode formed on the first main surface of the semiconductor chip and physically separated from the first electrode, the peripheral electrode being connected to the semiconductor chip in the peripheral region; a well region of a second conductivity type that is continuously formed in a surface layer portion of the first region from the active region to the peripheral region and that constitutes at least a part of the semiconductor element structure; a trench group including a plurality of annular trenches formed in the peripheral region on the inner side of the peripheral electrode and surrounding the active region; a first conductivity type region in which the well region is not selectively formed is present in the peripheral region so as to be exposed from the first main surface; the first conductivity type region is formed to include some of the plurality of annular trenches therein and to overlap the group of trenches; The annular trench included inside the first conductivity type region is contained within the first conductivity type region in a plan view.

2. a peripheral contact portion that connects the peripheral electrode and the semiconductor chip; 2. The semiconductor device according to claim 1, wherein said first conductivity type region includes said peripheral contact portion therein and is formed opposite to said peripheral electrode in a thickness direction of said semiconductor chip.

3. the first conductivity type region is formed to reach the end surface of the semiconductor chip, 3. The semiconductor device according to claim 2, wherein said well region is formed in an inner region surrounded by said first conductivity type region.

4. the first conductive type region is formed in a ring shape surrounding the active region, 3. The semiconductor device according to claim 1, wherein the well region is divided into a first portion formed in an inner region surrounded by the first conductivity type region and a second portion formed in an annular outer region surrounding the first conductivity type region.

5. 5. The semiconductor device according to claim 4, wherein a width of said first conductivity type region sandwiched between said first portion and said second portion is not less than 8 [mu]m and not more than 15 [mu]m.

6. 6. The semiconductor device according to claim 1, wherein the first conductivity type region is formed by exposing a portion of the first region from the first main surface of the semiconductor chip.

7. The semiconductor device according to any one of claims 1 to 5, wherein the first conductivity type region includes a second region selectively formed in a surface layer portion of the first region and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first region.

8. A semiconductor chip having a first main surface, a second main surface opposite the first main surface, and an end face surrounding the first main surface, with an active area and a peripheral area around the active area defined on the first main surface side; a first electrode formed on the first main surface of the semiconductor chip; a second electrode formed on the second main surface of the semiconductor chip; a first region of a first conductivity type formed in the semiconductor chip and electrically connected to the second electrode; a vertical semiconductor element structure formed in the active region and configured to pass a current between the first electrode and the second electrode; a peripheral electrode formed on the first main surface of the semiconductor chip and physically separated from the first electrode, the peripheral electrode being connected to the semiconductor chip in the peripheral region; a well region of a second conductivity type that is continuously formed in a surface layer portion of the first region from the active region to the peripheral region and that constitutes at least a part of the semiconductor element structure; a first conductivity type region in which the well region is not selectively formed is present in the peripheral region; The semiconductor device structure includes a cell trench, a control electrode embedded in the cell trench, and a channel region formed on a side of the cell trench and constituted by the well region; a first peripheral trench formed in the peripheral region on the inner side of the peripheral electrode; a first buried electrode buried in the first outer periphery trench and electrically connected to the control electrode; a second outer periphery trench group including a plurality of annular second outer periphery trenches formed in the outer periphery region outside the first outer periphery trenches and inside the outer periphery electrode, the second outer periphery trench group being physically separated from the first outer periphery trenches; a second buried electrode buried in the second outer periphery trench and electrically isolated from the first buried electrode; the well region is continuous in a lateral direction along the first main surface from the channel region, except for portions where the first outer periphery trench and the second outer periphery trench group are formed, and the first conductivity type region.

9. the first conductivity type region is formed to selectively include some of the second outer periphery trench group inside and overlap the second outer periphery trench group, 9. The semiconductor device according to claim 8, wherein said first outer periphery trench is formed so as to penetrate said well region in a thickness direction of said semiconductor chip and reach said first region.

10. a peripheral contact portion that connects the peripheral electrode and the semiconductor chip; 10. The semiconductor device according to claim 8, wherein said first conductivity type region includes said peripheral contact portion therein and is formed opposite to said peripheral electrode in a thickness direction of said semiconductor chip.

11. the second outer periphery trench group includes a first trench formed at a first outer periphery pitch on the end face side from the first outer periphery trench, and a plurality of second trenches formed at a second outer periphery pitch on the end face side from the first trench and arranged at a third outer periphery pitch narrower than the first outer periphery pitch and the second outer periphery pitch, 11. The semiconductor device according to claim 8, wherein the plurality of second trenches include a boundary trench that forms a first boundary between the well region and the first conductivity type region.

12. 12. The semiconductor device according to claim 11, wherein the well region includes a first portion formed in an inner region surrounded by the boundary trench, and a second portion having a second boundary with the first conductivity type region in a region directly below the peripheral electrode and formed in an annular outer region closer to the end face than the second boundary.

13. 13. The semiconductor device according to claim 12, wherein a width of said first conductivity type region sandwiched between said first portion and said second portion is not less than 8 [mu]m and not more than 15 [mu]m.

14. the first conductivity type region is formed to extend from the boundary trench to the end surface of the semiconductor chip; The semiconductor device according to claim 11 , wherein the well region is formed in an inner region surrounded by the boundary trench.

15. The semiconductor device according to any one of claims 8 to 14, wherein the well region includes a first potential well region formed in an inner region surrounded by the first outer periphery trench and electrically connected to the first electrode, and a floating region formed in an outer region of the first outer periphery trench and electrically floating.

16. The semiconductor device according to any one of claims 1 to 15, having a breakdown voltage of 100V or more.

17. 17. The semiconductor device according to claim 1, wherein the first region has a resistivity of 3.5 Ω·cm or more and 4.5 Ω·cm or less.

18. The semiconductor chip includes a semiconductor substrate of a first conductivity type having a first impurity concentration, and an epitaxial layer of the first conductivity type formed on the semiconductor substrate, having a second impurity concentration lower than the first impurity concentration, and constituting the first region; 18. The semiconductor device according to claim 1, wherein the epitaxial layer has a thickness of 7 μm or more and 15 μm or less.

19. The first impurity concentration is 1×10 １８ cm －３ Above 1 x 10 ２０ cm －３ is as follows: The second impurity concentration is 1×10 １５ cm －３ Above 1 x 10 １９ cm －３ 20. The semiconductor device according to claim 18, wherein:

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