Photoelectric conversion device, photoelectric conversion system and transportation equipment

Abstract

To provide an advantageous technique for ensuring long time operation and high reliability of a semiconductor device.SOLUTION: An integrated circuit used in a semiconductor device includes: a first element executing a prescribed operation; a second element; and a control section for controlling to make the second element inoperative when performance degradation in the first element is of a first degree and make operative when performance degradation in the first element is of a second degree larger than the first degree.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. and transport aircraft In a vessel Regarding. [Background technology]

[0002] Semiconductor devices are also incorporated and used in surveillance cameras that require long-term operation and in-vehicle cameras that require high reliability. In order to ensure long-term operation and high reliability of semiconductor devices, configurations that make integrated circuits included in the semiconductor devices redundant have been considered. Patent Document 1 shows that a plurality of semiconductor circuits having the same configuration are mounted in order to increase redundancy. In Patent Document 1, when the magnitude relationship between a value measured for a physical characteristic of a semiconductor circuit during operation of the semiconductor circuit and a predetermined threshold value is reversed, power supply to the semiconductor circuit in use is stopped and the semiconductor circuit to be used is switched, thereby operating the system for a long period of time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5408362 Summary of the Invention [Problem to be solved by the invention]

[0004] Semiconductor devices need to be operated for longer periods of time while ensuring higher reliability.

[0005] An object of the present invention is to provide a technique that is advantageous for ensuring long-term operation and high reliability of a semiconductor device. [Means for solving the problem]

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device including an integrated circuit and a photoelectric conversion unit in which a plurality of pixels are arranged, each including a photoelectric conversion element for converting incident light into an electrical signal, the integrated circuit including a first element that executes a predetermined operation, a second element, and a control unit that performs control to make the second element inoperative when the performance degradation of the first element is at a first degree, and to operate the second element when the performance degradation of the first element is at a second degree that is greater than the first degree. The integrated circuit includes a plurality of second elements, and the control unit changes the number of second elements to be operated among the plurality of second elements when the deterioration in performance of the first element is at a second degree and when the deterioration is at a degree between the first degree and the second degree. It is characterized by: Effect of the Invention

[0007] According to the present invention, it is possible to provide a technique that is advantageous for ensuring long-term operation and high reliability of a semiconductor device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a configuration example of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 2 is a flow diagram showing an example of the operation of the semiconductor device in FIG. 1; [Diagram 3] FIG. 2 is a block diagram showing a case where the semiconductor device in FIG. 1 is applied to a clock tree. [Figure 4] 2 is a block diagram showing a case where the semiconductor device in FIG. 1 is applied to a power cutoff switch. [Diagram 5] 2 is a block diagram showing a case where the semiconductor device in FIG. 1 is applied to a driver circuit of a photoelectric conversion device. [Figure 6] 2 is a block diagram showing a case where the semiconductor device in FIG. 1 is applied to a driver circuit of a photoelectric conversion device. [Figure 7] FIG. 2 is a block diagram showing a modification of the semiconductor device in FIG. [Figure 8] 8 is a block diagram showing a configuration example of a monitor circuit of the semiconductor device in FIG. 7; [Figure 9] 9 is a flow diagram showing an example of the operation of the monitor circuit of FIG. 8; [Figure 10] 9 is a block diagram showing an example of the layout of monitor circuits in the semiconductor device of FIG. 8. [Figure 11] FIG. 2 is a block diagram showing a modification of the semiconductor device in FIG. [Figure 12] FIG. 2 is a block diagram showing a modification of the semiconductor device in FIG. [Figure 13] 13 is a block diagram showing an example of the layout of a monitor circuit of the semiconductor device of FIG. 12. [Figure 14] 4 is a timing chart showing an example of an operation when switching the operation mode of the semiconductor device in FIG. 1; [Figure 15] 2 is a diagram showing an example of the configuration of an imaging system in which the semiconductor device in FIG. 1 is incorporated. [Figure 16] 2 is a diagram showing a configuration example of a transport device including an imaging system in which the semiconductor device of FIG. 1 is incorporated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] The configuration and operation of a semiconductor device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 13. Figure 1 is a block diagram illustrating an example of the configuration of a semiconductor device 100 according to this embodiment.

[0011] The semiconductor device 100 includes an integrated circuit 101. The integrated circuit 101 includes a circuit 102 including an element for executing a predetermined operation, a circuit 103 having a configuration similar to that of the circuit 102, and a control unit 105 that controls the element included in the circuit 103 based on a signal 104 (degradation signal) indicating a degradation in performance of the element included in the circuit 102 during operation. The circuit 102 is a circuit that normally operates regardless of the degree of degradation in performance, such as a change over time (e.g., deterioration) caused by using the semiconductor device 100. The element included in the circuit 103 is inactive until the degree of degradation in performance of the element included in the circuit 102 reaches a predetermined degree for the predetermined operation. On the other hand, the element included in the circuit 103 operates under the control of the control unit 105 when it becomes difficult for the element included in the circuit 102 to execute a predetermined operation due to a change over time, in other words, when the degradation in performance becomes greater than the predetermined degree. That is, the circuit 102 is a circuit to be made redundancy in the semiconductor device 100, and the circuit 103 is a redundant circuit arranged to ensure the redundancy of the circuit 102. In the following description, it is assumed that the elements included in the circuit 103 operate to ensure the redundancy of the circuit 102 in response to the deterioration of the characteristics (decrease in performance) of the elements included in the circuit 102 due to changes over time or the like.

[0012] The state of the circuit 102 is notified to the control unit 105 by a signal 104 (a degradation signal). The control unit 105 selects an element to be operated in the circuit 103 through a control signal 106 in response to the signal 104. For example, the circuit 102 and an element selected by the control unit 105 in the circuit 103 operate for the circuit 102 including an element whose performance has been degraded, thereby executing a predetermined operation of the circuit 102. The signal 104 may be generated within the integrated circuit 101, as described later, or may be supplied from outside the integrated circuit 101. The control unit 105 may control the state of the circuit 102 by the signal 104 and another signal. This "another signal" is a signal (normal signal) indicating that the degradation of the performance of the circuit 102 has not reached a predetermined level. In other words, when the degradation of the performance of the element included in the circuit 102 has not reached a predetermined level, a normal signal is generated. This normal signal is a signal indicating that the degradation of the performance of the element included in the circuit 102 is smaller than when a degradation signal is generated. When the control unit 105 receives this normal signal, it continues the predetermined operation by the circuit 102. On the other hand, when the control unit 105 receives the signal 104, the control unit 105 may select an element of the circuit 103 that is to be operated.

[0013] Next, a detailed description will be given of the operation of the integrated circuit 101. Fig. 2 is a flow chart for explaining the operation of the integrated circuit 101 of the semiconductor device 100 shown in Fig. 1.

[0014] When the control unit 105 starts operating, for example when the power is turned on, it repeats a reception standby process (S201) to receive the signal 104 and a determination of whether the signal 104 has been received (S202). The specific form of the signal 104 is not important, but for example, the signal 104 may be a binary signal that is at a High level when the performance of an element included in the circuit 102 has deteriorated and is at a Low level in other cases. In addition, for example, the signal 104 may be a multi-value signal having multiple bits corresponding to the degree of progress of deterioration in the performance of the element included in the circuit 102.

[0015] When the control unit 105 receives the signal 104, it executes a process (S203) of generating a control signal 106 for selecting an element to be operated in the circuit 103. The specific form of the control signal 106 is not limited. For example, when the signal 104 is a binary signal as described above, the control signal 106 may be a binary signal that is at a High level when an element included in the circuit 103 is used and at a Low level when an element included in the circuit 103 is not used. In this case, all elements among the elements arranged in the circuit 103 are in a selected state and can operate. Also, for example, the circuits 102 and 103 may each be composed of one element.

[0016] Regarding the control signal 106, consider the case where the signal 104 is a multi-level signal as described above. In this case, the control unit 105 may be provided with a storage unit in which multi-level control signals 106 corresponding to the multi-level signal 104 are stored in advance, and the control unit 105 may select a control signal 106 corresponding to each of the multi-level signals 104 from the storage unit and supply it to the circuit 103. The control unit 105 may also include a logical operation circuit capable of generating the multi-level control signal 106 corresponding to the multi-level signal 104. This allows the control unit 105 to generate the multi-level control signal 106 corresponding to the multi-level signal 104.

[0017] Next, the control unit 105 executes a control process (S204) for controlling elements included in the circuit 103 by supplying the control signal 106 to the circuit 103. When the control signal 106 is a binary signal, it is possible to control two states: to operate the circuit 103 in addition to the circuit 102, or to not operate the circuit 103. When the control signal 106 is a multi-value signal, it is possible to appropriately select the type of element to be operated in the circuit 103, the number of elements, etc., according to each signal.

[0018] 3 shows a case where this embodiment is applied to a circuit constituting a clock tree as a circuit 102 of a semiconductor device 100. In general, when a current is applied to an integrated circuit 101 of the semiconductor device 100, a phenomenon called NBTI (Negative Bias Temperature Instability) or hot carrier injection occurs. This is known to cause degradation of elements, such as changes in the threshold voltage and on-current of a transistor. It is difficult to design a desired product life span while taking into account the degradation of the threshold voltage and on-current of a transistor caused by the application of current.

[0019] One of the reasons that makes it difficult to design a product with a desired life span is malfunction of the circuit caused by deterioration of the clock buffer that constitutes the clock tree in the synchronous circuit. In synchronous circuit design, a clock tree is constructed to supply a clock signal to the flip-flop circuits in the circuit. In the synchronous circuit, the clock signal propagated by the clock tree has a higher toggle rate than other circuits that propagate data signals, and the progression of deterioration due to hot carrier injection can be faster than that of circuits that propagate data signals. The rapid progression of deterioration can make it impossible to propagate a normal clock signal to the flip-flop circuits in the synchronous circuit, which may cause the synchronous circuit to malfunction.

[0020] According to this embodiment, even if degradation occurs in a clock buffer, which is an element arranged in a circuit 102 to be made redundant, a clock buffer, which is an element arranged in a circuit 103 for making the circuit redundant, is used in combination. This makes it possible to supply a normal clock signal to a flip-flop circuit in an integrated circuit 101 of a semiconductor device 100. A specific operation will be described below with reference to FIG. 3.

[0021] Integrated circuit 101 of semiconductor device 100 includes clock tree 302, which is an example of circuit 102 that is normally operating and is to be made redundant, and clock tree 303, which is an example of circuit 103 for making clock tree 302 redundant. Clock tree 302 includes clock buffer 304. Clock tree 303 includes clock buffer 305 and clock buffer control switch 306 that function as a clock buffer in place of clock buffer 304 when the performance of clock buffer 304, an element included in clock tree 302, deteriorates.

[0022] Control unit 105 supplies control signal 106 to clock tree 303 in response to signal 104 indicating a degradation in performance of clock buffer 304 included in clock tree 302, which is an example of circuit 102. Clock buffer control switch 306 in clock tree 303 is controlled by control signal 106 to select clock buffer 305 to be used for operation. This allows clock buffer 304 and clock buffer 305 to be used in parallel, and even if the degree of degradation in performance of clock buffer 304 in clock tree 302 becomes large, clock propagation equivalent to that before the degradation in performance of clock buffer 304 can be achieved.

[0023] 3, only one row of clock trees 303 is arranged to ensure redundancy, but multiple rows of clock trees 303 may be arranged. By arranging multiple rows of clock trees 303 and using clock buffer 304 and multiple clock buffers 305 in parallel, it becomes possible to propagate the clock within integrated circuit 101 for a longer period of time even if degradation occurs in clock buffer 304.

[0024] 4, a case where the power cutoff function arranged in the semiconductor device 100 is made redundant will be described. The power cutoff function is a technology for suppressing leakage current by stopping the supply of power to some circuits (areas) that do not need to operate within the integrated circuit 101 of the semiconductor device 100.

[0025] In the power cutoff switch 404 that controls the power supply, a voltage that keeps the power cutoff switch 404 in an on state is applied to the gate during a non-power cutoff (power supply) period. If the power cutoff switch 404 is configured with a PMOS, a negative bias is always applied to the gate during a non-power cutoff period, causing degradation due to NBTI. As a result, the amount of current that the power cutoff switch 404 can pass may change over time as the semiconductor device 100 is used. This change in the amount of current causes a change in the time it takes for power supply to the power cutoff region 406 to be completed when switching the power cutoff.

[0026] When the on-current of the power cutoff switch 404 becomes small, the time for which power is supplied to the power cutoff area 406 becomes longer. When the power supply time becomes longer, the time for the power cutoff area 406 to return to normal becomes longer, and if the return is not completed at the desired timing, this causes the power cutoff area 406 to malfunction.

[0027] It is also conceivable that the on-current of the power cut-off switch 404 increases, shortening the time for which power is supplied to the power cut-off area. If the on-current of the power cut-off switch 404 increases due to the occurrence of degradation in the power cut-off switch 404, the amount of current flowing per unit time to the power cut-off area 406 increases when the power is changed from a power cut-off state to a power supply state. If the amount of current flowing into the power cut-off area 406 per unit time increases, power supply noise that changes the potential of the non-power cut-off area 410 may occur. If power supply noise occurs, there is a possibility that a malfunction will be caused in the non-power cut-off area 410.

[0028] According to this embodiment, even if deterioration occurs in the power cutoff switch 404, which is an element arranged in the circuit 102 to be made redundant, a power cutoff switch, which is an element arranged in the circuit 103 for making the circuit redundant, is used in combination. This makes it possible to perform the power cutoff function while suppressing malfunctions in the circuit operation. A specific operation will be described below with reference to FIG. 4.

[0029] The integrated circuit 101 of the semiconductor device 100 includes a power cut-off switch group 402 which is an example of the circuit 102 to be made redundant and which normally operates, and a power cut-off switch group 403 which is an example of the circuit 103 for making the power cut-off switch group 402 redundant. The power cut-off switch group 402 is composed of one or more power cut-off switches 404. The power cut-off switch group 403 is composed of one or more power cut-off switches 405. The power supply to a power cut-off area 406 is controlled by these power cut-off switches 404 and 405.

[0030] The control unit 105 supplies a control signal 106 to the power cut-off switch group 403 in response to a signal 104 indicating a deterioration in the performance of a power cut-off switch 404 included in the power cut-off switch group 402, which is an example of the circuit 102. The control signal 106 selects the power cut-off switch 405, which is an element to be operated in the power cut-off switch group 403. This allows the power cut-off switch 404 and the power cut-off switch 405 to be used in combination, and makes it possible to control the power supply time to the power cut-off area 406 even if the power cut-off switch 404 of the power cut-off switch group 402 deteriorates.

[0031] Next, an example in which the semiconductor device 100 is applied to a photoelectric conversion device 501 will be shown with reference to FIG. 5. Another example of a cause that makes it difficult to design a product with a desired product life is a malfunction of circuit operation caused by a deterioration in the performance of an element included in a drive circuit that drives a photoelectric conversion unit in which a plurality of pixels each including a photoelectric conversion element are arranged in the photoelectric conversion device. The photoelectric conversion device 501 captures an image by converting incident light into an electric signal using a photoelectric conversion element. When a drive circuit that generates a drive signal for the photoelectric conversion unit deteriorates over time, the generation timing of the drive signal changes over time. As a result, the operation timing when capturing an image, such as photoelectric conversion, changes, which may cause a malfunction such as not being able to capture an image at a desired timing.

[0032] According to this embodiment, even if degradation occurs in the driving circuit 511, which is the circuit 102 to be made redundant, the driving circuit 512, which is the circuit 103 for making the circuit redundant, is used in combination. This enables the circuit to operate at an appropriate timing in the photoelectric conversion device 501. A specific operation will be described below with reference to FIG.

[0033] The photoelectric conversion device 501 shown in FIG. 5 includes a pixel circuit layer 520 in which a photoelectric conversion unit 523 is arranged, in which pixels 522 each including a photoelectric conversion element 524 are arranged in an array, and a pixel drive circuit layer 510 that supplies a drive signal 516 to the pixel circuit layer 520. The pixel drive circuit layer 510 is an example of a layer including the integrated circuit 101 of the semiconductor device 100 described above. The pixel drive circuit layer 510 includes a drive circuit 511 which is an example of the circuit 102 to be made redundant, and a drive circuit 512 which is an example of the circuit 103 for making the drive circuit 511 redundant. In the configuration shown in FIG. 5, the photoelectric conversion device 501 includes a stacked structure including the pixel circuit layer 520 including the photoelectric conversion unit 523 and the pixel drive circuit layer 510 including the integrated circuit 101. However, this is not limited to this, and the photoelectric conversion unit 523 and the integrated circuit 101 including the drive circuit 512 may be arranged in the same layer.

[0034] In the pixel circuit layer 520, pixels 522 arranged in an array are connected to a drive circuit 511 by a drive signal line 521 shared by the pixels 522 arranged in the lateral direction (also called the row direction or horizontal direction) shown in Fig. 5. The pixels 522 connected to the common drive signal line 521 are controlled by a drive signal 516 output from the drive circuit 511. The drive signal 516 transmits drive timing to the pixels 522 in the pixel circuit layer 520, and allows the electric (charge) signal generated in the photoelectric conversion element 524 to be read out.

[0035] In this embodiment, since the configuration of the process after the pixels 522 convert light into an electrical signal does not matter, it is described as a pixel driving circuit layer 510, and a method for processing the electrical signal output from each pixel 522 of the pixel circuit layer 520 is not described. Various known processes can be applied to the processing of the electrical signal output from the pixels 522.

[0036] When an electrical signal is output from the pixel 522, the drive circuit 511 that outputs the drive signal 516 deteriorates over time, causing the timing at which the drive circuit 511 outputs the drive signal 516 to change over time. This change over time changes the timing at which the electrical signal is read out from the pixel 522. Thus, by using a combination of the drive circuit 511 and a drive circuit 512 for making the drive circuit 511 redundant, it is possible to adjust the timing at which the electrical signal is read out from the pixel 522.

[0037] More specifically, the control unit 105 supplies a control signal 106 to the drive circuit 512 in response to a signal 104 indicating a decrease in performance of the drive circuit 511, which is an example of the circuit 102. The drive circuit 512 that outputs the drive signal 517 is selected by the control signal 106. As a result, the drive signal line 521 is driven using the drive signal 516 supplied by the drive circuit 511 and the drive signal 517 supplied by the drive circuit 512. The drive circuit 512 is controlled by the control signal 106 output from the control unit 105, and the control timing may be controlled by the signal 104. In addition, the control timing of the drive circuit 512 may be controlled by a control circuit (not shown) for driving the drive circuit 511. In addition, the control timing of the drive circuits 511 and 512 may be controlled by the same control circuit (for example, the control unit 105).

[0038] In the above description, the driving circuit 511 is provided with redundancy, but as shown in Fig. 6, redundancy may be provided within the driving circuit 511. Specifically, the output buffer circuit 533 that finally outputs the driving signal 516 from the driving circuit 511 may be made the target of redundancy, and the driving signal 516 may be output by combining it with a buffer circuit 532 that is an element included in the circuit 103. The operation of the buffer circuit 532 is controlled by a buffer circuit control switch 531, which is controlled by a control signal 106 supplied by the control unit 105. This makes it possible to control the output timing of the driving signal 516 even if the output buffer circuit 533 is deteriorated.

[0039] In the above description, the driving circuits 511 and 512 are shown as examples of the circuits 102 and 103 in the photoelectric conversion device 501, but the present invention is not limited to this. For example, the pixel driving circuit layer 510 of the photoelectric conversion device 501 may be provided with a combination of the clock trees 302 and 303 described above, or may be provided with a combination of the power cutoff switch groups 402 and 403. The integrated circuit 101 of the semiconductor device 100 is applicable to various configurations of the photoelectric conversion device 501.

[0040] In the present embodiment, an imaging device has been described as an example of the photoelectric conversion device 501 to which the semiconductor device 100 is applied, but the present invention is not limited to this and can be applied to other examples of photoelectric conversion devices. For example, the semiconductor device 100 can be applied to photoelectric conversion devices such as distance measuring devices (devices for measuring distance using focus detection or TOF (Time Of Flight)) and photometric devices (devices for measuring the amount of incident light).

[0041] Next, the generation of signal 104 indicating the state of an element included in circuit 102 during operation will be described. Fig. 7 is a block diagram of semiconductor device 100 in the case where signal 104 is generated within integrated circuit 101. In the configuration shown in Fig. 7, integrated circuit 101 further includes a monitor circuit 700 for monitoring the state of an element included in circuit 102, in addition to the configuration shown in Fig. 1 above. Monitor circuit 700 generates signal 104 in accordance with the degree of degradation in performance of the element included in circuit 102, and supplies signal 104 to control unit 105.

[0042] Various known circuit configurations can be used as the circuit configuration of the monitor circuit 700. Fig. 8 is a diagram showing an example of the circuit configuration of the monitor circuit 700. The operation of the monitor circuit 700 will be described below.

[0043] 8, the monitor circuit 700 includes an oscillator circuit 804, and generates the signal 104 in response to a change in the oscillation frequency of the oscillator circuit 804. The monitor circuit 700 also includes a control circuit 802, a comparator 803, and a counter 805.

[0044] For example, a ring oscillator circuit in which an odd number of inverters are connected in multiple stages may be used as the oscillation circuit 804. Repeated switching of the transistors constituting the oscillation circuit 804 causes degradation in the transistors constituting the oscillation circuit 804, causing changes in the on-current and threshold voltage, and changing the oscillation frequency. This allows the monitor circuit 700 to monitor (estimate) the state of the elements included in the circuit 102.

[0045] 9 is a flow diagram showing an example of an operation in which the monitor circuit 700 generates the signal 104 and supplies it to the control unit 105. First, the control circuit 802 for controlling the operation of the monitor circuit 700 performs an oscillation start notification process (S901) in which the control circuit 802 supplies an oscillation start signal 810 to the oscillation circuit 804. In response to the oscillation start signal 810, the oscillation circuit 804 performs an oscillation start process (S902) in which the oscillation circuit 804 starts oscillation.

[0046] When the oscillation circuit starts oscillation, the counter 805 performs a counting process (S903) to count the number of oscillations of the oscillation signal 811 output by the oscillation circuit 804. The counter 805 notifies the comparator 803 of the count result 812.

[0047] The comparator 803 stores in advance the value of the oscillation frequency of the oscillation circuit 804 (hereinafter referred to as the relational value) corresponding to the relation between the state of the element included in the circuit 102 and the oscillation frequency (oscillation count) of the oscillation circuit 804. The comparator 803 performs a count result comparison process (S904) for comparing the relational value with the count result 812.

[0048] The comparator 803 judges the state (degree of performance degradation) of the elements included in the circuit 102 based on the result of the count result comparison process (S905). If the result of the count result comparison and judgment does not reach the count number indicating that the performance degradation of the circuit 102 is a predetermined degree when compared with the relational value (NO in S905), the process transitions to the count process (S903). If the count number indicates that the performance degradation of the circuit 102 is greater than the predetermined degree when compared with the relational value (YES in S905), the comparator 803 performs a degradation detection notification process (S906) that supplies a degradation detection notification signal 813 to the control circuit 802. The control circuit 802 that receives the degradation detection notification signal 813 performs a signal generation process (S907) that generates a signal 104.

[0049] Here, when the relational value is one value, the signal 104 can be the binary signal described above. When the relational value has two or more values ​​(e.g., value A and value B), the signal 104 can be a multi-value signal, such as a signal according to a count number less than value A, a signal according to a count number equal to or greater than value A and less than value B, and a signal according to a count number equal to or greater than value B.

[0050] Next, the physical arrangement of the monitor circuit 700 in the integrated circuit 101 will be described with reference to FIG. 10. Generally, in the integrated circuit 101, a gradient of the voltage and temperature of the power supply and the like occurs depending on the physical coordinate position. The degree of deterioration of elements such as transistors included in the circuit 102 varies depending on conditions such as voltage and temperature. Therefore, by bringing the temperature and voltage conditions applied to the monitor circuit 700 and the circuit 102 to be made redundant closer to each other, the monitor circuit 700 can more accurately detect the state of the elements included in the circuit 102.

[0051] 10, consider a case where the integrated circuit 101 further includes a circuit 1000 for performing a predetermined operation different from the predetermined operation performed by the element included in the circuit 102. Depending on the power consumption in the circuit 1000, which is different from the circuit 102, the voltage supplied to the element arranged around the circuit 1000 may be different from that around the circuit 102. In addition, the temperature around the circuit 102 may also be different from that around the circuit 1000. Therefore, when the distance between the circuit 1000 and the monitor circuit 700 becomes small, the difference between the voltage and temperature conditions in the monitor circuit 700 and the voltage and temperature conditions in the circuit 102 becomes large, and the voltage and temperature conditions may approach the voltage and temperature conditions in the circuit 1000. In other words, the monitor circuit 700 may not be able to accurately monitor the state of the element included in the circuit 102.

[0052] 10, the monitor circuit 700 is arranged so that a distance 2 between the elements included in the circuit 1000 and the monitor circuit 700 is greater than a distance 1 between the elements included in the circuit 102 and the monitor circuit 700. This makes the voltage and temperature conditions of the monitor circuit 700 and the elements included in the circuit 102 closer to each other, allowing the monitor circuit 700 to monitor the states of the elements included in the circuit 102 more accurately.

[0053] For example, the arrangement of each component of the integrated circuit 101 may be adjusted so that the circuit 1000 is disposed in a region other than between the elements included in the circuit 102 and the monitor circuit 700. In addition, for example, the monitor circuit 700 may be disposed adjacent to the circuit 102. By disposing the monitor circuit 700 adjacent to the circuit 102, conditions such as voltage and temperature can be made substantially equal between the elements included in the circuit 102 and the elements included in the monitor circuit 700.

[0054] In the configuration shown in FIG. 7, it has been described that the monitor circuit 700 for monitoring the elements included in the circuit 102 is disposed in the integrated circuit 101. However, the circuit for monitoring the circuit 102 is not limited to being disposed in the integrated circuit 101. As shown in FIG. 11, the semiconductor device 100 may further include an external monitor circuit 1100 for monitoring the state of the elements included in the circuit 102, in addition to the integrated circuit 101. The external monitor circuit 1100 generates a signal 104 according to the degree of deterioration of the performance of the elements included in the circuit 102, and supplies the signal 104 to the control unit 105 of the integrated circuit 101 from outside the integrated circuit 101. The external monitor circuit 1100 monitors the state of the elements included in the circuit 102, such as the degree of deterioration, from outside the integrated circuit 101, and generates the signal 104.

[0055] Various appropriate methods can be used to monitor the elements included in the circuit 102. For example, the external monitor circuit 1100 may have a configuration similar to that of the above-mentioned monitor circuit 700 and may be operated under the same or similar operating conditions as the circuit 102. Based on information on the oscillation frequency measured by an oscillation circuit arranged in the external monitor circuit 1100, the degree of degradation in the performance of the elements included in the circuit 102 can be monitored and a signal 104 can be supplied to the control unit 105.

[0056] Also, for example, the external monitor circuit 1100 may monitor operating conditions such as the temperature, operating voltage, total current-on time, and toggle rate of the elements included in the circuit 102. The external monitor circuit 1100 may determine a state of performance degradation, such as deterioration, of the elements included in the circuit 102 according to a result of monitoring at least one of these operating conditions of the circuit 102, and supply the signal 104 to the control unit 105. The external monitor circuit 1100 may calculate the state of the elements included in the circuit 102 from the monitoring results of these operating conditions of the circuit 102, and generate the signal 104. The external monitor circuit 1100 may also generate the signal 104 by referring to a prerecorded lookup table or the like that indicates the relationship between these operating conditions and the degree of performance degradation of the circuit 102.

[0057] In each of the above-described embodiments, the integrated circuit 101 includes one combination of the circuit 102 including an element to be made redundant, the circuit 103 including an element to make the circuit 102 redundant, and the control unit 105 that controls the circuit 103. However, the combination of the circuits 102, 103, and the control unit 105 included in the integrated circuit 101 is not limited to one combination, and a plurality of combinations may be arranged in the integrated circuit 101. In the configuration shown in FIG. 12, an example of the integrated circuit 101 including two sets of the circuits 102, 103, and the control unit 105 is shown. Although FIG. 12 shows an example of the configuration including two sets of the circuits 102, 103, and the control unit 105, the integrated circuit 101 may include three or more of the above combinations.

[0058] 12, the circuit 102a, the circuit 103a, and the control unit 105a function as one set to execute a predetermined operation. Similarly, the circuit 102b, the circuit 103b, and the control unit 105b function as one set to execute a predetermined operation. Signals 104a and 104b indicating a state such as a deterioration in performance of elements included in the operating circuits 102a and 102b may be supplied to the control units 105a and 105b by the monitor circuit 700 disposed in the integrated circuit 101 as described above.

[0059] FIG. 13 shows a block diagram of the configuration shown in FIG. 12 in which the signals 104a and 104b are generated by a monitor circuit 700 arranged in the integrated circuit 101. The monitor circuit 700 may be a common circuit in the circuits 102a and 102b that are the object of redundancy. However, as described above, the closer the voltage and temperature conditions during operation of the monitor circuit 700 and the circuits 102a and 102b, the more likely it is that the monitor circuit 700 can accurately detect the degree of performance degradation, such as deterioration of elements included in the circuits 102a and 102b that are the object of redundancy. Therefore, in the configuration shown in FIG. 13, the integrated circuit 101 is provided with a monitor circuit 700a and a monitor circuit 700b. The monitor circuit 700a monitors the state of the circuit 102a, generates a signal 104a according to the degree of performance degradation of the elements included in the circuit 102a, and supplies the signal 104a to the control unit 105a. Similarly, the monitor circuit 700b monitors the state of the circuit 102b, generates a signal 104b according to the degree of deterioration in the performance of the elements included in the circuit 102b, and supplies the signal 104b to the control unit 105b.

[0060] Here, the physical arrangement of the monitor circuit 700a in the integrated circuit 101 will be described. As described above, in the integrated circuit 101, a gradient of the voltage and temperature of the power supply and the like occurs depending on the physical coordinate position. The degree of deterioration of elements such as transistors included in the circuit 102a varies depending on conditions such as voltage and temperature. Therefore, by bringing the temperature and voltage conditions applied to the monitor circuit 700a and the circuit 102a to be made redundant closer to each other, the monitor circuit 700a can more accurately detect the state of the elements included in the circuit 102a.

[0061] Therefore, the distance 3 between the elements included in the circuit 102a and the monitor circuit 700a may be shorter than the distance 4 between the elements included in the circuit 102b and the monitor circuit 700a. By making the distance 3 shorter than the distance 4, the conditions such as the voltage and temperature applied to the monitor circuit 700a and the elements included in the circuit 102a become closer than the conditions of the monitor circuit 700a and the circuit 102b. This allows the monitor circuit 700a to more accurately detect the state of the elements included in the circuit 102a. By arranging the physical arrangement of the circuit 102b and the monitor circuit 700b that monitors the state of the circuit 102b in the same manner as the circuit 102a and the monitor circuit 700a, the monitor circuit 700b can more accurately detect the state of the elements included in the circuit 102b. For example, the monitor circuit 700a may be arranged adjacent to the circuit 102a, and similarly, the monitor circuit 700b may be arranged adjacent to the circuit 102b.

[0062] 12 and 13, the control units 105a and 105b for controlling the circuits 103a and 103b are arranged separately, but this is not limited to the above. A single control unit 105 may be arranged in the integrated circuit 101, and the control unit 105 may control elements included in the circuit 103a in response to the signal 104a, and may control elements included in the circuit 103b in response to the signal 104b.

[0063] Furthermore, the signals 104a and 104b may be supplied to the control units 105a and 105b by an external monitor circuit 1100 arranged separately from the integrated circuit 101 as described above. In this case, the external monitor circuit 1100 may be a combination of an external monitor circuit corresponding to the circuit 102a and an external monitor circuit corresponding to the circuit 102b. Furthermore, the external monitor circuit 1100 may be a circuit in which a circuit corresponding to the circuit 102a and a circuit corresponding to the circuit 102b are integrated into one. The configuration of the external monitor circuit 1100 may be any configuration as long as it can generate the signals 104a and 104b according to the respective states of the circuit 102a and the circuit 102b.

[0064] Here, a further modified example of the present embodiment described above will be described. For example, the signal 104 for notifying the state of the circuit 102 shown in FIG. 1 can be replaced by another signal inside the integrated circuit 101. This other signal can be, for example, a signal indicating the total power-on time of the integrated circuit 101 itself, a signal indicating the temperature, a signal indicating the operation mode, etc. For example, the other signal can be a signal indicating the state of a circuit (element) different from the circuit 102 arranged in the integrated circuit 101, separate from the above-mentioned monitor circuit 700, such as a signal indicating the total power-on time of the circuit, a signal indicating the temperature, a signal indicating the operation mode, etc. The circuit can be a circuit for performing the same operation as the circuit 102, or a circuit for performing a different operation. It is possible to predict the state of the circuit 102 from not only the signal 104 indicating the state of the circuit 102 but also the signals indicating the states of these integrated circuits 101. In other words, the signal different from these signals 104 can be a signal (degradation signal) indicating the degree of degradation of the performance of the circuit 102. Therefore, the control unit 105 may make the determination of S202 in FIG. 2 using a signal indicating the state of the integrated circuit 101 instead of the signal 104, or using both the signal 104 indicating the state of the circuit 102 and the signal indicating the state of the integrated circuit 101.

[0065] Similarly, the external monitor circuit 1100 shown in FIG. 11 may be replaced with another circuit arranged in the semiconductor device 100 related to information on operating conditions such as the temperature, operating voltage, total power-on time, and toggle rate of elements included in the circuit 102. There may be a circuit related to such information inside the semiconductor device 100. For this reason, an internal signal of a circuit related to information on the state of the circuit 102 can be used instead of the signal 104. Also, for example, in the configuration shown in FIG. 12, the signals 104a and 104b can be replaced with other signals of a circuit related to information on the state of the circuit 102 arranged inside the integrated circuit 101. The other signals can be, for example, signals of a circuit other than the circuit 102 indicating information related to the total power-on time, temperature, operation mode, etc. of the circuit 102.

[0066] 3, only one row of clock trees 303 for ensuring redundancy is arranged, but as described above, multiple rows of clock trees 303 may be arranged. In this case, the number of clock trees 303 used in parallel may be controlled according to the degree of deterioration of clock trees 302. When controlling the number of clock trees 303 used in parallel, signal 104 is a multi-valued signal, and based on this signal 104, control signal 106 supplied from control unit 105 to clock tree 303 also becomes a multi-valued signal, which makes it possible to change (control) the number of clock trees 303 used in parallel.

[0067] 4, the control unit 105 may control the number of power cut-off switches 405 included in the power cut-off switch group 403 to be operated in parallel in accordance with the state (performance degradation) of the power cut-off switch group 402. In this case, the signal 104 output in accordance with the performance degradation becomes a multi-value signal, and the control signal 106 supplied from the control unit 105 to the power cut-off switch group 403 based on the multi-value signal 104 becomes a multi-value signal. This makes it possible to change (control) the number of power cut-off switches 405 used in parallel. Also, a plurality of power cut-off switch groups 403 may be provided, and the number of power cut-off switch groups 403 and the number of power cut-off switches 405 operating in parallel with the power cut-off switch group 402 may be changed.

[0068] 5, a plurality of driving circuits 512 may be provided, and the control unit 105 may control the number of driving circuits 512 to be operated in parallel in accordance with the state (performance degradation) of the driving circuits 511. In this case, the signal 104 output in accordance with the degradation in performance becomes a multi-value signal, and the control signal 106 supplied from the control unit 105 to the driving circuits 512 based on the multi-value signal 104 becomes a multi-value signal. This makes it possible to change (control) the number of driving circuits 512 used in parallel.

[0069] Furthermore, the semiconductor device 100 may have a configuration capable of operating in a plurality of operation modes. That is, the integrated circuit 101 may switch between a plurality of different operation modes and operate in each operation mode. For this reason, the operation of the integrated circuit 101 of the semiconductor device 100 shown in FIG. 2 may be performed not only when the power is turned on, but also, for example, when the operation mode of the integrated circuit 101 is switched. This is because the speed and amount of performance degradation of the circuit 102 and the type of the circuit 103 operating for redundancy may differ depending on the operation mode in which the integrated circuit 101 operates.

[0070] The switching of the operation mode may be, for example, a case where the integrated circuit 101 is operated in two operation modes, a power saving mode and a high-speed signal processing mode, in the redundancy of the clock tree shown in FIG. 3. The high-speed signal processing mode may be a mode for improving the processing capability of the integrated circuit 101 more than the power saving mode by increasing the power supply voltage and the clock frequency more than the power saving mode. In such a high-speed signal processing mode, the performance of the clock tree 302 may be degraded more than in the power saving mode. In addition, the high-speed signal processing mode requires faster signal processing than the power saving mode, so the number of circuits operating for redundancy may change, more specifically, increase. In other words, there may be a case where a plurality of clock trees 303 are arranged in parallel, and more clock trees 303 are operated in the high-speed signal processing mode than in the power saving mode, thereby performing faster signal processing. For this reason, when the operation mode of the integrated circuit 101 is switched, the flow shown in FIG. 2 may be executed.

[0071] 14 is a diagram showing an example of the operation of the circuits 102 and 103 when the operation mode of the integrated circuit 101 is switched from the high-speed signal processing mode to the power saving mode. The circuit 102 continues to operate at all times as described above. Meanwhile, the circuit 103 may start operating at the timing described below in the power saving mode and the high-speed signal processing mode.

[0072] As shown in FIG. 14, the circuit 103 is stopped (non-operating) at time t1 when it starts to operate in the high-speed signal processing mode. Then, the circuit 103 receives a control signal 106 from the control unit 105 at time t2 and starts to operate. When the operation mode of the integrated circuit 101 is switched to the power saving mode at time t3, the control unit 105 transmits the control signal 106 to the circuit 103 to make the circuit 103 non-operating, and the circuit 103 stops operating and becomes non-operating according to the control signal 106. Then, the circuit 103 receives the control signal 106 from the control unit 105 at time t4 and starts to operate. As shown in FIG. 14, the time from time t1 when the integrated circuit 101 starts to operate in the high-speed signal processing mode to time t2 when the circuit 103 starts to operate can be shorter than the time from time t3 when the operation mode is switched and the integrated circuit 101 starts to operate in the power saving mode to time t4 when the circuit 103 starts to operate.

[0073] 14, the circuit 103 is deactivated when the operation mode is switched, and the circuit 103 operates at a timing when the performance of the circuit 102 to be made redundant is deteriorated and the circuit 103 needs to operate, so that the operation time is shortened. This makes it possible to suppress the deterioration of the performance of the circuit 103 for making the circuit 102 redundant. In addition, since the circuit 103 does not operate during the period from time t1 to time t2 and the period from time t3 to time t4, for example, a recovery effect occurs against the deterioration caused by NBTI, and the deterioration of the circuit 103 can be recovered. Therefore, by operating the circuit 103 at a timing suitable for each operation mode of the integrated circuit 101, it is possible to guarantee the operation of the integrated circuit 101 for a longer period, and a highly reliable semiconductor device 100 can be realized.

[0074] The high-speed signal processing mode may correspond to a high-resolution mode that processes data with a high number of pixels in a data processing circuit of a photoelectric conversion system such as a camera. The power saving mode may correspond to a live view mode that displays imaging data on a viewfinder or display in a data processing circuit of a photoelectric conversion system such as a camera. When the imaging mode is switched in a photoelectric conversion system such as a camera, for example, the frequency of the supplied clock may be changed without changing the operating voltage. Even in such a case, by performing the above-mentioned operation when the operating mode is switched, the circuit 103 arranged for making the circuit 102 redundant is operated only during the necessary period. This makes it possible to ensure high reliability for a long period of time in the semiconductor device 100 including the integrated circuit 101.

[0075] As described above, the semiconductor device 100 of this embodiment can be applied to a photoelectric conversion device. Here, a photoelectric conversion system using a photoelectric conversion device incorporating the semiconductor device 100 of this embodiment will be described with reference to Fig. 15. Fig. 15 is a block diagram showing a schematic configuration of a photoelectric conversion system 1400 according to this embodiment.

[0076] A photoelectric conversion device incorporating the semiconductor device 100 can be applied to various photoelectric conversion systems. Examples of the applicable photoelectric conversion system include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and a photoelectric conversion device are also included in the photoelectric conversion system. FIG. 15 illustrates a block diagram of a digital still camera as an example of these.

[0077] 15 includes a photoelectric conversion device 1404 incorporating the semiconductor device 100, a lens 1402 that forms an optical image of a subject on a photoelectric conversion unit (e.g., photoelectric conversion unit 523 in FIG. 5) of the photoelectric conversion device 1404, an aperture 1403 that varies the amount of light passing through the lens 1402, and a barrier 1401 that protects the lens 1402. The lens 1402 and the aperture 1403 are an optical system that focuses light on the photoelectric conversion device 1404. The photoelectric conversion device 1404 converts the optical image formed by the lens 1402 into an electrical signal.

[0078] The photoelectric conversion system 1400 also has a signal processing unit 1407 which is an image generating unit that generates an image by processing an output signal output by the photoelectric conversion device 1404. The signal processing unit 1407 performs various corrections and compressions as necessary to output image data. The signal processing unit 1407 may be formed on a semiconductor substrate on which the photoelectric conversion device 1404 is provided, or may be formed on a semiconductor substrate separate from the photoelectric conversion device 1404. Moreover, the photoelectric conversion device 1404 and the signal processing unit 1407 may be formed on the same semiconductor substrate.

[0079] The photoelectric conversion system 1400 further includes a memory unit 1410 for temporarily storing image data, and an external interface unit (external I / F unit) 1413 for communicating with an external computer or the like. The photoelectric conversion system 1400 further includes a recording medium 1412 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1411 for recording or reading out on the recording medium 1412. The recording medium 1412 may be built into the photoelectric conversion system 1400, or may be removable.

[0080] Furthermore, the photoelectric conversion system 1400 has an overall control / calculation unit 1409 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1408 that outputs various timing signals to the photoelectric conversion device 1404 and the signal processing unit 1407. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system 1400 only needs to have at least the photoelectric conversion device 1404 and the signal processing unit 1407 that processes the output signal output from the photoelectric conversion device 1404.

[0081] The photoelectric conversion device 1404 outputs an imaging signal to a signal processing unit 1407. The signal processing unit 1407 performs predetermined signal processing on the imaging signal output from the photoelectric conversion device 1404, and outputs image data. The signal processing unit 1407 generates an image using the imaging signal.

[0082] As described above, according to the present embodiment, a photoelectric conversion system can be realized that employs the photoelectric conversion device 1404 (for example, an imaging device) incorporating the above-described semiconductor device 100.

[0083] Next, a photoelectric conversion system including a photoelectric conversion device incorporating the semiconductor device 100 of this embodiment and transportation equipment will be described with reference to Figures 16(a) and 16(b). Figures 16(a) and 16(b) are diagrams showing the configurations of a photoelectric conversion system 1500 incorporating the semiconductor device 100 of this embodiment and a transportation equipment 1501 incorporating the photoelectric conversion system 1500.

[0084] FIG. 16(a) shows an example of a photoelectric conversion system 1500 related to an in-vehicle camera. The photoelectric conversion system 1500 has a photoelectric conversion device 1510 in which the semiconductor device 100 is built. The photoelectric conversion system 1500 has an image processing unit 1512 that performs signal processing such as image processing on a plurality of image data acquired by the photoelectric conversion device 1510, and a parallax acquisition unit 1514 that calculates parallax (phase difference of parallax images) from the plurality of image data signal-processed by the image processing unit 1512. The photoelectric conversion system 1500 also has a distance acquisition unit 1516 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 1518 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 1514 and the distance acquisition unit 1516 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information on the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 1518 may determine the possibility of a collision using any of these pieces of distance information. The distance information acquisition means may be realized by dedicated hardware or a software module. In addition, it may be realized by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or may be realized by a combination of these.

[0085] The photoelectric conversion system 1500 is connected to a vehicle information acquisition device 1520 of a transportation device 1501 (for example, a vehicle) equipped with a drive unit, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1500 is also connected to a control ECU 1530, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 1518. The photoelectric conversion system 1500 is also connected to an alarm device 1540 that issues an alarm to the driver based on the judgment result of the collision judgment unit 1518. For example, when the judgment result of the collision judgment unit 1518 indicates that a collision is highly likely, the control ECU 1530 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1540 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0086] In this embodiment, the surroundings of the transportation equipment 1501, for example the front or rear, are imaged by the photoelectric conversion system 1500. Fig. 16(b) shows the photoelectric conversion system 1500 when imaging the front (imaging range 350) of the transportation equipment 1501. The vehicle information acquisition device 1520 sends an instruction to the photoelectric conversion system 1500 or the photoelectric conversion device 1510. With such a configuration, the accuracy of distance measurement can be further improved.

[0087] In the above, an example has been described in which the driving devices of the transportation equipment 1501, such as the brake, accelerator, and engine, are controlled based on the information obtained by the photoelectric conversion device 1510 so as not to collide with other vehicles. However, the present invention is not limited to this, and can also be applied to automatic driving control to follow other vehicles and automatic driving control to avoid going out of a lane. In addition, an example has been shown in which the photoelectric conversion system 1500 incorporating the semiconductor device 100 is incorporated in the transportation equipment 1501, but the semiconductor device 100 may be incorporated in the vehicle information acquisition device 1520, the control ECU 1530, or the alarm device 1540. Furthermore, the photoelectric conversion system 1500 incorporating the semiconductor device 100 can be applied to transportation equipment equipped with driving devices, such as ships, aircraft, railroad vehicles, and industrial robots, in addition to vehicles such as automobiles. In addition, the present invention can be applied to a wide range of equipment that uses object recognition, such as an intelligent transport system (ITS), in addition to moving objects.

[0088] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0089] 100: semiconductor device, 101: integrated circuit, 105: control unit

Claims

1. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that performs control to deactivate the second element when the degradation in performance of the first element is a first degree, and to operate the second element when the degradation in performance of the first element is a second degree that is greater than the first degree; Including, the integrated circuit includes a plurality of the second elements; The control unit changes the number of second elements to be operated among the plurality of second elements when the deterioration in performance of the first element is at the second degree and when the deterioration is at a degree between the first degree and the second degree.

2. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that operates the second element when a degradation signal indicating degradation of the performance of the first element is received, and that controls the second element to be inoperative when the degradation signal is not received; Including, the integrated circuit includes a plurality of the second elements; the degradation signal is a multi-value signal corresponding to a degradation in performance of the first element, The control unit changes the number of second elements to be operated among the plurality of second elements based on the degradation signal corresponding to the degradation of performance of the first element.

3. The photoelectric conversion device according to claim 2, characterized in that when the degradation signal is not received, a signal indicating that the degradation in performance of the first element is smaller than when the degradation signal is generated is received.

4. the integrated circuit further includes a third element; 4. The photoelectric conversion device according to claim 2, wherein the decrease signal includes a signal indicating a state of the third element.

5. the integrated circuit further includes a monitor circuit for monitoring a state of the first element; 5. The photoelectric conversion device according to claim 2, wherein the monitor circuit supplies the degradation signal to the control unit in accordance with a degree of degradation in performance of the first element.

6. the integrated circuit further includes a fourth element for performing an operation different from the predetermined operation; 6. The photoelectric conversion device according to claim 5, wherein the fourth element is disposed in a region other than between the first element and the monitor circuit.

7. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that operates the second element when a degradation signal indicating degradation of the performance of the first element is received, and that controls the second element to be inoperative when the degradation signal is not received; Including, the integrated circuit further includes a monitor circuit for monitoring a state of the first element; the monitor circuit supplies the degradation signal to the control unit in response to a degree of degradation in performance of the first element; the integrated circuit further includes a fourth element for performing an operation different from the predetermined operation; a fourth element disposed in a region other than between the first element and the monitor circuit;

8. 8. The photoelectric conversion device according to claim 6, wherein the distance between the fourth element and the monitor circuit is greater than the distance between the first element and the monitor circuit.

9. the monitor circuit includes an oscillator circuit; 9. The photoelectric conversion device according to claim 5, wherein the monitor circuit supplies the decrease signal to the control unit in response to an oscillation frequency of the oscillation circuit.

10. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that operates the second element when a degradation signal indicating degradation of the performance of the first element is received, and that controls the second element to be inoperative when the degradation signal is not received; Including, the integrated circuit further includes a monitor circuit for monitoring a state of the first element; the monitor circuit supplies the degradation signal to the control unit in response to a degree of degradation in performance of the first element; the monitor circuit includes an oscillator circuit; The photoelectric conversion device according to claim 1, wherein the monitor circuit supplies the decrease signal to the control unit in response to an oscillation frequency of the oscillation circuit.

11. The predetermined operation is a first operation, and the control unit is a first control unit. The integrated circuit comprises: a fifth element for performing a second operation; and A sixth element; and a control unit that performs control to deactivate the sixth element when the deterioration in performance of the fifth element is a third degree, and to operate the sixth element when the deterioration in performance of the fifth element is a fourth degree that is greater than the third degree; 11. The photoelectric conversion device according to claim 1, further comprising:

12. the predetermined operation as a first operation, the decrease signal as a first signal, the control unit as a first control unit, and the monitor circuit as a first monitor circuit; The integrated circuit comprises: a fifth element for performing a second operation; and A sixth element; and a control unit that operates the sixth element when a second signal indicating a deterioration in performance of the fifth element is received, and that controls the sixth element to be inoperative when the second signal is not received; 11. The photoelectric conversion device according to claim 5, further comprising:

13. 13. The photoelectric conversion device according to claim 12, wherein a distance between the first element and the first monitor circuit is shorter than a distance between the fifth element and the first monitor circuit.

14. the photoelectric conversion device further includes an external monitor circuit for monitoring a state of the first element, the external monitor circuit being separate from the integrated circuit; 11. The photoelectric conversion device according to claim 2, wherein the external monitor circuit supplies the degradation signal to the control unit in accordance with a degree of degradation in performance of the first element.

15. 15. The photoelectric conversion device according to claim 14, wherein the external monitor circuit supplies the decrease signal to the control unit in response to at least one of a temperature of the first element, an operating voltage, a total current-carrying time, and a toggle rate.

16. the first element includes a clock buffer that configures a clock tree; 16. The photoelectric conversion device according to claim 1, wherein the second element includes an element that functions as the clock buffer.

17. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that performs control to deactivate the second element when the degradation in performance of the first element is a first degree, and to operate the second element when the degradation in performance of the first element is a second degree that is greater than the first degree; Including, the first element includes a clock buffer that configures a clock tree; The photoelectric conversion device, wherein the second element includes an element that functions as the clock buffer.

18. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that operates the second element when a degradation signal indicating degradation of the performance of the first element is received, and that controls the second element to be inoperative when the degradation signal is not received; Including, the first element includes a clock buffer that configures a clock tree; The photoelectric conversion device, wherein the second element includes an element that functions as the clock buffer.

19. the first element includes a power cutoff switch for cutting off the supply of power to a portion of the integrated circuit; 19. The photoelectric conversion device according to claim 1, wherein the second element includes an element that functions as the power cutoff switch.

20. the integrated circuit operates in a plurality of operating modes; 20. The photoelectric conversion device according to claim 1, wherein the control unit deactivates the second element when switching from a first operating mode to a second operating mode, the first operating mode being different from the second operating mode among the plurality of operating modes.

21. the integrated circuit includes a plurality of the second elements; 21. The photoelectric conversion device according to claim 20, wherein the control unit changes the number of second elements to be operated among the plurality of second elements in accordance with each of the plurality of operation modes.

22. the first element includes a drive circuit for driving the photoelectric conversion unit, 22. The photoelectric conversion device according to claim 1, wherein the second element includes an element that functions as the drive circuit.

23. the first element includes an output buffer circuit disposed in the drive circuit; 23. The photoelectric conversion device according to claim 22, wherein the second element includes an element that functions as the output buffer circuit.

24. 24. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device has a laminated structure including a first layer having the photoelectric conversion section and a second layer having the integrated circuit.

25. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that performs control to deactivate the second element when the degradation in performance of the first element is a first degree, and to operate the second element when the degradation in performance of the first element is a second degree that is greater than the first degree; Including, The photoelectric conversion device has a laminated structure including a first layer having the photoelectric conversion section and a second layer having the integrated circuit.

26. An integrated circuit; A photoelectric conversion unit in which a plurality of pixels are arranged, each of which includes a photoelectric conversion element for converting incident light into an electrical signal, The integrated circuit comprises: A first element that performs a predetermined operation; A second element; and a control unit that operates the second element when a degradation signal indicating degradation of the performance of the first element is received, and that controls the second element to be inoperative when the degradation signal is not received; Including, The photoelectric conversion device has a laminated structure including a first layer having the photoelectric conversion section and a second layer having the integrated circuit.

27. A photoelectric conversion device according to any one of claims 1 to 26, an optical system for forming an image on the photoelectric conversion unit of the photoelectric conversion device; a signal processing unit that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

28. 27. A transportation device having a drive unit, the transportation device being equipped with a photoelectric conversion device according to claim 1, and further comprising a control device that controls the drive unit based on information obtained by the photoelectric conversion device.

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