Route Monitoring on FPGA using Satellite ADC

Abstract

Systems and methods for monitoring several operating conditions of a programmable device are disclosed. In some implementations, the system may include a route monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed throughout the programmable device, and an interconnection system coupled to the route monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be proximate a corresponding one of the plurality of sensors and coupled to them via a local interconnect. The interconnection system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors and may include one or more digital channels configured to selectively route digital data as data packets from each of the plurality of satellite monitors to the root monitor.

Description

[Technical field]

[0001] The present disclosure relates generally to integrated circuits, and more particularly to monitoring one or more operational aspects of an integrated circuit. [Background technology]

[0002] A programmable logic device (PLD) is a device that can be programmed by a user to implement various user-specified circuit designs. One example of a PLD is a field programmable gate array (FPGA). An FPGA may contain an array of configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), input / output blocks (IOBs), digital signal processors (DSPs), several processing cores, and other subsystems (such as memory controllers, device management resources, and configuration circuitry) that can be selectively connected to each other by a programmable interconnect structure. A user-specified circuit design can be implemented in a programmable device by loading configuration data representing the user-specified circuit design into configuration registers that collectively determine the functions and operations performed by the various blocks, interconnect structures, and subsystems of the programmable device.

[0003] Electrical components within a programmable device typically operate within a range of specified operating conditions. As one example, an electrical component may be designed to operate within a specified temperature range and may be disabled or turned off if the operating temperature rises above a certain level. As another example, a supply voltage is typically maintained between a minimum and a maximum voltage level to provide a relatively constant operating voltage to other electrical components provided within the programmable device. As the size and complexity of programmable devices increases, while using lower supply voltages and smaller device geometries, the precision with which the device's operating conditions can be monitored becomes increasingly important. Summary of the Invention

[0004] This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Moreover, the systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.

[0005] One innovative aspect of the subject matter described in this disclosure can be implemented to monitor the operating conditions of various circuits and components distributed throughout a programmable device. In some implementations, the programmable device may include a plurality of configurable logic resources, a root monitor, a number of sensors distributed at various locations throughout the programmable device, a plurality of satellite monitors distributed at various locations throughout the programmable device, and a network interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the plurality of satellite monitors. Each of the sensors may be configured to measure an operating condition of an associated circuit at a corresponding one of the various locations and may provide an analog signal indicative of the measured operating condition to a corresponding one of the satellite monitors. In some aspects, the operating condition may include at least one of a temperature or a voltage level of the associated circuit.

[0006] Each of the satellite monitors may include an analog-digital converter (ADC) having an input for receiving analog signals from one or more associated sensors and having an output for providing digital data to the network interconnect system. The ADC may convert the analog signals into digital data indicative of the operating status of the one or more associated sensors and may provide the digital data via the network interconnect system to the route monitor.

[0007] The route monitor may include circuitry configured to generate a reference voltage and may include a memory configured to store digital data received from the plurality of satellite monitors. In some implementations, the route monitor may include a bandgap reference circuit that compensates the reference voltage for temperature changes. Additionally or alternatively, the route monitor may include a controller configured to determine whether a measured operating condition of an associated circuit is within a range. In some aspects, the controller may be further configured to generate an alarm based on a determination indicating that the measured operating condition is not within a range.

[0008] The network interconnection system may be configured to distribute the reference voltage from the route monitor to each of the plurality of satellite monitors and may be configured to selectively route the digital data from each of the plurality of satellite monitors to the route monitor. In some implementations, the network interconnection system may include one or more analog channels configured to distribute the reference voltage from the route monitor to each of the plurality of satellite monitors and may include one or more digital channels configured to selectively route the digital data from the satellite monitor to the route monitor. In some aspects, the digital data may be routed through the network interconnection system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnection system as non-packetized digital signals.

[0009] In some implementations, each of the satellite monitors may include a switch configured to selectively couple a reference voltage distributed by the interconnect system to the satellite monitor based on a control signal. The control signal may be generated by the route monitor and distributed to the corresponding satellite monitor via the network interconnect system (or by other suitable signal interconnect). In some aspects, the route monitor may selectively assert the control signal based on a timing schedule that allows only one of the satellite monitors to access the reference voltage distributed from the network interconnect system at any given time.

[0010] An example system for monitoring several operating conditions of a programmable device may include a route monitor, a plurality of sensors distributed throughout the programmable device, a plurality of satellite monitors distributed throughout the programmable device, and a network interconnect system coupled to at least the route monitor and each of the plurality of satellite monitors. The route monitor may include a circuit device configured to generate a reference voltage usable to perform analog-to-digital conversion. In some implementations, the route monitor may include a bandgap reference circuit that compensates the reference voltage for temperature changes. Additionally or alternatively, the route monitor may include a controller configured to determine whether a measured operating condition of an associated circuit is within a range. In some aspects, the controller may be further configured to generate an alarm based on a determination indicating that the measured operating condition is not within a range.

[0011] Each of the sensors may be configured to generate an analog signal indicative of the operating status of an associated circuit, and each of the satellite monitors may be configured to convert the analog signals generated by one or more associated sensors into digital data that may be routed to the root monitor via the network interconnection system.

[0012] The network interconnect system may include one or more analog channels configured to distribute a reference voltage to each of the plurality of satellite monitors and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor. In some aspects, the digital data may be routed through the network interconnect system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnect system as unpacketized digital signals.

[0013] Each of the satellite monitors may include an analog-to-digital converter (ADC) configured to convert analog signals to digital data. In some implementations, each of the satellite monitors may include a switch configured to selectively couple a reference voltage distributed by the interconnect system to the satellite monitor based on a control signal. The control signal may be generated by the route monitor and distributed to the corresponding satellite monitor via the network interconnect system (or by other suitable signal interconnect). In some aspects, the route monitor may selectively assert the control signal based on a timing schedule that allows only one of the satellite monitors to access the reference voltage distributed from the network interconnect system at any given time.

[0014] Illustrative methods disclosed herein may be used to monitor several operating conditions of a programmable device. The method may include generating a reference voltage using a voltage generator associated with a route monitor provided within the programmable device, and distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of a network interconnect system integrated within the programmable device. In some implementations, distributing the reference voltage may include selectively coupling each of the plurality of satellite monitors to the network interconnect system based on a corresponding control signal. The control signal may be generated by the route monitor and distributed by the network interconnect system to the plurality of satellite monitors. In some aspects, the route monitor may selectively assert the control signal based on a timing schedule that allows only one of the satellite monitors to access the distributed reference voltage from the network interconnect system at any one time.

[0015] The method may also include generating, using each of the several sensors, an analog signal indicative of an operating condition of an associated circuit, and providing the analog signal to a corresponding one of the plurality of satellite monitors. The analog signal may be converted to digital data using the plurality of satellite monitors, and the digital data may be selectively routed from the plurality of satellite monitors to a root monitor using one or more digital channels of the network interconnect system. In some aspects, the digital data may be routed through the network interconnect system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnect system as non-packetized digital signals.

[0016] The method may also include determining whether an operating condition of the associated circuits is within a range and selectively generating one or more alarms based on the determination. In some implementations, an alarm may be generated when an operating condition of at least one of the associated circuits is not within a range, which may indicate that at least one of the associated circuits is operating outside of a particular condition.

[0017] One innovative aspect of the subject matter described in this disclosure can be implemented to monitor the operating conditions of various circuits and components distributed throughout a programmable device. In some implementations, the programmable device may include programmable logic including a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed at various locations throughout the programmable device, and a plurality of satellite monitors distributed at various locations throughout the programmable device. Each of the sensors may be configured to generate an analog signal indicative of a measured operating condition of one or more associated circuits in the vicinity of a corresponding one of the various locations and may provide the analog signal to an associated one of the satellite monitors via one or more local signal lines. In some aspects, the operating condition may include at least one of a temperature or a voltage level of the associated circuit.

[0018] The route monitor may include a bandgap voltage generator configured to generate a temperature independent reference voltage and may include a memory for storing digital data received from the plurality of satellite monitors. The route monitor may also include a controller configured to determine whether a measured operating condition of an associated circuit is within a range. In some aspects, the controller may be further configured to generate an alarm based on a determination indicating that the measured operating condition is not within a range.

[0019] Each of the satellite monitors may include a relatively small local voltage source configured to generate a local reference voltage, an analog-to-digital converter (ADC), a calibration circuit, and a correction circuit. The ADC may include a reference terminal for receiving the local reference voltage and may be configured to convert an analog signal generated by one or more associated sensors into a digital code indicative of a measured operating condition. The calibration circuit may be configured to generate a correction factor indicative of an error in the digital code, and the correction circuit may be configured to correct the digital code generated by the ADC based on the correction factor.

[0020] In some implementations, each of the satellite monitors may include a switch including a first input terminal coupled to receive a temperature independent reference voltage, a second input terminal coupled to receive an analog signal generated by one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of an ADC in the satellite monitor. During a calibration operation, the switch may provide the temperature independent reference voltage as an input signal to the ADC, and the ADC may sample the temperature independent reference voltage to generate a reference code. The calibration circuit may generate a correction factor based on a difference between the reference code generated by the ADC and a predetermined digital code indicative of the temperature independent reference. During a monitoring operation, the switch may provide an analog signal from the sensor as an input signal to the ADC, and the ADC may sample the analog signal from the one or more associated sensors to generate a digital code, and the correction circuit may use the correction factor to correct the digital code.

[0021] The root monitor may generate the control signal based at least in part on a timing schedule for calibrating the multiple satellite monitors. In some implementations, the timing schedule may be configured to sequentially enable calibration of each of the multiple satellite monitors by allowing only one of the satellite monitors to simultaneously access the temperature independent reference voltage.

[0022] In some implementations, the programmable device may include a network-on-chip (NoC) interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the multiple satellite monitors. The NoC interconnect system may be configured to route control signals from the root monitor to each of the multiple satellite monitors and may be configured to selectively route digital data from each of the multiple satellite monitors to the root monitor. Additionally, or in another manner, the programmable device may include one or more analog channels configured to distribute a temperature independent reference voltage from the root monitor to each of the multiple satellite monitors.

[0023] Illustrative methods disclosed herein may be used to monitor the operational status of a plurality of circuits distributed at various locations throughout a programmable device. In some implementations, the method may include: generating an analog signal indicative of the operational status of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed at various locations throughout the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed at various locations throughout the programmable device; generating a local reference voltage using a local voltage source at each of the plurality of satellite monitors; converting a corresponding one of the plurality of analog signals to a digital code using an analog-to-digital converter (ADC) at each of the plurality of satellite monitors based on the local reference voltage; distributing the temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the distributed temperature-independent reference voltage; and selectively routing the corrected digital code from each of the plurality of satellite monitors to the root monitor. In some implementations, distributing the temperature-independent reference voltage may include sequentially enabling each of the multiple satellite monitors to access the temperature-independent reference voltage based on corresponding multiple control signals generated by the root monitor.

[0024] In some implementations, the corrected digital code may be selectively routed from the multiple satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system linking the programmable logic, and the temperature-independent reference voltage may be distributed from the root monitor to the multiple satellite monitors using one or more analog channels linking the programmable logic. In some implementations, correcting the digital code may include providing the temperature-independent reference voltage as an input signal to an ADC, converting the temperature-independent reference voltage to a reference code using the ADC, generating a correction factor based on a difference between the reference code and a predetermined digital code indicative of the temperature-independent reference voltage, and adjusting the digital code based on the correction factor.

[0025] One innovative aspect of the subject matter described in this disclosure can be implemented to monitor the operating conditions of various circuits and components distributed throughout a programmable device. In some implementations, the programmable device may include programmable logic including a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed at various locations throughout the programmable device, and a plurality of satellite monitors distributed at various locations throughout the programmable device. Each of the sensors may be configured to generate an analog signal indicative of a measured operating condition of one or more associated circuits in the vicinity of a corresponding one of the various locations and may provide the analog signal to an associated one of the satellite monitors via one or more local signal lines. In some aspects, the operating condition may include at least one of a temperature or a voltage level of the associated circuit.

[0026] The route monitor may include a bandgap voltage generator configured to generate a temperature independent reference voltage and may include a memory for storing digital data received from the plurality of satellite monitors. The route monitor may also include a controller configured to determine whether a measured operating condition of an associated circuit is within a range. In some aspects, the controller may be further configured to generate an alarm based on a determination indicating that the measured operating condition is not within a range.

[0027] Each of the satellite monitors may include a voltage store configured to store a local reference voltage based on a temperature-independent reference voltage generated by the bandgap voltage generator, an analog-to-digital converter (ADC), a calibration circuit, and a correction circuit. The ADC may include a reference terminal for receiving the local reference voltage and may be configured to convert an analog signal generated by one or more associated sensors into a digital code indicative of a measured operating condition. The calibration circuit may be configured to generate a correction factor indicative of an error in the digital code, and the correction circuit may be configured to correct the digital code generated by the ADC based on the correction factor.

[0028] In some implementations, each of the satellite monitors may include a first switch and a second switch. The first switch may include a first input terminal coupled to receive a temperature independent reference voltage, a second input terminal coupled to receive an analog signal generated by one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of an ADC in the satellite monitor. The second switch may include an input terminal coupled to receive the temperature independent reference voltage, a control terminal coupled to receive a control signal, and an output terminal coupled to a voltage store.

[0029] During a calibration operation, the first switch may provide a temperature independent reference voltage as an input signal to the ADC, the second switch may isolate the voltage store from the temperature independent reference voltage, and the ADC may sample the temperature independent reference voltage to generate a reference code. The calibration circuit may generate a correction factor based on a difference between the reference code generated by the ADC and a predetermined digital code indicative of the temperature independent reference. During a monitoring operation, the first switch may provide an analog signal from the sensor as an input signal to the ADC, the second switch may provide a temperature independent reference voltage to the voltage store, the ADC may sample analog signals from one or more associated sensors to generate a digital code, and the correction circuit may use the correction factor to correct the digital code.

[0030] The root monitor may generate the control signal based at least in part on a timing schedule for calibrating the multiple satellite monitors. In some implementations, the timing schedule may be configured to sequentially enable calibration of each of the multiple satellite monitors by allowing only one of the satellite monitors to simultaneously access the temperature independent reference voltage.

[0031] In some implementations, the programmable device may include a network-on-chip (NoC) interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the multiple satellite monitors. The NoC interconnect system may be configured to route control signals from the root monitor to each of the multiple satellite monitors and may be configured to selectively route digital data from each of the multiple satellite monitors to the root monitor. Additionally, or in another manner, the programmable device may include one or more analog channels configured to distribute a temperature-independent reference voltage from the root monitor to each of the multiple satellite monitors.

[0032] Illustrative methods disclosed herein may be used to monitor the operational status of a plurality of circuits distributed at various locations throughout a programmable device. In some implementations, the method may include: generating an analog signal indicative of the operational status of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed at various locations throughout the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed at various locations throughout the programmable device; storing, at each of the plurality of satellite monitors, a local reference voltage based on a temperature independent reference voltage; converting, at each of the plurality of satellite monitors, the corresponding one of the plurality of analog signals to a digital code using an analog-to-digital converter (ADC) based on the local reference voltage; distributing the temperature independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the distributed temperature independent reference voltage; and selectively routing the corrected digital code from each of the plurality of satellite monitors to the root monitor. In some implementations, the voltage store may be a capacitor and the local reference voltage may be relatively inaccurate compared to the temperature independent reference voltage. In some implementations, distributing the temperature independent reference voltage may include sequentially enabling each of the multiple satellite monitors to access the temperature independent reference voltage based on corresponding control signals generated by the root monitor.

[0033] The corrected digital code may be selectively routed from the multiple satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system linking the programmable logic, and the temperature-independent reference voltage may be distributed from the root monitor to the multiple satellite monitors using one or more analog channels linking the programmable logic. In some implementations, correcting the digital code may include providing the temperature-independent reference voltage as an input signal to an ADC, converting the temperature-independent reference voltage to a reference code using the ADC, generating a correction factor based on a difference between the reference code and a predetermined digital code indicative of the temperature-independent reference voltage, and adjusting the digital code based on the correction factor.

[0034] Example implementations are illustrated by way of example and are not intended to be limiting by the figures of the accompanying drawings. Like numbers refer to like elements throughout the drawings and specification. It should be noted that the relative dimensions of the following figures may not be drawn to scale. [Brief description of the drawings]

[0035] [Figure 1] FIG. 1 is a block diagram of an example programmable device in which various aspects of the present disclosure may be implemented. [Diagram 2] 2 is a functional block diagram of a portion of the programmable device of FIG. 1 according to some implementations. [Diagram 3] FIG. 2 is a block diagram of an example programmable fabric in accordance with some implementations. [Figure 4] FIG. 1 is a functional block diagram of a monitoring system, according to some implementations. [Diagram 5] 1 is a block diagram of an example route monitor, according to some implementations. [Figure 6] 1 is a block diagram of an example satellite monitor, according to some implementations. [Figure 7]1 is an illustrative flowchart depicting example operations for monitoring certain operational aspects of a programmable device, according to some implementations. [Figure 8] FIG. 1 is a block diagram of an example programmable device in which various aspects of the present disclosure may be implemented. [Figure 9] 9 is a functional block diagram of a portion of the programmable device of FIG. 8 according to some implementations. [Figure 10] FIG. 2 is a block diagram of an example programmable fabric in accordance with some implementations. [Figure 11] FIG. 1 is a functional block diagram of a monitoring system, according to some implementations. [Figure 12] 1 is a block diagram of an example route monitor, according to some implementations. [Figure 13] 1 is a block diagram of an example satellite monitor, according to some implementations. [Figure 14] 1 is an illustrative flowchart depicting example operations for monitoring certain operational aspects of a programmable device, according to some implementations. [Figure 15] 1 is an illustrative flowchart depicting example operations for correcting a digital code, according to some implementations. [Figure 16] 1 is a block diagram of an example satellite monitor, according to some implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Implementations of the subject matter described in this disclosure may be used to monitor several operating conditions of a programmable device. The operating conditions may be any suitable indication of an operating characteristic or parameter of the device, including, for example, the temperature of circuits or components provided within the programmable device, the temperature of circuits or devices external to the programmable device, the voltage level of a supply voltage, and the like. According to some aspects of the present disclosure, a monitoring system may be implemented within a programmable device that includes programmable logic, dedicated circuitry such as processors and DSPs, and a network interconnect system (capable of routing information between the programmable logic, the dedicated circuitry, and other circuits or components of the programmable device using individually addressable data packets).

[0037] The monitoring system may include a root monitor, a number of sensors distributed at various locations throughout the programmable device, and a number of satellite monitors distributed at various locations throughout the programmable device. Each of the sensors may generate an analog signal indicative of one or more operational conditions of an associated circuit and may provide the analog signal to a corresponding one of the satellite monitors. Each of the satellite monitors may include an ADC for converting the analog signal to digital data, and the network interconnect system may route the digital data from each of the satellite monitors to the root monitor. In some implementations, each of the satellite monitors may be positioned in proximity to a corresponding sensor such that an analog signal generated by the corresponding sensor is routed a relatively short distance via a local signal wire to the corresponding satellite monitor for conversion to digital data, rather than being routed across the programmable device to the root monitor for conversion to digital data.

[0038] In other implementations, the digital data generated by the satellite monitors may be routed to the root monitor using a clock distribution network, a programmable interconnect fabric, and / or other suitable routing resources provided within the device, including (but not limited to) routing resources provided within each of the programmable logic tiles within the device.

[0039] The root monitor may receive, via the network interconnection system, the digital data generated by each of the satellite monitors and may analyze the digital data to determine if one or more of the circuits being monitored are not operating within a specified operating range. In some implementations, the root monitor may generate a trimmed and temperature compensated reference voltage, and the network interconnection system may distribute the trimmed and temperature compensated reference voltage to each of the satellite monitors throughout the device.

[0040] Conventional systems for monitoring the operational status of various circuits distributed throughout a programmable device typically include a central system monitor and a number of sensors located near the circuits to be monitored. Each sensor generates an analog signal indicative of the operational status of the associated circuit, and the analog signal is routed from each of the sensors to the system monitor for conversion to digital data. The sensors are typically distributed at various locations throughout the device, so that analog signals generated by at least some of the sensors may be routed across most of the device to reach the system monitor. Because analog signals indicative of operational status may be particularly susceptible to noise and interference, some programmable devices may use dedicated metal layer routing resources with shielding properties to route these analog signals from the various sensors to the system monitor for conversion to digital data.

[0041] Although the shielding properties of such dedicated metal layer routing resources may reduce signal degradation and data loss, the dedicated metal layer routing resources are expensive and consume a significant amount of the metal layers of the device. Furthermore, because programmable logic is typically implemented as multiple repeatable tiles arranged in several rows or columns, the signal routing resources embedded within each of the repeatable tiles are typically based on a worst-case routing scenario (such as placing the tile in a location with the greatest device density). As a result, many of the repeatable tiles are over-equipped with signal routing resources, which may result in unused routing resources and / or limit the scalability of the programmable device.

[0042] Particular implementations of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages: By introducing multiple satellite monitors with analog-to-digital conversion capabilities at locations throughout the programmable device proximate to sensors monitoring the operational status of various circuits, the monitoring system disclosed herein may use local satellite monitors to convert analog signals generated by the sensors to digital data and then route the digital data from various locations throughout the device to a root monitor. As a result, rather than being routed across most of the device and then converted to digital data, the analog signal is transmitted a relatively short distance to the nearest satellite monitor for conversion to digital data, which is then routed to the root monitor using a network interconnection system. In some aspects, the digital data generated by the satellite monitors may be routed to the root monitor as individually addressable data packets. In other aspects, the digital data generated by the satellite monitors may be routed to the root monitor as non-packetized data. By using satellite monitors located near the sensors to convert analog signals to digital data rather than performing analog-to-digital conversion in the root monitor, the monitoring system disclosed herein may not require metal layer routing resources, reducing costs while improving scalability of the programmable device. Furthermore, performing analog-to-digital conversion locally (e.g., near the sensors) and routing the resulting digital data from the satellite monitors to the root monitor may allow more sensor data to be collected and analyzed by the root monitor (compared to traditional techniques that route analog signals from various sensors throughout the device to ADCs provided in the system monitor), since, for example, ADCs distributed throughout the programmable device may perform analog-to-digital conversion in parallel (e.g., simultaneously).

[0043] In the following description, numerous specific details are given, such as examples of specific components, circuits, and processes, to fully understand the present disclosure. The term "coupled" as used herein means directly coupled or coupled through one or more intervening components or circuits. In addition, in the following description, and for purposes of explanation, specific terminology and / or details are given to fully understand the implementation of the examples. Nevertheless, it will be apparent to those skilled in the art that these specific details may not be required to practice the implementation of the examples. In other examples, well-known circuits and devices are shown in block diagram form so as not to obscure the present disclosure. Any of the signals provided on the various buses described herein may be time-shared with other signals and provided on one or more common buses. Furthermore, the interconnections between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, each of the single signal lines may alternatively be a bus, and the single line or bus may represent any one or more of the myriad physical or logical mechanisms for communication between the components. Example implementations should not be construed as limited to the specific examples described herein, but rather should include within their scope all implementations defined by the appended claims.

[0044] FIG. 1 illustrates a block diagram of an example programmable device 100 in which various aspects of the disclosure may be implemented. The device 100 may include several subsystems, such as, for example, a programmable logic (PL) 110, a network interconnect system 120, a processing and management resource (PMR) 130, a CCIX and PCIe module (CPM) 140, a transceiver block 150, an input / output (I / O) block 160, a memory controller 170, a configuration logic 180, a route monitor 190, a number of satellite monitors 192(1)-192(19), and several sensors (S). In one or more implementations, the device 100 may include other subsystems or components not shown in FIG. 1. Additionally, although not shown for simplicity, the device 100 may be coupled to several peripheral components (such as a high-performance memory device) and / or other devices or chips (such as another programmable device).

[0045] The PL 110 includes programmable circuitry that can be configured or programmed to perform a number of different user-defined functions or operations. In some implementations, the PL 110 can include a number of programmable circuit blocks implemented as repeatable tiles arranged in columns within the programmable device 100, for example, as depicted in FIG. 1. The programmable circuit blocks can be referred to as programmable fabric subregions (FSRs) and can include programmable interconnect circuitry and programmable logic circuitry, respectively. In some implementations, the programmable circuit blocks can include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAMs), digital signal processing blocks (DSPs), clock managers, delay-locked loops (DLLs), and / or other logic or circuitry that can be programmed or configured to implement a user-specified circuit design.

[0046] The programmable interconnect circuitry in each of the programmable circuit blocks or tiles may include multiple interconnect wires of various lengths interconnected by programmable interconnect points (PIPs). The interconnect wires may be configured to provide connections between components within a particular programmable tile, between components within different programmable tiles, and between components of a programmable tile and other subsystems or devices. The programmable interconnect circuitry and the programmable circuit blocks may be programmed or configured by loading configuration data into configuration registers that define how the programmable elements are configured and operate to implement the corresponding user-specified circuit design. In some aspects, the programmable interconnect circuitry in each of the several programmable circuit blocks may form part of a programmable interconnect fabric (not shown for simplicity) that provides block-level and / or device-level signal routing resources to the device 100.

[0047] Network interconnect system 120 may be fabricated as part of device 100 and may include any number of horizontal and vertical segments (and / or diagonal segments) connected together to implement a high-speed, high-bandwidth programmable signal routing network selectively interconnectable with various device resources (such as PL 110, PMR 130, CPM 140, transmit / receive block 150, I / O block 160, memory controller 170, configuration logic 180, route monitor 190, and satellite monitors 192(1)-192(19)) with each other and with other components not shown for simplicity. For the example implementation of FIG. 1, network interconnect system 120 is shown to include two horizontal segments and four vertical segments. A first horizontal segment that extends across the width of device 100 is positioned along a bottom boundary of device 100, and a second horizontal segment that extends across the width of device 100 is positioned along a top boundary of device 100. The four vertical segments extend across the entire height of the device 100 and are connected to first and second horizontal segments of the network interconnect system 120. In some aspects, the horizontal segments may enable the network interconnect system 120 to exchange signals and data with the I / O block 160 and the memory controller 170 without intervening circuits or interfaces, and the vertical segments may enable the network interconnect system 120 to exchange signals and data with the transceiver block 150, the processing and management resources (PMR) 130, and the CPM 140 without intervening circuits or interfaces. In other implementations, the network interconnect system 120 may include other numbers of horizontal and vertical segments, and these segments may occupy other positions in the device 100. Thus, the particular layout, shape, size, orientation, and other physical characteristics of the example network interconnect system 120 depicted in FIG. 1 are merely illustrative of various implementations disclosed herein.

[0048] The network interconnect system 120 may be configured to transmit information between various device resources as data packets that are individually addressable and routable from a source location to a destination location. In some aspects, data packets transmitted over the network interconnect system 120 may be dynamically addressable. In one or more implementations, the network interconnect system 120 may route data packets from any number of source locations to any number of destination locations using an appropriate data packet protocol (such as a token ring protocol) and / or using memory-mapped addresses. The data packets may include header information (such as a source address, a destination address, and protocol information) usable by the network interconnect system 120 to route the data packet to its designated destination.

[0049] In some implementations, the data packets may include quality of service (QoS) information that allows transmission of the data packets through the network interconnect system 120 to be prioritized based, for example, on assigned priority, traffic type, traffic flow, and / or other measures. In such implementations, the network interconnect system 120 may include priority logic capable of determining a priority level or traffic class of a received data packet and may use the determined priority level or traffic class when queuing the data packet for transmission. By transmitting information between various device resources as individually addressable data packets, the network interconnect system 120 may provide connections between various device resources without regard to the particular user-specified circuit design, thereby significantly improving the signal routing capabilities of the device 100 (compared to conventional programmable devices). For example, while the programmable interconnect fabric and other tile-based signal routing structures of device 100 are typically configured to provide point-to-point signal connections between designated circuits, network interconnect system 120 may simultaneously route each of multiple data packets from any source address to any destination address on device 100, thereby providing system-level connectivity to device 100.

[0050] Although not shown for simplicity, the network interconnect system 120 may also include a scheduler and arbitration logic. The scheduler may be used to schedule the transmission of data packets from a source address to a destination address using one or more physical and / or virtual channels of the network interconnect system 120. The arbitration logic may be used to arbitrate access to the network interconnect system 120, for example, to minimize collisions and other contention-related latencies. For implementations in which the device 100 is fabricated using stacked silicon interconnect (SSI) technology, the columnar portions of the network interconnect system 120 may provide signal connections between adjacent super logic regions (SLRs), for example, to allow configuration data to be routed between the master SLR and the slave SLR.

[0051] The network interconnect system 120 may be programmed by loading configuration data into corresponding configuration registers that define how various switches, interfaces, and routers within or associated with the network interconnect system 120 are configured to implement a particular user-specified circuit design. In some implementations, the network interconnect system 120 may include multiple nodes, ports, or other interfaces (not shown for simplicity) that provide selective connections between the network interconnect system 120 and various resources, subsystems, circuits, and other components of the device 100. For example, the network interconnect system 120 may enable multiple subsystems of the device 100 to share on-chip memory (OCM) resources, processing resources, I / O resources, and / or access to the transmit / receive block 150. The nodes, ports, or other interfaces of the network interconnect system 120 may be programmed to implement a particular connection profile by loading configuration data into certain associated configuration registers.

[0052] By selectively interconnecting various resources, subsystems, circuits, and other components of device 100 that may require and use large amounts of data, network interconnect system 120 may relieve signal routing loads on local interconnect resources, thereby improving device performance and allowing greater configuration flexibility than other programmable devices. Moreover, by providing a high-performance signal routing network with higher data transmission rates and lower error rates than device-level and block-level programmable interconnects, network interconnect system 120 may increase the processing power and data throughput of device 100 (relative to other programmable devices).

[0053] The processing and management resource (PMR) 130 may provide dedicated data processing capabilities and platform management resources to the device 100. The PMR 130 may include a processing system (PS) and a platform management controller (PMC), as described in more detail with respect to FIG. 2. In some implementations, the PS may include several processor cores, cache memory, a memory controller, and unidirectional and / or bidirectional interfaces configurable to directly couple to I / O pins of the device 100. In some aspects, each processor core may include a central processing unit (CPU) or scalar processor available for sequential data processing. The PMC may be used to boot and configure the device 100 based on configuration data (such as a configuration bitstream) provided from an external memory. The PMC may also be used to configure the PL 110 and to control various encryption, authentication, route monitoring, and debug capabilities of the device 100.

[0054] CCIX and PCIe module (CPM) 140 may include several interfaces that provide connections between device 100 and several peripheral components (such as external devices or chips). In some implementations, CPM 140 may include several Peripheral Interconnect Express (PCIe) and Cache Coherent Interconnect for Accelerators (CCIX) interfaces that provide connections to other devices or chips via transceiver block 150. In some aspects, the PCIe and CCIX interfaces may be implemented as part of transceiver block 150. One example implementation of CPM 140 is described with respect to FIG. 2.

[0055] The transmit / receive block 150 may provide signal connections with one or more other devices or chips (not shown for simplicity) connected to the device 100. The transmit / receive block 150 may include several different serial transceivers, such as, for example, Gigabit serial transceivers (GTs). In some implementations, the transmit / receive block 150 may be implemented as several repeatable tiles positioned at various locations along the right and left sides of the device 100, as depicted in FIG. 1. In other implementations, the transmit / receive block 150 may be positioned at other suitable locations on the device 100. In one or more implementations, each of the transmit / receive blocks 150 may be coupled to one or more associated voltage supplies (not shown for simplicity). In some aspects, each bank of transmit / receive circuits in a given transmit / receive block 150 may include or be coupled to a corresponding voltage supply, such that, for example, each bank of transmit / receive circuits may be powered using a separate voltage supply.

[0056] I / O blocks 160 may be coupled to I / O pins (not shown for simplicity) of the device and provide I / O capabilities to device 100. For example, I / O blocks 160 may receive data from one or more other devices and move the received data to several destinations within device 100. I / O blocks 160 may also receive data from several sources within device 100 and move the received data to one or more other devices via I / O pins of the device. In some implementations, I / O blocks 160 may be implemented as repeatable tiles. Device 100 may include any suitable number of I / O blocks 160, and thus the example implementation depicted in FIG. 1 is merely illustrative.

[0057] I / O block 160 may include any number of suitable I / O circuits or devices. In some implementations, I / O block 160 may include ultra-high performance I / O (XPIO) circuits, high density I / O (HDIO) circuits, and multiplexed I / O (MIO) circuits. XPIO circuits may be optimized for high performance communications, such as providing a high speed low latency interface to memory controller 170. In one or more implementations, XPIO circuits may include dedicated memory resources accessible by other subsystems of device 100 without using memory controller 170. HDIO circuits may provide a cost-effective solution supporting lower speed and higher voltage I / O capabilities (compared to XPIO circuits). MIO circuits may provide general purpose I / O resources accessible by various subsystems, such as, for example, PL 110, PMR 130, and CPM 140.

[0058] The memory controller 170 may be used to control access to various memory resources provided within and / or outside the device 100. In some implementations, the memory controller 170 may be used to access dedicated memory residing in one or more of the I / O blocks 160. The memory controller 170 may include a double data rate v4 (DDR4) memory controller, a high bandwidth memory (HBM) controller, and / or other suitable memory controller. In one or more implementations, some or all of the memory controllers 170 may include a scheduler with transaction reordering capabilities that may improve memory access efficiency. Additionally, or in another manner, the repeatable tiles implementing the memory controllers 170 may differ from one another. For example, a first number of the memory controllers 170 may implement a DDR4 memory controller, a second number of the memory controllers 170 may implement a LPDDR4 memory controller, and a third number of the memory controllers 170 may implement an HBM controller.

[0059] Device 100 may include any number of I / O blocks 160 and memory controllers 170, and thus the number and location of I / O blocks 160 and memory controllers 170 depicted in FIG. 1 are merely illustrative. In some implementations, a first row of I / O blocks 160 and memory controllers 170 may be implemented as a repeatable tile positioned along a bottom edge of device 100, and a second row of I / O blocks 160 and memory controllers 170 may be implemented as a repeatable tile positioned along a top edge of device 100. In some implementations, I / O blocks 160 and memory controllers 170 may be interleaved or distributed with respect to each other, for example, as depicted in the example of FIG. 1. In other implementations, pairs of I / O blocks 160 and memory controllers 170 may be implemented within the same repeatable tile.

[0060] In some implementations, a first row of I / O blocks 160 and memory controllers 170 located along the bottom of device 100 may be coupled to a first horizontal segment of network interconnect system 120, and a second row of I / O blocks 160 and memory controllers 170 located along the top of device 100 may be coupled to a second horizontal segment of network interconnect system 120. In this manner, network interconnect system 120 may provide connections between programmable resources of device 100 and its I / O pins (not shown for simplicity).

[0061] In some implementations, device 100 may include one or more columns of connection fabric (not shown for simplicity) that extends vertically across the height of device 100 and is positioned proximate to transmit / receive block 150. The connection fabric may include a number of hardwired circuitry including (but not limited to) a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC (MRMAC), a PCIe controller, a CCIX controller, and / or other components to provide a connection between transmit / receive block 150 and PL 110.

[0062] Configuration logic 180 may be used to load configuration data (such as a configuration bitstream) from external memory, as well as root portions of the configuration data (such as frames, words, bytes, and / or bits), into appropriate configuration registers that define how various programmable resources of device 100 are configured. Configuration logic 180 may also be used to partially reconfigure device 100 and / or to internally reconfigure one or more portions of device 100. In some implementations, configuration logic 180 may include configuration registers, boundary scan test circuitry (such as a TAP controller circuitry), encryption circuitry for encrypting a bitstream of configuration data read from device 100, and decryption circuitry for decrypting a bitstream of configuration data loaded into device 100.

[0063] Although not shown for simplicity, device 100 may include an interface between the programmable fabric and each of the rows of I / O blocks 160 and memory controllers 170 located at the boundaries of device 100. This interface, sometimes referred to herein as a boundary logic interface (BLI), may allow large, complex external devices (such as HBM) to appear as much smaller blocks (such as CLBs) within the programmable fabric of device 100. In some implementations, the BLI may be located in rows located at the top and bottom boundaries or edges of the programmable fabric. In this manner, the BLI may be used to route signals between columnar logic structures (such as CLB columns or DSP columns) and rows of I / O resources (such as I / O blocks 160).

[0064] According to various aspects of the present disclosure, the programmable device 100 may include a monitoring system capable of monitoring one or more operational conditions of a plurality of selected circuits provided throughout the programmable device 100, for example, to ensure that the selected circuits operate within specified operable parameters. The monitoring system disclosed herein may measure any suitable operational condition of the selected circuits, including, for example, temperature, voltage levels, and current levels. As used herein, the term "selected circuit" may refer to any circuit, component, supply voltage, structure, or device that can be selected to monitor one or more operational conditions to ensure proper operation of the device 100. In some implementations, the monitoring system may generate an alarm (or multiple alarms) when one or more measured operational conditions of the selected circuits do not fall within a specified range of operational conditions. In some aspects, the alarm may be used to power down some circuits or components of the device 100. In other aspects, the alarm may be used to power down the entire device 100.

[0065] The monitoring system may include (or may be formed by) a route monitor 190, satellite monitors 192(1)-192(19), sensors (S), and at least a portion of the network interconnection system 120. The route monitor 190 may include circuitry coupled to the network interconnection system 120 and configured to generate a reference voltage. The reference voltage generated by the route monitor 190 may be a trimmed and temperature compensated voltage suitable for analog-to-digital conversion. In some implementations, the route monitor 190 may be located within a processor system of the device 100, for example, as depicted in FIG. 1. In other implementations, the route monitor 190 may be located in other suitable locations within the device 100.

[0066] The reference voltage may be distributed to each of the satellite monitors 192(1)-192(19) via the network interconnection system 120, thereby eliminating the need for multiple voltage generators at various locations throughout the device 100 to provide a reference voltage to each of the satellite monitors 192(1)-192(19). In some implementations, the network interconnection system 120 may include one or more analog channels for distributing the reference voltage from the route monitor 190 to each of the satellite monitors 192(1)-192(19) and may include one or more digital channels for selectively routing digital data from the satellite monitors 192(1)-192(19) to the route monitor 190.

[0067] The sensors (S) may be any suitable sensing circuit or device capable of generating an electrical signal indicative of one or more operating conditions of at least one of the selected circuits, and may include (but are not limited to) a temperature sensor, a voltage sensor, and / or a current sensor. In some implementations, each sensor (S) may measure an operating condition of one or more selected circuits and provide an analog signal indicative of the measured operating condition to a corresponding one of the satellite monitors 192(1)-192(19).

[0068] The satellite monitors 192(1)-192(19) may be any suitable circuit or device capable of converting analog signals generated by the sensors (S) into digital data indicative of the measured operating conditions of the selected circuits. Although not shown in FIG. 1 for simplicity, in some implementations, each of the satellite monitors 192(1)-192(19) may include at least an analog-to-digital converter (ADC) and a memory. The ADC may be any suitable circuit capable of converting analog signals into digital data and may include one or more inputs for receiving analog signals generated by a number of associated sensors (S), one or more outputs for providing digital data indicative of the operating conditions measured by the associated sensors (S), and one or more reference terminals for receiving a local reference voltage. In some implementations, the local reference voltage may be based at least in part on a reference voltage generated by the root monitor and distributed to the satellite monitors 192(1)-192(19) by the network interconnection system 120. The memory may store the digital data generated by the ADC and may provide the digital data to the network interconnect system 120 for routing to the route monitor.

[0069] The sensors (S) and satellite monitors 192(1)-192(19) may be distributed throughout the programmable device 100 and positioned at various locations near selected circuits, such that analog signals indicative of operational conditions of the selected circuits may be converted to digital signals at the various distributed locations (rather than being sent to a central hub and then converted to digital data). In some implementations, each of the sensors (S) may be positioned near a corresponding selected circuit, such that the sensor (S) and the corresponding selected circuit may be coupled together using a local signal line. Similarly, each of the satellite monitors 192(1)-192(19) may be positioned near one or more associated sensors (S), such that the satellite monitor 192 and the one or more associated sensors (S) may be coupled together using a local signal line. In some aspects, the term "nearby" as used herein may refer to the distance over which an analog signal indicative of operational conditions may be transmitted over a relatively short local signal wire with minimal signal degradation.

[0070] 1 , a first group of sensors (S) within the transceiver block 150 may be positioned proximate each of the voltage supplies (not shown for simplicity) associated with the transceiver block 150, and a first group of satellite monitors 192(1)-192(6) may be positioned proximate the first group of sensors (S), such that each of the first group of sensors (S) may be coupled to a corresponding supply voltage and corresponding satellite monitor 190 by a relatively short local signal wire. In some implementations, each of the first group of sensors (S) may be configured to generate an analog signal indicative of one or more operating conditions of the corresponding voltage supply, and each of the first group of satellite monitors 192(1)-192(6) may be configured to convert the analog signal generated by the associated sensor (S) into digital data transmittable to the route monitor 190 via the network interconnection system 120.

[0071] The second group of sensors (S) within PL 110 may be positioned proximate some corresponding selected circuits (not shown for simplicity) within or associated with PL 110, and the second group of satellite monitors 192(7)-192(19) may be positioned proximate the second group of sensors (S), such that, for example, each of the second group of sensors (S) may be coupled to the corresponding selected circuit and a corresponding one of the second group of satellite monitors 192(7)-192(19) by a relatively short local signal wire. In some implementations, each of the second group of sensors (S) may be configured to generate an analog signal indicative of one or more operating conditions of the corresponding selected circuit, and each of the second group of satellite monitors 192(7)-192(19) may be configured to convert the analog signal generated by the associated sensor (S) into digital data transmittable to route monitor 190 via network interconnect system 120.

[0072] Each of the satellite monitors 192(1)-192(19) may be coupled to any suitable number of sensors (S) by local signal lines. As one example, the satellite monitor 192(1) may be coupled to a single sensor (S) located in the transmit / receive block 150 and may generate a digital signal indicative of one or more operational conditions of a corresponding voltage supply associated with the transmit / receive block 150. As another example, the satellite monitor 192(16) may be coupled to two sensors (S) located in the PL 110 and may generate a digital signal indicative of one or more operational conditions of selected circuits associated with the two sensors (S) located in the PL 110. As another example, the satellite monitor 192(17) may be coupled to four sensors (S) located in the PL 110 and may generate a digital signal indicative of one or more operational conditions of selected circuits associated with the four sensors (S) located in the PL 110. Additionally, although shown in FIG. 1 as including nineteen satellite monitors 192(1)-192(19), programmable device 100 may include other numbers of satellite monitors 192 positioned at other suitable locations on programmable device 100.

[0073] As described above, the satellite monitors 192(1)-192(19) may be positioned close enough to the sensors (S) that relatively short local signal wires may be used to couple each of the sensors (S) to a corresponding satellite monitor 192, rather than using a central system monitor to transmit analog signals over relatively long distances for conversion to digital data. In this manner, implementations of the monitoring system disclosed herein may eliminate the need for metal layer signal routing resources to route these analog signals from various locations distributed throughout the device 100 to a central monitor for conversion to digital data, which may reduce the complexity and cost of the device while further improving the scalability of the monitoring system. Moreover, by using multiple satellite monitors 192(1)-192(19) distributed throughout the device 100 to perform analog-to-digital conversion of analog sensor data and then route the digital data to the route monitor 190 for analysis, the number of sensors that can be measured simultaneously is not limited by the number of input channels of the ADC provided within the satellite monitors. In contrast, the number of sensors that can be simultaneously measured by conventional solutions that route analog sensor data to a central system monitor for conversion to digital data is limited by the number of input channels of the ADC associated with the system monitor. Thus, by distributing the conversion of analog sensor data to digital information throughout device 100 via satellite monitors 192(1)-192(19), the number of sensors that can be simultaneously measured by the monitoring system disclosed herein is based on the number of satellite monitors 192(1)-192(19) rather than the number of input channels of any particular ADC. As a result, the monitoring system disclosed herein can simultaneously measure a much larger number of sensors than the conventional solutions discussed above.

[0074] The route monitor 190 may receive the digital data routed from each of the satellite monitors 192(1)-192(19) by the network interconnection system 120 and may process the received digital data to determine the operating conditions of selected circuits monitored by the sensors. In some implementations, the route monitor 190 may compare the measured operating conditions to one or more reference values ​​to determine whether each of the selected circuits is operating within its specified operating range.

[0075] It should be noted that Figure 1 is intended to depict just one illustrative architecture for programmable device 100. For example, the number of logic blocks in a column (or row), the relative widths of the columns (or rows), the number and order of the columns (or rows), the types of logic blocks included in the columns (or rows), the relative sizes of the logic blocks, and other structural aspects depicted in Figure 1 are merely illustrative of various implementations of the inventive subject matter disclosed herein.

[0076] 2 illustrates a functional block diagram of a programmable device 200, which may be an example of the programmable device 100 of FIG. 1, according to some implementations. The device 200 is shown to include a transceiver block 150, a programmable logic (PL) 210, a CPM 220, a processing system (PS) 230, a platform management controller (PMC) 240, and an I / O block+memory controller 260. The PL 210 may be an implementation of the PL 110 of FIG. 1 and may be adjacent to and directly connected to the transceiver block 150, the CPM 220, the PMC 240, and the network interconnect system 120. The I / O block+memory controller 260 may be an implementation of the I / O block 160 and the memory controller 170 of FIG. 1 and may be implemented as multiple repeatable tiles arranged along the bottom edge of the programmable device 200. 2 for simplicity, I / O block+memory controller 260 may also be implemented as multiple repeatable tiles arranged along the top edge of programmable device 200. Additionally, or in the alternative, I / O block+memory controller 260 may be implemented as multiple repeatable tiles arranged along the right and left edges of programmable device 200.

[0077] CPM 220 may be one implementation of CPM 140 of FIG. 1 and may provide interface capabilities for several different bus standards. In some implementations, CPM 220 may include a Peripheral Component Interconnect Express (PCIe) interface 222, a Direct Memory Access (DMA) circuit 224, and a Cache Coherent Interconnect for Accelerators (CCIX) interface 226. PCIe interface 222 may be used to exchange data between PS 230 and one or more other devices or chips via transmit / receive block 150 according to the PCI protocol. Similarly, CCIX interface 226 may be used to exchange data between PS 230 and one or more other devices or chips via transmit / receive block 150 according to the CCIX protocol.

[0078] The PS 230 may provide dedicated data processing capabilities to the device 200 and is shown to include an application processing unit (APU) 232, a real-time processing unit (RPU) 234, a cache memory 236, and a system-on-a-chip (SoC) interface 238. Although not shown for simplicity, the PS 230 may also include peripherals for communication standards (such as Ethernet and USB 2.0 interfaces), as well as various controllers (such as SPI, I2C, UART, and CAN-FD controllers). The APU 232 and RPU 234 may each include one or more processing cores (such as a CPU) capable of providing dedicated scalar processing capabilities to the device 200. In some aspects, the PS 230 may be selectively connected to other subsystems of the device 200 by a programmable interconnect fabric and network interconnect system 120.

[0079] In some implementations, the APU 232 may include a multi-core ARM processor supporting hardware virtualization and may have a built-in interrupt controller and snoop control unit. The interrupt controller may support virtual interrupts, and the snoop control unit may be used to maintain coherency between one or more caches used and / or shared by the APU 232 and the RPU 234. The APU 232 may communicate with other components of the PS 230 using an AXI coherent extension (ACE) port and may communicate with the PL 210 using an accelerator coherency port (ACP). In some implementations, the RPU 234 may include a multi-core ARM processor supporting real-time data processing, may include a tightly coupled memory (TCM) interface for real-time single cycle access, and may have a dedicated interrupt controller and floating point unit. The RPU 234 may communicate with other components of the PS 230 and / or with the PL 210 using an AXI port.

[0080] The cache memory 236 may be any suitable high-speed cache that allows shared access by the APU 232 and the RPU 234. The SoC interface 238 may provide a connection between various resources of the PS 230 and the network interconnect system 120.

[0081] PMC 240 may include security circuitry 242, boot and reconfiguration circuitry 244, analog circuitry 246, and root monitor 190 of FIG. 1. Security circuitry 242 may provide data encryption / decryption capabilities and other security features. Boot and reconfiguration circuitry 244 may provide a multi-stage boot process supporting both non-secure and secure boot. Analog circuitry 246 may include any suitable analog circuit components. Additionally, although not shown in FIG. 2 for simplicity, PMC 240 may include test and debugging resources (such as JTAG circuitry), an external flash memory interface, and other components or circuits. In some implementations, PMC 240 may enable a portion of PL 210 to be reconfigured using a partial reconfiguration operation. For example, a new configuration bitstream for a portion of PL 210 may be loaded from PS 230 via a primary or secondary boot interface (such as PCIe or Ethernet) and then stored in a configuration register associated with the portion of PL 210 to be reconfigured. The ability to allow partial reconfiguration of one or more portions of PL 210 may enable a user to more quickly reconfigure device 200 to reflect changes or updates to a user-specified circuit design (such as comparable to other programmable devices).

[0082] FIG. 3 illustrates a block diagram of an example programmable fabric 300 according to some implementations. In some implementations, the programmable fabric 300 may be the PL 110 of FIG. 1, the PL 210 of FIG. 2, or both. The programmable fabric 300 is shown to include a number of different programmable circuit blocks or tiles that may be arranged in columns (or rows). The programmable circuit blocks may include (but are not limited to) programmable interconnect elements (INTs) 310, configurable logic elements (CLEs) 320, DSPs 330, and block RAMs (BRAMs) 340 arranged in a columnar architecture. As an example of FIG. 3, the programmable fabric 300 is shown to include eleven columns of programmable interconnect elements 310, five columns of CLEs 320, two columns of DSPs 330, and two columns of BRAMs 340. In other implementations, programmable fabric 300 may include other numbers of columns of programmable interconnect elements 310, CLEs 320, DSPs 330, and BRAMs 340. Programmable fabric 300 may also include several other subsystems or components (such as processing cores, programmable interconnect structures, and the like) that are not shown in FIG. 3 for simplicity.

[0083] Programmable interconnect elements 310, CLEs 320, DSPs 330, and BRAMs 340 may be implemented as repeatable tiles throughout programmable fabric 300. Each of the tiles may include at least one programmable interconnect element 310 that provides local signal interconnects to programmable logic elements within the same tile, to programmable interconnect elements 310 in adjacent tiles, and / or to other signal routing resources. The programmable interconnect elements 310 may collectively form at least a portion of a programmable interconnect fabric (or other suitable block-level and / or device-level signal routing structure).

[0084] In some implementations, programmable fabric 300 may include a cylindrical hard block 350 that extends vertically across the height of programmable fabric 300. Hard block 350 may include several hardwired circuits, such as, for example, a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC, a PCIe controller, a CCIX controller, and / or other suitable circuits or components that implement the physical, data link, and transaction layers of the PCIe protocol. In some implementations, hard block 350 may be an implementation of one of the connectivity fabrics described above with respect to FIG.

[0085] 4 illustrates a functional block diagram of a monitoring system 400 according to some implementations. The monitoring system 400 may be implemented within the programmable device 100 of FIG. 1 and is shown to include a route monitor 410, a plurality of satellite monitors SAT1-SAT15, a plurality of supply voltage sensors SV1-SV4, a plurality of temperature sensors T5-T15, and a plurality of selected circuits CKT5-CKT15. The route monitor 410 may be one implementation of the route monitor 190 of FIG. 1 and is coupled to the network interconnect system 120 and is configured to monitor a reference voltage (V REFIn some implementations, the route monitor 410 may include circuitry for generating a temperature compensated reference voltage V REF A bandgap reference circuit (not shown for simplicity) may be included to generate

[0086] The satellite monitors SAT1-SAT15 may be distributed throughout the device 100 and positioned such that each of the satellite monitors SAT1-SAT15 is located proximate a corresponding one of the sensors SV1-SV4 and T5-T15. For the example implementation of FIG. 4, the satellite monitors SAT1-SAT4 are coupled to respective supply voltage sensors SV1-SV4 via local signal wires, and the satellite monitors SAT5-SAT15 are coupled to respective temperature sensors T5-T15 via local signal wires. In this manner, analog signals generated by the supply voltage sensors SV1-SV4 may be provided by the local signal wires to the respective satellite monitors SAT1-SAT4, and analog signals generated by the temperature sensors T5-T15 may be provided by the local signal wires to the respective satellite monitors SAT5-SAT15. By positioning the satellite monitors SAT5-SAT15 in close proximity to (e.g., near) the associated sensors SV1-SV4 and T5-T15, the analog signals generated by the sensors SV1-SV4 and T5-T15 do not need to be routed across a large portion of the device 100 to reach the route monitor 410, thereby minimizing signal degradation associated with routing relatively small analog signals across metal layer interconnects spread throughout the device 100. Moreover, because each of the analog signals generated by the sensors SV1-SV4 and T5-T15 can be converted locally to digital data using a nearby one of the satellite monitors SAT1-STA15, expensive metal layer routing resources are not required to implement the monitoring system 400 within a programmable device (such as the programmable device 100 of FIG. 1).

[0087] As one example, a sensor SV1 may monitor the operating condition of an associated supply voltage by generating an analog signal indicative of the voltage level of the associated supply voltage. By positioning a corresponding satellite monitor SAT1 in the vicinity of the sensor SV1, the analog signal generated by the sensor SV1 does not have to be routed across the device 100 to the route monitor 410, but instead can be routed a relatively short distance to the satellite monitor SAT1 via a local signal wire. As another example, a sensor T5 may monitor the operating condition of an associated circuit CKT5 by generating an analog signal indicative of the temperature of the associated circuit CKT5. By positioning a corresponding satellite monitor SAT5 in the vicinity of the sensor T5, the analog signal generated by the sensor T5 does not have to be routed across the device 100 to the route monitor 410, but can instead be routed a relatively short distance to the satellite monitor SAT5 via a local signal wire.

[0088] Reference voltage V REF may be distributed throughout device 100 and made accessible to each of satellite monitors SAT1-STA15 by one or more dedicated analog channels of network interconnection system 120, and digital data may be selectively routed from each of satellite monitors SAT1-STA15 to route monitor 410 by one or more digital channels of network interconnection system 120. In some implementations, the one or more analog channels may be physically separate from the one or more digital channels.

[0089] 5 shows a block diagram of an example route monitor 500, according to some implementations. The route monitor 500 may be one implementation of the route monitor 190 of FIG. 1 or the route monitor 410 of FIG. 4 (or both), and is shown to include a voltage generator 510, a memory 520, and a controller 530. The voltage generator 510 generates a reference voltage V REF1, in some implementations, the reference voltage V generated by the voltage generator 510 may be any suitable circuit or device capable of generating a trimmed voltage suitable for use as a trimmed voltage, including an output coupled to one or more analog channels 121 of the network interconnect system 120. With further reference to FIG. 1, in some implementations, the reference voltage V generated by the voltage generator 510 may be REF may be distributed to each of the satellite monitors 192(1)-192(19) located throughout the device 100 using one or more analog channels 121 of the network interconnection system 120. The satellite monitors 192(1)-192(19) receive a reference voltage V from the network interconnection system 120. REF , and has access to a distributed reference voltage V REF It may be used to perform analog-to-digital conversion (or for other suitable operations).

[0090] In some implementations, the voltage generator 510 may generate, for example, a reference voltage V REF In some embodiments, the reference voltage V may include a bandgap circuit 512 capable of generating a temperature compensated voltage such that V is adjusted for temperature changes. Additionally, or in the alternative, the voltage generator 510 may provide both a positive and a negative reference voltage to one or more analog channels 121 of the network interconnect system 120. In some embodiments, the reference voltage V may be REF can be equal to 1.25 volts, but other suitable voltages are REF It can be used as:

[0091] The memory 520 includes a data input coupled to one or more digital channels 122 of the network interconnect system 120, a control input coupled to the controller 530, a data output coupled to the controller 530, and one or more output ports that allow access by a user to data stored in the memory 520 via one or more of a JTAG interface, a multiplexed input / output (MIO) block, or an AXI interface. In some implementations, the memory 520 may include several status registers 521 and several alarm registers 522. The status registers 521 may store digital data indicative of the operating status of selected circuits provided throughout the device 100, and the alarm registers 522 may store a number of reference values ​​that define several specified operating ranges. The status registers 521 may be loaded with digital data routed from the satellite monitors 192(1)-192(19) to the root monitor 500 via the network interconnect system 120, and the alarm registers 522 may be loaded with reference values ​​during configuration (or reconfiguration) of the programmable device 100.

[0092] The controller 530 may control various operations of the route monitor 500, may analyze digital data received from the satellite monitors 192(1)-192(19) to determine if any of the selected circuits are not operating within their specified operating ranges, and may generate result data accessible by a user. In some implementations, the controller 530 may determine if the selected circuits are operating within the specified operating ranges by comparing the measured operating conditions stored in the status registers 521 with corresponding reference values ​​stored in the alarm registers 522. If it is determined that the selected circuits are operating outside their specified operating ranges, the controller 530 may generate an alarm. In some aspects, the alarm may, for example, disable or power down the selected circuits until the operating conditions of the selected circuits are within their specified operating ranges. In other aspects, the alarm may, for example, cause the programmable device 100 to power down or operate at a reduced power level until the operating conditions of the selected circuits are within their specified operating ranges.

[0093] Some of the specified operating ranges stored in the alarm register 522 may be defined by minimum and maximum reference values. In some implementations, the specified voltage ranges may include a minimum voltage value and a maximum voltage value. In such implementations, the controller 530 may compare the measured voltage of the selected circuit to the minimum and maximum voltage values ​​stored in the alarm register 522 and generate one or more alarms based on the comparison. For example, if the measured voltage is between the minimum and maximum voltage values, the controller 530 may indicate that the selected circuit is operating within its specified voltage range. Conversely, if the measured voltage is less than the minimum voltage value or greater than the maximum voltage value, the controller 530 may generate an alarm to indicate that the selected circuit is not operating within its specified voltage range.

[0094] Other specified operating ranges stored in alarm register 522 may include reference values ​​that define upper operable limits. In some implementations, the specified temperature range of the selected circuit may be defined by a reference temperature value. In such implementations, controller 530 may compare the measured temperature of the selected circuit to the reference temperature value stored in alarm register 522 and generate one or more alarms based on the comparison. For example, if the measured temperature is less than (or equal to) the reference temperature value, controller 530 may indicate that the selected circuit is operating within its specified temperature range. Conversely, if the measured temperature is greater than the reference temperature value, controller 530 may generate an alarm to indicate that the selected circuit is too hot or overheated.

[0095] FIG. 6 illustrates a block diagram of an example satellite monitor 600 according to some implementations. The satellite monitor 600 may be an example of any number of one of the satellite monitors 192(1)-192(19) of FIG. 1 or the satellite monitors SAT1-SAT15 of FIG. 4 (or both), and includes a data input coupled to one or more sensors 20, an output coupled to the network interconnection system 120, and a reference terminal coupled to the network interconnection system 120 by a first switch SW1. With further reference to FIG. 1 and FIG. 5, in some implementations, the satellite monitor 600 receives a reference voltage V generated by the route monitor 500 and distributed by one or more analog channels 121 of the network interconnection system 120 via the first switch SW1. REF In some aspects, the sensors 20 may include (but are not limited to) a temperature sensor 21, a supply voltage sensor 22, and an external sensor 23.

[0096] 6, the satellite monitor 600 is shown to include an ADC circuit 610, a memory 620, and a local reference circuit 630. The ADC circuit 610 includes an input coupled to one or more sensors 20 via a second switch SW2, an output coupled to the memory 620, and one or more reference terminals coupled to the local reference circuit 630. The ADC circuit 610 may be (or may include) any suitable ADC capable of converting analog signals generated by one or more of the sensors 20 into digital signals or data. In some implementations, the ADC circuit 610 may utilize a scaled architecture to digitize analog sensed data provided by the sensors 20.

[0097] The memory 620 may be any suitable storage device and includes an input coupled to the output of the ADC circuit 610 and includes an output coupled to the network interconnect system 120. The memory 620 may store digital data generated by the ADC circuit 610 in response to the analog signals provided by one or more of the sensors 20 and may provide the digital data to one or more digital channels 122 of the network interconnect system 120 for routing to the route monitor 500 of FIG. 5. In some implementations, the memory 620 may be or include a plurality of registers for respectively storing digital data indicative of an operating condition of a corresponding one of the plurality of circuits selected for monitoring. In this manner, the satellite monitor 600 may receive an analog signal indicative of an operating condition of a corresponding one of the selected circuits from the sensor 20, convert the analog signal to digital data, and provide the digital data indicative of the operating condition of the selected circuit to one or more digital channels 122 of the network interconnect system 120.

[0098] A local reference circuit 630 is coupled between the first switch SW1 and one or more reference terminals of the satellite monitor 600 and provides a local reference voltage (V REF_LOCAL) to the ADC circuit 610. In some implementations, the local reference voltage V REF_LOCAL is the reference voltage V distributed by the network interconnection system 120 REF and may be used by the ADC circuit 610 to perform analog-to-digital conversion.

[0099] The first switch SW1 is connected to the reference voltage V V distributed by the network interconnection system 120 based on a first control signal (CTRL1). REF to the satellite monitor 600. In some implementations, the first switch SW1 may couple a reference terminal of the satellite monitor 600 to the network interconnection system 120 when the first control signal CTRL1 is in an asserted state (e.g., logic high) and may isolate the satellite monitor 600 from the network interconnection system 120 when the first control signal CTRL1 is in a deasserted state (e.g., logic low). In this manner, the first switch SW1 allows the satellite monitor 600 to selectively couple a reference terminal of the satellite monitor 600 to the network interconnection system 120 when the first control signal CTRL1 is in a deasserted state (e.g., logic low). REF can be used to control when (and for how long) a user can access

[0100] 5 and may be routed by the network interconnection system 120 (or by other suitable signal interconnections) to the satellite monitors 600. With further reference to FIGS. 1 and 5, in some implementations, the route monitor 500 may, for example, be configured to transmit a reference voltage V REF The first control signal CTRL1 may be asserted for each of a plurality of satellite monitors 600 distributed throughout the programmable device based on a timing schedule so that the satellite monitors 600 can access the distributed reference voltage V. REFA distributed reference voltage V caused by two or more of the satellite monitors 600 simultaneously accessing REF This can prevent the drop in the

[0101] A second switch SW2 may selectively couple one of the sensors 21-23 to an input of the ADC circuit 610 based on a second control signal (CTRL2). In some implementations, the second control signal CTRL2 may be generated by the route monitor 500 of FIG. 5 and routed to the satellite monitor 600 by the network interconnection system 120 (or by other suitable signal interconnections).

[0102] 7 is an illustrative flowchart depicting example operations 700 for monitoring certain operational conditions of a programmable device according to some implementations. The example operations 700 are described below for the programmable device 100 of FIG 1, the monitoring system 400 of FIG 4, the route monitor 500 of FIG 5, and the satellite monitor 600 of FIG 6, for illustrative purposes only. It will be understood that the example operations 700 may be performed by other programmable devices disclosed herein and / or by other suitable devices.

[0103] The operation 700 starts in block 701 with generating a reference voltage (V REF In some implementations, the route monitor 190 may begin by generating a trimmed and temperature compensated reference voltage V, for example using the bandgap circuit 512 of FIG. REF This can cause the following problems.

[0104] The operations 700 begin in block 702 by using one or more analog channels 121 of the interconnect system 120 to generate a reference voltage V REF , from the root monitor 190 to each of the multiple satellite monitors 192. In some implementations, the reference voltage V REFDistributing the reference voltage V may include selectively coupling each of the plurality of satellite monitors 192(1)-192(19) to the interconnection system 120 based on a corresponding control signal CTRL1 generated by the route monitor 190. In some aspects, the first switch SW1 of FIG. 6 is configured to cause the satellite monitor 600 to selectively couple the reference voltage V based on a first state of CTRL1. REF from network interconnection system 120, and a first switch SW1 may isolate satellite monitor 600 from network interconnection system 120 based on a second state of CTRL1.

[0105] The operations 700 may proceed at block 703 by using each of the number of sensors 20 to generate an analog signal indicative of an operating condition of an associated circuit. In some implementations, each of the number of sensors 20 may be in proximity to the associated circuit. In some aspects, the sensor 20 may be (or may include) at least one of a temperature sensor 21, a supply voltage sensor 22, or an external sensor 23.

[0106] The operations 700 may proceed at block 704 by providing analog signals generated by several of the sensors 20 to corresponding ones of the multiple satellite monitors 192(1)-192(19). In some implementations, the analog signals generated by the sensors 20 may be provided to corresponding satellite monitors 192(1)-192(19) using relatively short local signal wires, as opposed to conventional programmable devices in which analog signals indicative of, for example, the operating status of various circuits are routed throughout the device using metal layer signal routing structures and provided to a central monitor.

[0107] The operations 700 may proceed, at block 705, by converting analog signals to digital data using a plurality of satellite monitors 192(1)-192(19). With further reference to FIG. 6, ADC circuitry 610 provided within each of the satellite monitors 192(1)-192(19) may convert the analog signals to digital data that may be stored in a memory 620 of each of the satellite monitors 192(1)-192(19). The memory 620 may selectively provide the stored digital data to the interconnect system 120 for routing to the route monitor 190.

[0108] The operations 700 may proceed, at block 706, by selectively routing the digital data from the plurality of satellite monitors 192(1)-192(19) to the route monitor 190 using one or more digital channels 122 of the interconnection system 120. With further reference to FIG. 4, the digital channels 122 may be physically separate from the analog channels 121 of the interconnection system 120. In some implementations, the satellite monitors 192(1)-192(19) may provide the digital data to the interconnection system 120 in response to a signal (e.g., a trigger signal) generated by the route monitor 190, for example, to schedule or prioritize delivery of the digital data from the plurality of satellite monitors 192(1)-192(19) to the route monitor 190. In other implementations, the satellite monitors 192(1)-192(19) may provide the digital data to the interconnection system 120 without prompting and / or control by the route monitor 190.

[0109] The operations 700 may proceed by determining, at block 707, whether an operating condition of at least one of the associated circuits is within a range, and may proceed by selectively generating an alarm, at block 708, based on the determination. With further reference to FIG. 5, the route monitor 500 may receive digital data from a selected one of the satellite monitors 192(1)-192(19) and compare the received digital data to one or more reference values ​​to determine whether an operating condition of the associated circuit is within a range. In some implementations, the route monitor 500 may generate an alarm and / or power down one or more portions of the programmable device 100 (or the entire programmable device 100 if several various circuits, blocks, and subsystems do not remain within their specified operating parameters).

[0110] For implementations in which the analog signal indicates the voltage of an associated circuit (such as a voltage supply), the route monitor 500 may compare the measured voltage of the associated circuit to minimum and maximum reference voltage levels. If the measured voltage of the associated circuit is between the minimum and maximum reference voltage levels, the route monitor 190 may determine that the associated circuit is operating within a specified voltage range. Conversely, if the measured voltage of the associated circuit is less than the minimum reference voltage level or greater than the maximum reference voltage level, the route monitor 190 may determine that the associated circuit is not operating within the specified voltage range.

[0111] For implementations in which the analog signal indicates the temperature of the associated circuit, the route monitor 500 may compare the measured temperature of the associated circuit to a reference temperature value. If the measured temperature of the associated circuit is not greater than the reference temperature value, the route monitor 190 may determine that the associated circuit is operating within its specified temperature range. Conversely, if the measured temperature of the associated circuit is greater than the reference temperature value, the route monitor 190 may determine that the associated circuit is not operating within the specified temperature range.

[0112] Implementations of the subject matter described in this disclosure may be used to monitor several operating conditions of a programmable device. The operating conditions may be any suitable indication of an operating characteristic or parameter of the device, including, for example, the temperature of a circuit or component provided within the programmable device, the temperature of a circuit or device external to the programmable device, the voltage level of a supply voltage, and the like. According to some aspects of the present disclosure, a monitoring system may include a root monitor, a number of sensors distributed at various locations throughout the programmable device, and a number of satellite monitors distributed at various locations throughout the programmable device. The root monitor may include a bandgap voltage generator configured to generate a high-precision and temperature-independent reference voltage, which may be distributed from the root monitor to each of the satellite monitors via one or more analog channels that interface with the programmable logic.

[0113] Each of the sensors may generate an analog signal indicative of one or more operational conditions of the associated circuitry and may provide the analog signal to a corresponding one of the satellite monitors via one or more local signal lines. Each of the satellite monitors may include an ADC for converting the analog signal to digital data and may be positioned proximate to one or more associated sensors such that, for example, an analog signal generated by one or more associated sensors may be routed a relatively short distance via a local signal line to a respective one of the satellite monitors for conversion to digital data. In some implementations, the programmable device may include a network-on-chip (NoC) interconnect system capable of selectively routing digital data from each of the satellite monitors to the root monitor for processing, and of routing control signals and other information from the root monitor to each of the satellite monitors. Additionally or in another manner, the digital data generated by each of the satellite monitors may be routed to the root monitor using a clock distribution network, a programmable interconnect fabric, and / or other suitable routing resources provided within the device, including, but not limited to, routing resources provided within repeatable tiles forming the programmable logic of the device.

[0114] The accuracy of the thermal and voltage monitoring of the multiple sensors distributed throughout the programmable device depends on accurate analog-to-digital conversion in each of the multiple satellite monitors distributed throughout the programmable device. The accuracy of the analog-to-digital conversion may be based at least in part on the accuracy of the reference voltages provided to the ADCs in each of the satellite monitors. Although a bandgap voltage generator may be used to generate the highly accurate and temperature independent reference voltages, the bandgap voltage generator consumes a significant amount of circuit area and requires expensive and time consuming trimming during manufacturing of the programmable device.

[0115] To avoid silicon costs of providing an accurate reference voltage to each of the multiple satellite monitors distributed across the device and to eliminate the need to trim the corresponding multiple voltage generators, each of the satellite monitors may include a relatively small voltage source (e.g., an area-efficient voltage source) configured to generate a local reference voltage for the corresponding ADC. The local voltage source may be relatively small and therefore "area-efficient" compared to the bandgap voltage generator provided in the root monitor. In some implementations, the local voltage source may include less than 12 transistors and consume at least an order of magnitude less circuit area than the bandgap voltage generator. In some implementations, each of the satellite monitors may include a local voltage store configured to store a local reference voltage for the corresponding ADC. The local voltage store may consist of a capacitor coupled to a switch (e.g., a transistor).

[0116] The local reference voltage may be relatively inaccurate compared to the high-precision temperature-independent reference voltage generated by the bandgap voltage generator, resulting in errors in the digital code generated by the ADC provided in a corresponding one of the satellite monitors. In some implementations, each of the satellite monitors may include a calibration circuit configured to generate a correction factor indicative of an error in the digital code, and may include a correction circuit configured to correct the digital code based on the correction factor. The ADCs provided in the multiple satellite monitors may be periodically calibrated against the high-precision and temperature-independent reference voltage by their corresponding calibration and correction circuits, as described in more detail below.

[0117] Conventional systems for monitoring the operational status of various circuits distributed throughout a programmable device typically include a central system monitor and a number of sensors located near the circuits to be monitored. Each sensor generates an analog signal indicative of the operational status of the associated circuit, and the analog signal is routed from each of the sensors to the system monitor for conversion to digital data. The sensors are typically distributed at various locations throughout the device, so that analog signals generated by at least some of the sensors may be routed across most of the device to reach the system monitor. Because analog signals indicative of operational status may be particularly susceptible to noise and interference, some programmable devices may use dedicated metal layer routing resources with shielding properties to route these analog signals from the various sensors to the system monitor for conversion to digital data.

[0118] While the shielding properties of such dedicated metal layer routing resources may reduce signal degradation and data loss, the dedicated metal layer routing resources are expensive and consume a significant amount of the metal layers of the device. Furthermore, because programmable logic is typically implemented as multiple repeatable tiles arranged in multiple rows or columns, the signal routing resources embedded within each of the repeatable tiles are typically based on a worst-case routing scenario (such as placing the tile in a location with the greatest device density). As a result, many of the repeatable tiles are over-equipped with signal routing resources, which may result in unused routing resources and / or limit the scalability of the programmable device.

[0119] By introducing multiple satellite monitors at locations throughout the programmable device in close proximity to sensors monitoring the operational status of various circuits, the monitoring system disclosed herein may use local satellite monitors to convert analog signals generated by the sensors to digital data and then route the digital data from various locations throughout the device to the root monitor. As a result, the analog signal is not routed across most of the device and then converted to digital data, but is transmitted a relatively short distance to the nearest satellite monitor for conversion to digital data, which is then routed to the root monitor using the NoC interconnect system. In some aspects, the digital data generated by the satellite monitors may be routed to the root monitor as individually addressable data packets. In other aspects, the digital data generated by the satellite monitors may be routed to the root monitor as non-packetized data. By using satellite monitors located near the sensors to convert analog signals to digital data rather than performing analog-to-digital conversion in the root monitor, the monitoring system disclosed herein may not require metal layer routing resources, reducing costs while improving scalability of the programmable device. Furthermore, performing the analog-to-digital conversion locally (e.g., near the sensor) and routing the resulting digital data from the satellite monitor to the root monitor may allow more sensor data to be collected and analyzed by the root monitor (compared to traditional techniques that route analog signals from various sensors throughout the device to ADCs provided in the system monitor), since, for example, ADCs distributed throughout the programmable device may perform the analog-to-digital conversion in parallel (e.g., simultaneously).

[0120] In the following description, numerous specific details are given, such as examples of specific components, circuits, and processes, to fully understand the present disclosure. The term "coupled" as used herein means directly coupled or coupled through one or more intervening components or circuits. In addition, in the following description, and for purposes of explanation, specific terminology and / or details are given to fully understand the implementation of the examples. Nevertheless, it will be apparent to those skilled in the art that these specific details may not be required to practice the implementation of the examples. In other examples, well-known circuits and devices are shown in block diagram form so as not to obscure the present disclosure. Any of the signals provided on the various buses described herein may be time-shared with other signals and provided on one or more common buses. Furthermore, the interconnections between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, each of the single signal lines may alternatively be a bus, and the single line or bus may represent any one or more of the myriad physical or logical mechanisms for communication between the components. Example implementations should not be construed as limited to the specific examples described herein, but rather should include within their scope all implementations defined by the appended claims.

[0121] FIG. 8 illustrates a block diagram of an example programmable device 800 in which various aspects of the disclosure may be implemented. The device 800 may include several subsystems, such as, for example, a programmable logic (PL) 810, a network-on-chip (NoC) interconnect system 820 that couples the PL 810, one or more analog channels 821 that couple the PL 810, a dedicated circuit device 830, a CCIX and PCIe module (CPM) 840, a transmit / receive block 850, an input / output (I / O) block 860, a memory controller 870, a configuration logic 880, a route monitor 890, a number of satellite monitors 892(1)-892(19), and a number of sensors (S). In one or more implementations, the device 800 may include other subsystems or components not shown in FIG. 8. Additionally, although not shown for simplicity, the device 800 may be coupled to several peripheral components (such as a high-performance memory device) and / or other devices or chips (such as another programmable device).

[0122] The PL 810 includes programmable circuitry that can be configured or programmed to perform a number of different user-defined functions or operations. In some implementations, the PL 810 can include a number of programmable circuit blocks implemented as repeatable tiles arranged in columns within the programmable device 800, for example, as depicted in FIG. 8. The programmable circuit blocks can be referred to as programmable fabric subregions (FSRs) and can include programmable interconnect circuitry and programmable logic circuitry, respectively. In some implementations, the programmable circuit blocks can include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAMs), digital signal processing blocks (DSPs), clock managers, delay-locked loops (DLLs), and / or other logic or circuitry that can be programmed or configured to implement a user-specified circuit design.

[0123] The programmable interconnect circuitry in each of the programmable circuit blocks or tiles may include multiple interconnect wires of various lengths interconnected by programmable interconnect points (PIPs). The interconnect wires may be configured to provide connections between components within a particular programmable tile, between components within different programmable tiles, and between components of a programmable tile and other subsystems or devices. The programmable interconnect circuitry and the programmable circuit blocks may be programmed or configured by loading configuration data into configuration registers that define how the programmable elements are configured and operate to implement the corresponding user-specified circuit design. In some aspects, the programmable interconnect circuitry in each of the several programmable circuit blocks may form part of a programmable interconnect fabric (not shown for simplicity) that provides block-level and / or device-level signal routing resources to the device 800.

[0124] The NoC interconnect system 820 may be fabricated as part of the device 800 and may include any number of horizontal and vertical segments (and / or diagonal segments) connected together to implement a high-speed, high-bandwidth programmable signal routing network selectively interconnectable with various device resources (such as PL 810, special purpose circuitry 830, CPM 840, transmit / receive block 850, I / O block 860, memory controller 870, configuration logic 880, route monitor 890, and satellite monitors 892(1)-892(19)) with each other and with other components not shown for simplicity. For the example implementation of FIG. 8, the NoC interconnect system 820 is shown to include two horizontal segments and four vertical segments. A first horizontal segment that extends across the width of the device 800 is positioned along a bottom boundary of the device 800, and a second horizontal segment that extends across the width of the device 800 is positioned along a top boundary of the device 800. The four vertical segments extend across the entire height of the device 800 and connect to first and second horizontal segments of the NoC interconnect system 820. In some aspects, the horizontal segments may enable the NoC interconnect system 820 to exchange signals and data with the I / O block 860 and the memory controller 870 without intervening circuits or interfaces, and the vertical segments may enable the NoC interconnect system 820 to exchange signals and data with the transceiver block 850, the dedicated circuit equipment 830, and the CPM 840 without intervening circuits or interfaces. In other implementations, the NoC interconnect system 820 may include other numbers of horizontal and vertical segments, and these segments may occupy other locations in the device 800. Thus, the particular layout, shape, size, orientation, and other physical characteristics of the example NoC interconnect system 820 depicted in FIG. 8 are merely illustrative of various implementations disclosed herein.

[0125] The NoC interconnect system 820 may be configured to transmit information between various device resources as data packets that are individually addressable and routable from a source location to a destination location. In some aspects, data packets transmitted over the NoC interconnect system 820 may be dynamically addressable. In one or more implementations, the NoC interconnect system 820 may route data packets from any number of source locations to any number of destination locations using an appropriate data packet protocol (such as a token ring protocol) and / or using memory-mapped addresses. The data packets may include header information (such as a source address, a destination address, and protocol information) usable by the NoC interconnect system 820 to route the data packet to its designated destination.

[0126] In some implementations, the data packets may include quality of service (QoS) information that enables transmission of the data packets through the NoC interconnect system 820 to be prioritized based, for example, on assigned priority, traffic type, traffic flow, and / or other measures. In such implementations, the NoC interconnect system 820 may include priority logic capable of determining a priority level or traffic class of a received data packet and use the determined priority level or traffic class when queuing the data packet for transmission. By transmitting information between various device resources as individually addressable data packets, the NoC interconnect system 820 may provide connections between various device resources regardless of the particular user-specified circuit design, thereby significantly improving the signal routing capabilities of the device 800 (compared to conventional programmable devices). For example, while the programmable interconnect fabric and other tile-based signal routing structures of device 800 are typically configured to provide point-to-point signal connections between designated circuits, NoC interconnect system 820 may simultaneously route each of multiple data packets from any source address to any destination address on device 800, thereby providing system-level connectivity to device 800.

[0127] Although not shown for simplicity, the NoC interconnect system 820 may also include a scheduler and arbitration logic. The scheduler may be used to schedule the transmission of data packets from a source address to a destination address using one or more physical and / or virtual channels of the NoC interconnect system 820. The arbitration logic may be used to arbitrate access to the NoC interconnect system 820, for example, to minimize collisions and other contention-related latencies. For implementations in which the device 800 is fabricated using stacked silicon interconnect (SSI) technology, the columnar portions of the NoC interconnect system 820 may provide signal connections between neighboring super logic regions (SLRs), for example, to allow configuration data to be routed between master and slave SLRs.

[0128] The NoC interconnect system 820 may be programmed by loading configuration data into corresponding configuration registers that define how various switches, interfaces, and routers within or associated with the NoC interconnect system 820 are configured to implement a particular user-specified circuit design. In some implementations, the NoC interconnect system 820 may include multiple nodes, ports, or other interfaces (not shown for simplicity) that provide selective connections between the NoC interconnect system 820 and various resources, subsystems, circuits, and other components of the device 800. For example, the NoC interconnect system 820 may enable multiple subsystems of the device 800 to share on-chip memory (OCM) resources, processing resources, I / O resources, and / or access to the transmit / receive block 850. The nodes, ports, or other interfaces of the NoC interconnect system 820 may be programmed to implement a particular connection profile by loading configuration data into one or more associated configuration registers.

[0129] By selectively interconnecting various resources, subsystems, circuits, and other components of device 800 that may require and use large amounts of data, NoC interconnect system 820 may relieve signal routing burdens on local interconnect resources, thereby improving device performance and allowing greater configuration flexibility than other programmable devices. Moreover, by providing a high-performance signal routing network that has higher data transmission rates and lower error rates than device-level and block-level programmable interconnects, NoC interconnect system 820 may increase the processing power and data throughput of device 800 (relative to other programmable devices).

[0130] Analog channels 821 spanning the programmable device 800 may be used to distribute high-precision, temperature-independent reference voltages from the root monitor 890 to each of the multiple satellite monitors 892(1)-892(19). In some implementations, the analog channels 821 may be adjacent to (or integrated within) a corresponding segment of the NoC interconnect system 820. In other implementations, the analog channels 821 may be separate from the NoC interconnect system 820. In some other implementations, the analog channels 821 may be part of a clock distribution network or some other suitable signal interconnect system provided within the device 800.

[0131] The special purpose circuit equipment 830 may include any suitable hard-wired circuitry, including (but not limited to) a processor, a serial transceiver, a digital signal processor (DSP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), device management resources, device monitoring resources, device test management resources, and the like. In some embodiments, the special purpose circuit equipment 830 may include a processing system (PS) and a platform management controller (PMC) as described with respect to FIG. 9. In some implementations, the PS may include one or more processor cores, cache memory, a memory controller, and unidirectional and / or bidirectional interfaces configurable to directly couple to I / O pins of the device 800. In some aspects, each processor core may include a central processing unit (CPU) or a scalar processor usable for sequential data processing. The PMC may be used to boot and configure the device 800 based on configuration data (such as a configuration bitstream) provided from an external memory. The PMC may also be used to configure the PL 810 and to control various encryption, authentication, route monitoring, and debug capabilities of the device 800.

[0132] CCIX and PCIe module (CPM) 840 may include several interfaces that provide connections between device 800 and several peripheral components (such as external devices or chips). In some implementations, CPM 840 may include multiple Peripheral Interconnect Express (PCIe) and Cache Coherent Interconnect for Accelerators (CCIX) interfaces that provide connections to other devices or chips via transceiver block 850. In some aspects, the PCIe and CCIX interfaces may be implemented as part of transceiver block 850. One example implementation of CPM 840 is described with respect to FIG. 9.

[0133] The transmit / receive block 850 may provide signal connections with one or more other devices or chips (not shown for simplicity) connected to the device 800. The transmit / receive block 850 may include several different serial transceivers, such as, for example, Gigabit serial transceivers (GTs). In some implementations, the transmit / receive block 850 may be implemented as multiple repeatable tiles positioned at various locations along the right and left sides of the device 800, as depicted in FIG. 8. In other implementations, the transmit / receive block 850 may be positioned at other suitable locations on the device 800. In one or more implementations, each of the transmit / receive blocks 850 may be coupled to one or more associated voltage supplies (not shown for simplicity). In some aspects, each bank of transmit / receive circuits in a given transmit / receive block 850 may include or be coupled to a corresponding voltage supply, such that, for example, each bank of transmit / receive circuits may be powered using a separate voltage supply.

[0134] The I / O blocks 860 may be coupled to I / O pins (not shown for simplicity) of the device and provide I / O capabilities to the device 800. For example, the I / O blocks 860 may receive data from one or more other devices and move the received data to several destinations within the device 800. The I / O blocks 860 may also receive data from several sources within the device 800 and move the received data to one or more other devices via the I / O pins of the device. In some implementations, the I / O blocks 860 may be implemented as repeatable tiles. The device 800 may include any suitable number of I / O blocks 860, and thus, the example implementation depicted in FIG. 8 is merely illustrative.

[0135] The I / O block 860 may include any number of suitable I / O circuits or devices. In some implementations, the I / O block 860 may include an ultra-high performance I / O (XPIO) circuit, a high density I / O (HDIO) circuit, and a multiplexed I / O (MIO) circuit. The XPIO circuit may be optimized for high performance communications, such as providing a high speed low latency interface to the memory controller 870. In one or more implementations, the XPIO circuit may include dedicated memory resources accessible by other subsystems of the device 800 without using the memory controller 870. The HDIO circuit may provide a cost-effective solution that supports lower speed and higher voltage I / O capabilities (compared to the XPIO circuit). The MIO circuit may provide general purpose I / O resources accessible by various subsystems, such as, for example, the PL 810, the dedicated circuit equipment 830, and the CPM 840.

[0136] The memory controller 870 may be used to control access to various memory resources provided within and / or outside the device 800. In some implementations, the memory controller 870 may be used to access dedicated memory resident in one or more of the I / O blocks 860. The memory controller 870 may include a double data rate v4 (DDR4) memory controller, a high bandwidth memory (HBM) controller, and / or other suitable memory controller. In one or more implementations, some or all of the memory controllers 870 may include a scheduler with transaction reordering capabilities that may improve memory access efficiency. Additionally, or in another manner, the repeatable tiles implementing the memory controllers 870 may differ from one another. For example, a first number of memory controllers 870 may implement a DDR4 memory controller, a second number of memory controllers 870 may implement an LPDDR4 memory controller, and a third number of memory controllers 870 may implement an HBM controller.

[0137] The device 800 may include any number of I / O blocks 860 and memory controllers 870, and thus the number and location of I / O blocks 860 and memory controllers 870 depicted in FIG. 8 are merely illustrative. In some implementations, a first row of I / O blocks 860 and memory controllers 870 may be implemented as a repeatable tile positioned along a bottom edge of the device 800, and a second row of I / O blocks 860 and memory controllers 870 may be implemented as a repeatable tile positioned along a top edge of the device 800. In some implementations, the I / O blocks 860 and memory controllers 870 may be interleaved or distributed with respect to each other, for example, as depicted in the example of FIG. 8. In other implementations, pairs of I / O blocks 860 and memory controllers 870 may be implemented within the same repeatable tile.

[0138] In some implementations, a first row of I / O blocks 860 and memory controllers 870 located along a bottom of device 800 may be coupled to a first horizontal segment of NoC interconnect system 820, and a second row of I / O blocks 860 and memory controllers 870 located along a top of device 800 may be coupled to a second horizontal segment of NoC interconnect system 820. In this manner, NoC interconnect system 820 may provide connections between programmable resources of device 800 and its I / O pins (not shown for simplicity).

[0139] In some implementations, device 800 may include one or more columns of connection fabric (not shown for simplicity) that extends vertically across the height of device 800 and is positioned proximate to transmit / receive block 850. The connection fabric may include one or more hardwire connection circuits including (but not limited to) a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC (MRMAC), a PCIe controller, a CCIX controller, and / or other components to provide connections between transmit / receive block 850 and PL 810.

[0140] The configuration logic 880 may be used to load configuration data (such as a configuration bitstream) from an external memory, as well as root portions of the configuration data (such as frames, words, bytes, and / or bits), into appropriate configuration registers that define how various programmable resources of the device 800 are configured. The configuration logic 880 may also be used to partially reconfigure the device 800 and / or to internally reconfigure one or more portions of the device 800. In some implementations, the configuration logic 880 may include configuration registers, boundary scan test circuitry (such as a TAP controller circuitry), encryption circuitry for encrypting a bitstream of configuration data read from the device 800, and decryption circuitry for decrypting a bitstream of configuration data loaded into the device 800.

[0141] Although not shown for simplicity, device 800 may include an interface between the programmable fabric and each of the rows of I / O blocks 860 and memory controllers 870 located at the boundaries of device 800. This interface, sometimes referred to herein as a boundary logic interface (BLI), may allow large, complex external devices (such as HBMs) to appear as much smaller blocks (such as CLBs) within the programmable fabric of device 800. In some implementations, the BLI may be located in rows located at the top and bottom boundaries or edges of the programmable fabric. In this manner, the BLI may be used to route signals between columnar logic structures (such as CLB columns or DSP columns) and rows of I / O resources (such as I / O blocks 860).

[0142] According to various aspects of the present disclosure, the programmable device 800 may include a monitoring system capable of monitoring one or more operational conditions of a plurality of selected circuits provided throughout the programmable device 800, for example, to ensure that the selected circuits operate within specified operational parameters. The monitoring system disclosed herein may measure any suitable operational condition of the selected circuits, including, for example, temperature, voltage levels, and current levels. As used herein, the term "selected circuit" may refer to any circuit, component, supply voltage, structure, or device that can be selected to monitor one or more operational conditions to ensure proper operation of the device 800. In some implementations, the monitoring system may generate an alarm (or multiple alarms) when one or more measured operational conditions of the selected circuit do not fall within a specified range of operational conditions. In some aspects, the alarm may be used to power down one or more circuits or components of the device 800. In other aspects, the alarm may be used to power down the entire device 800.

[0143] The monitoring system may include (or may be formed by) a route monitor 890, satellite monitors 892(1)-892(19), and sensors (S). The route monitor 890 may include circuitry coupled to the NoC interconnect system 820 and analog channels 821 and configured to generate a high-precision, temperature-independent reference voltage. The temperature-independent reference voltage may be distributed to each of the satellite monitors 892(1)-892(19) via one or more analog channels 821, thereby eliminating the need for each of the satellite monitors 892(1)-892(19) to generate its own high-precision, temperature-independent reference voltage. In some implementations, the route monitor 890 may be located within a processor system of the device 800, for example, as depicted in FIG. 8. In other implementations, the route monitor 890 may be located in other suitable locations within the device 800.

[0144] The sensors (S) may be any suitable sensing circuit or device capable of generating an electrical signal indicative of one or more operating conditions of at least one of the selected circuits, and may include (but are not limited to) a temperature sensor, a voltage sensor, and / or a current sensor. In some implementations, each sensor (S) may measure an operating condition of one or more selected circuits and provide an analog signal indicative of the measured operating condition to a corresponding one of the satellite monitors 892(1)-892(19).

[0145] The satellite monitors 892(1)-892(19) may be any suitable circuit or device capable of converting an analog signal (S) generated by a sensor into digital data indicative of a measured operating condition of a selected circuit. Although not shown in FIG. 8 for simplicity, in some implementations, each of the satellite monitors 892(1)-892(19) may include at least an analog-to-digital converter (ADC), a local voltage source having a relatively small size (such as compared to a bandgap voltage generator), a calibration circuit, and a correction circuit. The ADC may be any suitable circuit capable of converting an analog signal into digital data and may include one or more inputs for receiving an analog signal generated by one or more associated sensors (S), one or more outputs for providing digital data indicative of an operating condition measured by the associated sensor (S), and one or more reference terminals for receiving a local reference voltage. In some implementations, each of the satellite monitors 192(1)-192(19) may include at least an analog-to-digital converter (ADC), a local voltage store configured to store a local reference voltage for the corresponding ADC, a calibration circuit, and a correction circuit. The local voltage store may be or use a capacitor for some implementations and has a relatively small size compared to the bandgap voltage generator. In some implementations, the circuit area consumed by the local voltage store may be at least an order of magnitude smaller than the circuit area consumed by the bandgap voltage generator. The voltage store may be selectively coupled to one or more analog channels to charge the voltage store to a value approximately equal to the temperature-independent reference voltage. The resulting charge stored in the voltage store may be a local reference voltage provided to a reference terminal of the ADC.

[0146] The local voltage source may generate a local reference voltage, which may be relatively inaccurate compared to the highly accurate and temperature independent reference voltage provided by the route monitor 890. In some implementations, the local reference voltage may be at least one order of magnitude less accurate than the temperature independent reference voltage generated by the bandgap voltage generator. In one or more implementations, the local reference voltage may have an accuracy of approximately 5% within the target voltage, while the temperature independent reference voltage may have an accuracy of approximately 0.5% within the target voltage. The calibration circuit may generate a correction factor indicative of an error in the digital code generated by the ADC, and the correction circuit may correct the digital code based on the correction factor.

[0147] The sensors (S) and satellite monitors 892(1)-892(19) may be distributed throughout the programmable device 800 and positioned at various locations near selected circuits, such that analog signals indicative of operational conditions of the selected circuits may be converted to digital signals at the various distributed locations (rather than being sent to a central hub and then converted to digital data). In some implementations, each of the sensors (S) may be positioned near a corresponding selected circuit, such that the sensor (S) and the corresponding selected circuit may be coupled together using a local signal line. Similarly, each of the satellite monitors 892(1)-892(19) may be positioned near one or more associated sensors (S), such that the satellite monitor 892 and the one or more associated sensors (S) may be coupled together using a local signal line. In some aspects, the term "nearby" as used herein may refer to the distance over which an analog signal indicative of operational conditions may be transmitted over a relatively short local signal wire with minimal signal degradation.

[0148] 8 , a first group of sensors (S) within the transceiver block 850 may be positioned proximate each of the voltage supplies (not shown for simplicity) associated with the transceiver block 850, and a first group of satellite monitors 892(1)-892(6) may be positioned proximate the first group of sensors (S), such that each of the first group of sensors (S) may be coupled to a corresponding supply voltage and corresponding satellite monitor 890 by a relatively short local signal wire. In some implementations, each of the first group of sensors (S) may be configured to generate an analog signal indicative of one or more operating conditions of the corresponding voltage supply, and each of the first group of satellite monitors 892(1)-892(6) may be configured to convert the analog signal generated by the associated sensor (S) into digital data transmittable to the route monitor 890 via the NoC interconnect system 820.

[0149] The second group of sensors (S) within the PL 810 may be positioned proximate one or more corresponding selected circuits (not shown for simplicity) within or associated with the PL 810, and the second group of satellite monitors 892(7)-892(19) may be positioned proximate the second group of sensors (S), such that, for example, each of the second group of sensors (S) may be coupled to the corresponding selected circuit and a corresponding one of the second group of satellite monitors 892(7)-892(19) by a relatively short local signal wire. In some implementations, each of the second group of sensors (S) may be configured to generate an analog signal indicative of one or more operating conditions of the corresponding selected circuit, and each of the second group of satellite monitors 892(7)-892(19) may be configured to convert the analog signal generated by the associated sensor (S) into digital data transmittable to the root monitor 890 via the NoC interconnect system 820.

[0150] Each of the satellite monitors 892(1)-892(19) may be coupled to any suitable number of sensors (S) by local signal lines. As one example, the satellite monitor 892(1) may be coupled to a single sensor (S) located in the transmit / receive block 850 and may generate a digital signal indicative of one or more operational conditions of a corresponding voltage supply associated with the transmit / receive block 850. As another example, the satellite monitor 892(16) may be coupled to two sensors (S) located in the PL 810 and may generate a digital signal indicative of one or more operational conditions of selected circuits associated with the two sensors (S) located in the PL 810. As another example, the satellite monitor 892(17) may be coupled to four sensors (S) located in the PL 810 and may generate a digital signal indicative of one or more operational conditions of selected circuits associated with the four sensors (S) located in the PL 810. Additionally, although shown in FIG. 8 as including nineteen satellite monitors 892(1) through 892(19), the programmable device 800 may include other numbers of satellite monitors 892 positioned in other suitable locations on the programmable device 800.

[0151] As described above, the satellite monitors 892(1)-892(19) may be positioned close enough to the sensors (S) that relatively short local signal wires may be used to couple each of the sensors (S) to a corresponding satellite monitor 892, rather than using a central system monitor to transmit analog signals over relatively long distances for conversion to digital data. In this manner, implementations of the monitoring system disclosed herein may eliminate the need for metal layer signal routing resources to route these analog signals from various locations distributed throughout the device 800 to a central monitor for conversion to digital data, which may reduce the complexity and cost of the device while further improving the scalability of the monitoring system. Moreover, by using multiple satellite monitors 892(1)-892(19) distributed throughout the device 800 to perform analog-to-digital conversion of analog sensor data and then route the digital data to the route monitor 890 for analysis, the number of sensors that can be measured simultaneously is not limited by the number of input channels of the ADC provided within the satellite monitors. In contrast, the number of sensors that can be simultaneously measured by conventional solutions that route analog sensor data to a central system monitor for conversion to digital data is limited by the number of input channels of the ADC associated with the system monitor. Thus, by distributing the conversion of analog sensor data to digital information at various locations throughout the device 800 via satellite monitors 892(1)-892(19), the number of sensors that can be simultaneously measured by the monitoring system disclosed herein may be based on the number of satellite monitors 892(1)-892(19) rather than the number of input channels of a central ADC that receives analog signals from sensors distributed throughout the device. As a result, the monitoring system disclosed herein may simultaneously measure a much larger number of sensors than the conventional solutions discussed above.

[0152] The route monitor 890 may receive the digital data routed from each of the satellite monitors 892(1)-892(19) by the NoC interconnect system 820 and may process the received digital data to determine the operating conditions of the selected circuits monitored by the sensors. In some implementations, the route monitor 890 may compare the measured operating conditions to one or more reference values ​​to determine whether each of the selected circuits is operating within its specified operating range.

[0153] It should be noted that Figure 8 is intended to depict just one illustrative architecture for programmable device 800. For example, the number of logic blocks in a column (or row), the relative widths of the columns (or rows), the number and order of columns (or rows), the types of logic blocks included in the columns (or rows), the relative sizes of the logic blocks, and other structural aspects depicted in Figure 8 are merely illustrative of various implementations of the inventive subject matter disclosed herein.

[0154] 9 illustrates a functional block diagram of a programmable device 900 that may be one example of the programmable device 800 of FIG. 8 according to some implementations. The device 900 is shown to include a transceiver block 850, a programmable logic (PL) 910, a CPM 920, a processing system (PS) 930, a platform management controller (PMC) 940, and an I / O block + memory controller 960. The PL 910 may be one implementation of the PL 810 of FIG. 8 and may be adjacent to and directly connected to the transceiver block 850, the CPM 920, the PMC 940, and the NoC interconnect system 820. The I / O block + memory controller 960 may be one implementation of the I / O block 860 and the memory controller 870 of FIG. 8 and may be implemented as multiple repeatable tiles arranged along the bottom edge of the programmable device 900. 9 for simplicity, the I / O block+memory controller 960 may also be implemented as multiple repeatable tiles arranged along the top edge of the programmable device 900. Additionally, or in the alternative, the I / O block+memory controller 960 may be implemented as multiple repeatable tiles arranged along the right and left edges of the programmable device 900.

[0155] CPM 920 may be one implementation of CPM 840 of FIG. 8 and may provide interface capabilities for several different bus standards. In some implementations, CPM 920 may include a Peripheral Component Interconnect Express (PCIe) interface 922, a direct memory access (DMA) circuit 924, and a Cache Coherent Interconnect for Accelerators (CCIX) interface 926. PCIe interface 922 may be used to exchange data between PS 930 and one or more other devices or chips via transmit / receive block 850 in accordance with the PCI protocol. Similarly, CCIX interface 926 may be used to exchange data between PS 930 and one or more other devices or chips via transmit / receive block 850 in accordance with the CCIX protocol.

[0156] The PS 930 may provide dedicated data processing capabilities to the device 900 and is shown to include an application processing unit (APU) 932, a real-time processing unit (RPU) 934, a cache memory 936, and a system-on-a-chip (SoC) interface 938. Although not shown for simplicity, the PS 930 may also include peripherals for communication standards (such as Ethernet and USB 2.0 interfaces), as well as various controllers (such as SPI, I2C, UART, and CAN-FD controllers). The APU 932 and RPU 934 may each include one or more processing cores (such as CPUs) capable of providing dedicated scalar processing capabilities to the device 900. In some aspects, the PS 930 may be selectively connected to other subsystems of the device 900 by the programmable interconnect fabric and NoC interconnect system 820.

[0157] In some implementations, the APU 932 may include a multi-core ARM processor supporting hardware virtualization and may have a built-in interrupt controller and snoop control unit. The interrupt controller may support virtual interrupts, and the snoop control unit may be used to maintain coherency between one or more caches used and / or shared by the APU 932 and the RPU 934. The APU 932 may communicate with other components of the PS 930 using an AXI coherent extension (ACE) port and may communicate with the PL 910 using an accelerator coherency port (ACP). In some implementations, the RPU 934 may include a multi-core ARM processor supporting real-time data processing, may include a tightly coupled memory (TCM) interface for real-time single cycle access, and may have a dedicated interrupt controller and floating point unit. The RPU 934 may communicate with other components of the PS 930 and / or with the PL 910 using an AXI port.

[0158] The cache memory 936 may be any suitable high-speed cache that allows shared access by the APU 932 and the RPU 934. The SoC interface 938 may provide a connection between various resources of the PS 930 and the NoC interconnect system 820.

[0159] The PMC 940 may include a security circuit device 942, a boot and reconfiguration circuit device 944, an analog circuit device 946, and the root monitor 890 of FIG. 8. The security circuit device 942 may provide data encryption / decryption capabilities and other security features. The boot and reconfiguration circuit device 944 may provide a multi-stage boot process that supports both non-secure and secure boot. The analog circuit device 946 may include any suitable analog circuit device components. Additionally, although not shown in FIG. 9 for simplicity, the PMC 940 may include test and debugging resources (such as JTAG circuit devices), an external flash memory interface, and other components or circuits. In some implementations, the PMC 940 may enable a portion of the PL 910 to be reconfigured using a partial reconfiguration operation. For example, a new configuration bitstream for a portion of the PL 910 may be loaded from the PS 930 via a primary or secondary boot interface (such as PCIe or Ethernet) and then stored in a configuration register associated with the portion of the PL 910 to be reconfigured. The ability to allow partial reconfiguration of one or more portions of the PL 910 may enable a user to more quickly reconfigure the device 900 to reflect changes or updates to a user-specified circuit design (such as comparable to other programmable devices).

[0160] FIG. 10 illustrates a block diagram of an example programmable fabric 1000 according to some implementations. In some implementations, the programmable fabric 1000 can be the PL 810 of FIG. 8, the PL 910 of FIG. 9, or both. The programmable fabric 1000 is shown to include a number of different programmable circuit blocks or tiles that can be arranged in columns (or rows). The programmable circuit blocks can include (but are not limited to) programmable interconnect elements (INT) 1010, configurable logic elements (CLEs) 1020, DSPs 1030, and block RAMs (BRAMs) 1040 arranged in a columnar architecture. As an example of FIG. 10, the programmable fabric 1000 is shown to include eleven columns of programmable interconnect elements 1010, five columns of CLEs 1020, two columns of DSPs 1030, and two columns of BRAMs 1040. In other implementations, programmable fabric 1000 may include other numbers of columns of programmable interconnect elements 1010, CLEs 1020, DSPs 1030, and BRAMs 31040. Programmable fabric 1000 may also include several other subsystems or components (such as processing cores, programmable interconnect structures, and the like) that are not shown in FIG. 10 for simplicity.

[0161] The programmable interconnect elements 1010, CLEs 1020, DSPs 1030, and BRAMs 1040 may be implemented as repeatable tiles throughout the programmable fabric 1000. Each of the tiles may include at least one programmable interconnect element 1010 that provides local signal interconnects to programmable logic elements within the same tile, to programmable interconnect elements 1010 in adjacent tiles, and / or to other signal routing resources. The programmable interconnect elements 1010 may collectively form at least a portion of the programmable interconnect fabric (or other suitable block-level and / or device-level signal routing structure).

[0162] In some implementations, the programmable fabric 1000 may include a cylindrical hard block 1050 that extends vertically across the height of the programmable fabric 1000. The hard block 1050 may include several hardwired circuits, such as, for example, a USB controller, an Ethernet MAC, a multi-rate (MR) Ethernet MAC, a PCIe controller, a CCIX controller, and / or other suitable circuits or components that implement the physical, data link, and transaction layers of the PCIe protocol. In some implementations, the hard block 1050 may be an implementation of one of the connectivity fabrics described above with respect to FIG.

[0163] 11 illustrates a functional block diagram of a monitoring system 1100 according to some implementations. The monitoring system 1100 may be implemented within the programmable device 800 of FIG. 8 and is shown to include a route monitor 1110, a plurality of satellite monitors SAT1-SAT15, a plurality of supply voltage sensors SV1-SV4, a plurality of temperature sensors T5-T15, and a plurality of selected circuits CKT5-CKT15. The route monitor 1110 may be one implementation of the route monitor 890 of FIG. 8 and is coupled to the NoC interconnect system 820 and one or more analog channels 821. In some implementations, the route monitor 1110 is coupled to a temperature independent reference voltage V REF A bandgap voltage generator (not shown for simplicity) may be included to generate

[0164] The satellite monitors SAT1-SAT15 may be distributed throughout the device 800 and positioned such that each of the satellite monitors SAT1-SAT15 is located proximate a corresponding one of the sensors SV1-SV4 and T5-T15. For the example implementation of FIG. 11, the satellite monitors SAT1-SAT4 are coupled to respective supply voltage sensors SV1-SV4 via local signal wires, and the satellite monitors SAT5-SAT15 are coupled to respective temperature sensors T5-T15 via local signal wires. In this manner, analog signals generated by the supply voltage sensors SV1-SV4 may be provided by the local signal wires to the respective satellite monitors SAT1-SAT4, and analog signals generated by the temperature sensors T5-T15 may be provided by the local signal wires to the respective satellite monitors SAT5-SAT15. By positioning the satellite monitors SAT5-SAT15 in close proximity to (e.g., near) the associated sensors SV1-SV4 and T5-T15, the analog signals generated by the sensors SV1-SV4 and T5-T15 do not need to be routed across large portions of the device 800 to reach the route monitor 1110, thereby minimizing signal degradation associated with routing relatively small analog signals across metal layer interconnects spread throughout the device 800. Moreover, because each of the analog signals generated by the sensors SV1-SV4 and T5-T15 can be converted locally to digital data using a nearby one of the satellite monitors SAT1-STA15, expensive metal layer routing resources are not required to implement the monitoring system 1100 within a programmable device (such as the programmable device 800 of FIG. 8).

[0165] As one example, a sensor SV1 may monitor the operating condition of an associated supply voltage by generating an analog signal indicative of the voltage level of the associated supply voltage. By positioning a corresponding satellite monitor SAT1 in the vicinity of the sensor SV1, the analog signal generated by the sensor SV1 does not have to be routed across the device 800 to the route monitor 1110, but instead can be routed a relatively short distance to the satellite monitor SAT1 via a local signal wire. As another example, a sensor T5 may monitor the operating condition of an associated circuit CKT5 by generating an analog signal indicative of the temperature of the associated circuit CKT5. By positioning a corresponding satellite monitor SAT5 in the vicinity of the sensor T5, the analog signal generated by the sensor T5 does not have to be routed across the device 800 to the route monitor 1110, but can instead be routed a relatively short distance to the satellite monitor SAT5 via a local signal wire.

[0166] Temperature-independent reference voltage V REF may be distributed throughout the device 800 and made accessible to each of the satellite monitors SAT1-STA15 by one or more analog channels 821, and digital data may be selectively routed from each of the satellite monitors SAT1-STA15 to the root monitor 1110 by the NoC interconnect system 820. In some implementations, the one or more analog channels 821 may extend along corresponding portions of the NoC interconnect system 820. In other implementations, the one or more analog channels 821 may be separate from the NoC interconnect system 820.

[0167] 12 shows a block diagram of an example route monitor 1200 according to some implementations. The route monitor 500 may be one implementation of the route monitor 890 of FIG. 8 or the route monitor 1110 of FIG. 11 (or both) and is shown to include a bandgap voltage generator 1210, a memory 1220, and a controller 1230. The bandgap voltage generator 1210 generates a high-precision and temperature-independent reference voltage VREF , and includes an output coupled to one or more analog channels 821. In some implementations, the bandgap voltage generator 1210 generates a temperature independent reference voltage V REF may be provided to one or more analog channels 821 as a differential voltage (e.g., including both a positive and a negative reference voltage). In some embodiments, the temperature independent reference voltage V REF can be equal to 1.25 volts, but other suitable voltages are REF It can be used as:

[0168] With further reference to FIG. 8 , in some implementations, the temperature independent reference voltage V generated by the bandgap voltage generator 1210 REF may be distributed to each of the satellite monitors 892(1)-892(19) located throughout the device 800 using one or more analog channels 821. The satellite monitors 892(1)-892(19) may each provide, for example, a high-precision, temperature-independent reference voltage V REF To compensate for analog-to-digital conversion errors associated with using a relatively inaccurate local reference voltage to sample the analog signal (rather than using a temperature-independent reference voltage V REF may be selectively accessed to charge their respective voltage stores and periodically calibrate their ADCs.

[0169] The memory 1220 includes a data input coupled to the NoC interconnect system 820, a control input coupled to the controller 1230, a data output coupled to the controller 1230, and one or more output ports that allow a user to access data stored in the memory 1220 via one or more of a JTAG interface, a multiplexed input / output (MIO) block, or an AXI interface. In some implementations, the memory 1220 may include a number of status registers 1221 and a number of alarm registers 1222. The status registers 1221 may store digital data indicative of the operating status of selected circuits provided throughout the device 800, and the alarm registers 1222 may store a number of reference values ​​that define a number of specified operating ranges. The status register 1221 may be loaded with digital data routed from the satellite monitors 892(1)-892(19) to the root monitor 1200 via the NoC interconnect system 820, and the alarm register 1222 may be loaded with a reference value during configuration (or reconfiguration) of the programmable device 800.

[0170] The controller 1230 may control various operations of the route monitor 1200, may analyze digital data received from the satellite monitors 892(1)-892(19) to determine if any of the selected circuits are not operating within their specified operating ranges, and may generate result data accessible by a user. In some implementations, the controller 1230 may determine if the selected circuits are operating within the specified operating ranges by comparing the measured operating conditions stored in the status registers 1221 with corresponding reference values ​​stored in the alarm registers 1222. If it is determined that the selected circuits are operating outside their specified operating ranges, the controller 1230 may generate an alarm. In some aspects, the alarm may, for example, disable or power down the selected circuits until the operating conditions of the selected circuits are within their specified operating ranges. In other aspects, the alarm may, for example, cause the programmable device 800 to power down or operate at a reduced power level until the operating conditions of the selected circuits are within their specified operating ranges.

[0171] Some of the specified operating ranges stored in the alarm register 1222 may be defined by minimum and maximum reference values. In some implementations, the specified voltage ranges may include a minimum voltage value and a maximum voltage value. In such implementations, the controller 1230 may compare the measured voltage of the selected circuit to the minimum and maximum voltage values ​​stored in the alarm register 1222 and generate one or more alarms based on the comparison. For example, if the measured voltage is between the minimum and maximum voltage values, the controller 1230 may indicate that the selected circuit is operating within its specified voltage range. Conversely, if the measured voltage is less than the minimum voltage value or greater than the maximum voltage value, the controller 1230 may generate an alarm to indicate that the selected circuit is not operating within its specified voltage range.

[0172] Other specified operating ranges stored in the alarm register 1222 may include reference values ​​that define upper operable limits. In some implementations, the specified temperature range of the selected circuit may be defined by a reference temperature value. In such implementations, the controller 1230 may compare the measured temperature of the selected circuit to the reference temperature value stored in the alarm register 1222 and generate one or more alarms based on the comparison. For example, if the measured temperature is less than (or equal to) the reference temperature value, the controller 1230 may indicate that the selected circuit is operating within its specified temperature range. Conversely, if the measured temperature is greater than the reference temperature value, the controller 1230 may generate an alarm to indicate that the selected circuit is too hot or overheated.

[0173] In some implementations, the controller 1230 may be configured to generate control signals CTRL[1:19] that can be used by each satellite monitor 892(1)-892(19) to operate in a calibration mode or a monitoring mode. When operating in a calibration mode, each satellite monitor 892 receives a temperature independent reference voltage V from one or more analog channels 821. REF , and a correction factor indicative of analog-to-digital conversion errors resulting from inaccuracies in a relatively inaccurate local reference voltage (such as that described with respect to FIG. 13 ) can be obtained by REF When operating in a monitoring mode, each satellite monitor 892 may convert an analog signal generated by one or more sensors (S) into a digital code and may correct the digital code based on a correction factor (such as those described with respect to FIG. 13 ). In some implementations, the controller 1230 may control whether only one of the satellite monitors 892(1)-892(19) receives the V from one or more analog channels 821. REF In this manner, the route monitor 1200 may selectively assert the control signals CTRL[1:19] based on a timing schedule such that two or more of the satellite monitors 892(1)-892(19) may simultaneously access the temperature independent reference voltage V REFThe temperature-independent reference voltage V REF This can prevent the drop in the

[0174] The timing schedule may be stored in memory 1220 and may be, for example, synchronized with V to ensure that any periodic variations in the local reference voltages used by and / or stored in each of the satellite monitors 892(1)-892(19) are compensated for by corresponding updates to the correction factors. REF The timing schedule may include a schedule for periodically calibrating each of the satellite monitors 892(1)-892(19) using the VREF signal. For example, in one or more implementations, the controller 1230 may sequentially assert the control signals CTRL[1:19] every N milliseconds, where N may be any suitable number, such that each of the satellite monitors 892(1)-892(19) performs a calibration operation every N milliseconds. The timing schedule may also include, for example, a schedule for periodically calibrating each of the satellite monitors 892(1)-892(19) using the VREF signal to maintain a local reference voltage held by the voltage store within a range (e.g., within the value of a temperature independent reference voltage). REF The satellite monitors 192(1)-192(19) may be used to include a schedule for periodically charging the voltage stores in each of the satellite monitors 192(1)-192(19).

[0175] 13 shows a block diagram of an example satellite monitor 1300 according to some implementations. Satellite monitor 1300 may be an example of any number of satellite monitors 892(1)-892(19) of FIG. 8 or one of satellite monitors SAT1-SAT15 (or both) of FIG. 11 and is shown to include an ADC 1310, a memory 1320, a local voltage source 1330, a calibration circuit 1340, a correction circuit 1345, and a switch SW. Switch SW couples a temperature independent reference voltage V REFa first input terminal coupled to receive an analog signal generated by one or more associated sensors 20, a control terminal coupled to receive a corresponding control signal CTRL generated by the route monitor 1200, and an output terminal coupled to an input terminal of the ADC 1310. In some aspects, the sensors 20 may include (but are not limited to) a temperature sensor 21, a supply voltage sensor 22, and an external sensor 23.

[0176] The ADC 1310 includes an output terminal coupled to the memory 1320 and includes one or more reference terminals coupled to a local voltage source 1330. The ADC 1310 may be (or may include) any suitable ADC capable of converting analog signals generated by one or more of the sensors 20 into digital data or digital code. In some implementations, the ADC 1310 may utilize a scaled architecture to digitize the analog sensed data provided by the sensors 20.

[0177] The memory 1320 may be any suitable storage device and includes an input coupled to an output terminal of the ADC 1310 and an output coupled to the NoC interconnect system 820. The memory 1320 may store digital data generated by the ADC 1310 in response to an analog signal provided by one or more of the sensors 20 and may provide the digital data to the NoC interconnect system 820 for routing to the route monitor 1200 of FIG. 12. In some implementations, the memory 1320 may be or include a plurality of registers for respectively storing digital data indicative of an operating condition of a corresponding one of the plurality of circuits selected for monitoring. In this manner, the satellite monitor 1300 may receive an analog signal indicative of an operating condition of a corresponding one of the selected circuits from the sensor 20, convert the analog signal to digital data, and provide the digital data indicative of the operating condition of the selected circuit to the route monitor 1200 via the NoC interconnect system 820.

[0178] The local voltage source 1330 provides a local reference voltage V suitable for use by the ADC1310. REF_LOCAL 12. The local voltage source 1330 may be constructed using as few as ten transistors and occupies a circuit area significantly smaller than the bandgap voltage generator 1210 of FIG. 12. In some implementations, the local voltage source 1330 may occupy at least an order of magnitude smaller circuit area than the bandgap voltage generator 1210 of FIG. 12. For example, in one or more implementations, the circuit area occupied by the local voltage source may be on the order of tens of square microns.

[0179] Local reference voltage V REF_LOCAL is the temperature independent reference voltage V generated by the band gap voltage generator 1210. REF , which may cause errors in the digital code generated by the ADC 1310. In some implementations, the local reference voltage provided by the local voltage source 1330 may be at least one order of magnitude less accurate than the temperature independent reference voltage generated by the bandgap voltage generator 1210. In one or more implementations, the local reference voltage may have an accuracy of approximately 5% within the target voltage, while the temperature independent reference voltage may have an accuracy of approximately 0.5% within the target voltage.

[0180] The calibration circuit 1340 may include an input coupled to receive the digital code from the output terminal of the ADC 1310, an output for providing a correction factor to the correction circuit 1345, and a control terminal for receiving a corresponding control signal CTRL from the route monitor 1200. The correction circuit 1345 may be coupled between the ADC 1310 and the memory 1320 and includes a terminal for receiving the correction factor provided by the calibration circuit 1340. In some implementations, the calibration circuit 1340 may be configured to generate a correction factor to compensate for errors in the digital code generated by the ADC 1310, and the correction circuit 1345 may be configured to correct the digital code generated by the ADC 1310 based on the correction factor.

[0181] For example, during a calibration operation, the asserted state of the control signal CTRL causes the switch SW to connect to the temperature independent reference voltage V REF may be provided as an input signal to the ADC 1310 and may enable the calibration circuit 1340. The ADC 1310 may use a temperature independent reference voltage V REF , and the calibration circuit 1340 samples the reference code generated by the ADC 1310 and V REF A correction factor may be generated based on the difference between a predetermined digital code representing a known value of V. During monitoring operation, a deasserted state of the control signal CTRL may cause the switch SW to provide an analog signal from the sensor 20 as an input signal to the ADC 1310, REF and / or may isolate the satellite monitor 1300 from the NoC interconnect system 820. The ADC 1310 may sample the analog signal provided by the sensor 20 and generate a digital code. The correction circuit 1345 may use the correction factor to correct the digital code, for example, by adjusting the digital code based on the correction factor. In this manner, the satellite monitor 1300 may correct the relatively inaccurate local reference voltage V REF_LOCAL This can compensate for analog-to-digital conversion errors resulting from errors in the

[0182] Figure 14 is an illustrative flowchart depicting example operations 1400 for monitoring the operational status of multiple circuits distributed at various locations throughout a programmable device, according to some implementations. The example operations 1400 are described below for the programmable device 800 of Figure 8, the monitoring system 1100 of Figure 11, the root monitor 1200 of Figure 12, and the satellite monitor 1300 of Figure 13, for illustrative purposes only. It will be understood that the example operations 1400 may be performed by other programmable devices disclosed herein and / or by other suitable devices.

[0183] The operations 1400 may begin at block 1401 by generating an analog signal indicative of an operating condition of each of a plurality of circuits using a corresponding one of a plurality of sensors distributed at various locations throughout the programmable device. In some implementations, each of a number of sensors 20 may be in the vicinity of an associated circuit. In some aspects, the sensor 20 may be (or may include) at least one of a temperature sensor 21, a supply voltage sensor 22, or an external sensor 23. In some implementations, the route monitor 890 may generate a trimmed and temperature independent reference voltage V, e.g., using the bandgap circuit 1212 of FIG. 12. REF This can cause the following problems.

[0184] The operations 1400 may proceed, at block 1402, by providing each of the analog signals to a corresponding one of a number of satellite monitors distributed at various locations throughout the programmable device. In some implementations, the analog signals generated by the sensors 20 may be provided to corresponding satellite monitors 892(1)-892(19) using relatively short local signal wires, as opposed to conventional programmable devices in which analog signals indicative of operational status of various circuits, for example, are routed throughout the device using metal layer signal routing structures and provided to a central monitor.

[0185] The operations 1400 may proceed, in block 1403, by generating a local reference voltage using a local voltage source 1330 (e.g., based on a temperature-independent reference voltage) in each of the multiple satellite monitors 892(1)-892(19). The local voltage source 1330 may be relatively small and "area efficient" compared to the bandgap voltage generator 1210 provided in the route monitor 1200. In some implementations, the local voltage source 1330 may include fewer than 12 transistors and consume at least an order of magnitude less circuit area than the bandgap voltage generator 1210. In one or more implementations, the circuit area occupied by the local voltage source 1330 may be on the order of tens of square microns, while the circuit area occupied by the bandgap voltage generator 1210 may be on the order of hundreds of square microns (or possibly thousands of square microns).

[0186] The local reference voltage may be relatively inaccurate compared to the temperature independent reference voltage generated by the bandgap voltage generator 1210. In some implementations, the local reference voltage provided by and / or stored in the local voltage source 1330 may be at least one order of magnitude less accurate than the temperature independent reference voltage generated by the bandgap voltage generator 1210. In one or more implementations, the local reference voltage may have an accuracy of approximately 5% within the target voltage, while the temperature independent reference voltage may have an accuracy of approximately 0.5% within the target voltage.

[0187] The operations 1400 may proceed, at block 1404, by converting the corresponding analog signals to digital code using an analog-to-digital converter (ADC) in each of the plurality of satellite monitors 892(1)-892(19) based on a local reference voltage. With further reference to FIG. 13, the ADC circuitry 1310 provided in each of the satellite monitors 892(1)-892(19) may convert the analog signals to digital data that may be stored in a memory 1320 of each of the satellite monitors 892(1)-892(19). The memory 1320 may selectively provide the stored digital data to the interconnect system 820 for routing to the route monitor 890.

[0188] The operations 1400 may proceed at block 1405 by distributing a temperature independent reference voltage from the root monitor 890 to each of the multiple satellite monitors 892(1)-892(19). In some implementations, the temperature independent reference voltage may be distributed to each of the multiple satellite monitors 892(1)-892(19) using one or more analog channels 821 spanning the programmable fabric.

[0189] The operations 1400 may proceed at block 1406 by correcting a digital code generated by the ADC 1310 in each of the plurality of satellite monitors 892(1)-892(19) based at least in part on the distributed temperature-independent reference voltage. In some implementations, the digital code may be adjusted based on a correction factor indicative of an analog-to-digital conversion error resulting from an error in the local reference voltage.

[0190] The operations 1400 may proceed, at block 1407, by selectively routing the corrected digital code from the multiple satellite monitors 892(1)-892(19) to the root monitor 890. The corrected digital code may be selectively routed from the multiple satellite monitors 892(1)-892(19) to the root monitor 890 using the NoC interconnect system 820. In some implementations, each of the satellite monitors 892(1)-892(19) may provide the corrected digital code to the NoC interconnect system 820 in response to a signal (e.g., a trigger signal) generated by the route monitor 890, for example, to schedule or prioritize delivery of the digital data from the satellite monitors 892(1)-892(19) to the root monitor 890. In other implementations, the satellite monitors 892(1)-892(19) may provide digital data to the NoC interconnect system 820 without prompting and / or control by the root monitor 890.

[0191] FIG. 15 is an illustrative flowchart depicting example operations 1500 for correcting digital codes generated by ADCs provided in each of the satellite monitors. The example operations 1500 are described below for the programmable device 800 of FIG. 8, the monitoring system 1100 of FIG. 11, the route monitor 1200 of FIG. 12, and the satellite monitor 1300 of FIG. 13, for illustrative purposes only. It will be understood that the example operations 1500 may be performed by other programmable devices disclosed herein and / or by other suitable devices. In some implementations, the example operations may be examples of the process 1408 of the operations 1400 described above for FIG. 14.

[0192] The operations 1500 may begin, at block 1501, by providing a temperature independent reference voltage as an input signal to the ADC 1310. The operations 1500 may proceed, at block 1502, by converting the temperature independent reference voltage into a reference code using the ADC 1310. The operations 1500 may proceed, at block 1503, by generating a correction factor based on a difference between the reference code and a predetermined digital code indicative of the temperature independent reference voltage. The operations 1500 may proceed, at block 1504, by adjusting the digital code based on the correction factor.

[0193] FIG. 16 shows a block diagram of an example satellite monitor 1600 according to some implementations. The satellite monitor 1600 may be an example of any number of satellite monitors 892(1)-892(19) of FIG. 8 or one of the satellite monitors SAT1-SAT15 (or both) of FIG. 4 and is shown to include an ADC 1610, a memory 1620, a voltage store 1630, a calibration circuit 1640, a correction circuit 1645, a first switch SW1, and a second switch SW2. The first switch SW1 couples a temperature independent reference voltage V REF a first input terminal coupled to receive an analog signal generated by one or more associated sensors 20, a control terminal coupled to receive a corresponding one of the first control signals CTRL1, and an output terminal coupled to an input terminal of the ADC 1610. The second switch SW2 includes an input terminal coupled to receive a temperature independent reference voltage from one or more analog channels, a control terminal coupled to receive a corresponding one of the second control signals CTRL2, and an output terminal coupled to the voltage store 1630. In some embodiments, the sensors 20 may include (but are not limited to) a temperature sensor 21, a supply voltage sensor 22, and an external sensor 23.

[0194] The ADC 1610 includes an output terminal coupled to a memory 1620 and includes one or more reference terminals coupled to a voltage store 1630. The ADC 1610 may be (or may include) any suitable ADC capable of converting analog signals generated by one or more of the sensors 20 into digital data or code. In some implementations, the ADC 1610 may utilize a scaled architecture to digitize the analog sensed data provided by the sensors 20.

[0195] The memory 1620 may be any suitable storage device and includes an input coupled to an output terminal of the ADC 1610 and an output coupled to the NoC interconnect system 820. The memory 1620 may store digital data generated by the ADC 1610 in response to an analog signal provided by one or more of the sensors 20 and provide the digital data to the NoC interconnect system 820 for routing to the route monitor 1200 of FIG. 12. In some implementations, the memory 1620 may be or include a plurality of registers for respectively storing digital data indicative of an operating condition of a corresponding one of the plurality of circuits selected for monitoring. In this manner, the satellite monitor 1600 may receive an analog signal indicative of an operating condition of a corresponding one of the selected circuits from the sensor 20, convert the analog signal to digital data, and provide the digital data indicative of the operating condition of the selected circuit to the route monitor 1200 via the NoC interconnect system 820.

[0196] The Voltage Store 1630 stores a local reference voltage V suitable for use by the ADC1610. REF_LOCAL12. In some implementations, the voltage store 1630 may be a capacitor, for example, as depicted in FIG. 16. More specifically, in some implementations, the voltage store 1630 may be implemented as a capacitor C1, and the second switch SW2 may be implemented as a CMOS transistor M1. The capacitor C1 is coupled between the transistor M1 (acting as the second switch SW2) and a reference terminal of the ADC 1610, and may occupy a significantly smaller circuit area than the bandgap voltage generator 1210 of FIG. 12. Furthermore, the capacitor does not need to be trimmed during manufacturing, as a precision voltage reference, such as the bandgap voltage generator 1210. In some implementations, the voltage store 1630 may occupy at least an order of magnitude smaller circuit area than the bandgap voltage generator 1210 of FIG. 12. For example, in one or more implementations, the circuit area occupied by the local voltage store 1630 may be on the order of tens of square microns.

[0197] Local reference voltage V REF_LOCAL is the temperature independent reference voltage V generated by the band gap voltage generator 1210. REF , which may cause errors in the digital code generated by the ADC 1610. In some implementations, the local reference voltage provided by the local voltage store 1630 may be at least an order of magnitude less accurate than the temperature independent reference voltage generated by the bandgap voltage generator 1210. In one or more implementations, the local reference voltage may have an accuracy of approximately 5% within the target voltage, while the temperature independent reference voltage may have an accuracy of approximately 0.5% within the target voltage.

[0198] The calibration circuit 1640 may include an input coupled to receive the digital code from the output terminal of the ADC 1610, an output for providing a correction factor to the correction circuit 1645, and a control terminal for receiving a corresponding first control signal CTRL1 from the route monitor 1200. The correction circuit 1645 may be coupled between the ADC 1610 and the memory 1620 and includes a terminal for receiving the correction factor provided by the calibration circuit 1640. In some implementations, the calibration circuit 1640 may be configured to generate a correction factor to compensate for an error in the digital code generated by the ADC 1610, and the correction circuit 1645 may be configured to correct the digital code generated by the ADC 1610 based on the correction factor.

[0199] For example, during a calibration operation, the first control signal CTRL1 may be asserted (e.g., logic high) and the second control signal CTRL2 may be asserted (e.g., logic high). The asserted state of the first control signal CTRL1 causes the first switch SW1 to be connected to the temperature independent reference voltage V REF as an input signal to the ADC 1610 and may enable the calibration circuit 1640. An asserted state of the second control signal CTRL2 may open the second switch SW2 and couple the voltage store 1630 to one or more analog channels 821, thereby (causing) the stored charge to be coupled to the local reference voltage V REF_LOCAL The conduction state of switches SW1 and SW2 is then adjusted to, for example, V _REF may cause disturbances (such as a drop) in the temperature independent reference voltage caused by the ADC 1610 being coupled to the input terminal and to the voltage store 1630.

[0200] The voltage store 1630 is sufficiently charged to supply the local reference voltage V REF_LOCALUpon storing the temperature independent reference voltage V, the second control signal CTRL2 may be deasserted (e.g., to a logic low). The deasserted state of the second control signal CTRL2 may close the second switch SW2 and prevent the voltage store 1630 from accessing the temperature independent reference voltage V from one or more analog channels 821. The deassertion of the second control signal CTRL2 may also close the second switch SW2 and prevent the voltage store 1630 from accessing the temperature independent reference voltage V _REF In some implementations, the first control signal CTRL1 may cause a disturbance (such as a drop) in the temperature independent reference voltage V REF The first control signal CTRL1 may then be deasserted (e.g., to a logic low) and the ADC 1610 may use the temperature independent reference voltage V REF The calibration circuit 1640 may sample the reference code generated by the ADC 1610 and V REF A correction factor may be generated based on the difference between the predetermined digital code representing the known value of . The correction factor may be provided to (and stored in) the correction circuit 1645.

[0201] During the monitoring operation, the first control signal CTRL1 may remain in a deasserted state, thereby enabling the first switch SW1 to provide an analog signal generated by the sensor 20 as an input signal to the ADC 1610 (and may also disable the calibration circuit 1640). The ADC 1610 may sample the analog signal provided by the sensor 20 and generate a digital code indicative of the sampled analog signal. The correction circuit 1645 may use a correction factor generated during the calibration operation to correct the digital code, for example, by adjusting the digital code based on the correction factor. In this manner, the satellite monitor 1600 may calibrate the relatively inaccurate local reference voltage V REF_LOCAL This can compensate for analog-to-digital conversion errors resulting from errors in the

[0202] In some implementations, the calibration operation is REF_LOCAL) to maintain a minimum voltage level stored by the voltage store 1630 and to ensure that the satellite monitor 1600 remains properly calibrated.

[0203] example Example 1: A programmable device comprising: a plurality of configurable logic resources; a root monitor including a circuit device configured to generate a reference voltage; a number of sensors distributed at various locations throughout the programmable device, each of the sensors configured to measure an operating condition of an associated circuit at a corresponding one of the various locations; a number of satellite monitors distributed at various locations throughout the programmable device, each of the satellite monitors coupled to one or more associated sensors in a vicinity of the corresponding satellite monitor; and an interconnection system coupled to the configurable logic resources, to the root monitor, and to each of the plurality of satellite monitors, the interconnection system configured to distribute a reference voltage from the root monitor to each of the plurality of satellite monitors and to selectively route digital data from each of the plurality of satellite monitors to the root monitor, the digital data being indicative of a measured operating condition.

[0204] Example 2: The programmable device of example 1, wherein the operating condition includes at least one of a temperature or a voltage level.

[0205] Example 3: The programmable device of example 1, wherein the route monitor comprises a bandgap circuit configured to compensate the reference voltage for temperature changes.

[0206] Example 4: The programmable device of Example 1, wherein each of the satellite monitors comprises an analog-to-digital converter (ADC) including an input for receiving an analog signal indicative of an operating condition measured by one or more associated sensors, an output for providing digital data to an interconnection system, and a reference terminal for receiving a local reference voltage.

[0207] Example 5: The programmable device of example 4, wherein the local reference voltage is based at least in part on a reference voltage distributed by the interconnect system.

[0208] Example 6: The programmable device of Example 4, wherein each of the satellite monitors includes an input coupled to the output of the ADC and an output coupled to the interconnect system, and further includes a memory configured to store digital data provided by the ADC.

[0209] Example 7: The programmable device of Example 4, wherein each of the satellite monitors further comprises a switch configured to selectively couple a reference voltage distributed by the interconnect system to the satellite monitor based on a control signal generated by the root monitor.

[0210] Example 8: The programmable device of example 7, wherein the control signal is configured to simultaneously couple the reference voltage distributed by the interconnect system to only one of the satellite monitors.

[0211] Example 9: The programmable device of example 1, wherein at least some of the plurality of satellite monitors are integrated within an interconnection system.

[0212] Example 10: The programmable device of Example 1, wherein the interconnection system further includes one or more analog channels configured to distribute a reference voltage from the root monitor to each of the plurality of satellite monitors, and one or more digital channels configured to selectively route digital data from the satellite monitors to the root monitor as individually addressable data packets.

[0213] Example 11: The programmable device of Example 1, wherein the root monitor further comprises a memory configured to store digital data received from each of the plurality of satellite monitors and a controller configured to determine whether at least one measured operating condition of an associated circuit is within a range.

[0214] Example 12: A system for monitoring several operating conditions of a programmable device, the system comprising: a route monitor including a circuit device configured to generate a reference voltage; a plurality of sensors distributed throughout the programmable device, each of the sensors configured to generate an analog signal indicative of an operating condition of an associated circuit; a plurality of satellite monitors distributed throughout the programmable device, each of the satellite monitors configured to convert analog signals generated by one or more corresponding sensors into digital data; and an interconnection system coupled to at least the root monitor and each of the plurality of satellite monitors, the interconnection system comprising one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors, and one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.

[0215] Example 13: The system of example 12, wherein the operating condition includes at least one of a temperature or a voltage level.

[0216] Example 14: The system of Example 12, wherein each of the satellite monitors comprises an analog-to-digital converter (ADC) configured to convert analog signals generated by one or more associated sensors into digital data.

[0217] Example 15: The system of Example 14, wherein each of the satellite monitors further comprises a switch configured to selectively couple a reference voltage distributed by the interconnect system to the satellite monitor based on a control signal generated by the root monitor.

[0218] Example 16: The system of example 15, wherein the control signal is configured to simultaneously couple the reference voltage distributed by the interconnect system to only one of the satellite monitors.

[0219] Example 17: A method for monitoring several operating conditions of a programmable device, comprising: generating a reference voltage using a voltage generator associated with a root monitor provided within the programmable device; distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of an interconnection system integrated within the programmable device; generating, using each of a number of sensors, an analog signal indicative of an operating condition of an associated circuit; providing the analog signals generated by the number of sensors to corresponding ones of the plurality of satellite monitors; converting, using the plurality of satellite monitors, the analog signals to digital data; and selectively routing the digital data from the plurality of satellite monitors to the root monitor using one or more digital channels of the interconnection system.

[0220] Example 18: The method of example 17, wherein the operating condition includes at least one of a temperature or a voltage level.

[0221] Example 19: The method of Example 17, wherein distributing the reference voltage further includes selectively coupling each of the plurality of satellite monitors to the interconnection system based on a corresponding control signal generated by the root monitor.

[0222] Example 20: The method of example 19, wherein the control signal is configured to couple the reference voltage distributed by the interconnect system to only one of the satellite monitors at a time.

[0223] Example 21: A programmable device comprising: programmable logic including a plurality of configurable logic resources; a root monitor including a bandgap voltage generator configured to generate a temperature independent reference voltage; a plurality of sensors distributed at various locations throughout the programmable device, each of the sensors configured to generate an analog signal indicative of a measured operating condition of one or more associated circuits in a vicinity of a corresponding one of the various locations; and a plurality of satellite monitors distributed throughout the programmable device at various locations, each of the satellite monitors coupled to one or more associated sensors via one or more local signal lines and including a relatively small local voltage source configured to generate a local reference voltage, a reference terminal for receiving the local reference voltage, an analog-to-digital converter (ADC) configured to convert the analog signal generated by the one or more associated sensors into a digital code indicative of the measured operating condition, a calibration circuit configured to generate a correction factor indicative of an error in the digital code, and a correction circuit configured to correct the digital code based on the correction factor.

[0224] Example 22: The programmable device of example 21, wherein the local voltage source is comprised of fewer than 12 transistors and consumes at least an order of magnitude less circuit area than the bandgap voltage generator.

[0225] Example 23: The programmable device of example 21, wherein an error in the digital code is associated with a deviation of the local reference voltage from a temperature independent reference voltage.

[0226] Example 24: The programmable device of example 21, wherein the correction factor is based on a difference between a reference code generated by the ADC in response to sampling the temperature independent reference voltage and a predetermined digital code indicative of the temperature independent reference voltage.

[0227] Example 25: The programmable device of Example 21, further comprising a network-on-chip (NoC) interconnect system spanning the programmable logic and configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.

[0228] Example 26: The programmable device of Example 25, wherein the root monitor further comprises a memory configured to store digital data received from the plurality of satellite monitors via the NoC interconnect system, and a controller configured to determine whether the measured operating conditions embodied by the digital data are within a range.

[0229] Example 27: The programmable device of Example 25, further comprising one or more analog channels configured to distribute a temperature independent reference voltage from the root monitor to each of the plurality of satellite monitors.

[0230] Example 28: The programmable device of example 27, wherein the NoC interconnect system comprises one or more analog channels.

[0231] Example 29: The programmable device of Example 27, wherein each of the satellite monitors further comprises a switch including a first input terminal coupled to receive a temperature independent reference voltage from one or more analog channels, a second input terminal coupled to receive an analog signal generated by one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of an ADC in the satellite monitor.

[0232] Example 30: The programmable device of example 29, wherein during a calibration operation, the switch provides a temperature independent reference voltage as an input signal to the ADC, and during a monitoring operation, the switch provides an analog signal from the sensor as an input signal to the ADC.

[0233] Example 31: The programmable device of Example 30, wherein during a calibration operation, the ADC samples a temperature independent reference voltage to generate a reference code, and during a monitoring operation, the ADC samples analog signals from one or more associated sensors to generate a digital code.

[0234] Example 32: The programmable device of Example 31, wherein the calibration circuit is configured to generate a correction factor based on a difference between a reference code generated by the ADC and a predetermined digital code indicative of a temperature independent reference voltage.

[0235] Example 33: The programmable device of example 29, wherein the route monitor is configured to generate the control signal based at least in part on a timing schedule for calibrating the plurality of satellite monitors.

[0236] Example 34: The programmable device of Example 33, wherein the timing schedule is configured to sequentially enable calibration of each of the multiple satellite monitors by providing the temperature independent reference voltage to only one of the satellite monitors at a time.

[0237] Example 35: A method for monitoring the operating status of a plurality of circuits distributed at various locations throughout a programmable device, the method comprising: generating an analog signal indicative of the operating status of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed at various locations throughout the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed at various locations throughout the programmable device; generating a local reference voltage using a relatively small local voltage source at each of the plurality of satellite monitors; converting the corresponding one of the plurality of analog signals to a digital code using an analog-to-digital converter (ADC) at each of the plurality of satellite monitors based on the local reference voltage; distributing the temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the distributed temperature-independent reference voltage; and selectively routing the corrected digital code from each of the plurality of satellite monitors to the root monitor.

[0238] Example 36: The method of example 35, wherein the local voltage source is comprised of fewer than 12 transistors and consumes at least an order of magnitude less circuit area than a bandgap voltage generator.

[0239] Example 37: The method of Example 35, wherein the corrected digital code is selectively routed from the multiple satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system spanning the programmable device, and the temperature-independent reference voltage is distributed from the root monitor to the multiple satellite monitors using one or more analog channels spanning the programmable device.

[0240] Example 38: The method of Example 35, wherein distributing the temperature independent reference voltage further includes sequentially enabling each of the plurality of satellite monitors to access the temperature independent reference voltage based on a corresponding plurality of control signals generated by the root monitor.

[0241] Example 39: The method of Example 35, wherein the correcting includes providing a temperature-independent reference voltage as an input signal to an ADC, converting the temperature-independent reference voltage to a reference code using the ADC, generating a correction factor based on a difference between the reference code and a predetermined digital code indicative of the temperature-independent reference voltage, and adjusting the digital code based on the correction factor.

[0242] Example 40: The method of example 39, wherein the correction factor is configured to compensate for an error in the digital code associated with a deviation of the local reference voltage from a temperature independent reference voltage.

[0243] Example 41: A programmable device comprising: programmable logic including a plurality of configurable logic resources; a root monitor including a bandgap voltage generator configured to generate a temperature independent reference voltage; a plurality of sensors distributed at various locations throughout the programmable device, each of the sensors configured to generate an analog signal indicative of a measured operating condition of one or more associated circuits in a vicinity of a corresponding one of the various locations; and a plurality of satellite monitors distributed throughout the programmable device at various locations, each of the satellite monitors coupled to one or more associated sensors via one or more local signal lines and comprising: a voltage store configured to store a local reference voltage based on the temperature independent reference voltage generated by the bandgap voltage generator; a reference terminal for receiving the local reference voltage; an analog-to-digital converter (ADC) configured to convert the analog signal generated by the one or more associated sensors into a digital code indicative of the measured operating condition; a calibration circuit configured to generate a correction factor indicative of an error in the digital code; and a correction circuit configured to correct the digital code based on the correction factor.

[0244] Example 42: The programmable device of example 41, wherein the local reference voltage is at least an order of magnitude less accurate than the temperature independent reference voltage generated by the bandgap voltage generator.

[0245] Example 43: The programmable device of example 41, wherein the voltage store includes a capacitor.

[0246] Example 44: The programmable device of example 41, wherein an error in the digital code is associated with a deviation of the local reference voltage from a temperature independent reference voltage.

[0247] Example 45: The programmable device of example 41, wherein the correction factor is based on a difference between a reference code generated by the ADC in response to sampling the temperature independent reference voltage and a predetermined digital code indicative of the temperature independent reference voltage.

[0248] Example 46: The programmable device of Example 41, further comprising a network-on-chip (NoC) interconnect system spanning the programmable logic and configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.

[0249] Example 47: The programmable device of Example 46, wherein the root monitor further comprises a memory configured to store digital data received from the plurality of satellite monitors via the NoC interconnect system, and a controller configured to determine whether the measured operating conditions embodied by the digital data are within a range.

[0250] Example 48: The programmable device of Example 46, further comprising one or more analog channels configured to distribute a temperature independent reference voltage from the root monitor to each of the plurality of satellite monitors.

[0251] Example 49: The programmable device of example 48, wherein the NoC interconnect system comprises one or more analog channels.

[0252] Example 50: The programmable device of Example 48, wherein each of the satellite monitors further comprises a first switch including a first input terminal coupled to receive a temperature independent reference voltage from one or more analog channels, a second input terminal coupled to receive an analog signal generated by one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of an ADC in the satellite monitor.

[0253] Example 51: The programmable device of Example 50, wherein each of the satellite monitors further comprises a second switch including an input terminal coupled to receive a temperature independent reference voltage from one or more analog channels, a control terminal coupled to receive a control signal, and an output terminal coupled to the voltage store.

[0254] Example 52: The programmable device of Example 51, wherein during a calibration operation, the first switch provides a temperature independent reference voltage as an input signal to the ADC, the second switch charges the voltage store and then isolates the voltage store from the temperature independent reference voltage, and the ADC samples the temperature independent reference voltage to generate the reference code.

[0255] Example 53: During a monitoring operation: the programmable device of example 52, wherein the first switch provides an analog signal from the sensor as an input signal to the ADC, the second switch periodically provides a temperature independent reference voltage to the voltage store, and the ADC samples the analog signal from the one or more associated sensors to generate a digital code.

[0256] Example 54: The programmable device of example 51, wherein the route monitor is configured to generate a control signal based at least in part on a timing schedule for calibrating the plurality of satellite monitors.

[0257] Example 55: The programmable device of example 54, wherein the timing schedule is configured to sequentially enable calibration of each of the multiple satellite monitors by providing the temperature independent reference voltage to only one of the satellite monitors at a time.

[0258] Example 56: A method for monitoring the operating status of a plurality of circuits distributed at various locations throughout a programmable device, the method comprising: generating an analog signal indicative of the operating status of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed at various locations throughout the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed at various locations throughout the programmable device; storing, at each of the plurality of satellite monitors, a local reference voltage based on a temperature independent reference voltage; converting, at each of the plurality of satellite monitors, the corresponding one of the plurality of analog signals to a digital code using an analog-to-digital converter (ADC) based on the local reference voltage; distributing the temperature independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the distributed temperature independent reference voltage; and selectively routing the corrected digital code from each of the plurality of satellite monitors to the root monitor.

[0259] Example 57: The method of Example 56, wherein the corrected digital code is selectively routed from the multiple satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system spanning the programmable device, and the temperature-independent reference voltage is distributed from the root monitor to the multiple satellite monitors using one or more analog channels spanning the programmable device.

[0260] Example 58: The method of example 57, wherein the storing includes selectively charging a capacitor provided within each satellite monitor using a temperature independent reference voltage distributed by the one or more analog channels.

[0261] Example 59: The method of Example 56, wherein distributing the temperature independent reference voltage further includes sequentially enabling each of the plurality of satellite monitors to access the temperature independent reference voltage based on a corresponding plurality of control signals generated by the root monitor.

[0262] Example 60: The method of Example 56, wherein the correcting includes providing the temperature independent reference voltage as an input signal to an ADC, converting the temperature independent reference voltage to a reference code using the ADC, generating a correction factor based on a difference between the reference code and a predetermined digital code indicative of the temperature independent reference voltage, and adjusting the digital code based on the correction factor.

[0263] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0264] Moreover, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0265] The methods, sequences, or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may reside in RAM latches, flash latches, ROM latches, EPROM latches, EEPROM latches, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[0266] In the foregoing specification, example implementations have been described with reference to specific example implementations thereof. It will nevertheless be apparent that various modifications and changes may be made to the example implementations without departing from the broader scope of the disclosure as set forth in the appended claims. The specification and drawings should therefore be evaluated in an illustrative rather than a restrictive sense.

Claims

1. 1. A programmable device, comprising: A plurality of configurable logic resources; a route monitor including a circuit device configured to generate a reference voltage; a number of sensors distributed at various locations throughout the programmable device, each of the sensors configured to measure an operational state of an associated circuit at a corresponding one of the various locations; a plurality of satellite monitors distributed at various locations throughout the programmable device, each of the satellite monitors coupled to one or more associated sensors in a vicinity of a corresponding one of the satellite monitors, each of the satellite monitors including an analog-to-digital converter (ADC) having an input for receiving an analog signal indicative of an operating condition measured by the one or more associated sensors, an output for providing digital data to an interconnection system, and a reference terminal for receiving a local reference voltage, the local reference voltage being based at least in part on the reference voltage distributed by the interconnection system; the interconnection system coupled to the configurable logic resource, to the root monitor, and to each of the plurality of satellite monitors, distributing said reference voltage from said root monitor to each of said plurality of satellite monitors; and selectively routing said digital data from each of said plurality of satellite monitors to said root monitor, said digital data being indicative of said measured operating condition; an interconnection system configured to A programmable device comprising:

2. The route monitor, a bandgap circuit configured to compensate the reference voltage for temperature variations; a memory configured to store the digital data received from each of the plurality of satellite monitors; a controller configured to determine whether the measured operating condition of at least one of the associated circuits is within a range; and The programmable device of claim 1 , comprising at least one of:

3. Each of the satellite monitors a memory having an input coupled to the output of the ADC and an output coupled to the interconnect system, the memory configured to store the digital data provided by the ADC; a switch configured to selectively couple the reference voltage distributed by the interconnection system to the satellite monitors based on a control signal generated by the root monitor, the control signal being configured to couple the reference voltage distributed by the interconnection system to only one of the satellite monitors at a time; The programmable device of claim 1 , comprising at least one of:

4. said interconnect system comprising: one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; one or more digital channels configured to selectively route the digital data from the satellite monitor to the root monitor as individually addressable data packets; The programmable device of claim 1 further comprising:

5. each of the satellite monitors is coupled to one or more associated sensors via one or more local signal lines; A local voltage source; an analog-to-digital converter (ADC) including a reference terminal for receiving a local reference voltage and configured to convert an analog signal generated by the one or more associated sensors into a digital code indicative of the measured operating condition; a calibration circuit configured to generate a correction factor indicative of an error in the digital code; a correction circuit configured to correct the digital code based on the correction factor; Equipped with 2. The programmable device of claim 1.

6. The local voltage source: generating said local reference voltage; or storing the local reference voltage based on a temperature independent reference voltage generated by a bandgap voltage generator; The programmable device of claim 5 configured to:

7. a network-on-chip (NoC) interconnect system spanning programmable logic and configured to selectively route digital data from each of said plurality of satellite monitors to said root monitor. The programmable device of claim 5 further comprising:

8. Each of the satellite monitors a first switch including a first input terminal coupled to receive a temperature independent reference voltage from the one or more analog channels, a second input terminal coupled to receive the analog signal generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC in the satellite monitor; The programmable device of claim 5 further comprising:

9. during a calibration operation, the first switch provides the temperature independent reference voltage as an input signal to the ADC; during a monitoring operation, the first switch provides the analog signal from the sensor as an input signal to the ADC; 9. A programmable device according to claim 8.

10. During the calibration operation, the ADC samples the temperature independent reference voltage to generate a reference code; during the monitoring operation, the ADC samples the analog signals from the one or more associated sensors to generate the digital code; 10. A programmable device according to claim 9.

11. Each of the satellite monitors a second switch including an input terminal coupled to receive the temperature independent reference voltage from the one or more analog channels, a control terminal coupled to receive the control signal, and an output terminal coupled to a voltage store; The programmable device of claim 8 further comprising:

12. During the calibration operation, the second switch charges the voltage store and then isolates the voltage store from the temperature independent reference voltage; the ADC samples the temperature independent reference voltage to generate a reference code; 12. A programmable device according to claim 11.

13. 1. A system for monitoring certain operational aspects of a programmable device, comprising: a route monitor including a circuit device configured to generate a reference voltage; a plurality of sensors distributed throughout the programmable device, each of the sensors configured to generate an analog signal indicative of an operational condition of an associated circuit; a plurality of satellite monitors distributed throughout the programmable device, each of the satellite monitors configured to convert the analog signals generated by one or more corresponding sensors into digital data, each of the satellite monitors including a local voltage source and a reference terminal for receiving a local reference voltage; an analog-to-digital converter (ADC) configured to convert the analog signals generated by one or more of the plurality of sensors into a digital code indicative of the measured operating condition; a calibration circuit configured to generate a correction factor indicative of an error in the digital code using a reference voltage; and a correction circuit configured to correct the digital code based on the correction factor; an interconnection system coupled to at least the route monitor and each of the plurality of satellite monitors, one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and one or more digital channels configured to selectively route the digital data from each of the plurality of satellite monitors to the root monitor; An interconnection system comprising: A system comprising:

14. Each of the satellite monitors a switch configured to selectively couple the reference voltage distributed by the interconnect system to the satellite monitor based on a control signal generated by the route monitor; the control signal is configured to couple the reference voltage distributed by the interconnect system to only one of the satellite monitors at a time. The system of claim 13.

15. 1. A method for monitoring certain operational aspects of a programmable device, comprising the steps of: One or more processors, generating a reference voltage using a voltage generator associated with a route monitor provided within the programmable device; distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of an interconnect system integrated within the programmable device, each of the satellite monitors including an analog-to-digital converter (ADC) including a reference terminal for receiving a local reference voltage, and an output for providing digital data to the interconnect system, the local reference voltage being based at least in part on the reference voltage distributed by the interconnect system; generating an analog signal indicative of an operational condition of an associated circuit using each of a number of sensors; providing the analog signals generated by the several sensors to corresponding ones of the plurality of satellite monitors; converting said analog signals to said digital data using said plurality of satellite monitors; selectively routing said digital data from said plurality of satellite monitors to said root monitor using one or more digital channels of said interconnection system; The method includes:

16. Distributing the reference voltage selectively coupling each of the plurality of satellite monitors to the interconnection system based on a corresponding control signal generated by the root monitor, the control signal being configured to couple the reference voltage distributed by the interconnection system to only one of the satellite monitors at a time; The method of claim 15 further comprising:

17. 16. The method of claim 15, further comprising correcting a digital code generated by the ADC in each of the plurality of satellite monitors based at least in part on the reference voltage.

18. 20. The method of claim 17, wherein the reference voltage is a temperature independent reference voltage.

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