Semiconductor device, power conversion device, and method for manufacturing the same

Abstract

This semiconductor device comprises: a semiconductor substrate (1) having a first main surface (1a) and a second main surface (1b) that is on the opposite side from the first main surface (1a); a first surface electrode (2) formed on the first main surface (1a); a second surface electrode (3) formed at a location set apart from the first surface electrode (2) in plan view, the second surface electrode (3) being electrically insulated from the first surface electrode (2); an electroconductive layer (5) having electroconductive properties, the electroconductive layer (5) being formed, on the first surface (1a) between the first surface electrode (2) and the second surface electrode (3), at a location set apart from the first surface electrode (2) and the second surface electrode (3) in plan view; an insulating layer (6) having insulating properties, the insulating layer (6) being formed so as to cover the electroconductive layer (5), the first surface (1a) between the first surface electrode (2) and the second surface electrode (3), and end sections of the first surface electrode (2) and the second surface electrode (3) that are on the side near the electroconductive layer (5); a short-circuiting prevention layer (7) having insulating properties, the short-circuiting prevention layer (7) being formed so as to cover the portion of the insulating layer (6) between the first surface electrode (2) and the electroconductive layer (5) and so as to cover the portion of the insulating layer (6) between the second surface electrode (3) and the electroconductive layer (5), having a thickness equal to or greater than the height from the lower end of the electroconductive layer (5) to the upper end thereof, and being formed from a different material than the insulating layer (6); a metal plating layer (8) formed on each of the first surface electrode (2) and the second surface electrode (3); and a reverse-surface electrode (9) formed on the second main surface (2). Due to this configuration, it is possible to prevent short-circuiting between the first surface electrode (2) and the second surface electrode (3).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the semiconductor device, and a power conversion device using the same. [Background technology]

[0002] Semiconductor devices are used for power control in in-vehicle devices, industrial equipment, and the like, and are comprised of switching elements such as insulated gate bipolar transistors (IGBTs) and insulated gate field effect transistors (MOSFETs) and diodes, and the semiconductor substrates used for these devices are made thin to reduce conduction loss and turn-off loss, for example.

[0003] When a semiconductor substrate is made thinner, the thermal capacity of the semiconductor substrate decreases, and the heat dissipation performance also decreases, so that, for example, in an IGBT, the time during which it can be turned on in a short-circuit state without being destroyed, i.e., the short-circuit resistance, may decrease. On the other hand, semiconductor devices may be used in high-temperature environments or may have large control currents and heat generation, and therefore there is a demand for improving the heat dissipation performance of the semiconductor substrate.

[0004] Conventionally, there has been known a power semiconductor device in which a metal layer is formed on the surface of a semiconductor element by a plating method to promote heat dissipation. Patent Document 1 discloses a technology in which a metal layer containing nickel is formed on a surface electrode of a semiconductor element by an electroless plating method, and heat is dissipated from the surface of the semiconductor element via the metal layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5494559 (see pages 3-4, etc.) Summary of the Invention [Problem to be solved by the invention]

[0006] On the surface of the semiconductor element, for example, a gate electrode and an emitter electrode, a gate wiring provided in the wiring region between the gate electrode and the emitter electrode, and an insulating film covering the gate wiring are formed. In this way, when the semiconductor element has electrodes insulated from each other, a conductive layer provided in the region between these electrodes and spaced apart from these electrodes, and an insulating layer covering the conductive layer, a concave-convex structure is formed. Then, when a metal plating layer is formed on each of the insulated electrodes, a conductive coating is formed due to the substances contained in the plating solution, such as the plating solution and the plating solution cleaning agent, remaining on the surface of the insulating layer covering the conductive layer, especially in the recess between the electrode and the conductive layer, and this may cause a short circuit between the insulated electrodes.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that prevents short circuits between electrodes when metal plating layers are formed on each of the mutually insulated electrodes on the surface of a semiconductor element. [Means for solving the problem]

[0008] The semiconductor device of the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, a first surface electrode formed on the first main surface, a second surface electrode formed at a distance from the first surface electrode in a plan view and electrically insulated from the first surface electrode, a conductive layer formed at a distance from the first surface electrode and the second surface electrode in a plan view on the first main surface between the first surface electrode and the second surface electrode and having conductivity, the conductive layer, the first main surface between the first surface electrode and the second surface electrode, and the first surface electrode. the first surface electrode and the second surface electrode, and an insulating layer having insulating properties formed to cover the ends of the first surface electrode and the second surface electrode that are closer to the conductive layer; a short-circuit prevention layer formed to cover the top of the insulating layer between the first surface electrode and the conductive layer and the top of the insulating layer between the second surface electrode and the conductive layer, having a thickness equal to or greater than the height from the bottom end to the top end of the conductive layer, made of a material different from the insulating layer, and having insulating properties; metal plating layers formed on the first surface electrode and the second surface electrode, respectively; and a back surface electrode formed on the second main surface.

[0009] The method for manufacturing a semiconductor device according to the present disclosure includes a surface electrode and conductive layer forming step of forming a planar electrode layer on a first main surface of a semiconductor substrate and patterning the planar electrode layer to form a first surface electrode, a second surface electrode, and a conductive layer that are spaced apart from each other in a planar view; an insulating layer forming step of forming, by a PVD method or a CVD method, an insulating layer that covers the conductive layer, the first main surface between the first surface electrode and the second surface electrode, and each end of the first surface electrode and the second surface electrode that is closer to the conductive layer; The method includes a short-circuit prevention layer forming step of forming a short-circuit prevention layer that covers the insulating layer between the electrode and the conductive layer, has a thickness equal to or greater than the height from the bottom to the top of the conductive layer, is made of a material different from the insulating layer, and has insulating properties; a metal plating layer forming step of forming a metal plating layer on the first surface electrode and the second surface electrode by immersing the first surface electrode, the second surface electrode, and the short-circuit prevention layer in a plating solution using a plating method after the short-circuit prevention layer forming step; and a back surface electrode forming step of forming a back surface electrode on the second main surface, which is the surface opposite to the first main surface of the semiconductor substrate. Effect of the Invention

[0010] According to the present disclosure, a short-circuit prevention layer can be formed between electrodes insulated from each other on the surface of a semiconductor element, thereby obtaining a semiconductor device in which short-circuiting between these electrodes is prevented. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view showing a schematic configuration of a semiconductor device in a first embodiment. [Diagram 2] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device in a first embodiment. [Diagram 3] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device in a first embodiment. [Figure 4] 1 is a cross-sectional view showing a schematic configuration of a semiconductor device in a first embodiment. [Diagram 5] 11 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment. FIG. [Figure 6] 13 is a graph showing the short-circuit withstand capability of the semiconductor device in the second embodiment. [Figure 7] 1 is a plan view showing a schematic configuration of a semiconductor device according to first and second embodiments. [Figure 8] FIG. 11 is a schematic diagram showing a schematic configuration of a power conversion system to which a power conversion device according to a third embodiment is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Here, an IGBT will be described as an example. However, the present invention can be modified as appropriate as long as the semiconductor element has electrodes insulated from each other on the surface thereof, a conductive layer provided separately in the region between the electrodes in a plan view, and an insulating layer covering the conductive layer. The present invention may be a MOSFET or a combination of an IGBT and a MOSFET.

[0013] <Embodiment 1> 1 and 2 are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to the present embodiment. The semiconductor device is provided with an active region 10, which is a region through which the main current of the semiconductor device flows, and a termination region 11, which is a region outside the active region 10. An emitter electrode 2a and a gate electrode 3a are spaced apart from each other on the surface of a semiconductor substrate 1. A gate wiring 5a covered with an insulating layer 6 is formed in a gate wiring region 4 between the emitter electrode 2a and the gate electrode 3a. A short-circuit prevention layer 7 is provided between the emitter electrode 2a and the gate wiring 5a and between the gate electrode 3a and the gate wiring 5a. In addition, in the semiconductor device, a metal plating layer 8 is formed on the emitter electrode 2a and the gate electrode 3a, and a collector electrode 9a is formed on the back surface of the semiconductor substrate 1. Here, in FIG. 1, the insulating layer 6 and the metal plating layer 8 are omitted for the sake of simplicity.

[0014] 2, the semiconductor substrate 1 has a first main surface 1a on the front side and a second main surface 1b on the back side. Semiconductor layers (not shown), such as a drift layer, an emitter layer, a collector layer, a field stop layer, and an electrolytic relaxation layer, are formed on the first main surface 1a side or the second main surface 1b side of the semiconductor substrate 1. The semiconductor substrate 1 may be, for example, a substrate made of silicon.

[0015] The emitter electrode 2a and the gate electrode 3a are the first surface electrode 2 and the second surface electrode 3, and are formed to be separated from and electrically insulated from each other on the first main surface 1a of the active region 10 of the semiconductor substrate 1. The emitter electrode 2a and the gate electrode 3a may be made of aluminum, for example, or an alloy material such as an alloy of aluminum and silicon may be used.

[0016] The gate wiring region 4 is a region on the first main surface 1a of the semiconductor substrate 1 where the gate wiring 5a and the insulating layer 6 are provided, and has a convex portion 4a and a concave portion 4b. In FIG. 1 and FIG. 2, the region between the emitter electrode 2a and the gate electrode 3a is the gate wiring region 4. In FIG. 2, the width of the gate wiring region 4, that is, the horizontal distance between the outer periphery of the emitter electrode 2a and the gate electrode 3a, is, for example, about 100 μm. In order to expand the region through which the main current of the semiconductor device flows, the width of the gate wiring region 4 may be set to 100 μm or less. Here, although not shown, the gate wiring 5a is also provided in the termination region 11.

[0017] 1 and 2, the gate wiring 5a is a conductive layer 5 formed on the first main surface 1a between the emitter electrode 2a and the gate electrode 3a, separated from the emitter electrode 2a and the gate electrode 3a in a plan view. The gate wiring 5a may be made of a conductive material such as aluminum, or may be made of an alloy material such as an alloy of aluminum and silicon.

[0018] As shown in FIG. 2, the insulating layer 6 is formed to cover the gate wiring 5a, the first main surface 1a between the emitter electrode 2a and the gate electrode 3a, and the ends of the emitter electrode 2a and the gate electrode 3a on the side closer to the gate wiring 5a. Here, the ends include the end faces of the emitter electrode 2a and the gate electrode 3a, and are defined as the region on the upper surface of the emitter electrode 2a and the gate electrode 3a from the outer periphery to 100 μm inside the outer periphery, but this region can be increased or decreased according to the design of the semiconductor device. In this way, a convex portion 4a is formed on the gate wiring 5a on which the insulating layer 6 is laminated, and a concave portion 4b is formed between the emitter electrode 2a and the gate wiring 5a and between the gate electrode 3a and the gate wiring 5a. The insulating layer 6 may be made of a material having insulating properties, such as silicon nitride.

[0019] As shown in Fig. 2, the short-circuit prevention layer 7 is formed to cover the insulating layer 6 between the emitter electrode 2a and the gate wiring 5a and the insulating layer 6 between the gate electrode 3a and the gate wiring 5a. The short-circuit prevention layer 7 also fills the recesses 4b so as to flatten the protrusions 4a and the recesses 4b. The thickness of the short-circuit prevention layer 7 indicates the height from the bottom to the top of the short-circuit prevention layer 7, and is equal to or greater than the thickness of the gate wiring 5a, in other words, equal to or greater than the height from the bottom to the top of the gate wiring 5a. In this way, the height of the top of the short-circuit prevention layer 7 is equal to or greater than the height of the top of the protrusion 4a.

[0020] The short-circuit prevention layer 7 has insulating properties and is made of a material different from the insulating layer 6. For example, when silicon nitride or silicon oxide is used for the insulating layer 6, materials such as polyimide, polybenzoxazole, polytetrafluoroethylene, and siloxane can be used for the short-circuit prevention layer 7. It is preferable that the short-circuit prevention layer 7 is made of a material having high chemical resistance to a plating solution, moisture resistance, heat resistance, adhesion, thixotropy that promotes flattening of the convex portion 4a and the concave portion 4b, and fluidity such as viscosity, as described below, compared to the insulating materials such as silicon nitride and silicon oxide used for the insulating layer 6. Here, polyimide and polybenzoxazole are preferable in terms of chemical resistance, moisture resistance, heat resistance, fluidity, and the like.

[0021] When the metal plating layer 8 described later is formed without forming the short-circuit prevention layer 7 in the recess 4b, the liquid containing the conductive substance adheres to and remains at the bottom of the recess 4b, particularly near the bottom and sidewalls of the recess 4b, where surface tension is likely to occur and where it is difficult to detach and evaporate. In addition, the residual substance may spread to the bottom and sidewalls of the recess 4b, forming a conductive film between the emitter electrode 2a and the gate electrode 3a. Therefore, if the short-circuit prevention layer 7 is formed to fill the recess 4b and the metal plating layer 8 is formed, it is possible to prevent the conductive substance from adhering to and remaining at the bottom of the recess 4b and to prevent the conductive film from being formed between the emitter electrode 2a and the gate electrode 3a. In addition, it is possible to prevent the emitter electrode 2a and the gate electrode 3a from being short-circuited.

[0022] The metal plating layer 8 is formed on the emitter electrode 2a and the gate electrode 3a, respectively, and promotes heat dissipation from the emitter electrode 2a and the gate electrode 3a. Here, as shown in Fig. 2, when the metal plating layer 8 is formed, the heat capacity on the front side of the semiconductor device can be increased compared to a case in which the metal plating layer 8 is not formed. Then, the heat generated in the semiconductor device is dissipated from the metal plating layer 8 to the external space or external material, or is conducted to the metal plating layer 8, thereby improving the short circuit resistance of the semiconductor device.

[0023] The metal plating layer 8 may be made of, for example, nickel, or an alloy of nickel and phosphorus, nickel and boron, or a laminate of nickel and gold, copper and gold, etc. Using an alloy of nickel and phosphorus can reduce the manufacturing cost and improve the heat dissipation and short circuit resistance of the semiconductor device.

[0024] 2, the collector electrode 9a is formed on the second main surface 1b of the semiconductor substrate 1. The collector electrode 9a may be made of, for example, aluminum, titanium, or a laminate of aluminum, nickel, gold, or the like.

[0025] Next, a method for manufacturing a semiconductor device according to the present embodiment will be described. For the sake of brevity, a description of a method for manufacturing a semiconductor layer will be omitted. In addition, the order of the manufacturing steps may differ from that described unless otherwise specified.

[0026] In the surface electrode and conductive layer forming process, an electrode layer made of aluminum is formed in a planar shape on the first main surface 1a of the semiconductor substrate 1 on which the semiconductor layer is formed, for example, by sputtering, and patterned by etching. Then, the emitter electrode 2a, the gate electrode 3a, and the gate wiring 5a are formed collectively so as to be spaced apart from each other. When the emitter electrode 2a, the gate electrode 3a, and the gate wiring 5a are formed collectively, the thicknesses of the emitter electrode 2a, the gate electrode 3a, and the gate wiring 5a become the same, the depth of the recess 4b becomes constant regardless of the position, and the short-circuit prevention layer 7 can be easily embedded in the recess 4b. Furthermore, the manufacturing process becomes easier and the manufacturing cost can be reduced. Here, the same thickness or constant depth does not only mean that the thickness is completely the same or the depth is constant, but also includes that the thickness or depth is within about 10% of the maximum value.

[0027] In the insulating layer forming step, a silicon nitride layer is formed as an insulating layer 6 on the first main surface 1a of the semiconductor substrate 1 between the emitter electrode 2a and the gate electrode 3a and on the gate wiring 5a by, for example, a PVD (Physical Vapor Deposition) method such as a sputtering method or a deposition method or a CVD (Chemical Vapor Deposition) method. In addition, the upper surfaces of the emitter electrode 2a and the gate electrode 3a except for their ends are exposed by photolithography and etching methods. Here, a convex portion 4a and a concave portion 4b are formed in the gate wiring region 4 between the emitter electrode 2a and the gate electrode 3a.

[0028] In the short-circuit prevention layer forming step, a liquid photosensitive polyimide is applied using, for example, a dispenser or a spin coater so as to cover the insulating layer 6 in the recess 4b and have a thickness equal to or greater than the thickness of the gate wiring 5a. Then, the photosensitive polyimide is irradiated with light to harden the photosensitive polyimide, forming the short-circuit prevention layer 7. When the photosensitive polyimide is applied to areas other than the gate wiring region 4, the short-circuit prevention layer 7 may be formed by patterning the photosensitive polyimide. Here, the short-circuit prevention layer 7 may also be formed on the insulating layer 6 in the protrusion 4a. Alternatively, the short-circuit prevention layer 7 may be formed only on the insulating layer 6 in the recess 4b using photolithography.

[0029] In the metal plating layer formation process following the short circuit prevention layer formation process, for example, electroless plating is used to form a nickel and gold laminate, i.e., metal plating layer 8, on emitter electrode 2a and gate electrode 3a. Here, the emitter electrode 2a, gate electrode 3a, and short circuit prevention layer 7 that are immersed in plating liquid, i.e., chemicals such as degreasing liquid, etching liquid, conditioning liquid, replacement liquid, plating liquid, and cleaning liquid, are collectively referred to as an immersion part, and an example of plating process will be described.

[0030] First, the immersion part is immersed in a degreasing liquid, and the natural oxide film formed on the surface of the immersion part is partially dissolved, and the organic matter attached to the surface of the immersion part is removed. Next, the surface of the immersion part is washed with pure water, and the immersion part is immersed in an etching liquid, and the surface oxide film is dissolved and removed. Since the residue generated by etching adheres to the surface of the immersion part, the immersion part is washed with pure water or the like, and immersed in a conditioning liquid to remove the residue and form a less contaminated oxide film on the immersion part. Here, if the short-circuit prevention layer 7 is not formed, the residue may remain on the recessed part 4b or the protruding part 4a, forming a conductive coating, but if the short-circuit prevention layer 7 is formed, the residue attached to the surface of the short-circuit prevention layer 7 can be easily removed by washing.

[0031] Next, the surface of the immersed portion is washed with pure water or the like and immersed in a zinc substitution solution, whereby the oxide film formed on the immersed portion dissolves, and the aluminum on the surfaces of the emitter electrode 2a and the gate electrode 3a is dissolved and ionized, and zinc is precipitated. Furthermore, the surface of the immersed portion is washed with pure water or the like and immersed in a nickel plating solution, whereby the zinc is substituted with nickel, and a nickel plating layer is formed. Here, if the short-circuit prevention layer 7 is not formed, the zinc may remain in the recessed portion 4b or the protruding portion 4a and be substituted with nickel, forming a conductive coating. On the other hand, if the short-circuit prevention layer 7 is formed, the residue adhering to the surface of the short-circuit prevention layer 7 can be easily removed by washing.

[0032] The surfaces of the short-circuit prevention layer 7 and the nickel plating layer are then washed with pure water or the like, and a gold plating process is performed to form a gold plating layer that prevents the oxidation of nickel on the surface of the nickel plating layer. This concludes the description of the metal plating layer forming process.

[0033] In the back surface electrode formation process, an aluminum layer, i.e., collector electrode 9a, is formed in a planar shape by, for example, sputtering on second main surface 1b of semiconductor substrate 1. In the manner described above, the semiconductor device according to the present embodiment is manufactured.

[0034] In this way, the short-circuit prevention layer 7 covers the insulating layer 6 between the emitter electrode 2a and the gate wiring 5a and the insulating layer 6 between the gate electrode 3a and the gate wiring 5a, and fills the recesses 4b so as to flatten the protrusions 4a and recesses 4b of the gate wiring region 4. When the metal plating layer 8 is formed, it is possible to prevent substances contained in the plating solution, such as the plating solution and the plating solution cleaning agent, from remaining on the surface of the insulating layer 6 covering the gate wiring 5a, especially on the recesses 4b, and to prevent a conductive coating from being formed between the emitter electrode 2a and the gate electrode 3a. Therefore, it is possible to provide a semiconductor device in which the metal plating layer 8 is formed on each of the emitter electrode 2a and the gate electrode 3a, which are insulated from each other on the surface of the semiconductor element, and in which a short circuit between the emitter electrode 2a and the gate electrode 3a is prevented.

[0035] 3, when the shape of the upper surface of the short-circuit prevention layer 7 is curved rather than flat, the thickness of the short-circuit prevention layer 7 does not need to be greater than or equal to the thickness of the gate wiring 5a at all positions, but only needs to be greater than or equal to the thickness of the gate wiring 5a at the upper end of the curved upper surface of the short-circuit prevention layer 7. Here, FIG. 3 is a schematic cross-sectional view showing another form of the present embodiment.

[0036] 4, the short-circuit prevention layer 7 may be formed to cover the insulating layer 6 that covers the gate wiring 5a, in other words, on the protrusion 4a. In this manner, similar to the above, it is possible to easily form the short-circuit prevention layer 7 while suppressing the formation of a conductive coating between the emitter electrode 2a and the gate electrode 3a. Here, the thickness of the short-circuit prevention layer 7 refers to the height from the lower end of the short-circuit prevention layer 7 formed in the recess 4b to the upper end of the short-circuit prevention layer 7 formed on the protrusion 4a.

[0037] Furthermore, if the surface of the short-circuit prevention layer 7 is hydrophobic, it is possible to further suppress the substances contained in the plating solution, such as the plating solution and the plating solution cleaner, from remaining on the surface of the short-circuit prevention layer 7 when forming the metal plating layer 8. It is also possible to prevent a conductive coating from being formed between the emitter electrode 2a and the gate electrode 3a, thereby preventing a short circuit between the emitter electrode 2a and the gate electrode 3a.

[0038] In addition, in the short-circuit prevention layer formation process, an example has been shown in which the short-circuit prevention layer 7 is formed using photosensitive polyimide, but the short-circuit prevention layer 7 may also be formed by using a liquid material, thermosetting polyimide, for example, by applying the thermosetting polyimide using a dispenser or spin coater, and then heating and hardening the thermosetting polyimide.

[0039] <Embodiment 2> In the first embodiment, an example was shown in which the short-circuit prevention layer 7 was formed inside the gate wiring region 4, but in the present embodiment, an example will be described in which the short-circuit prevention layer 7 is formed to extend outside the gate wiring region 4 and has a region in contact with the emitter electrode 2a and the gate electrode 3a. The rest of the configuration is the same as in the first embodiment.

[0040] 5, the short-circuit prevention layer 7 is formed to cover the insulating layer 6 that covers the ends of the emitter electrode 2a and the gate electrode 3a, and has an area in contact with the emitter electrode 2a and the gate electrode 3a. When the short-circuit prevention layer 7 is also formed on the emitter electrode 2a and the gate electrode 3a outside the gate wiring region 4, the area in which the short-circuit prevention layer 7 is formed can be expanded compared to when the short-circuit prevention layer 7 is formed only inside the gate wiring region 4, and the short-circuit prevention layer 7 can be formed more easily.

[0041] 5 shows an example in which both ends of the short-circuit prevention layer 7 have regions in contact with the emitter electrode 2a and the gate electrode 3a, but the short-circuit prevention layer 7 may be formed on the insulating layer 6 that covers the ends of the emitter electrode 2a and the gate electrode 3a. In other words, both ends of the short-circuit prevention layer 7 may be formed so as not to have regions in contact with the emitter electrode 2a and the gate electrode 3a.

[0042] It is preferable that the area of ​​the region where the short-circuit prevention layer 7 contacts the emitter electrode 2a and the gate electrode 3a, in other words the contact area, is small. If this contact area is small, the contact area of ​​the metal plating layer 8 between the emitter electrode 2a and the gate electrode 3a can be made large, and heat dissipation from the emitter electrode 2a and the gate electrode 3a through the metal plating layer 8 is promoted.

[0043] Next, a semiconductor device having the short-circuit prevention layer 7 formed thereon was fabricated, and the results of evaluating the short-circuit prevention effect and short-circuit resistance are shown. For the evaluation, a test sample was used in which a DBA (Direct Bonded Aluminum) substrate and a semiconductor element were connected by solder and wire bonding.

[0044] Here, the semiconductor element used had a short-circuit prevention layer 7 formed also on the ends of the emitter electrode 2a and gate electrode 3a outside the gate wiring region 4, and a metal plating layer 8 of different thickness formed on the emitter electrode 2a and gate electrode 3a. The semiconductor substrate 1 of the semiconductor element was a silicon substrate, and the thickness of the silicon substrate was 90 μm, the horizontal distance between the ends of the emitter electrode 2a and gate electrode 3a was 90 μm, the width of the recess 4b was 20 μm, and the height of the protrusion 4a was 5 μm.

[0045] In evaluating the short-circuit prevention effect, the electrical resistance between the emitter electrode 2a and the gate electrode 3a was measured. The electrical resistance of all test samples exceeded 30 MΩ, which was the upper limit of the measurement of the measuring device used for the measurement, and it was confirmed that the emitter electrode 2a and the gate electrode 3a were not short-circuited.

[0046] In evaluating the short circuit withstand capability, the test conditions were: applied voltage to gate electrode 3a: 20 V; applied voltage to the capacitor used as the short circuit current source: 800 V; and test sample temperature: 150° C. The time during which emitter electrode 2a and gate electrode 3a were short-circuited was increased in increments of 0.2 μs from 4.0 μs, and the maximum short circuit time during which no breakdown occurred was taken as the short circuit withstand capability.

[0047] Fig. 6 is a graph showing the relative value of the short circuit withstand capability of the semiconductor device in this embodiment. Here, the dotted line in Fig. 6 is an auxiliary line showing the behavior of the relative value of the short circuit withstand capability for each thickness. As shown in Fig. 6, if the thickness of the metal plating layer 8 is 0 μm, that is, the short circuit withstand capability when the metal plating layer 8 is not formed is set to 1, it was confirmed that when the metal plating layer 8 is formed, the relative value of the short circuit withstand capability, which is positively correlated with the heat dissipation property, exceeds 1.

[0048] In this way, even if the short-circuit prevention layer 7 is formed on the ends of the emitter electrode 2a and the gate electrode 3a outside the gate wiring region 4, it is possible to prevent the emitter electrode 2a and the gate electrode 3a from shorting by forming the metal plating layer 8 on each of the emitter electrode 2a and the gate electrode 3a, which are insulated from each other, on the surface of the semiconductor element. Furthermore, by increasing the thickness of the metal plating layer 8, it is possible to prevent a short circuit between the emitter electrode 2a and the gate electrode 3a and to improve the short-circuit resistance of the semiconductor device.

[0049] In the first and second embodiments, the first surface electrode 2, the second surface electrode 3, the conductive layer 5, and the back surface electrode 9 are respectively configured as the emitter electrode 2a, the gate electrode 3a, the gate wiring 5a, and the collector electrode 9a, and an example is shown in which an insulated gate bipolar transistor is formed in the semiconductor device. However, they may be respectively configured as the source electrode, the gate electrode 3a, the gate wiring 5a, and the drain electrode, and an insulated gate field effect transistor may be formed in the semiconductor device.

[0050] In addition, in the gate wiring region 4 shown in FIG. 2, when the horizontal distance between the insulating layer 6 covering the emitter electrode 2a and the insulating layer 6 covering the gate wiring 5a, that is, the width of the recess 4b, is 1 μm or more and 30 μm or less, and further when the height from the lower end of the gate wiring 5a to the upper end of the insulating layer 6 covering the gate wiring 5a, that is, the height of the protrusion 4a, is 0.5 μm or more and 10 μm or less, a conductive coating is likely to be formed on the protrusion 4a or the recess 4b. Since the recess 4b has a narrow width and a deep configuration, liquid containing a conductive substance is likely to adhere and remain, and the conductive coating is likely to spread from the recess 4b to the protrusion 4a. The same is true for the horizontal distance between the insulating layer 6 covering the gate electrode 3a and the insulating layer 6 covering the gate wiring 5a. Therefore, it can be said that it is more preferable to form a short-circuit prevention layer 7 to prevent a short circuit between the emitter electrode 2a and the gate electrode 3a.

[0051] The thickness of the emitter electrode 2a and the gate electrode 3a is preferably 1 μm or more and less than 10 μm. By making the thickness of the emitter electrode 2a and the gate electrode 3a 1 μm or more and less than 10 μm, the time required for electrode formation can be reduced and the heat dissipation and short circuit resistance of the semiconductor device can be improved.

[0052] The thickness of the metal plating layer 8 may be 1 μm or more and 50 μm or less, and preferably 5 μm or more and 40 μm or less. If the thickness of the metal plating layer 8 is 5 μm or more and 40 μm or less, the time required for plating layer formation can be reduced, and the heat dissipation and short circuit resistance of the semiconductor device can be improved. If the thickness of the metal plating layer 8 exceeds 50 μm, the stress generated in the semiconductor element becomes large, and the semiconductor element may be warped.

[0053] The semiconductor substrate 1 may be made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, or gallium oxide. When a compound semiconductor substrate is used, the semiconductor device may be operated at a higher temperature than when a silicon substrate is used. Therefore, the short-circuit prevention layer 7 and the metal plating layer 8 are formed to increase the heat dissipation effect from the metal plating layer 8 without shorting the semiconductor device.

[0054] In addition, the thickness of the semiconductor substrate 1 may be 1 μm or more and 150 μm or less, preferably 50 μm or more and 100 μm or less, from the viewpoint of the conduction loss, turn-off loss, and heat dissipation of the semiconductor device. If the thickness of the semiconductor substrate 1 is 50 μm or more and 100 μm or less, the semiconductor substrate 1 can be easily handled in the manufacturing process, and defects such as cracks and breaks in the semiconductor substrate 1 can be suppressed, and the conduction loss and turn-off loss can be suppressed. If the thickness of the semiconductor substrate 1 is thinned to 100 μm or less, the heat capacity of the semiconductor substrate 1 decreases, and the short-circuit resistance of the semiconductor device may decrease. In this case, it is more preferable to form a short-circuit prevention layer 7 to prevent short circuits and form a metal plating layer 8 to improve the heat dissipation of the semiconductor device.

[0055] Furthermore, if the thickness of the short-circuit prevention layer 7 is the same as that of the gate wiring 5a or the difference therebetween is 5 μm or less, the pressure applied to the semiconductor element can be dispersed when a process in which the semiconductor element is pressed from above during a mounting process, and cracks in the semiconductor element due to excessive pressure or pressure-bonding defects in the semiconductor element due to insufficient pressure can be suppressed.

[0056] In addition, although an example has been shown in which the back electrode 9 is only the collector electrode 9a, a metal plating layer may be formed on the surface of the collector electrode 9a opposite to the surface in contact with the semiconductor substrate 1. For example, a second metal plating layer may be formed on the collector electrode 9a at the same time as the metal plating layer 8 formed on the emitter electrode 2a and gate electrode 3a of the front electrode. Forming the second metal plating layer on the collector electrode 9a can promote heat dissipation from the back side of the semiconductor device.

[0057] Although not shown, the gate electrode 3a and the gate wiring 5a are connected via a conductive wiring layer, for example, a polysilicon layer, formed below the gate electrode 3a and the gate wiring 5a in the active region 10 or the termination region 11. The gate wiring 5a may be formed not only between the emitter electrode 2a and the gate electrode 3a, but also on the region where the emitter electrode 2a is divided in plan view, that is, on the gate wiring region 4 between the emitter electrodes 2a, as shown in a schematic plan view in FIG.

[0058] <Embodiment 3> In this embodiment, the semiconductor device according to the above-mentioned first or second embodiment is applied to a power conversion device 200. The application of the semiconductor device according to the first or second embodiment is not limited to a specific power conversion device, but the following describes a case where the semiconductor device according to the first or second embodiment is applied to a three-phase inverter.

[0059] 8 is a schematic diagram showing a schematic configuration of a power conversion system to which the power conversion device 200 according to the present embodiment is applied. The power conversion system includes a power source 100, the power conversion device 200, and a load 300.

[0060] The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 may be configured from various sources, for example, a DC system, a solar cell, or a storage battery, or may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0061] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 8, the power conversion device 200 has a main conversion circuit 201 that converts input DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.

[0062] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.

[0063] The power conversion device 200 will be described in detail below. The main conversion circuit 201 has a switching element and a freewheeling diode (not shown), and converts DC power supplied from the power source 100 into AC power by switching the switching element, and supplies the AC power to the load 300.

[0064] There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit that can be composed of six switching elements and six free wheel diodes connected in inverse parallel to each switching element. The semiconductor device according to the first or second embodiment is applied to each switching element of the main conversion circuit 201. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms the U phase, V phase, and W phase of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0065] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal that is higher than the threshold voltage of the switching element, in other words, an on signal, and when maintaining a switching element in the off state, the drive signal is a voltage signal that is lower than the threshold voltage of the switching element, in other words, an off signal.

[0066] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the on-time, which is the time during which each switching element of the main conversion circuit 201 should be in the on-state, based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by pulse width modulation control, which modulates the on-time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control signal as a control command to the drive circuit 202 so that an on signal is output to the switching element that should be in the on-state at each point in time, and an off signal is output to the switching element that should be in the off-state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with this control signal.

[0067] In the power conversion device 200 according to this embodiment, the semiconductor device according to the first or second embodiment is applied as the switching element of the main conversion circuit 201, so that a short circuit of the switching element can be prevented, and a power conversion device 200 with improved short circuit resistance can be realized.

[0068] In this embodiment, an example in which the first or second embodiment is applied to a two-level three-phase inverter has been described, but the present invention is not limited to this and can be applied to various power conversion devices. For example, the power conversion device may be a multi-level device such as a three-level device. Furthermore, when power is supplied to a single-phase load, the first or second embodiment may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the first or second embodiment may be applied to a DC / DC converter or an AC / DC converter.

[0069] Furthermore, the power conversion device to which embodiment 1 or 2 is applied is not limited to use when the load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0070] In addition to the above, the embodiments can be freely combined, any of the components of the embodiments can be modified, or any of the components of the embodiments can be omitted. [Explanation of symbols]

[0071] 1 semiconductor substrate, 1a first main surface, 1b second main surface, 2 first surface electrode, 2a emitter electrode, 3 second surface electrode, 3a gate electrode, 4 gate wiring region, 4a convex portion, 4b concave portion, 5 conductive layer, 5a gate wiring, 6 insulating layer, 7 short circuit prevention layer, 8 metal plating layer, 9 back surface electrode, 9a collector electrode, 10 active region, 11 termination region, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

1. A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first surface electrode formed on the first major surface; a second surface electrode formed apart from the first surface electrode in a plan view and electrically insulated from the first surface electrode; a conductive layer that is formed on the first main surface between the first surface electrode and the second surface electrode and is spaced apart from the first surface electrode and the second surface electrode in a plan view, and has conductivity; an insulating layer having insulating properties, the insulating layer being formed to cover the conductive layer, the first main surface between the first surface electrode and the second surface electrode, and end portions of the first surface electrode and the second surface electrode that are closer to the conductive layer; a short-circuit prevention layer formed to cover the insulating layer between the first surface electrode and the conductive layer and the insulating layer between the second surface electrode and the conductive layer, having a thickness equal to or greater than the height from the lower end to the upper end of the conductive layer, being made of a material different from the insulating layer, and having insulating properties; a metal plating layer formed on each of the first surface electrode and the second surface electrode; a back electrode formed on the second major surface; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said short circuit prevention layer is formed so as to cover said insulating layer which further covers said conductive layer.

3. 3. The semiconductor device according to claim 1, wherein the short-circuit prevention layer is formed over the insulating layer that further covers the ends of the first surface electrode and the second surface electrode, and has an area in contact with the first surface electrode and the second surface electrode.

4. 4. The semiconductor device according to claim 1, wherein the short-circuit prevention layer is made of polyimide or polybenzoxazole.

5. 5. The semiconductor device according to claim 1, wherein the surface of the short-circuit prevention layer is hydrophobic.

6. 6. The semiconductor device according to claim 1, wherein the conductive layer has a thickness equal to that of the first surface electrode and the second surface electrode.

7. 7. The semiconductor device according to claim 1, wherein the first surface electrode, the second surface electrode, the conductive layer, and the back surface electrode are an emitter electrode, a gate electrode, a gate wiring, and a collector electrode of an insulated gate bipolar transistor, respectively.

8. 7. The semiconductor device according to claim 1, wherein the first surface electrode, the second surface electrode, the conductive layer, and the back surface electrode are a source electrode, a gate electrode, a gate wiring, and a drain electrode of an insulated gate field effect transistor, respectively.

9. 9. The semiconductor device according to claim 1, wherein at least one of a horizontal distance between the insulating layer covering the first surface electrode and the insulating layer covering the conductive layer, and a horizontal distance between the insulating layer covering the second surface electrode and the insulating layer covering the conductive layer is 1 μm or more and 30 μm or less.

10. 10. The semiconductor device according to claim 9, wherein a height from a lower end of said conductive layer to an upper end of said insulating layer covering said conductive layer is 0.5 [mu]m or more and 10 [mu]m or less.

11. 11. The semiconductor device according to claim 1, wherein the first surface electrode and the second surface electrode each have a thickness of 1 μm or more and less than 10 μm, and the metal plating layer has a thickness of 5 μm or more and 40 μm or less.

12. 12. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon, silicon carbide, gallium arsenide, gallium nitride or gallium oxide and has a thickness of 50 [mu]m or more and 100 [mu]m or less.

13. A semiconductor device according to any one of claims 1 to 12, A main conversion circuit that converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit; A power conversion device comprising:

14. a surface electrode and conductive layer forming step of forming a planar electrode layer on a first main surface of the semiconductor substrate and patterning the planar electrode layer to form a first surface electrode, a second surface electrode, and a conductive layer that are spaced apart from each other in a plan view; an insulating layer forming step of forming an insulating layer covering the conductive layer, the first main surface between the first surface electrode and the second surface electrode, and ends of the first surface electrode and the second surface electrode that are closer to the conductive layer, by using a PVD method or a CVD method; a short-circuit prevention layer forming step of forming a short-circuit prevention layer that covers the insulating layer between the first surface electrode and the conductive layer and the insulating layer between the second surface electrode and the conductive layer, has a thickness equal to or greater than the height from the lower end to the upper end of the conductive layer, is made of a material different from the insulating layer, and has insulating properties; a metal plating layer forming step of, after the short circuit prevention layer forming step, immersing the first surface electrode, the second surface electrode, and the short circuit prevention layer in a plating treatment solution by using a plating method to form a metal plating layer on the first surface electrode and the second surface electrode; a back surface electrode forming step of forming a back surface electrode on a second main surface of the semiconductor substrate, the second main surface being the surface opposite to the first main surface; A method for manufacturing a semiconductor device comprising the steps of:

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein in the short-circuit prevention layer forming step, the insulating layer covering the conductive layer is further covered with the short-circuit prevention layer.

16. 16. The method for manufacturing a semiconductor device according to claim 14, wherein in the short-circuit prevention layer forming step, the insulating layer covering the ends of the first surface electrode and the second surface electrode is further covered with the short-circuit prevention layer, and the short-circuit prevention layer is brought into contact with the first surface electrode and the second surface electrode.

17. 17. The method for manufacturing a semiconductor device according to claim 14, wherein the first surface electrode, the second surface electrode, the conductive layer, and the back surface electrode are an emitter electrode, a gate electrode, a gate wiring, and a collector electrode of an insulated gate bipolar transistor, respectively.

18. 17. The method for manufacturing a semiconductor device according to claim 14, wherein the first surface electrode, the second surface electrode, the conductive layer, and the back surface electrode are a source electrode, a gate electrode, a gate wiring, and a drain electrode of an insulated gate field effect transistor, respectively.

19. 19. The method for manufacturing a semiconductor device according to claim 14, wherein the short-circuit prevention layer is formed by applying a liquid material with a dispenser and curing the liquid material with light or heat.

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